1771fe6b9SJerome Glisse /*
2771fe6b9SJerome Glisse * Copyright 2009 Jerome Glisse.
3771fe6b9SJerome Glisse *
4771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a
5771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"),
6771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation
7771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the
9771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions:
10771fe6b9SJerome Glisse *
11771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in
12771fe6b9SJerome Glisse * all copies or substantial portions of the Software.
13771fe6b9SJerome Glisse *
14771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE.
21771fe6b9SJerome Glisse *
22771fe6b9SJerome Glisse * Authors: Jerome Glisse
23771fe6b9SJerome Glisse */
24f9183127SSam Ravnborg
25771fe6b9SJerome Glisse #include <drm/radeon_drm.h>
26771fe6b9SJerome Glisse #include "radeon_reg.h"
27771fe6b9SJerome Glisse #include "radeon.h"
28771fe6b9SJerome Glisse
29cc340515SIlija Hadzic #define RADEON_BENCHMARK_COPY_BLIT 1
30cc340515SIlija Hadzic #define RADEON_BENCHMARK_COPY_DMA 0
31cc340515SIlija Hadzic
32cc340515SIlija Hadzic #define RADEON_BENCHMARK_ITERATIONS 1024
33638dd7dbSIlija Hadzic #define RADEON_BENCHMARK_COMMON_MODES_N 17
34cc340515SIlija Hadzic
radeon_benchmark_do_move(struct radeon_device * rdev,unsigned size,uint64_t saddr,uint64_t daddr,int flag,int n,struct dma_resv * resv)35cc340515SIlija Hadzic static int radeon_benchmark_do_move(struct radeon_device *rdev, unsigned size,
36cc340515SIlija Hadzic uint64_t saddr, uint64_t daddr,
373f5e1b4fSIlija Hadzic int flag, int n,
38*52791eeeSChristian König struct dma_resv *resv)
39cc340515SIlija Hadzic {
40cc340515SIlija Hadzic unsigned long start_jiffies;
41cc340515SIlija Hadzic unsigned long end_jiffies;
42cc340515SIlija Hadzic struct radeon_fence *fence = NULL;
43cc340515SIlija Hadzic int i, r;
44cc340515SIlija Hadzic
45cc340515SIlija Hadzic start_jiffies = jiffies;
46cc340515SIlija Hadzic for (i = 0; i < n; i++) {
47cc340515SIlija Hadzic switch (flag) {
48cc340515SIlija Hadzic case RADEON_BENCHMARK_COPY_DMA:
4957d20a43SChristian König fence = radeon_copy_dma(rdev, saddr, daddr,
50cc340515SIlija Hadzic size / RADEON_GPU_PAGE_SIZE,
513f5e1b4fSIlija Hadzic resv);
52cc340515SIlija Hadzic break;
53cc340515SIlija Hadzic case RADEON_BENCHMARK_COPY_BLIT:
5457d20a43SChristian König fence = radeon_copy_blit(rdev, saddr, daddr,
55cc340515SIlija Hadzic size / RADEON_GPU_PAGE_SIZE,
563f5e1b4fSIlija Hadzic resv);
57cc340515SIlija Hadzic break;
58cc340515SIlija Hadzic default:
59cc340515SIlija Hadzic DRM_ERROR("Unknown copy method\n");
6057d20a43SChristian König return -EINVAL;
61cc340515SIlija Hadzic }
6257d20a43SChristian König if (IS_ERR(fence))
6357d20a43SChristian König return PTR_ERR(fence);
6457d20a43SChristian König
65cc340515SIlija Hadzic r = radeon_fence_wait(fence, false);
66cc340515SIlija Hadzic radeon_fence_unref(&fence);
6757d20a43SChristian König if (r)
6857d20a43SChristian König return r;
69cc340515SIlija Hadzic }
70cc340515SIlija Hadzic end_jiffies = jiffies;
7157d20a43SChristian König return jiffies_to_msecs(end_jiffies - start_jiffies);
72cc340515SIlija Hadzic }
73cc340515SIlija Hadzic
74cc340515SIlija Hadzic
radeon_benchmark_log_results(int n,unsigned size,unsigned int time,unsigned sdomain,unsigned ddomain,char * kind)75cc340515SIlija Hadzic static void radeon_benchmark_log_results(int n, unsigned size,
76cc340515SIlija Hadzic unsigned int time,
77cc340515SIlija Hadzic unsigned sdomain, unsigned ddomain,
78cc340515SIlija Hadzic char *kind)
79cc340515SIlija Hadzic {
80cc340515SIlija Hadzic unsigned int throughput = (n * (size >> 10)) / time;
81cc340515SIlija Hadzic DRM_INFO("radeon: %s %u bo moves of %u kB from"
82cc340515SIlija Hadzic " %d to %d in %u ms, throughput: %u Mb/s or %u MB/s\n",
83cc340515SIlija Hadzic kind, n, size >> 10, sdomain, ddomain, time,
84cc340515SIlija Hadzic throughput * 8, throughput);
85cc340515SIlija Hadzic }
86cc340515SIlija Hadzic
radeon_benchmark_move(struct radeon_device * rdev,unsigned size,unsigned sdomain,unsigned ddomain)87cc340515SIlija Hadzic static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size,
88771fe6b9SJerome Glisse unsigned sdomain, unsigned ddomain)
89771fe6b9SJerome Glisse {
904c788679SJerome Glisse struct radeon_bo *dobj = NULL;
914c788679SJerome Glisse struct radeon_bo *sobj = NULL;
92771fe6b9SJerome Glisse uint64_t saddr, daddr;
93cc340515SIlija Hadzic int r, n;
94bfba1658SDan Carpenter int time;
95771fe6b9SJerome Glisse
96cc340515SIlija Hadzic n = RADEON_BENCHMARK_ITERATIONS;
97831b6966SMaarten Lankhorst r = radeon_bo_create(rdev, size, PAGE_SIZE, true, sdomain, 0, NULL, NULL, &sobj);
98771fe6b9SJerome Glisse if (r) {
99771fe6b9SJerome Glisse goto out_cleanup;
100771fe6b9SJerome Glisse }
1014c788679SJerome Glisse r = radeon_bo_reserve(sobj, false);
1024c788679SJerome Glisse if (unlikely(r != 0))
1034c788679SJerome Glisse goto out_cleanup;
1044c788679SJerome Glisse r = radeon_bo_pin(sobj, sdomain, &saddr);
1054c788679SJerome Glisse radeon_bo_unreserve(sobj);
106771fe6b9SJerome Glisse if (r) {
107771fe6b9SJerome Glisse goto out_cleanup;
108771fe6b9SJerome Glisse }
109831b6966SMaarten Lankhorst r = radeon_bo_create(rdev, size, PAGE_SIZE, true, ddomain, 0, NULL, NULL, &dobj);
110771fe6b9SJerome Glisse if (r) {
111771fe6b9SJerome Glisse goto out_cleanup;
112771fe6b9SJerome Glisse }
1134c788679SJerome Glisse r = radeon_bo_reserve(dobj, false);
1144c788679SJerome Glisse if (unlikely(r != 0))
1154c788679SJerome Glisse goto out_cleanup;
1164c788679SJerome Glisse r = radeon_bo_pin(dobj, ddomain, &daddr);
1174c788679SJerome Glisse radeon_bo_unreserve(dobj);
118771fe6b9SJerome Glisse if (r) {
119771fe6b9SJerome Glisse goto out_cleanup;
120771fe6b9SJerome Glisse }
121c60a284cSPauli Nieminen
122271e53dcSAlex Deucher if (rdev->asic->copy.dma) {
123cc340515SIlija Hadzic time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
1243f5e1b4fSIlija Hadzic RADEON_BENCHMARK_COPY_DMA, n,
125336ac942SGerd Hoffmann dobj->tbo.base.resv);
126cc340515SIlija Hadzic if (time < 0)
127771fe6b9SJerome Glisse goto out_cleanup;
128cc340515SIlija Hadzic if (time > 0)
129cc340515SIlija Hadzic radeon_benchmark_log_results(n, size, time,
130cc340515SIlija Hadzic sdomain, ddomain, "dma");
131771fe6b9SJerome Glisse }
132c60a284cSPauli Nieminen
133fa8d387dSAlex Deucher if (rdev->asic->copy.blit) {
134cc340515SIlija Hadzic time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
1353f5e1b4fSIlija Hadzic RADEON_BENCHMARK_COPY_BLIT, n,
136336ac942SGerd Hoffmann dobj->tbo.base.resv);
137cc340515SIlija Hadzic if (time < 0)
138cc340515SIlija Hadzic goto out_cleanup;
139cc340515SIlija Hadzic if (time > 0)
140cc340515SIlija Hadzic radeon_benchmark_log_results(n, size, time,
141cc340515SIlija Hadzic sdomain, ddomain, "blit");
142fa8d387dSAlex Deucher }
143c60a284cSPauli Nieminen
144771fe6b9SJerome Glisse out_cleanup:
145771fe6b9SJerome Glisse if (sobj) {
1464c788679SJerome Glisse r = radeon_bo_reserve(sobj, false);
1474c788679SJerome Glisse if (likely(r == 0)) {
1484c788679SJerome Glisse radeon_bo_unpin(sobj);
1494c788679SJerome Glisse radeon_bo_unreserve(sobj);
1504c788679SJerome Glisse }
1514c788679SJerome Glisse radeon_bo_unref(&sobj);
152771fe6b9SJerome Glisse }
153771fe6b9SJerome Glisse if (dobj) {
1544c788679SJerome Glisse r = radeon_bo_reserve(dobj, false);
1554c788679SJerome Glisse if (likely(r == 0)) {
1564c788679SJerome Glisse radeon_bo_unpin(dobj);
1574c788679SJerome Glisse radeon_bo_unreserve(dobj);
1584c788679SJerome Glisse }
1594c788679SJerome Glisse radeon_bo_unref(&dobj);
160771fe6b9SJerome Glisse }
161cc340515SIlija Hadzic
162771fe6b9SJerome Glisse if (r) {
163cc340515SIlija Hadzic DRM_ERROR("Error while benchmarking BO move.\n");
164771fe6b9SJerome Glisse }
165771fe6b9SJerome Glisse }
166771fe6b9SJerome Glisse
radeon_benchmark(struct radeon_device * rdev,int test_number)167638dd7dbSIlija Hadzic void radeon_benchmark(struct radeon_device *rdev, int test_number)
168771fe6b9SJerome Glisse {
169638dd7dbSIlija Hadzic int i;
170638dd7dbSIlija Hadzic int common_modes[RADEON_BENCHMARK_COMMON_MODES_N] = {
171638dd7dbSIlija Hadzic 640 * 480 * 4,
172638dd7dbSIlija Hadzic 720 * 480 * 4,
173638dd7dbSIlija Hadzic 800 * 600 * 4,
174638dd7dbSIlija Hadzic 848 * 480 * 4,
175638dd7dbSIlija Hadzic 1024 * 768 * 4,
176638dd7dbSIlija Hadzic 1152 * 768 * 4,
177638dd7dbSIlija Hadzic 1280 * 720 * 4,
178638dd7dbSIlija Hadzic 1280 * 800 * 4,
179638dd7dbSIlija Hadzic 1280 * 854 * 4,
180638dd7dbSIlija Hadzic 1280 * 960 * 4,
181638dd7dbSIlija Hadzic 1280 * 1024 * 4,
182638dd7dbSIlija Hadzic 1440 * 900 * 4,
183638dd7dbSIlija Hadzic 1400 * 1050 * 4,
184638dd7dbSIlija Hadzic 1680 * 1050 * 4,
185638dd7dbSIlija Hadzic 1600 * 1200 * 4,
186638dd7dbSIlija Hadzic 1920 * 1080 * 4,
187638dd7dbSIlija Hadzic 1920 * 1200 * 4
188638dd7dbSIlija Hadzic };
189638dd7dbSIlija Hadzic
190638dd7dbSIlija Hadzic switch (test_number) {
191638dd7dbSIlija Hadzic case 1:
192638dd7dbSIlija Hadzic /* simple test, VRAM to GTT and GTT to VRAM */
193771fe6b9SJerome Glisse radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_GTT,
194771fe6b9SJerome Glisse RADEON_GEM_DOMAIN_VRAM);
195771fe6b9SJerome Glisse radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_VRAM,
196771fe6b9SJerome Glisse RADEON_GEM_DOMAIN_GTT);
197638dd7dbSIlija Hadzic break;
198638dd7dbSIlija Hadzic case 2:
199638dd7dbSIlija Hadzic /* simple test, VRAM to VRAM */
200638dd7dbSIlija Hadzic radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_VRAM,
201638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_VRAM);
202638dd7dbSIlija Hadzic break;
203638dd7dbSIlija Hadzic case 3:
204638dd7dbSIlija Hadzic /* GTT to VRAM, buffer size sweep, powers of 2 */
2056d75e83eSIlija Hadzic for (i = 1; i <= 16384; i <<= 1)
2066d75e83eSIlija Hadzic radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
207638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_GTT,
208638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_VRAM);
209638dd7dbSIlija Hadzic break;
210638dd7dbSIlija Hadzic case 4:
211638dd7dbSIlija Hadzic /* VRAM to GTT, buffer size sweep, powers of 2 */
2126d75e83eSIlija Hadzic for (i = 1; i <= 16384; i <<= 1)
2136d75e83eSIlija Hadzic radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
214638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_VRAM,
215638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_GTT);
216638dd7dbSIlija Hadzic break;
217638dd7dbSIlija Hadzic case 5:
218638dd7dbSIlija Hadzic /* VRAM to VRAM, buffer size sweep, powers of 2 */
2196d75e83eSIlija Hadzic for (i = 1; i <= 16384; i <<= 1)
2206d75e83eSIlija Hadzic radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
221638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_VRAM,
222638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_VRAM);
223638dd7dbSIlija Hadzic break;
224638dd7dbSIlija Hadzic case 6:
225638dd7dbSIlija Hadzic /* GTT to VRAM, buffer size sweep, common modes */
226d7d0a75cSChen Jie for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
227638dd7dbSIlija Hadzic radeon_benchmark_move(rdev, common_modes[i],
228638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_GTT,
229638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_VRAM);
230638dd7dbSIlija Hadzic break;
231638dd7dbSIlija Hadzic case 7:
232638dd7dbSIlija Hadzic /* VRAM to GTT, buffer size sweep, common modes */
233d7d0a75cSChen Jie for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
234638dd7dbSIlija Hadzic radeon_benchmark_move(rdev, common_modes[i],
235638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_VRAM,
236638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_GTT);
237638dd7dbSIlija Hadzic break;
238638dd7dbSIlija Hadzic case 8:
239638dd7dbSIlija Hadzic /* VRAM to VRAM, buffer size sweep, common modes */
240d7d0a75cSChen Jie for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
241638dd7dbSIlija Hadzic radeon_benchmark_move(rdev, common_modes[i],
242638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_VRAM,
243638dd7dbSIlija Hadzic RADEON_GEM_DOMAIN_VRAM);
244638dd7dbSIlija Hadzic break;
245638dd7dbSIlija Hadzic
246638dd7dbSIlija Hadzic default:
247638dd7dbSIlija Hadzic DRM_ERROR("Unknown benchmark\n");
248638dd7dbSIlija Hadzic }
249771fe6b9SJerome Glisse }
250