1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 68 #include <ttm/ttm_bo_api.h> 69 #include <ttm/ttm_bo_driver.h> 70 #include <ttm/ttm_placement.h> 71 #include <ttm/ttm_module.h> 72 #include <ttm/ttm_execbuf_util.h> 73 74 #include "radeon_family.h" 75 #include "radeon_mode.h" 76 #include "radeon_reg.h" 77 78 /* 79 * Modules parameters. 80 */ 81 extern int radeon_no_wb; 82 extern int radeon_modeset; 83 extern int radeon_dynclks; 84 extern int radeon_r4xx_atom; 85 extern int radeon_agpmode; 86 extern int radeon_vram_limit; 87 extern int radeon_gart_size; 88 extern int radeon_benchmarking; 89 extern int radeon_testing; 90 extern int radeon_connector_table; 91 extern int radeon_tv; 92 extern int radeon_audio; 93 extern int radeon_disp_priority; 94 extern int radeon_hw_i2c; 95 extern int radeon_pcie_gen2; 96 extern int radeon_msi; 97 extern int radeon_lockup_timeout; 98 extern int radeon_fastfb; 99 extern int radeon_dpm; 100 101 /* 102 * Copy from radeon_drv.h so we don't have to include both and have conflicting 103 * symbol; 104 */ 105 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 106 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 107 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 108 #define RADEON_IB_POOL_SIZE 16 109 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 110 #define RADEONFB_CONN_LIMIT 4 111 #define RADEON_BIOS_NUM_SCRATCH 8 112 113 /* max number of rings */ 114 #define RADEON_NUM_RINGS 6 115 116 /* fence seq are set to this number when signaled */ 117 #define RADEON_FENCE_SIGNALED_SEQ 0LL 118 119 /* internal ring indices */ 120 /* r1xx+ has gfx CP ring */ 121 #define RADEON_RING_TYPE_GFX_INDEX 0 122 123 /* cayman has 2 compute CP rings */ 124 #define CAYMAN_RING_TYPE_CP1_INDEX 1 125 #define CAYMAN_RING_TYPE_CP2_INDEX 2 126 127 /* R600+ has an async dma ring */ 128 #define R600_RING_TYPE_DMA_INDEX 3 129 /* cayman add a second async dma ring */ 130 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 131 132 /* R600+ */ 133 #define R600_RING_TYPE_UVD_INDEX 5 134 135 /* hardcode those limit for now */ 136 #define RADEON_VA_IB_OFFSET (1 << 20) 137 #define RADEON_VA_RESERVED_SIZE (8 << 20) 138 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 139 140 /* reset flags */ 141 #define RADEON_RESET_GFX (1 << 0) 142 #define RADEON_RESET_COMPUTE (1 << 1) 143 #define RADEON_RESET_DMA (1 << 2) 144 #define RADEON_RESET_CP (1 << 3) 145 #define RADEON_RESET_GRBM (1 << 4) 146 #define RADEON_RESET_DMA1 (1 << 5) 147 #define RADEON_RESET_RLC (1 << 6) 148 #define RADEON_RESET_SEM (1 << 7) 149 #define RADEON_RESET_IH (1 << 8) 150 #define RADEON_RESET_VMC (1 << 9) 151 #define RADEON_RESET_MC (1 << 10) 152 #define RADEON_RESET_DISPLAY (1 << 11) 153 154 /* max cursor sizes (in pixels) */ 155 #define CURSOR_WIDTH 64 156 #define CURSOR_HEIGHT 64 157 158 #define CIK_CURSOR_WIDTH 128 159 #define CIK_CURSOR_HEIGHT 128 160 161 /* 162 * Errata workarounds. 163 */ 164 enum radeon_pll_errata { 165 CHIP_ERRATA_R300_CG = 0x00000001, 166 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 167 CHIP_ERRATA_PLL_DELAY = 0x00000004 168 }; 169 170 171 struct radeon_device; 172 173 174 /* 175 * BIOS. 176 */ 177 bool radeon_get_bios(struct radeon_device *rdev); 178 179 /* 180 * Dummy page 181 */ 182 struct radeon_dummy_page { 183 struct page *page; 184 dma_addr_t addr; 185 }; 186 int radeon_dummy_page_init(struct radeon_device *rdev); 187 void radeon_dummy_page_fini(struct radeon_device *rdev); 188 189 190 /* 191 * Clocks 192 */ 193 struct radeon_clock { 194 struct radeon_pll p1pll; 195 struct radeon_pll p2pll; 196 struct radeon_pll dcpll; 197 struct radeon_pll spll; 198 struct radeon_pll mpll; 199 /* 10 Khz units */ 200 uint32_t default_mclk; 201 uint32_t default_sclk; 202 uint32_t default_dispclk; 203 uint32_t dp_extclk; 204 uint32_t max_pixel_clock; 205 }; 206 207 /* 208 * Power management 209 */ 210 int radeon_pm_init(struct radeon_device *rdev); 211 void radeon_pm_fini(struct radeon_device *rdev); 212 void radeon_pm_compute_clocks(struct radeon_device *rdev); 213 void radeon_pm_suspend(struct radeon_device *rdev); 214 void radeon_pm_resume(struct radeon_device *rdev); 215 void radeon_combios_get_power_modes(struct radeon_device *rdev); 216 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 217 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 218 u8 clock_type, 219 u32 clock, 220 bool strobe_mode, 221 struct atom_clock_dividers *dividers); 222 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 223 u32 clock, 224 bool strobe_mode, 225 struct atom_mpll_param *mpll_param); 226 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 227 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 228 u16 voltage_level, u8 voltage_type, 229 u32 *gpio_value, u32 *gpio_mask); 230 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 231 u32 eng_clock, u32 mem_clock); 232 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 233 u8 voltage_type, u16 *voltage_step); 234 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 235 u16 voltage_id, u16 *voltage); 236 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 237 u8 voltage_type, 238 u16 nominal_voltage, 239 u16 *true_voltage); 240 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 241 u8 voltage_type, u16 *min_voltage); 242 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 243 u8 voltage_type, u16 *max_voltage); 244 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 245 u8 voltage_type, 246 struct atom_voltage_table *voltage_table); 247 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, u8 voltage_type); 248 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 249 u32 mem_clock); 250 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 251 u32 mem_clock); 252 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 253 u8 module_index, 254 struct atom_mc_reg_table *reg_table); 255 int radeon_atom_get_memory_info(struct radeon_device *rdev, 256 u8 module_index, struct atom_memory_info *mem_info); 257 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 258 bool gddr5, u8 module_index, 259 struct atom_memory_clock_range_table *mclk_range_table); 260 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 261 u16 voltage_id, u16 *voltage); 262 void rs690_pm_info(struct radeon_device *rdev); 263 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 264 unsigned *bankh, unsigned *mtaspect, 265 unsigned *tile_split); 266 267 /* 268 * Fences. 269 */ 270 struct radeon_fence_driver { 271 uint32_t scratch_reg; 272 uint64_t gpu_addr; 273 volatile uint32_t *cpu_addr; 274 /* sync_seq is protected by ring emission lock */ 275 uint64_t sync_seq[RADEON_NUM_RINGS]; 276 atomic64_t last_seq; 277 unsigned long last_activity; 278 bool initialized; 279 }; 280 281 struct radeon_fence { 282 struct radeon_device *rdev; 283 struct kref kref; 284 /* protected by radeon_fence.lock */ 285 uint64_t seq; 286 /* RB, DMA, etc. */ 287 unsigned ring; 288 }; 289 290 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 291 int radeon_fence_driver_init(struct radeon_device *rdev); 292 void radeon_fence_driver_fini(struct radeon_device *rdev); 293 void radeon_fence_driver_force_completion(struct radeon_device *rdev); 294 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 295 void radeon_fence_process(struct radeon_device *rdev, int ring); 296 bool radeon_fence_signaled(struct radeon_fence *fence); 297 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 298 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 299 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 300 int radeon_fence_wait_any(struct radeon_device *rdev, 301 struct radeon_fence **fences, 302 bool intr); 303 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 304 void radeon_fence_unref(struct radeon_fence **fence); 305 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 306 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 307 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 308 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 309 struct radeon_fence *b) 310 { 311 if (!a) { 312 return b; 313 } 314 315 if (!b) { 316 return a; 317 } 318 319 BUG_ON(a->ring != b->ring); 320 321 if (a->seq > b->seq) { 322 return a; 323 } else { 324 return b; 325 } 326 } 327 328 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 329 struct radeon_fence *b) 330 { 331 if (!a) { 332 return false; 333 } 334 335 if (!b) { 336 return true; 337 } 338 339 BUG_ON(a->ring != b->ring); 340 341 return a->seq < b->seq; 342 } 343 344 /* 345 * Tiling registers 346 */ 347 struct radeon_surface_reg { 348 struct radeon_bo *bo; 349 }; 350 351 #define RADEON_GEM_MAX_SURFACES 8 352 353 /* 354 * TTM. 355 */ 356 struct radeon_mman { 357 struct ttm_bo_global_ref bo_global_ref; 358 struct drm_global_reference mem_global_ref; 359 struct ttm_bo_device bdev; 360 bool mem_global_referenced; 361 bool initialized; 362 }; 363 364 /* bo virtual address in a specific vm */ 365 struct radeon_bo_va { 366 /* protected by bo being reserved */ 367 struct list_head bo_list; 368 uint64_t soffset; 369 uint64_t eoffset; 370 uint32_t flags; 371 bool valid; 372 unsigned ref_count; 373 374 /* protected by vm mutex */ 375 struct list_head vm_list; 376 377 /* constant after initialization */ 378 struct radeon_vm *vm; 379 struct radeon_bo *bo; 380 }; 381 382 struct radeon_bo { 383 /* Protected by gem.mutex */ 384 struct list_head list; 385 /* Protected by tbo.reserved */ 386 u32 placements[3]; 387 struct ttm_placement placement; 388 struct ttm_buffer_object tbo; 389 struct ttm_bo_kmap_obj kmap; 390 unsigned pin_count; 391 void *kptr; 392 u32 tiling_flags; 393 u32 pitch; 394 int surface_reg; 395 /* list of all virtual address to which this bo 396 * is associated to 397 */ 398 struct list_head va; 399 /* Constant after initialization */ 400 struct radeon_device *rdev; 401 struct drm_gem_object gem_base; 402 403 struct ttm_bo_kmap_obj dma_buf_vmap; 404 pid_t pid; 405 }; 406 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 407 408 struct radeon_bo_list { 409 struct ttm_validate_buffer tv; 410 struct radeon_bo *bo; 411 uint64_t gpu_offset; 412 bool written; 413 unsigned domain; 414 unsigned alt_domain; 415 u32 tiling_flags; 416 }; 417 418 int radeon_gem_debugfs_init(struct radeon_device *rdev); 419 420 /* sub-allocation manager, it has to be protected by another lock. 421 * By conception this is an helper for other part of the driver 422 * like the indirect buffer or semaphore, which both have their 423 * locking. 424 * 425 * Principe is simple, we keep a list of sub allocation in offset 426 * order (first entry has offset == 0, last entry has the highest 427 * offset). 428 * 429 * When allocating new object we first check if there is room at 430 * the end total_size - (last_object_offset + last_object_size) >= 431 * alloc_size. If so we allocate new object there. 432 * 433 * When there is not enough room at the end, we start waiting for 434 * each sub object until we reach object_offset+object_size >= 435 * alloc_size, this object then become the sub object we return. 436 * 437 * Alignment can't be bigger than page size. 438 * 439 * Hole are not considered for allocation to keep things simple. 440 * Assumption is that there won't be hole (all object on same 441 * alignment). 442 */ 443 struct radeon_sa_manager { 444 wait_queue_head_t wq; 445 struct radeon_bo *bo; 446 struct list_head *hole; 447 struct list_head flist[RADEON_NUM_RINGS]; 448 struct list_head olist; 449 unsigned size; 450 uint64_t gpu_addr; 451 void *cpu_ptr; 452 uint32_t domain; 453 }; 454 455 struct radeon_sa_bo; 456 457 /* sub-allocation buffer */ 458 struct radeon_sa_bo { 459 struct list_head olist; 460 struct list_head flist; 461 struct radeon_sa_manager *manager; 462 unsigned soffset; 463 unsigned eoffset; 464 struct radeon_fence *fence; 465 }; 466 467 /* 468 * GEM objects. 469 */ 470 struct radeon_gem { 471 struct mutex mutex; 472 struct list_head objects; 473 }; 474 475 int radeon_gem_init(struct radeon_device *rdev); 476 void radeon_gem_fini(struct radeon_device *rdev); 477 int radeon_gem_object_create(struct radeon_device *rdev, int size, 478 int alignment, int initial_domain, 479 bool discardable, bool kernel, 480 struct drm_gem_object **obj); 481 482 int radeon_mode_dumb_create(struct drm_file *file_priv, 483 struct drm_device *dev, 484 struct drm_mode_create_dumb *args); 485 int radeon_mode_dumb_mmap(struct drm_file *filp, 486 struct drm_device *dev, 487 uint32_t handle, uint64_t *offset_p); 488 int radeon_mode_dumb_destroy(struct drm_file *file_priv, 489 struct drm_device *dev, 490 uint32_t handle); 491 492 /* 493 * Semaphores. 494 */ 495 /* everything here is constant */ 496 struct radeon_semaphore { 497 struct radeon_sa_bo *sa_bo; 498 signed waiters; 499 uint64_t gpu_addr; 500 }; 501 502 int radeon_semaphore_create(struct radeon_device *rdev, 503 struct radeon_semaphore **semaphore); 504 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 505 struct radeon_semaphore *semaphore); 506 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 507 struct radeon_semaphore *semaphore); 508 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 509 struct radeon_semaphore *semaphore, 510 int signaler, int waiter); 511 void radeon_semaphore_free(struct radeon_device *rdev, 512 struct radeon_semaphore **semaphore, 513 struct radeon_fence *fence); 514 515 /* 516 * GART structures, functions & helpers 517 */ 518 struct radeon_mc; 519 520 #define RADEON_GPU_PAGE_SIZE 4096 521 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 522 #define RADEON_GPU_PAGE_SHIFT 12 523 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 524 525 struct radeon_gart { 526 dma_addr_t table_addr; 527 struct radeon_bo *robj; 528 void *ptr; 529 unsigned num_gpu_pages; 530 unsigned num_cpu_pages; 531 unsigned table_size; 532 struct page **pages; 533 dma_addr_t *pages_addr; 534 bool ready; 535 }; 536 537 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 538 void radeon_gart_table_ram_free(struct radeon_device *rdev); 539 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 540 void radeon_gart_table_vram_free(struct radeon_device *rdev); 541 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 542 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 543 int radeon_gart_init(struct radeon_device *rdev); 544 void radeon_gart_fini(struct radeon_device *rdev); 545 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 546 int pages); 547 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 548 int pages, struct page **pagelist, 549 dma_addr_t *dma_addr); 550 void radeon_gart_restore(struct radeon_device *rdev); 551 552 553 /* 554 * GPU MC structures, functions & helpers 555 */ 556 struct radeon_mc { 557 resource_size_t aper_size; 558 resource_size_t aper_base; 559 resource_size_t agp_base; 560 /* for some chips with <= 32MB we need to lie 561 * about vram size near mc fb location */ 562 u64 mc_vram_size; 563 u64 visible_vram_size; 564 u64 gtt_size; 565 u64 gtt_start; 566 u64 gtt_end; 567 u64 vram_start; 568 u64 vram_end; 569 unsigned vram_width; 570 u64 real_vram_size; 571 int vram_mtrr; 572 bool vram_is_ddr; 573 bool igp_sideport_enabled; 574 u64 gtt_base_align; 575 u64 mc_mask; 576 }; 577 578 bool radeon_combios_sideport_present(struct radeon_device *rdev); 579 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 580 581 /* 582 * GPU scratch registers structures, functions & helpers 583 */ 584 struct radeon_scratch { 585 unsigned num_reg; 586 uint32_t reg_base; 587 bool free[32]; 588 uint32_t reg[32]; 589 }; 590 591 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 592 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 593 594 /* 595 * GPU doorbell structures, functions & helpers 596 */ 597 struct radeon_doorbell { 598 u32 num_pages; 599 bool free[1024]; 600 /* doorbell mmio */ 601 resource_size_t base; 602 resource_size_t size; 603 void __iomem *ptr; 604 }; 605 606 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 607 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 608 609 /* 610 * IRQS. 611 */ 612 613 struct radeon_unpin_work { 614 struct work_struct work; 615 struct radeon_device *rdev; 616 int crtc_id; 617 struct radeon_fence *fence; 618 struct drm_pending_vblank_event *event; 619 struct radeon_bo *old_rbo; 620 u64 new_crtc_base; 621 }; 622 623 struct r500_irq_stat_regs { 624 u32 disp_int; 625 u32 hdmi0_status; 626 }; 627 628 struct r600_irq_stat_regs { 629 u32 disp_int; 630 u32 disp_int_cont; 631 u32 disp_int_cont2; 632 u32 d1grph_int; 633 u32 d2grph_int; 634 u32 hdmi0_status; 635 u32 hdmi1_status; 636 }; 637 638 struct evergreen_irq_stat_regs { 639 u32 disp_int; 640 u32 disp_int_cont; 641 u32 disp_int_cont2; 642 u32 disp_int_cont3; 643 u32 disp_int_cont4; 644 u32 disp_int_cont5; 645 u32 d1grph_int; 646 u32 d2grph_int; 647 u32 d3grph_int; 648 u32 d4grph_int; 649 u32 d5grph_int; 650 u32 d6grph_int; 651 u32 afmt_status1; 652 u32 afmt_status2; 653 u32 afmt_status3; 654 u32 afmt_status4; 655 u32 afmt_status5; 656 u32 afmt_status6; 657 }; 658 659 struct cik_irq_stat_regs { 660 u32 disp_int; 661 u32 disp_int_cont; 662 u32 disp_int_cont2; 663 u32 disp_int_cont3; 664 u32 disp_int_cont4; 665 u32 disp_int_cont5; 666 u32 disp_int_cont6; 667 }; 668 669 union radeon_irq_stat_regs { 670 struct r500_irq_stat_regs r500; 671 struct r600_irq_stat_regs r600; 672 struct evergreen_irq_stat_regs evergreen; 673 struct cik_irq_stat_regs cik; 674 }; 675 676 #define RADEON_MAX_HPD_PINS 6 677 #define RADEON_MAX_CRTCS 6 678 #define RADEON_MAX_AFMT_BLOCKS 6 679 680 struct radeon_irq { 681 bool installed; 682 spinlock_t lock; 683 atomic_t ring_int[RADEON_NUM_RINGS]; 684 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 685 atomic_t pflip[RADEON_MAX_CRTCS]; 686 wait_queue_head_t vblank_queue; 687 bool hpd[RADEON_MAX_HPD_PINS]; 688 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 689 union radeon_irq_stat_regs stat_regs; 690 bool dpm_thermal; 691 }; 692 693 int radeon_irq_kms_init(struct radeon_device *rdev); 694 void radeon_irq_kms_fini(struct radeon_device *rdev); 695 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 696 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 697 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 698 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 699 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 700 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 701 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 702 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 703 704 /* 705 * CP & rings. 706 */ 707 708 struct radeon_ib { 709 struct radeon_sa_bo *sa_bo; 710 uint32_t length_dw; 711 uint64_t gpu_addr; 712 uint32_t *ptr; 713 int ring; 714 struct radeon_fence *fence; 715 struct radeon_vm *vm; 716 bool is_const_ib; 717 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 718 struct radeon_semaphore *semaphore; 719 }; 720 721 struct radeon_ring { 722 struct radeon_bo *ring_obj; 723 volatile uint32_t *ring; 724 unsigned rptr; 725 unsigned rptr_offs; 726 unsigned rptr_reg; 727 unsigned rptr_save_reg; 728 u64 next_rptr_gpu_addr; 729 volatile u32 *next_rptr_cpu_addr; 730 unsigned wptr; 731 unsigned wptr_old; 732 unsigned wptr_reg; 733 unsigned ring_size; 734 unsigned ring_free_dw; 735 int count_dw; 736 unsigned long last_activity; 737 unsigned last_rptr; 738 uint64_t gpu_addr; 739 uint32_t align_mask; 740 uint32_t ptr_mask; 741 bool ready; 742 u32 ptr_reg_shift; 743 u32 ptr_reg_mask; 744 u32 nop; 745 u32 idx; 746 u64 last_semaphore_signal_addr; 747 u64 last_semaphore_wait_addr; 748 /* for CIK queues */ 749 u32 me; 750 u32 pipe; 751 u32 queue; 752 struct radeon_bo *mqd_obj; 753 u32 doorbell_page_num; 754 u32 doorbell_offset; 755 unsigned wptr_offs; 756 }; 757 758 struct radeon_mec { 759 struct radeon_bo *hpd_eop_obj; 760 u64 hpd_eop_gpu_addr; 761 u32 num_pipe; 762 u32 num_mec; 763 u32 num_queue; 764 }; 765 766 /* 767 * VM 768 */ 769 770 /* maximum number of VMIDs */ 771 #define RADEON_NUM_VM 16 772 773 /* defines number of bits in page table versus page directory, 774 * a page is 4KB so we have 12 bits offset, 9 bits in the page 775 * table and the remaining 19 bits are in the page directory */ 776 #define RADEON_VM_BLOCK_SIZE 9 777 778 /* number of entries in page table */ 779 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 780 781 struct radeon_vm { 782 struct list_head list; 783 struct list_head va; 784 unsigned id; 785 786 /* contains the page directory */ 787 struct radeon_sa_bo *page_directory; 788 uint64_t pd_gpu_addr; 789 790 /* array of page tables, one for each page directory entry */ 791 struct radeon_sa_bo **page_tables; 792 793 struct mutex mutex; 794 /* last fence for cs using this vm */ 795 struct radeon_fence *fence; 796 /* last flush or NULL if we still need to flush */ 797 struct radeon_fence *last_flush; 798 }; 799 800 struct radeon_vm_manager { 801 struct mutex lock; 802 struct list_head lru_vm; 803 struct radeon_fence *active[RADEON_NUM_VM]; 804 struct radeon_sa_manager sa_manager; 805 uint32_t max_pfn; 806 /* number of VMIDs */ 807 unsigned nvm; 808 /* vram base address for page table entry */ 809 u64 vram_base_offset; 810 /* is vm enabled? */ 811 bool enabled; 812 }; 813 814 /* 815 * file private structure 816 */ 817 struct radeon_fpriv { 818 struct radeon_vm vm; 819 }; 820 821 /* 822 * R6xx+ IH ring 823 */ 824 struct r600_ih { 825 struct radeon_bo *ring_obj; 826 volatile uint32_t *ring; 827 unsigned rptr; 828 unsigned ring_size; 829 uint64_t gpu_addr; 830 uint32_t ptr_mask; 831 atomic_t lock; 832 bool enabled; 833 }; 834 835 struct r600_blit_cp_primitives { 836 void (*set_render_target)(struct radeon_device *rdev, int format, 837 int w, int h, u64 gpu_addr); 838 void (*cp_set_surface_sync)(struct radeon_device *rdev, 839 u32 sync_type, u32 size, 840 u64 mc_addr); 841 void (*set_shaders)(struct radeon_device *rdev); 842 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 843 void (*set_tex_resource)(struct radeon_device *rdev, 844 int format, int w, int h, int pitch, 845 u64 gpu_addr, u32 size); 846 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 847 int x2, int y2); 848 void (*draw_auto)(struct radeon_device *rdev); 849 void (*set_default_state)(struct radeon_device *rdev); 850 }; 851 852 struct r600_blit { 853 struct radeon_bo *shader_obj; 854 struct r600_blit_cp_primitives primitives; 855 int max_dim; 856 int ring_size_common; 857 int ring_size_per_loop; 858 u64 shader_gpu_addr; 859 u32 vs_offset, ps_offset; 860 u32 state_offset; 861 u32 state_len; 862 }; 863 864 /* 865 * RLC stuff 866 */ 867 #include "clearstate_defs.h" 868 869 struct radeon_rlc { 870 /* for power gating */ 871 struct radeon_bo *save_restore_obj; 872 uint64_t save_restore_gpu_addr; 873 volatile uint32_t *sr_ptr; 874 u32 *reg_list; 875 u32 reg_list_size; 876 /* for clear state */ 877 struct radeon_bo *clear_state_obj; 878 uint64_t clear_state_gpu_addr; 879 volatile uint32_t *cs_ptr; 880 struct cs_section_def *cs_data; 881 }; 882 883 int radeon_ib_get(struct radeon_device *rdev, int ring, 884 struct radeon_ib *ib, struct radeon_vm *vm, 885 unsigned size); 886 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 887 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence); 888 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 889 struct radeon_ib *const_ib); 890 int radeon_ib_pool_init(struct radeon_device *rdev); 891 void radeon_ib_pool_fini(struct radeon_device *rdev); 892 int radeon_ib_ring_tests(struct radeon_device *rdev); 893 /* Ring access between begin & end cannot sleep */ 894 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 895 struct radeon_ring *ring); 896 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 897 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 898 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 899 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 900 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 901 void radeon_ring_undo(struct radeon_ring *ring); 902 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 903 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 904 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 905 void radeon_ring_lockup_update(struct radeon_ring *ring); 906 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 907 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 908 uint32_t **data); 909 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 910 unsigned size, uint32_t *data); 911 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 912 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 913 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 914 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 915 916 917 /* r600 async dma */ 918 void r600_dma_stop(struct radeon_device *rdev); 919 int r600_dma_resume(struct radeon_device *rdev); 920 void r600_dma_fini(struct radeon_device *rdev); 921 922 void cayman_dma_stop(struct radeon_device *rdev); 923 int cayman_dma_resume(struct radeon_device *rdev); 924 void cayman_dma_fini(struct radeon_device *rdev); 925 926 /* 927 * CS. 928 */ 929 struct radeon_cs_reloc { 930 struct drm_gem_object *gobj; 931 struct radeon_bo *robj; 932 struct radeon_bo_list lobj; 933 uint32_t handle; 934 uint32_t flags; 935 }; 936 937 struct radeon_cs_chunk { 938 uint32_t chunk_id; 939 uint32_t length_dw; 940 int kpage_idx[2]; 941 uint32_t *kpage[2]; 942 uint32_t *kdata; 943 void __user *user_ptr; 944 int last_copied_page; 945 int last_page_index; 946 }; 947 948 struct radeon_cs_parser { 949 struct device *dev; 950 struct radeon_device *rdev; 951 struct drm_file *filp; 952 /* chunks */ 953 unsigned nchunks; 954 struct radeon_cs_chunk *chunks; 955 uint64_t *chunks_array; 956 /* IB */ 957 unsigned idx; 958 /* relocations */ 959 unsigned nrelocs; 960 struct radeon_cs_reloc *relocs; 961 struct radeon_cs_reloc **relocs_ptr; 962 struct list_head validated; 963 unsigned dma_reloc_idx; 964 /* indices of various chunks */ 965 int chunk_ib_idx; 966 int chunk_relocs_idx; 967 int chunk_flags_idx; 968 int chunk_const_ib_idx; 969 struct radeon_ib ib; 970 struct radeon_ib const_ib; 971 void *track; 972 unsigned family; 973 int parser_error; 974 u32 cs_flags; 975 u32 ring; 976 s32 priority; 977 }; 978 979 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 980 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 981 982 struct radeon_cs_packet { 983 unsigned idx; 984 unsigned type; 985 unsigned reg; 986 unsigned opcode; 987 int count; 988 unsigned one_reg_wr; 989 }; 990 991 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 992 struct radeon_cs_packet *pkt, 993 unsigned idx, unsigned reg); 994 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 995 struct radeon_cs_packet *pkt); 996 997 998 /* 999 * AGP 1000 */ 1001 int radeon_agp_init(struct radeon_device *rdev); 1002 void radeon_agp_resume(struct radeon_device *rdev); 1003 void radeon_agp_suspend(struct radeon_device *rdev); 1004 void radeon_agp_fini(struct radeon_device *rdev); 1005 1006 1007 /* 1008 * Writeback 1009 */ 1010 struct radeon_wb { 1011 struct radeon_bo *wb_obj; 1012 volatile uint32_t *wb; 1013 uint64_t gpu_addr; 1014 bool enabled; 1015 bool use_event; 1016 }; 1017 1018 #define RADEON_WB_SCRATCH_OFFSET 0 1019 #define RADEON_WB_RING0_NEXT_RPTR 256 1020 #define RADEON_WB_CP_RPTR_OFFSET 1024 1021 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1022 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1023 #define R600_WB_DMA_RPTR_OFFSET 1792 1024 #define R600_WB_IH_WPTR_OFFSET 2048 1025 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1026 #define R600_WB_UVD_RPTR_OFFSET 2560 1027 #define R600_WB_EVENT_OFFSET 3072 1028 #define CIK_WB_CP1_WPTR_OFFSET 3328 1029 #define CIK_WB_CP2_WPTR_OFFSET 3584 1030 1031 /** 1032 * struct radeon_pm - power management datas 1033 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1034 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1035 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1036 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1037 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1038 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1039 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1040 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1041 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1042 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1043 * @needed_bandwidth: current bandwidth needs 1044 * 1045 * It keeps track of various data needed to take powermanagement decision. 1046 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1047 * Equation between gpu/memory clock and available bandwidth is hw dependent 1048 * (type of memory, bus size, efficiency, ...) 1049 */ 1050 1051 enum radeon_pm_method { 1052 PM_METHOD_PROFILE, 1053 PM_METHOD_DYNPM, 1054 PM_METHOD_DPM, 1055 }; 1056 1057 enum radeon_dynpm_state { 1058 DYNPM_STATE_DISABLED, 1059 DYNPM_STATE_MINIMUM, 1060 DYNPM_STATE_PAUSED, 1061 DYNPM_STATE_ACTIVE, 1062 DYNPM_STATE_SUSPENDED, 1063 }; 1064 enum radeon_dynpm_action { 1065 DYNPM_ACTION_NONE, 1066 DYNPM_ACTION_MINIMUM, 1067 DYNPM_ACTION_DOWNCLOCK, 1068 DYNPM_ACTION_UPCLOCK, 1069 DYNPM_ACTION_DEFAULT 1070 }; 1071 1072 enum radeon_voltage_type { 1073 VOLTAGE_NONE = 0, 1074 VOLTAGE_GPIO, 1075 VOLTAGE_VDDC, 1076 VOLTAGE_SW 1077 }; 1078 1079 enum radeon_pm_state_type { 1080 /* not used for dpm */ 1081 POWER_STATE_TYPE_DEFAULT, 1082 POWER_STATE_TYPE_POWERSAVE, 1083 /* user selectable states */ 1084 POWER_STATE_TYPE_BATTERY, 1085 POWER_STATE_TYPE_BALANCED, 1086 POWER_STATE_TYPE_PERFORMANCE, 1087 /* internal states */ 1088 POWER_STATE_TYPE_INTERNAL_UVD, 1089 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1090 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1091 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1092 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1093 POWER_STATE_TYPE_INTERNAL_BOOT, 1094 POWER_STATE_TYPE_INTERNAL_THERMAL, 1095 POWER_STATE_TYPE_INTERNAL_ACPI, 1096 POWER_STATE_TYPE_INTERNAL_ULV, 1097 }; 1098 1099 enum radeon_pm_profile_type { 1100 PM_PROFILE_DEFAULT, 1101 PM_PROFILE_AUTO, 1102 PM_PROFILE_LOW, 1103 PM_PROFILE_MID, 1104 PM_PROFILE_HIGH, 1105 }; 1106 1107 #define PM_PROFILE_DEFAULT_IDX 0 1108 #define PM_PROFILE_LOW_SH_IDX 1 1109 #define PM_PROFILE_MID_SH_IDX 2 1110 #define PM_PROFILE_HIGH_SH_IDX 3 1111 #define PM_PROFILE_LOW_MH_IDX 4 1112 #define PM_PROFILE_MID_MH_IDX 5 1113 #define PM_PROFILE_HIGH_MH_IDX 6 1114 #define PM_PROFILE_MAX 7 1115 1116 struct radeon_pm_profile { 1117 int dpms_off_ps_idx; 1118 int dpms_on_ps_idx; 1119 int dpms_off_cm_idx; 1120 int dpms_on_cm_idx; 1121 }; 1122 1123 enum radeon_int_thermal_type { 1124 THERMAL_TYPE_NONE, 1125 THERMAL_TYPE_EXTERNAL, 1126 THERMAL_TYPE_EXTERNAL_GPIO, 1127 THERMAL_TYPE_RV6XX, 1128 THERMAL_TYPE_RV770, 1129 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1130 THERMAL_TYPE_EVERGREEN, 1131 THERMAL_TYPE_SUMO, 1132 THERMAL_TYPE_NI, 1133 THERMAL_TYPE_SI, 1134 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1135 THERMAL_TYPE_CI, 1136 }; 1137 1138 struct radeon_voltage { 1139 enum radeon_voltage_type type; 1140 /* gpio voltage */ 1141 struct radeon_gpio_rec gpio; 1142 u32 delay; /* delay in usec from voltage drop to sclk change */ 1143 bool active_high; /* voltage drop is active when bit is high */ 1144 /* VDDC voltage */ 1145 u8 vddc_id; /* index into vddc voltage table */ 1146 u8 vddci_id; /* index into vddci voltage table */ 1147 bool vddci_enabled; 1148 /* r6xx+ sw */ 1149 u16 voltage; 1150 /* evergreen+ vddci */ 1151 u16 vddci; 1152 }; 1153 1154 /* clock mode flags */ 1155 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1156 1157 struct radeon_pm_clock_info { 1158 /* memory clock */ 1159 u32 mclk; 1160 /* engine clock */ 1161 u32 sclk; 1162 /* voltage info */ 1163 struct radeon_voltage voltage; 1164 /* standardized clock flags */ 1165 u32 flags; 1166 }; 1167 1168 /* state flags */ 1169 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1170 1171 struct radeon_power_state { 1172 enum radeon_pm_state_type type; 1173 struct radeon_pm_clock_info *clock_info; 1174 /* number of valid clock modes in this power state */ 1175 int num_clock_modes; 1176 struct radeon_pm_clock_info *default_clock_mode; 1177 /* standardized state flags */ 1178 u32 flags; 1179 u32 misc; /* vbios specific flags */ 1180 u32 misc2; /* vbios specific flags */ 1181 int pcie_lanes; /* pcie lanes */ 1182 }; 1183 1184 /* 1185 * Some modes are overclocked by very low value, accept them 1186 */ 1187 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1188 1189 enum radeon_dpm_auto_throttle_src { 1190 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1191 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1192 }; 1193 1194 enum radeon_dpm_event_src { 1195 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1196 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1197 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1198 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1199 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1200 }; 1201 1202 struct radeon_ps { 1203 u32 caps; /* vbios flags */ 1204 u32 class; /* vbios flags */ 1205 u32 class2; /* vbios flags */ 1206 /* UVD clocks */ 1207 u32 vclk; 1208 u32 dclk; 1209 /* asic priv */ 1210 void *ps_priv; 1211 }; 1212 1213 struct radeon_dpm_thermal { 1214 /* thermal interrupt work */ 1215 struct work_struct work; 1216 /* low temperature threshold */ 1217 int min_temp; 1218 /* high temperature threshold */ 1219 int max_temp; 1220 /* was interrupt low to high or high to low */ 1221 bool high_to_low; 1222 }; 1223 1224 enum radeon_clk_action 1225 { 1226 RADEON_SCLK_UP = 1, 1227 RADEON_SCLK_DOWN 1228 }; 1229 1230 struct radeon_blacklist_clocks 1231 { 1232 u32 sclk; 1233 u32 mclk; 1234 enum radeon_clk_action action; 1235 }; 1236 1237 struct radeon_clock_and_voltage_limits { 1238 u32 sclk; 1239 u32 mclk; 1240 u32 vddc; 1241 u32 vddci; 1242 }; 1243 1244 struct radeon_clock_array { 1245 u32 count; 1246 u32 *values; 1247 }; 1248 1249 struct radeon_clock_voltage_dependency_entry { 1250 u32 clk; 1251 u16 v; 1252 }; 1253 1254 struct radeon_clock_voltage_dependency_table { 1255 u32 count; 1256 struct radeon_clock_voltage_dependency_entry *entries; 1257 }; 1258 1259 struct radeon_cac_leakage_entry { 1260 u16 vddc; 1261 u32 leakage; 1262 }; 1263 1264 struct radeon_cac_leakage_table { 1265 u32 count; 1266 struct radeon_cac_leakage_entry *entries; 1267 }; 1268 1269 struct radeon_dpm_dynamic_state { 1270 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1271 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1272 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1273 struct radeon_clock_array valid_sclk_values; 1274 struct radeon_clock_array valid_mclk_values; 1275 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1276 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1277 u32 mclk_sclk_ratio; 1278 u32 sclk_mclk_delta; 1279 u16 vddc_vddci_delta; 1280 u16 min_vddc_for_pcie_gen2; 1281 struct radeon_cac_leakage_table cac_leakage_table; 1282 }; 1283 1284 struct radeon_dpm_fan { 1285 u16 t_min; 1286 u16 t_med; 1287 u16 t_high; 1288 u16 pwm_min; 1289 u16 pwm_med; 1290 u16 pwm_high; 1291 u8 t_hyst; 1292 u32 cycle_delay; 1293 u16 t_max; 1294 bool ucode_fan_control; 1295 }; 1296 1297 struct radeon_dpm { 1298 struct radeon_ps *ps; 1299 /* number of valid power states */ 1300 int num_ps; 1301 /* current power state that is active */ 1302 struct radeon_ps *current_ps; 1303 /* requested power state */ 1304 struct radeon_ps *requested_ps; 1305 /* boot up power state */ 1306 struct radeon_ps *boot_ps; 1307 /* default uvd power state */ 1308 struct radeon_ps *uvd_ps; 1309 enum radeon_pm_state_type state; 1310 enum radeon_pm_state_type user_state; 1311 u32 platform_caps; 1312 u32 voltage_response_time; 1313 u32 backbias_response_time; 1314 void *priv; 1315 u32 new_active_crtcs; 1316 int new_active_crtc_count; 1317 u32 current_active_crtcs; 1318 int current_active_crtc_count; 1319 struct radeon_dpm_dynamic_state dyn_state; 1320 struct radeon_dpm_fan fan; 1321 u32 tdp_limit; 1322 u32 near_tdp_limit; 1323 u32 sq_ramping_threshold; 1324 u32 cac_leakage; 1325 u16 tdp_od_limit; 1326 u32 tdp_adjustment; 1327 u16 load_line_slope; 1328 bool power_control; 1329 bool ac_power; 1330 /* special states active */ 1331 bool thermal_active; 1332 bool uvd_active; 1333 /* thermal handling */ 1334 struct radeon_dpm_thermal thermal; 1335 }; 1336 1337 void radeon_dpm_enable_power_state(struct radeon_device *rdev, 1338 enum radeon_pm_state_type dpm_state); 1339 1340 1341 struct radeon_pm { 1342 struct mutex mutex; 1343 /* write locked while reprogramming mclk */ 1344 struct rw_semaphore mclk_lock; 1345 u32 active_crtcs; 1346 int active_crtc_count; 1347 int req_vblank; 1348 bool vblank_sync; 1349 fixed20_12 max_bandwidth; 1350 fixed20_12 igp_sideport_mclk; 1351 fixed20_12 igp_system_mclk; 1352 fixed20_12 igp_ht_link_clk; 1353 fixed20_12 igp_ht_link_width; 1354 fixed20_12 k8_bandwidth; 1355 fixed20_12 sideport_bandwidth; 1356 fixed20_12 ht_bandwidth; 1357 fixed20_12 core_bandwidth; 1358 fixed20_12 sclk; 1359 fixed20_12 mclk; 1360 fixed20_12 needed_bandwidth; 1361 struct radeon_power_state *power_state; 1362 /* number of valid power states */ 1363 int num_power_states; 1364 int current_power_state_index; 1365 int current_clock_mode_index; 1366 int requested_power_state_index; 1367 int requested_clock_mode_index; 1368 int default_power_state_index; 1369 u32 current_sclk; 1370 u32 current_mclk; 1371 u16 current_vddc; 1372 u16 current_vddci; 1373 u32 default_sclk; 1374 u32 default_mclk; 1375 u16 default_vddc; 1376 u16 default_vddci; 1377 struct radeon_i2c_chan *i2c_bus; 1378 /* selected pm method */ 1379 enum radeon_pm_method pm_method; 1380 /* dynpm power management */ 1381 struct delayed_work dynpm_idle_work; 1382 enum radeon_dynpm_state dynpm_state; 1383 enum radeon_dynpm_action dynpm_planned_action; 1384 unsigned long dynpm_action_timeout; 1385 bool dynpm_can_upclock; 1386 bool dynpm_can_downclock; 1387 /* profile-based power management */ 1388 enum radeon_pm_profile_type profile; 1389 int profile_index; 1390 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1391 /* internal thermal controller on rv6xx+ */ 1392 enum radeon_int_thermal_type int_thermal_type; 1393 struct device *int_hwmon_dev; 1394 /* dpm */ 1395 bool dpm_enabled; 1396 struct radeon_dpm dpm; 1397 }; 1398 1399 int radeon_pm_get_type_index(struct radeon_device *rdev, 1400 enum radeon_pm_state_type ps_type, 1401 int instance); 1402 /* 1403 * UVD 1404 */ 1405 #define RADEON_MAX_UVD_HANDLES 10 1406 #define RADEON_UVD_STACK_SIZE (1024*1024) 1407 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1408 1409 struct radeon_uvd { 1410 struct radeon_bo *vcpu_bo; 1411 void *cpu_addr; 1412 uint64_t gpu_addr; 1413 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1414 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1415 struct delayed_work idle_work; 1416 }; 1417 1418 int radeon_uvd_init(struct radeon_device *rdev); 1419 void radeon_uvd_fini(struct radeon_device *rdev); 1420 int radeon_uvd_suspend(struct radeon_device *rdev); 1421 int radeon_uvd_resume(struct radeon_device *rdev); 1422 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1423 uint32_t handle, struct radeon_fence **fence); 1424 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1425 uint32_t handle, struct radeon_fence **fence); 1426 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); 1427 void radeon_uvd_free_handles(struct radeon_device *rdev, 1428 struct drm_file *filp); 1429 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1430 void radeon_uvd_note_usage(struct radeon_device *rdev); 1431 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1432 unsigned vclk, unsigned dclk, 1433 unsigned vco_min, unsigned vco_max, 1434 unsigned fb_factor, unsigned fb_mask, 1435 unsigned pd_min, unsigned pd_max, 1436 unsigned pd_even, 1437 unsigned *optimal_fb_div, 1438 unsigned *optimal_vclk_div, 1439 unsigned *optimal_dclk_div); 1440 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1441 unsigned cg_upll_func_cntl); 1442 1443 struct r600_audio { 1444 int channels; 1445 int rate; 1446 int bits_per_sample; 1447 u8 status_bits; 1448 u8 category_code; 1449 }; 1450 1451 /* 1452 * Benchmarking 1453 */ 1454 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1455 1456 1457 /* 1458 * Testing 1459 */ 1460 void radeon_test_moves(struct radeon_device *rdev); 1461 void radeon_test_ring_sync(struct radeon_device *rdev, 1462 struct radeon_ring *cpA, 1463 struct radeon_ring *cpB); 1464 void radeon_test_syncing(struct radeon_device *rdev); 1465 1466 1467 /* 1468 * Debugfs 1469 */ 1470 struct radeon_debugfs { 1471 struct drm_info_list *files; 1472 unsigned num_files; 1473 }; 1474 1475 int radeon_debugfs_add_files(struct radeon_device *rdev, 1476 struct drm_info_list *files, 1477 unsigned nfiles); 1478 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1479 1480 1481 /* 1482 * ASIC specific functions. 1483 */ 1484 struct radeon_asic { 1485 int (*init)(struct radeon_device *rdev); 1486 void (*fini)(struct radeon_device *rdev); 1487 int (*resume)(struct radeon_device *rdev); 1488 int (*suspend)(struct radeon_device *rdev); 1489 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1490 int (*asic_reset)(struct radeon_device *rdev); 1491 /* ioctl hw specific callback. Some hw might want to perform special 1492 * operation on specific ioctl. For instance on wait idle some hw 1493 * might want to perform and HDP flush through MMIO as it seems that 1494 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1495 * through ring. 1496 */ 1497 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1498 /* check if 3D engine is idle */ 1499 bool (*gui_idle)(struct radeon_device *rdev); 1500 /* wait for mc_idle */ 1501 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1502 /* get the reference clock */ 1503 u32 (*get_xclk)(struct radeon_device *rdev); 1504 /* get the gpu clock counter */ 1505 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1506 /* gart */ 1507 struct { 1508 void (*tlb_flush)(struct radeon_device *rdev); 1509 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1510 } gart; 1511 struct { 1512 int (*init)(struct radeon_device *rdev); 1513 void (*fini)(struct radeon_device *rdev); 1514 1515 u32 pt_ring_index; 1516 void (*set_page)(struct radeon_device *rdev, 1517 struct radeon_ib *ib, 1518 uint64_t pe, 1519 uint64_t addr, unsigned count, 1520 uint32_t incr, uint32_t flags); 1521 } vm; 1522 /* ring specific callbacks */ 1523 struct { 1524 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1525 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1526 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1527 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1528 struct radeon_semaphore *semaphore, bool emit_wait); 1529 int (*cs_parse)(struct radeon_cs_parser *p); 1530 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1531 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1532 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1533 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1534 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1535 1536 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1537 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1538 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1539 } ring[RADEON_NUM_RINGS]; 1540 /* irqs */ 1541 struct { 1542 int (*set)(struct radeon_device *rdev); 1543 int (*process)(struct radeon_device *rdev); 1544 } irq; 1545 /* displays */ 1546 struct { 1547 /* display watermarks */ 1548 void (*bandwidth_update)(struct radeon_device *rdev); 1549 /* get frame count */ 1550 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1551 /* wait for vblank */ 1552 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1553 /* set backlight level */ 1554 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1555 /* get backlight level */ 1556 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1557 /* audio callbacks */ 1558 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1559 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1560 } display; 1561 /* copy functions for bo handling */ 1562 struct { 1563 int (*blit)(struct radeon_device *rdev, 1564 uint64_t src_offset, 1565 uint64_t dst_offset, 1566 unsigned num_gpu_pages, 1567 struct radeon_fence **fence); 1568 u32 blit_ring_index; 1569 int (*dma)(struct radeon_device *rdev, 1570 uint64_t src_offset, 1571 uint64_t dst_offset, 1572 unsigned num_gpu_pages, 1573 struct radeon_fence **fence); 1574 u32 dma_ring_index; 1575 /* method used for bo copy */ 1576 int (*copy)(struct radeon_device *rdev, 1577 uint64_t src_offset, 1578 uint64_t dst_offset, 1579 unsigned num_gpu_pages, 1580 struct radeon_fence **fence); 1581 /* ring used for bo copies */ 1582 u32 copy_ring_index; 1583 } copy; 1584 /* surfaces */ 1585 struct { 1586 int (*set_reg)(struct radeon_device *rdev, int reg, 1587 uint32_t tiling_flags, uint32_t pitch, 1588 uint32_t offset, uint32_t obj_size); 1589 void (*clear_reg)(struct radeon_device *rdev, int reg); 1590 } surface; 1591 /* hotplug detect */ 1592 struct { 1593 void (*init)(struct radeon_device *rdev); 1594 void (*fini)(struct radeon_device *rdev); 1595 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1596 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1597 } hpd; 1598 /* static power management */ 1599 struct { 1600 void (*misc)(struct radeon_device *rdev); 1601 void (*prepare)(struct radeon_device *rdev); 1602 void (*finish)(struct radeon_device *rdev); 1603 void (*init_profile)(struct radeon_device *rdev); 1604 void (*get_dynpm_state)(struct radeon_device *rdev); 1605 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1606 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1607 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1608 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1609 int (*get_pcie_lanes)(struct radeon_device *rdev); 1610 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1611 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1612 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1613 int (*get_temperature)(struct radeon_device *rdev); 1614 } pm; 1615 /* dynamic power management */ 1616 struct { 1617 int (*init)(struct radeon_device *rdev); 1618 void (*setup_asic)(struct radeon_device *rdev); 1619 int (*enable)(struct radeon_device *rdev); 1620 void (*disable)(struct radeon_device *rdev); 1621 int (*pre_set_power_state)(struct radeon_device *rdev); 1622 int (*set_power_state)(struct radeon_device *rdev); 1623 void (*post_set_power_state)(struct radeon_device *rdev); 1624 void (*display_configuration_changed)(struct radeon_device *rdev); 1625 void (*fini)(struct radeon_device *rdev); 1626 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1627 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1628 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1629 } dpm; 1630 /* pageflipping */ 1631 struct { 1632 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1633 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1634 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1635 } pflip; 1636 }; 1637 1638 /* 1639 * Asic structures 1640 */ 1641 struct r100_asic { 1642 const unsigned *reg_safe_bm; 1643 unsigned reg_safe_bm_size; 1644 u32 hdp_cntl; 1645 }; 1646 1647 struct r300_asic { 1648 const unsigned *reg_safe_bm; 1649 unsigned reg_safe_bm_size; 1650 u32 resync_scratch; 1651 u32 hdp_cntl; 1652 }; 1653 1654 struct r600_asic { 1655 unsigned max_pipes; 1656 unsigned max_tile_pipes; 1657 unsigned max_simds; 1658 unsigned max_backends; 1659 unsigned max_gprs; 1660 unsigned max_threads; 1661 unsigned max_stack_entries; 1662 unsigned max_hw_contexts; 1663 unsigned max_gs_threads; 1664 unsigned sx_max_export_size; 1665 unsigned sx_max_export_pos_size; 1666 unsigned sx_max_export_smx_size; 1667 unsigned sq_num_cf_insts; 1668 unsigned tiling_nbanks; 1669 unsigned tiling_npipes; 1670 unsigned tiling_group_size; 1671 unsigned tile_config; 1672 unsigned backend_map; 1673 }; 1674 1675 struct rv770_asic { 1676 unsigned max_pipes; 1677 unsigned max_tile_pipes; 1678 unsigned max_simds; 1679 unsigned max_backends; 1680 unsigned max_gprs; 1681 unsigned max_threads; 1682 unsigned max_stack_entries; 1683 unsigned max_hw_contexts; 1684 unsigned max_gs_threads; 1685 unsigned sx_max_export_size; 1686 unsigned sx_max_export_pos_size; 1687 unsigned sx_max_export_smx_size; 1688 unsigned sq_num_cf_insts; 1689 unsigned sx_num_of_sets; 1690 unsigned sc_prim_fifo_size; 1691 unsigned sc_hiz_tile_fifo_size; 1692 unsigned sc_earlyz_tile_fifo_fize; 1693 unsigned tiling_nbanks; 1694 unsigned tiling_npipes; 1695 unsigned tiling_group_size; 1696 unsigned tile_config; 1697 unsigned backend_map; 1698 }; 1699 1700 struct evergreen_asic { 1701 unsigned num_ses; 1702 unsigned max_pipes; 1703 unsigned max_tile_pipes; 1704 unsigned max_simds; 1705 unsigned max_backends; 1706 unsigned max_gprs; 1707 unsigned max_threads; 1708 unsigned max_stack_entries; 1709 unsigned max_hw_contexts; 1710 unsigned max_gs_threads; 1711 unsigned sx_max_export_size; 1712 unsigned sx_max_export_pos_size; 1713 unsigned sx_max_export_smx_size; 1714 unsigned sq_num_cf_insts; 1715 unsigned sx_num_of_sets; 1716 unsigned sc_prim_fifo_size; 1717 unsigned sc_hiz_tile_fifo_size; 1718 unsigned sc_earlyz_tile_fifo_size; 1719 unsigned tiling_nbanks; 1720 unsigned tiling_npipes; 1721 unsigned tiling_group_size; 1722 unsigned tile_config; 1723 unsigned backend_map; 1724 }; 1725 1726 struct cayman_asic { 1727 unsigned max_shader_engines; 1728 unsigned max_pipes_per_simd; 1729 unsigned max_tile_pipes; 1730 unsigned max_simds_per_se; 1731 unsigned max_backends_per_se; 1732 unsigned max_texture_channel_caches; 1733 unsigned max_gprs; 1734 unsigned max_threads; 1735 unsigned max_gs_threads; 1736 unsigned max_stack_entries; 1737 unsigned sx_num_of_sets; 1738 unsigned sx_max_export_size; 1739 unsigned sx_max_export_pos_size; 1740 unsigned sx_max_export_smx_size; 1741 unsigned max_hw_contexts; 1742 unsigned sq_num_cf_insts; 1743 unsigned sc_prim_fifo_size; 1744 unsigned sc_hiz_tile_fifo_size; 1745 unsigned sc_earlyz_tile_fifo_size; 1746 1747 unsigned num_shader_engines; 1748 unsigned num_shader_pipes_per_simd; 1749 unsigned num_tile_pipes; 1750 unsigned num_simds_per_se; 1751 unsigned num_backends_per_se; 1752 unsigned backend_disable_mask_per_asic; 1753 unsigned backend_map; 1754 unsigned num_texture_channel_caches; 1755 unsigned mem_max_burst_length_bytes; 1756 unsigned mem_row_size_in_kb; 1757 unsigned shader_engine_tile_size; 1758 unsigned num_gpus; 1759 unsigned multi_gpu_tile_size; 1760 1761 unsigned tile_config; 1762 }; 1763 1764 struct si_asic { 1765 unsigned max_shader_engines; 1766 unsigned max_tile_pipes; 1767 unsigned max_cu_per_sh; 1768 unsigned max_sh_per_se; 1769 unsigned max_backends_per_se; 1770 unsigned max_texture_channel_caches; 1771 unsigned max_gprs; 1772 unsigned max_gs_threads; 1773 unsigned max_hw_contexts; 1774 unsigned sc_prim_fifo_size_frontend; 1775 unsigned sc_prim_fifo_size_backend; 1776 unsigned sc_hiz_tile_fifo_size; 1777 unsigned sc_earlyz_tile_fifo_size; 1778 1779 unsigned num_tile_pipes; 1780 unsigned num_backends_per_se; 1781 unsigned backend_disable_mask_per_asic; 1782 unsigned backend_map; 1783 unsigned num_texture_channel_caches; 1784 unsigned mem_max_burst_length_bytes; 1785 unsigned mem_row_size_in_kb; 1786 unsigned shader_engine_tile_size; 1787 unsigned num_gpus; 1788 unsigned multi_gpu_tile_size; 1789 1790 unsigned tile_config; 1791 uint32_t tile_mode_array[32]; 1792 }; 1793 1794 struct cik_asic { 1795 unsigned max_shader_engines; 1796 unsigned max_tile_pipes; 1797 unsigned max_cu_per_sh; 1798 unsigned max_sh_per_se; 1799 unsigned max_backends_per_se; 1800 unsigned max_texture_channel_caches; 1801 unsigned max_gprs; 1802 unsigned max_gs_threads; 1803 unsigned max_hw_contexts; 1804 unsigned sc_prim_fifo_size_frontend; 1805 unsigned sc_prim_fifo_size_backend; 1806 unsigned sc_hiz_tile_fifo_size; 1807 unsigned sc_earlyz_tile_fifo_size; 1808 1809 unsigned num_tile_pipes; 1810 unsigned num_backends_per_se; 1811 unsigned backend_disable_mask_per_asic; 1812 unsigned backend_map; 1813 unsigned num_texture_channel_caches; 1814 unsigned mem_max_burst_length_bytes; 1815 unsigned mem_row_size_in_kb; 1816 unsigned shader_engine_tile_size; 1817 unsigned num_gpus; 1818 unsigned multi_gpu_tile_size; 1819 1820 unsigned tile_config; 1821 uint32_t tile_mode_array[32]; 1822 }; 1823 1824 union radeon_asic_config { 1825 struct r300_asic r300; 1826 struct r100_asic r100; 1827 struct r600_asic r600; 1828 struct rv770_asic rv770; 1829 struct evergreen_asic evergreen; 1830 struct cayman_asic cayman; 1831 struct si_asic si; 1832 struct cik_asic cik; 1833 }; 1834 1835 /* 1836 * asic initizalization from radeon_asic.c 1837 */ 1838 void radeon_agp_disable(struct radeon_device *rdev); 1839 int radeon_asic_init(struct radeon_device *rdev); 1840 1841 1842 /* 1843 * IOCTL. 1844 */ 1845 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1846 struct drm_file *filp); 1847 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1848 struct drm_file *filp); 1849 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1850 struct drm_file *file_priv); 1851 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1852 struct drm_file *file_priv); 1853 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1854 struct drm_file *file_priv); 1855 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1856 struct drm_file *file_priv); 1857 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1858 struct drm_file *filp); 1859 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1860 struct drm_file *filp); 1861 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1862 struct drm_file *filp); 1863 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1864 struct drm_file *filp); 1865 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1866 struct drm_file *filp); 1867 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1868 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1869 struct drm_file *filp); 1870 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1871 struct drm_file *filp); 1872 1873 /* VRAM scratch page for HDP bug, default vram page */ 1874 struct r600_vram_scratch { 1875 struct radeon_bo *robj; 1876 volatile uint32_t *ptr; 1877 u64 gpu_addr; 1878 }; 1879 1880 /* 1881 * ACPI 1882 */ 1883 struct radeon_atif_notification_cfg { 1884 bool enabled; 1885 int command_code; 1886 }; 1887 1888 struct radeon_atif_notifications { 1889 bool display_switch; 1890 bool expansion_mode_change; 1891 bool thermal_state; 1892 bool forced_power_state; 1893 bool system_power_state; 1894 bool display_conf_change; 1895 bool px_gfx_switch; 1896 bool brightness_change; 1897 bool dgpu_display_event; 1898 }; 1899 1900 struct radeon_atif_functions { 1901 bool system_params; 1902 bool sbios_requests; 1903 bool select_active_disp; 1904 bool lid_state; 1905 bool get_tv_standard; 1906 bool set_tv_standard; 1907 bool get_panel_expansion_mode; 1908 bool set_panel_expansion_mode; 1909 bool temperature_change; 1910 bool graphics_device_types; 1911 }; 1912 1913 struct radeon_atif { 1914 struct radeon_atif_notifications notifications; 1915 struct radeon_atif_functions functions; 1916 struct radeon_atif_notification_cfg notification_cfg; 1917 struct radeon_encoder *encoder_for_bl; 1918 }; 1919 1920 struct radeon_atcs_functions { 1921 bool get_ext_state; 1922 bool pcie_perf_req; 1923 bool pcie_dev_rdy; 1924 bool pcie_bus_width; 1925 }; 1926 1927 struct radeon_atcs { 1928 struct radeon_atcs_functions functions; 1929 }; 1930 1931 /* 1932 * Core structure, functions and helpers. 1933 */ 1934 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1935 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1936 1937 struct radeon_device { 1938 struct device *dev; 1939 struct drm_device *ddev; 1940 struct pci_dev *pdev; 1941 struct rw_semaphore exclusive_lock; 1942 /* ASIC */ 1943 union radeon_asic_config config; 1944 enum radeon_family family; 1945 unsigned long flags; 1946 int usec_timeout; 1947 enum radeon_pll_errata pll_errata; 1948 int num_gb_pipes; 1949 int num_z_pipes; 1950 int disp_priority; 1951 /* BIOS */ 1952 uint8_t *bios; 1953 bool is_atom_bios; 1954 uint16_t bios_header_start; 1955 struct radeon_bo *stollen_vga_memory; 1956 /* Register mmio */ 1957 resource_size_t rmmio_base; 1958 resource_size_t rmmio_size; 1959 /* protects concurrent MM_INDEX/DATA based register access */ 1960 spinlock_t mmio_idx_lock; 1961 void __iomem *rmmio; 1962 radeon_rreg_t mc_rreg; 1963 radeon_wreg_t mc_wreg; 1964 radeon_rreg_t pll_rreg; 1965 radeon_wreg_t pll_wreg; 1966 uint32_t pcie_reg_mask; 1967 radeon_rreg_t pciep_rreg; 1968 radeon_wreg_t pciep_wreg; 1969 /* io port */ 1970 void __iomem *rio_mem; 1971 resource_size_t rio_mem_size; 1972 struct radeon_clock clock; 1973 struct radeon_mc mc; 1974 struct radeon_gart gart; 1975 struct radeon_mode_info mode_info; 1976 struct radeon_scratch scratch; 1977 struct radeon_doorbell doorbell; 1978 struct radeon_mman mman; 1979 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 1980 wait_queue_head_t fence_queue; 1981 struct mutex ring_lock; 1982 struct radeon_ring ring[RADEON_NUM_RINGS]; 1983 bool ib_pool_ready; 1984 struct radeon_sa_manager ring_tmp_bo; 1985 struct radeon_irq irq; 1986 struct radeon_asic *asic; 1987 struct radeon_gem gem; 1988 struct radeon_pm pm; 1989 struct radeon_uvd uvd; 1990 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1991 struct radeon_wb wb; 1992 struct radeon_dummy_page dummy_page; 1993 bool shutdown; 1994 bool suspend; 1995 bool need_dma32; 1996 bool accel_working; 1997 bool fastfb_working; /* IGP feature*/ 1998 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1999 const struct firmware *me_fw; /* all family ME firmware */ 2000 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2001 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2002 const struct firmware *mc_fw; /* NI MC firmware */ 2003 const struct firmware *ce_fw; /* SI CE firmware */ 2004 const struct firmware *uvd_fw; /* UVD firmware */ 2005 const struct firmware *mec_fw; /* CIK MEC firmware */ 2006 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2007 const struct firmware *smc_fw; /* SMC firmware */ 2008 struct r600_blit r600_blit; 2009 struct r600_vram_scratch vram_scratch; 2010 int msi_enabled; /* msi enabled */ 2011 struct r600_ih ih; /* r6/700 interrupt ring */ 2012 struct radeon_rlc rlc; 2013 struct radeon_mec mec; 2014 struct work_struct hotplug_work; 2015 struct work_struct audio_work; 2016 struct work_struct reset_work; 2017 int num_crtc; /* number of crtcs */ 2018 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2019 bool audio_enabled; 2020 bool has_uvd; 2021 struct r600_audio audio_status; /* audio stuff */ 2022 struct notifier_block acpi_nb; 2023 /* only one userspace can use Hyperz features or CMASK at a time */ 2024 struct drm_file *hyperz_filp; 2025 struct drm_file *cmask_filp; 2026 /* i2c buses */ 2027 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2028 /* debugfs */ 2029 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2030 unsigned debugfs_count; 2031 /* virtual memory */ 2032 struct radeon_vm_manager vm_manager; 2033 struct mutex gpu_clock_mutex; 2034 /* ACPI interface */ 2035 struct radeon_atif atif; 2036 struct radeon_atcs atcs; 2037 }; 2038 2039 int radeon_device_init(struct radeon_device *rdev, 2040 struct drm_device *ddev, 2041 struct pci_dev *pdev, 2042 uint32_t flags); 2043 void radeon_device_fini(struct radeon_device *rdev); 2044 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2045 2046 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2047 bool always_indirect); 2048 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2049 bool always_indirect); 2050 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2051 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2052 2053 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset); 2054 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v); 2055 2056 /* 2057 * Cast helper 2058 */ 2059 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 2060 2061 /* 2062 * Registers read & write functions. 2063 */ 2064 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2065 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2066 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2067 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2068 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2069 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2070 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2071 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2072 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2073 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2074 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2075 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2076 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2077 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2078 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2079 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2080 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2081 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2082 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2083 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2084 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2085 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2086 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2087 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2088 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2089 #define WREG32_P(reg, val, mask) \ 2090 do { \ 2091 uint32_t tmp_ = RREG32(reg); \ 2092 tmp_ &= (mask); \ 2093 tmp_ |= ((val) & ~(mask)); \ 2094 WREG32(reg, tmp_); \ 2095 } while (0) 2096 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2097 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~or) 2098 #define WREG32_PLL_P(reg, val, mask) \ 2099 do { \ 2100 uint32_t tmp_ = RREG32_PLL(reg); \ 2101 tmp_ &= (mask); \ 2102 tmp_ |= ((val) & ~(mask)); \ 2103 WREG32_PLL(reg, tmp_); \ 2104 } while (0) 2105 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2106 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2107 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2108 2109 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset)) 2110 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v)) 2111 2112 /* 2113 * Indirect registers accessor 2114 */ 2115 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2116 { 2117 uint32_t r; 2118 2119 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2120 r = RREG32(RADEON_PCIE_DATA); 2121 return r; 2122 } 2123 2124 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2125 { 2126 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2127 WREG32(RADEON_PCIE_DATA, (v)); 2128 } 2129 2130 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2131 { 2132 u32 r; 2133 2134 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2135 r = RREG32(TN_SMC_IND_DATA_0); 2136 return r; 2137 } 2138 2139 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2140 { 2141 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2142 WREG32(TN_SMC_IND_DATA_0, (v)); 2143 } 2144 2145 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2146 { 2147 u32 r; 2148 2149 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2150 r = RREG32(R600_RCU_DATA); 2151 return r; 2152 } 2153 2154 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2155 { 2156 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2157 WREG32(R600_RCU_DATA, (v)); 2158 } 2159 2160 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2161 { 2162 u32 r; 2163 2164 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2165 r = RREG32(EVERGREEN_CG_IND_DATA); 2166 return r; 2167 } 2168 2169 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2170 { 2171 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2172 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2173 } 2174 2175 void r100_pll_errata_after_index(struct radeon_device *rdev); 2176 2177 2178 /* 2179 * ASICs helpers. 2180 */ 2181 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2182 (rdev->pdev->device == 0x5969)) 2183 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2184 (rdev->family == CHIP_RV200) || \ 2185 (rdev->family == CHIP_RS100) || \ 2186 (rdev->family == CHIP_RS200) || \ 2187 (rdev->family == CHIP_RV250) || \ 2188 (rdev->family == CHIP_RV280) || \ 2189 (rdev->family == CHIP_RS300)) 2190 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2191 (rdev->family == CHIP_RV350) || \ 2192 (rdev->family == CHIP_R350) || \ 2193 (rdev->family == CHIP_RV380) || \ 2194 (rdev->family == CHIP_R420) || \ 2195 (rdev->family == CHIP_R423) || \ 2196 (rdev->family == CHIP_RV410) || \ 2197 (rdev->family == CHIP_RS400) || \ 2198 (rdev->family == CHIP_RS480)) 2199 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2200 (rdev->ddev->pdev->device == 0x9443) || \ 2201 (rdev->ddev->pdev->device == 0x944B) || \ 2202 (rdev->ddev->pdev->device == 0x9506) || \ 2203 (rdev->ddev->pdev->device == 0x9509) || \ 2204 (rdev->ddev->pdev->device == 0x950F) || \ 2205 (rdev->ddev->pdev->device == 0x689C) || \ 2206 (rdev->ddev->pdev->device == 0x689D)) 2207 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2208 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2209 (rdev->family == CHIP_RS690) || \ 2210 (rdev->family == CHIP_RS740) || \ 2211 (rdev->family >= CHIP_R600)) 2212 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2213 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2214 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2215 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2216 (rdev->flags & RADEON_IS_IGP)) 2217 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2218 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2219 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2220 (rdev->flags & RADEON_IS_IGP)) 2221 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2222 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2223 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2224 2225 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2226 (rdev->ddev->pdev->device == 0x6850) || \ 2227 (rdev->ddev->pdev->device == 0x6858) || \ 2228 (rdev->ddev->pdev->device == 0x6859) || \ 2229 (rdev->ddev->pdev->device == 0x6840) || \ 2230 (rdev->ddev->pdev->device == 0x6841) || \ 2231 (rdev->ddev->pdev->device == 0x6842) || \ 2232 (rdev->ddev->pdev->device == 0x6843)) 2233 2234 /* 2235 * BIOS helpers. 2236 */ 2237 #define RBIOS8(i) (rdev->bios[i]) 2238 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2239 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2240 2241 int radeon_combios_init(struct radeon_device *rdev); 2242 void radeon_combios_fini(struct radeon_device *rdev); 2243 int radeon_atombios_init(struct radeon_device *rdev); 2244 void radeon_atombios_fini(struct radeon_device *rdev); 2245 2246 2247 /* 2248 * RING helpers. 2249 */ 2250 #if DRM_DEBUG_CODE == 0 2251 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2252 { 2253 ring->ring[ring->wptr++] = v; 2254 ring->wptr &= ring->ptr_mask; 2255 ring->count_dw--; 2256 ring->ring_free_dw--; 2257 } 2258 #else 2259 /* With debugging this is just too big to inline */ 2260 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 2261 #endif 2262 2263 /* 2264 * ASICs macro. 2265 */ 2266 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2267 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2268 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2269 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2270 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 2271 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2272 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2273 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2274 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 2275 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2276 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2277 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2278 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 2279 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 2280 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 2281 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 2282 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 2283 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 2284 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 2285 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r)) 2286 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r)) 2287 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r)) 2288 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2289 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2290 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2291 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2292 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2293 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2294 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2295 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 2296 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2297 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2298 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2299 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2300 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2301 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2302 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2303 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2304 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2305 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2306 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2307 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2308 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2309 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2310 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2311 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2312 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2313 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2314 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2315 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2316 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2317 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2318 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2319 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2320 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2321 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2322 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2323 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2324 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2325 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 2326 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2327 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 2328 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2329 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2330 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2331 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2332 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2333 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2334 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2335 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2336 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2337 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2338 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2339 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2340 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2341 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2342 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2343 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2344 2345 /* Common functions */ 2346 /* AGP */ 2347 extern int radeon_gpu_reset(struct radeon_device *rdev); 2348 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2349 extern void radeon_agp_disable(struct radeon_device *rdev); 2350 extern int radeon_modeset_init(struct radeon_device *rdev); 2351 extern void radeon_modeset_fini(struct radeon_device *rdev); 2352 extern bool radeon_card_posted(struct radeon_device *rdev); 2353 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2354 extern void radeon_update_display_priority(struct radeon_device *rdev); 2355 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2356 extern void radeon_scratch_init(struct radeon_device *rdev); 2357 extern void radeon_wb_fini(struct radeon_device *rdev); 2358 extern int radeon_wb_init(struct radeon_device *rdev); 2359 extern void radeon_wb_disable(struct radeon_device *rdev); 2360 extern void radeon_surface_init(struct radeon_device *rdev); 2361 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2362 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2363 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2364 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2365 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2366 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2367 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2368 extern int radeon_resume_kms(struct drm_device *dev); 2369 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 2370 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2371 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2372 const u32 *registers, 2373 const u32 array_size); 2374 2375 /* 2376 * vm 2377 */ 2378 int radeon_vm_manager_init(struct radeon_device *rdev); 2379 void radeon_vm_manager_fini(struct radeon_device *rdev); 2380 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2381 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2382 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 2383 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); 2384 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2385 struct radeon_vm *vm, int ring); 2386 void radeon_vm_fence(struct radeon_device *rdev, 2387 struct radeon_vm *vm, 2388 struct radeon_fence *fence); 2389 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2390 int radeon_vm_bo_update_pte(struct radeon_device *rdev, 2391 struct radeon_vm *vm, 2392 struct radeon_bo *bo, 2393 struct ttm_mem_reg *mem); 2394 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2395 struct radeon_bo *bo); 2396 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2397 struct radeon_bo *bo); 2398 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2399 struct radeon_vm *vm, 2400 struct radeon_bo *bo); 2401 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2402 struct radeon_bo_va *bo_va, 2403 uint64_t offset, 2404 uint32_t flags); 2405 int radeon_vm_bo_rmv(struct radeon_device *rdev, 2406 struct radeon_bo_va *bo_va); 2407 2408 /* audio */ 2409 void r600_audio_update_hdmi(struct work_struct *work); 2410 2411 /* 2412 * R600 vram scratch functions 2413 */ 2414 int r600_vram_scratch_init(struct radeon_device *rdev); 2415 void r600_vram_scratch_fini(struct radeon_device *rdev); 2416 2417 /* 2418 * r600 cs checking helper 2419 */ 2420 unsigned r600_mip_minify(unsigned size, unsigned level); 2421 bool r600_fmt_is_valid_color(u32 format); 2422 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2423 int r600_fmt_get_blocksize(u32 format); 2424 int r600_fmt_get_nblocksx(u32 format, u32 w); 2425 int r600_fmt_get_nblocksy(u32 format, u32 h); 2426 2427 /* 2428 * r600 functions used by radeon_encoder.c 2429 */ 2430 struct radeon_hdmi_acr { 2431 u32 clock; 2432 2433 int n_32khz; 2434 int cts_32khz; 2435 2436 int n_44_1khz; 2437 int cts_44_1khz; 2438 2439 int n_48khz; 2440 int cts_48khz; 2441 2442 }; 2443 2444 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2445 2446 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2447 u32 tiling_pipe_num, 2448 u32 max_rb_num, 2449 u32 total_max_rb_num, 2450 u32 enabled_rb_mask); 2451 2452 /* 2453 * evergreen functions used by radeon_encoder.c 2454 */ 2455 2456 extern int ni_init_microcode(struct radeon_device *rdev); 2457 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2458 2459 /* radeon_acpi.c */ 2460 #if defined(CONFIG_ACPI) 2461 extern int radeon_acpi_init(struct radeon_device *rdev); 2462 extern void radeon_acpi_fini(struct radeon_device *rdev); 2463 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2464 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2465 u8 perf_req, bool advertise); 2466 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2467 #else 2468 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2469 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2470 #endif 2471 2472 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2473 struct radeon_cs_packet *pkt, 2474 unsigned idx); 2475 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2476 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2477 struct radeon_cs_packet *pkt); 2478 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2479 struct radeon_cs_reloc **cs_reloc, 2480 int nomm); 2481 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2482 uint32_t *vline_start_end, 2483 uint32_t *vline_status); 2484 2485 #include "radeon_object.h" 2486 2487 #endif 2488