1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 #include <linux/interval_tree.h> 68 #include <linux/hashtable.h> 69 #include <linux/fence.h> 70 71 #include <ttm/ttm_bo_api.h> 72 #include <ttm/ttm_bo_driver.h> 73 #include <ttm/ttm_placement.h> 74 #include <ttm/ttm_module.h> 75 #include <ttm/ttm_execbuf_util.h> 76 77 #include "radeon_family.h" 78 #include "radeon_mode.h" 79 #include "radeon_reg.h" 80 81 /* 82 * Modules parameters. 83 */ 84 extern int radeon_no_wb; 85 extern int radeon_modeset; 86 extern int radeon_dynclks; 87 extern int radeon_r4xx_atom; 88 extern int radeon_agpmode; 89 extern int radeon_vram_limit; 90 extern int radeon_gart_size; 91 extern int radeon_benchmarking; 92 extern int radeon_testing; 93 extern int radeon_connector_table; 94 extern int radeon_tv; 95 extern int radeon_audio; 96 extern int radeon_disp_priority; 97 extern int radeon_hw_i2c; 98 extern int radeon_pcie_gen2; 99 extern int radeon_msi; 100 extern int radeon_lockup_timeout; 101 extern int radeon_fastfb; 102 extern int radeon_dpm; 103 extern int radeon_aspm; 104 extern int radeon_runtime_pm; 105 extern int radeon_hard_reset; 106 extern int radeon_vm_size; 107 extern int radeon_vm_block_size; 108 extern int radeon_deep_color; 109 extern int radeon_use_pflipirq; 110 extern int radeon_bapm; 111 112 /* 113 * Copy from radeon_drv.h so we don't have to include both and have conflicting 114 * symbol; 115 */ 116 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 117 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 118 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 119 #define RADEON_IB_POOL_SIZE 16 120 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 121 #define RADEONFB_CONN_LIMIT 4 122 #define RADEON_BIOS_NUM_SCRATCH 8 123 124 /* internal ring indices */ 125 /* r1xx+ has gfx CP ring */ 126 #define RADEON_RING_TYPE_GFX_INDEX 0 127 128 /* cayman has 2 compute CP rings */ 129 #define CAYMAN_RING_TYPE_CP1_INDEX 1 130 #define CAYMAN_RING_TYPE_CP2_INDEX 2 131 132 /* R600+ has an async dma ring */ 133 #define R600_RING_TYPE_DMA_INDEX 3 134 /* cayman add a second async dma ring */ 135 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 136 137 /* R600+ */ 138 #define R600_RING_TYPE_UVD_INDEX 5 139 140 /* TN+ */ 141 #define TN_RING_TYPE_VCE1_INDEX 6 142 #define TN_RING_TYPE_VCE2_INDEX 7 143 144 /* max number of rings */ 145 #define RADEON_NUM_RINGS 8 146 147 /* number of hw syncs before falling back on blocking */ 148 #define RADEON_NUM_SYNCS 4 149 150 /* number of hw syncs before falling back on blocking */ 151 #define RADEON_NUM_SYNCS 4 152 153 /* hardcode those limit for now */ 154 #define RADEON_VA_IB_OFFSET (1 << 20) 155 #define RADEON_VA_RESERVED_SIZE (8 << 20) 156 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 157 158 /* hard reset data */ 159 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 160 161 /* reset flags */ 162 #define RADEON_RESET_GFX (1 << 0) 163 #define RADEON_RESET_COMPUTE (1 << 1) 164 #define RADEON_RESET_DMA (1 << 2) 165 #define RADEON_RESET_CP (1 << 3) 166 #define RADEON_RESET_GRBM (1 << 4) 167 #define RADEON_RESET_DMA1 (1 << 5) 168 #define RADEON_RESET_RLC (1 << 6) 169 #define RADEON_RESET_SEM (1 << 7) 170 #define RADEON_RESET_IH (1 << 8) 171 #define RADEON_RESET_VMC (1 << 9) 172 #define RADEON_RESET_MC (1 << 10) 173 #define RADEON_RESET_DISPLAY (1 << 11) 174 175 /* CG block flags */ 176 #define RADEON_CG_BLOCK_GFX (1 << 0) 177 #define RADEON_CG_BLOCK_MC (1 << 1) 178 #define RADEON_CG_BLOCK_SDMA (1 << 2) 179 #define RADEON_CG_BLOCK_UVD (1 << 3) 180 #define RADEON_CG_BLOCK_VCE (1 << 4) 181 #define RADEON_CG_BLOCK_HDP (1 << 5) 182 #define RADEON_CG_BLOCK_BIF (1 << 6) 183 184 /* CG flags */ 185 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 186 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 187 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 188 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 189 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 190 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 191 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 192 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 193 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 194 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 195 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 196 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 197 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 198 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 199 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 200 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 201 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 202 203 /* PG flags */ 204 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 205 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 206 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 207 #define RADEON_PG_SUPPORT_UVD (1 << 3) 208 #define RADEON_PG_SUPPORT_VCE (1 << 4) 209 #define RADEON_PG_SUPPORT_CP (1 << 5) 210 #define RADEON_PG_SUPPORT_GDS (1 << 6) 211 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 212 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 213 #define RADEON_PG_SUPPORT_ACP (1 << 9) 214 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 215 216 /* max cursor sizes (in pixels) */ 217 #define CURSOR_WIDTH 64 218 #define CURSOR_HEIGHT 64 219 220 #define CIK_CURSOR_WIDTH 128 221 #define CIK_CURSOR_HEIGHT 128 222 223 /* 224 * Errata workarounds. 225 */ 226 enum radeon_pll_errata { 227 CHIP_ERRATA_R300_CG = 0x00000001, 228 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 229 CHIP_ERRATA_PLL_DELAY = 0x00000004 230 }; 231 232 233 struct radeon_device; 234 235 236 /* 237 * BIOS. 238 */ 239 bool radeon_get_bios(struct radeon_device *rdev); 240 241 /* 242 * Dummy page 243 */ 244 struct radeon_dummy_page { 245 struct page *page; 246 dma_addr_t addr; 247 }; 248 int radeon_dummy_page_init(struct radeon_device *rdev); 249 void radeon_dummy_page_fini(struct radeon_device *rdev); 250 251 252 /* 253 * Clocks 254 */ 255 struct radeon_clock { 256 struct radeon_pll p1pll; 257 struct radeon_pll p2pll; 258 struct radeon_pll dcpll; 259 struct radeon_pll spll; 260 struct radeon_pll mpll; 261 /* 10 Khz units */ 262 uint32_t default_mclk; 263 uint32_t default_sclk; 264 uint32_t default_dispclk; 265 uint32_t current_dispclk; 266 uint32_t dp_extclk; 267 uint32_t max_pixel_clock; 268 }; 269 270 /* 271 * Power management 272 */ 273 int radeon_pm_init(struct radeon_device *rdev); 274 int radeon_pm_late_init(struct radeon_device *rdev); 275 void radeon_pm_fini(struct radeon_device *rdev); 276 void radeon_pm_compute_clocks(struct radeon_device *rdev); 277 void radeon_pm_suspend(struct radeon_device *rdev); 278 void radeon_pm_resume(struct radeon_device *rdev); 279 void radeon_combios_get_power_modes(struct radeon_device *rdev); 280 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 281 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 282 u8 clock_type, 283 u32 clock, 284 bool strobe_mode, 285 struct atom_clock_dividers *dividers); 286 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 287 u32 clock, 288 bool strobe_mode, 289 struct atom_mpll_param *mpll_param); 290 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 291 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 292 u16 voltage_level, u8 voltage_type, 293 u32 *gpio_value, u32 *gpio_mask); 294 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 295 u32 eng_clock, u32 mem_clock); 296 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 297 u8 voltage_type, u16 *voltage_step); 298 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 299 u16 voltage_id, u16 *voltage); 300 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 301 u16 *voltage, 302 u16 leakage_idx); 303 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 304 u16 *leakage_id); 305 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 306 u16 *vddc, u16 *vddci, 307 u16 virtual_voltage_id, 308 u16 vbios_voltage_id); 309 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 310 u16 virtual_voltage_id, 311 u16 *voltage); 312 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 313 u8 voltage_type, 314 u16 nominal_voltage, 315 u16 *true_voltage); 316 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 317 u8 voltage_type, u16 *min_voltage); 318 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 319 u8 voltage_type, u16 *max_voltage); 320 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 321 u8 voltage_type, u8 voltage_mode, 322 struct atom_voltage_table *voltage_table); 323 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 324 u8 voltage_type, u8 voltage_mode); 325 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 326 u8 voltage_type, 327 u8 *svd_gpio_id, u8 *svc_gpio_id); 328 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 329 u32 mem_clock); 330 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 331 u32 mem_clock); 332 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 333 u8 module_index, 334 struct atom_mc_reg_table *reg_table); 335 int radeon_atom_get_memory_info(struct radeon_device *rdev, 336 u8 module_index, struct atom_memory_info *mem_info); 337 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 338 bool gddr5, u8 module_index, 339 struct atom_memory_clock_range_table *mclk_range_table); 340 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 341 u16 voltage_id, u16 *voltage); 342 void rs690_pm_info(struct radeon_device *rdev); 343 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 344 unsigned *bankh, unsigned *mtaspect, 345 unsigned *tile_split); 346 347 /* 348 * Fences. 349 */ 350 struct radeon_fence_driver { 351 struct radeon_device *rdev; 352 uint32_t scratch_reg; 353 uint64_t gpu_addr; 354 volatile uint32_t *cpu_addr; 355 /* sync_seq is protected by ring emission lock */ 356 uint64_t sync_seq[RADEON_NUM_RINGS]; 357 atomic64_t last_seq; 358 bool initialized, delayed_irq; 359 struct delayed_work lockup_work; 360 }; 361 362 struct radeon_fence { 363 struct fence base; 364 365 struct radeon_device *rdev; 366 uint64_t seq; 367 /* RB, DMA, etc. */ 368 unsigned ring; 369 370 wait_queue_t fence_wake; 371 }; 372 373 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 374 int radeon_fence_driver_init(struct radeon_device *rdev); 375 void radeon_fence_driver_fini(struct radeon_device *rdev); 376 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 377 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 378 void radeon_fence_process(struct radeon_device *rdev, int ring); 379 bool radeon_fence_signaled(struct radeon_fence *fence); 380 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 381 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 382 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 383 int radeon_fence_wait_any(struct radeon_device *rdev, 384 struct radeon_fence **fences, 385 bool intr); 386 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 387 void radeon_fence_unref(struct radeon_fence **fence); 388 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 389 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 390 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 391 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 392 struct radeon_fence *b) 393 { 394 if (!a) { 395 return b; 396 } 397 398 if (!b) { 399 return a; 400 } 401 402 BUG_ON(a->ring != b->ring); 403 404 if (a->seq > b->seq) { 405 return a; 406 } else { 407 return b; 408 } 409 } 410 411 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 412 struct radeon_fence *b) 413 { 414 if (!a) { 415 return false; 416 } 417 418 if (!b) { 419 return true; 420 } 421 422 BUG_ON(a->ring != b->ring); 423 424 return a->seq < b->seq; 425 } 426 427 /* 428 * Tiling registers 429 */ 430 struct radeon_surface_reg { 431 struct radeon_bo *bo; 432 }; 433 434 #define RADEON_GEM_MAX_SURFACES 8 435 436 /* 437 * TTM. 438 */ 439 struct radeon_mman { 440 struct ttm_bo_global_ref bo_global_ref; 441 struct drm_global_reference mem_global_ref; 442 struct ttm_bo_device bdev; 443 bool mem_global_referenced; 444 bool initialized; 445 446 #if defined(CONFIG_DEBUG_FS) 447 struct dentry *vram; 448 struct dentry *gtt; 449 #endif 450 }; 451 452 /* bo virtual address in a specific vm */ 453 struct radeon_bo_va { 454 /* protected by bo being reserved */ 455 struct list_head bo_list; 456 uint32_t flags; 457 uint64_t addr; 458 unsigned ref_count; 459 460 /* protected by vm mutex */ 461 struct interval_tree_node it; 462 struct list_head vm_status; 463 464 /* constant after initialization */ 465 struct radeon_vm *vm; 466 struct radeon_bo *bo; 467 }; 468 469 struct radeon_bo { 470 /* Protected by gem.mutex */ 471 struct list_head list; 472 /* Protected by tbo.reserved */ 473 u32 initial_domain; 474 struct ttm_place placements[3]; 475 struct ttm_placement placement; 476 struct ttm_buffer_object tbo; 477 struct ttm_bo_kmap_obj kmap; 478 u32 flags; 479 unsigned pin_count; 480 void *kptr; 481 u32 tiling_flags; 482 u32 pitch; 483 int surface_reg; 484 /* list of all virtual address to which this bo 485 * is associated to 486 */ 487 struct list_head va; 488 /* Constant after initialization */ 489 struct radeon_device *rdev; 490 struct drm_gem_object gem_base; 491 492 struct ttm_bo_kmap_obj dma_buf_vmap; 493 pid_t pid; 494 495 struct radeon_mn *mn; 496 struct interval_tree_node mn_it; 497 }; 498 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 499 500 int radeon_gem_debugfs_init(struct radeon_device *rdev); 501 502 /* sub-allocation manager, it has to be protected by another lock. 503 * By conception this is an helper for other part of the driver 504 * like the indirect buffer or semaphore, which both have their 505 * locking. 506 * 507 * Principe is simple, we keep a list of sub allocation in offset 508 * order (first entry has offset == 0, last entry has the highest 509 * offset). 510 * 511 * When allocating new object we first check if there is room at 512 * the end total_size - (last_object_offset + last_object_size) >= 513 * alloc_size. If so we allocate new object there. 514 * 515 * When there is not enough room at the end, we start waiting for 516 * each sub object until we reach object_offset+object_size >= 517 * alloc_size, this object then become the sub object we return. 518 * 519 * Alignment can't be bigger than page size. 520 * 521 * Hole are not considered for allocation to keep things simple. 522 * Assumption is that there won't be hole (all object on same 523 * alignment). 524 */ 525 struct radeon_sa_manager { 526 wait_queue_head_t wq; 527 struct radeon_bo *bo; 528 struct list_head *hole; 529 struct list_head flist[RADEON_NUM_RINGS]; 530 struct list_head olist; 531 unsigned size; 532 uint64_t gpu_addr; 533 void *cpu_ptr; 534 uint32_t domain; 535 uint32_t align; 536 }; 537 538 struct radeon_sa_bo; 539 540 /* sub-allocation buffer */ 541 struct radeon_sa_bo { 542 struct list_head olist; 543 struct list_head flist; 544 struct radeon_sa_manager *manager; 545 unsigned soffset; 546 unsigned eoffset; 547 struct radeon_fence *fence; 548 }; 549 550 /* 551 * GEM objects. 552 */ 553 struct radeon_gem { 554 struct mutex mutex; 555 struct list_head objects; 556 }; 557 558 int radeon_gem_init(struct radeon_device *rdev); 559 void radeon_gem_fini(struct radeon_device *rdev); 560 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 561 int alignment, int initial_domain, 562 u32 flags, bool kernel, 563 struct drm_gem_object **obj); 564 565 int radeon_mode_dumb_create(struct drm_file *file_priv, 566 struct drm_device *dev, 567 struct drm_mode_create_dumb *args); 568 int radeon_mode_dumb_mmap(struct drm_file *filp, 569 struct drm_device *dev, 570 uint32_t handle, uint64_t *offset_p); 571 572 /* 573 * Semaphores. 574 */ 575 struct radeon_semaphore { 576 struct radeon_sa_bo *sa_bo; 577 signed waiters; 578 uint64_t gpu_addr; 579 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 580 }; 581 582 int radeon_semaphore_create(struct radeon_device *rdev, 583 struct radeon_semaphore **semaphore); 584 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 585 struct radeon_semaphore *semaphore); 586 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 587 struct radeon_semaphore *semaphore); 588 void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore, 589 struct radeon_fence *fence); 590 void radeon_semaphore_sync_resv(struct radeon_semaphore *semaphore, 591 struct reservation_object *resv, 592 bool shared); 593 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 594 struct radeon_semaphore *semaphore, 595 int waiting_ring); 596 void radeon_semaphore_free(struct radeon_device *rdev, 597 struct radeon_semaphore **semaphore, 598 struct radeon_fence *fence); 599 600 /* 601 * GART structures, functions & helpers 602 */ 603 struct radeon_mc; 604 605 #define RADEON_GPU_PAGE_SIZE 4096 606 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 607 #define RADEON_GPU_PAGE_SHIFT 12 608 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 609 610 #define RADEON_GART_PAGE_DUMMY 0 611 #define RADEON_GART_PAGE_VALID (1 << 0) 612 #define RADEON_GART_PAGE_READ (1 << 1) 613 #define RADEON_GART_PAGE_WRITE (1 << 2) 614 #define RADEON_GART_PAGE_SNOOP (1 << 3) 615 616 struct radeon_gart { 617 dma_addr_t table_addr; 618 struct radeon_bo *robj; 619 void *ptr; 620 unsigned num_gpu_pages; 621 unsigned num_cpu_pages; 622 unsigned table_size; 623 struct page **pages; 624 dma_addr_t *pages_addr; 625 bool ready; 626 }; 627 628 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 629 void radeon_gart_table_ram_free(struct radeon_device *rdev); 630 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 631 void radeon_gart_table_vram_free(struct radeon_device *rdev); 632 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 633 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 634 int radeon_gart_init(struct radeon_device *rdev); 635 void radeon_gart_fini(struct radeon_device *rdev); 636 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 637 int pages); 638 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 639 int pages, struct page **pagelist, 640 dma_addr_t *dma_addr, uint32_t flags); 641 642 643 /* 644 * GPU MC structures, functions & helpers 645 */ 646 struct radeon_mc { 647 resource_size_t aper_size; 648 resource_size_t aper_base; 649 resource_size_t agp_base; 650 /* for some chips with <= 32MB we need to lie 651 * about vram size near mc fb location */ 652 u64 mc_vram_size; 653 u64 visible_vram_size; 654 u64 gtt_size; 655 u64 gtt_start; 656 u64 gtt_end; 657 u64 vram_start; 658 u64 vram_end; 659 unsigned vram_width; 660 u64 real_vram_size; 661 int vram_mtrr; 662 bool vram_is_ddr; 663 bool igp_sideport_enabled; 664 u64 gtt_base_align; 665 u64 mc_mask; 666 }; 667 668 bool radeon_combios_sideport_present(struct radeon_device *rdev); 669 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 670 671 /* 672 * GPU scratch registers structures, functions & helpers 673 */ 674 struct radeon_scratch { 675 unsigned num_reg; 676 uint32_t reg_base; 677 bool free[32]; 678 uint32_t reg[32]; 679 }; 680 681 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 682 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 683 684 /* 685 * GPU doorbell structures, functions & helpers 686 */ 687 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 688 689 struct radeon_doorbell { 690 /* doorbell mmio */ 691 resource_size_t base; 692 resource_size_t size; 693 u32 __iomem *ptr; 694 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 695 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 696 }; 697 698 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 699 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 700 701 /* 702 * IRQS. 703 */ 704 705 struct radeon_flip_work { 706 struct work_struct flip_work; 707 struct work_struct unpin_work; 708 struct radeon_device *rdev; 709 int crtc_id; 710 uint64_t base; 711 struct drm_pending_vblank_event *event; 712 struct radeon_bo *old_rbo; 713 struct radeon_fence *fence; 714 }; 715 716 struct r500_irq_stat_regs { 717 u32 disp_int; 718 u32 hdmi0_status; 719 }; 720 721 struct r600_irq_stat_regs { 722 u32 disp_int; 723 u32 disp_int_cont; 724 u32 disp_int_cont2; 725 u32 d1grph_int; 726 u32 d2grph_int; 727 u32 hdmi0_status; 728 u32 hdmi1_status; 729 }; 730 731 struct evergreen_irq_stat_regs { 732 u32 disp_int; 733 u32 disp_int_cont; 734 u32 disp_int_cont2; 735 u32 disp_int_cont3; 736 u32 disp_int_cont4; 737 u32 disp_int_cont5; 738 u32 d1grph_int; 739 u32 d2grph_int; 740 u32 d3grph_int; 741 u32 d4grph_int; 742 u32 d5grph_int; 743 u32 d6grph_int; 744 u32 afmt_status1; 745 u32 afmt_status2; 746 u32 afmt_status3; 747 u32 afmt_status4; 748 u32 afmt_status5; 749 u32 afmt_status6; 750 }; 751 752 struct cik_irq_stat_regs { 753 u32 disp_int; 754 u32 disp_int_cont; 755 u32 disp_int_cont2; 756 u32 disp_int_cont3; 757 u32 disp_int_cont4; 758 u32 disp_int_cont5; 759 u32 disp_int_cont6; 760 u32 d1grph_int; 761 u32 d2grph_int; 762 u32 d3grph_int; 763 u32 d4grph_int; 764 u32 d5grph_int; 765 u32 d6grph_int; 766 }; 767 768 union radeon_irq_stat_regs { 769 struct r500_irq_stat_regs r500; 770 struct r600_irq_stat_regs r600; 771 struct evergreen_irq_stat_regs evergreen; 772 struct cik_irq_stat_regs cik; 773 }; 774 775 struct radeon_irq { 776 bool installed; 777 spinlock_t lock; 778 atomic_t ring_int[RADEON_NUM_RINGS]; 779 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 780 atomic_t pflip[RADEON_MAX_CRTCS]; 781 wait_queue_head_t vblank_queue; 782 bool hpd[RADEON_MAX_HPD_PINS]; 783 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 784 union radeon_irq_stat_regs stat_regs; 785 bool dpm_thermal; 786 }; 787 788 int radeon_irq_kms_init(struct radeon_device *rdev); 789 void radeon_irq_kms_fini(struct radeon_device *rdev); 790 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 791 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 792 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 793 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 794 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 795 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 796 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 797 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 798 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 799 800 /* 801 * CP & rings. 802 */ 803 804 struct radeon_ib { 805 struct radeon_sa_bo *sa_bo; 806 uint32_t length_dw; 807 uint64_t gpu_addr; 808 uint32_t *ptr; 809 int ring; 810 struct radeon_fence *fence; 811 struct radeon_vm *vm; 812 bool is_const_ib; 813 struct radeon_semaphore *semaphore; 814 }; 815 816 struct radeon_ring { 817 struct radeon_bo *ring_obj; 818 volatile uint32_t *ring; 819 unsigned rptr_offs; 820 unsigned rptr_save_reg; 821 u64 next_rptr_gpu_addr; 822 volatile u32 *next_rptr_cpu_addr; 823 unsigned wptr; 824 unsigned wptr_old; 825 unsigned ring_size; 826 unsigned ring_free_dw; 827 int count_dw; 828 atomic_t last_rptr; 829 atomic64_t last_activity; 830 uint64_t gpu_addr; 831 uint32_t align_mask; 832 uint32_t ptr_mask; 833 bool ready; 834 u32 nop; 835 u32 idx; 836 u64 last_semaphore_signal_addr; 837 u64 last_semaphore_wait_addr; 838 /* for CIK queues */ 839 u32 me; 840 u32 pipe; 841 u32 queue; 842 struct radeon_bo *mqd_obj; 843 u32 doorbell_index; 844 unsigned wptr_offs; 845 }; 846 847 struct radeon_mec { 848 struct radeon_bo *hpd_eop_obj; 849 u64 hpd_eop_gpu_addr; 850 u32 num_pipe; 851 u32 num_mec; 852 u32 num_queue; 853 }; 854 855 /* 856 * VM 857 */ 858 859 /* maximum number of VMIDs */ 860 #define RADEON_NUM_VM 16 861 862 /* number of entries in page table */ 863 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 864 865 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 866 #define RADEON_VM_PTB_ALIGN_SIZE 32768 867 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 868 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 869 870 #define R600_PTE_VALID (1 << 0) 871 #define R600_PTE_SYSTEM (1 << 1) 872 #define R600_PTE_SNOOPED (1 << 2) 873 #define R600_PTE_READABLE (1 << 5) 874 #define R600_PTE_WRITEABLE (1 << 6) 875 876 /* PTE (Page Table Entry) fragment field for different page sizes */ 877 #define R600_PTE_FRAG_4KB (0 << 7) 878 #define R600_PTE_FRAG_64KB (4 << 7) 879 #define R600_PTE_FRAG_256KB (6 << 7) 880 881 /* flags needed to be set so we can copy directly from the GART table */ 882 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 883 R600_PTE_SYSTEM | R600_PTE_VALID ) 884 885 struct radeon_vm_pt { 886 struct radeon_bo *bo; 887 uint64_t addr; 888 }; 889 890 struct radeon_vm { 891 struct rb_root va; 892 unsigned id; 893 894 /* BOs moved, but not yet updated in the PT */ 895 struct list_head invalidated; 896 897 /* BOs freed, but not yet updated in the PT */ 898 struct list_head freed; 899 900 /* contains the page directory */ 901 struct radeon_bo *page_directory; 902 uint64_t pd_gpu_addr; 903 unsigned max_pde_used; 904 905 /* array of page tables, one for each page directory entry */ 906 struct radeon_vm_pt *page_tables; 907 908 struct radeon_bo_va *ib_bo_va; 909 910 struct mutex mutex; 911 /* last fence for cs using this vm */ 912 struct radeon_fence *fence; 913 /* last flush or NULL if we still need to flush */ 914 struct radeon_fence *last_flush; 915 /* last use of vmid */ 916 struct radeon_fence *last_id_use; 917 }; 918 919 struct radeon_vm_manager { 920 struct radeon_fence *active[RADEON_NUM_VM]; 921 uint32_t max_pfn; 922 /* number of VMIDs */ 923 unsigned nvm; 924 /* vram base address for page table entry */ 925 u64 vram_base_offset; 926 /* is vm enabled? */ 927 bool enabled; 928 }; 929 930 /* 931 * file private structure 932 */ 933 struct radeon_fpriv { 934 struct radeon_vm vm; 935 }; 936 937 /* 938 * R6xx+ IH ring 939 */ 940 struct r600_ih { 941 struct radeon_bo *ring_obj; 942 volatile uint32_t *ring; 943 unsigned rptr; 944 unsigned ring_size; 945 uint64_t gpu_addr; 946 uint32_t ptr_mask; 947 atomic_t lock; 948 bool enabled; 949 }; 950 951 /* 952 * RLC stuff 953 */ 954 #include "clearstate_defs.h" 955 956 struct radeon_rlc { 957 /* for power gating */ 958 struct radeon_bo *save_restore_obj; 959 uint64_t save_restore_gpu_addr; 960 volatile uint32_t *sr_ptr; 961 const u32 *reg_list; 962 u32 reg_list_size; 963 /* for clear state */ 964 struct radeon_bo *clear_state_obj; 965 uint64_t clear_state_gpu_addr; 966 volatile uint32_t *cs_ptr; 967 const struct cs_section_def *cs_data; 968 u32 clear_state_size; 969 /* for cp tables */ 970 struct radeon_bo *cp_table_obj; 971 uint64_t cp_table_gpu_addr; 972 volatile uint32_t *cp_table_ptr; 973 u32 cp_table_size; 974 }; 975 976 int radeon_ib_get(struct radeon_device *rdev, int ring, 977 struct radeon_ib *ib, struct radeon_vm *vm, 978 unsigned size); 979 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 980 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 981 struct radeon_ib *const_ib, bool hdp_flush); 982 int radeon_ib_pool_init(struct radeon_device *rdev); 983 void radeon_ib_pool_fini(struct radeon_device *rdev); 984 int radeon_ib_ring_tests(struct radeon_device *rdev); 985 /* Ring access between begin & end cannot sleep */ 986 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 987 struct radeon_ring *ring); 988 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 989 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 990 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 991 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 992 bool hdp_flush); 993 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 994 bool hdp_flush); 995 void radeon_ring_undo(struct radeon_ring *ring); 996 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 997 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 998 void radeon_ring_lockup_update(struct radeon_device *rdev, 999 struct radeon_ring *ring); 1000 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1001 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1002 uint32_t **data); 1003 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1004 unsigned size, uint32_t *data); 1005 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1006 unsigned rptr_offs, u32 nop); 1007 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1008 1009 1010 /* r600 async dma */ 1011 void r600_dma_stop(struct radeon_device *rdev); 1012 int r600_dma_resume(struct radeon_device *rdev); 1013 void r600_dma_fini(struct radeon_device *rdev); 1014 1015 void cayman_dma_stop(struct radeon_device *rdev); 1016 int cayman_dma_resume(struct radeon_device *rdev); 1017 void cayman_dma_fini(struct radeon_device *rdev); 1018 1019 /* 1020 * CS. 1021 */ 1022 struct radeon_cs_reloc { 1023 struct drm_gem_object *gobj; 1024 struct radeon_bo *robj; 1025 struct ttm_validate_buffer tv; 1026 uint64_t gpu_offset; 1027 unsigned prefered_domains; 1028 unsigned allowed_domains; 1029 uint32_t tiling_flags; 1030 uint32_t handle; 1031 }; 1032 1033 struct radeon_cs_chunk { 1034 uint32_t chunk_id; 1035 uint32_t length_dw; 1036 uint32_t *kdata; 1037 void __user *user_ptr; 1038 }; 1039 1040 struct radeon_cs_parser { 1041 struct device *dev; 1042 struct radeon_device *rdev; 1043 struct drm_file *filp; 1044 /* chunks */ 1045 unsigned nchunks; 1046 struct radeon_cs_chunk *chunks; 1047 uint64_t *chunks_array; 1048 /* IB */ 1049 unsigned idx; 1050 /* relocations */ 1051 unsigned nrelocs; 1052 struct radeon_cs_reloc *relocs; 1053 struct radeon_cs_reloc **relocs_ptr; 1054 struct radeon_cs_reloc *vm_bos; 1055 struct list_head validated; 1056 unsigned dma_reloc_idx; 1057 /* indices of various chunks */ 1058 int chunk_ib_idx; 1059 int chunk_relocs_idx; 1060 int chunk_flags_idx; 1061 int chunk_const_ib_idx; 1062 struct radeon_ib ib; 1063 struct radeon_ib const_ib; 1064 void *track; 1065 unsigned family; 1066 int parser_error; 1067 u32 cs_flags; 1068 u32 ring; 1069 s32 priority; 1070 struct ww_acquire_ctx ticket; 1071 }; 1072 1073 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1074 { 1075 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1076 1077 if (ibc->kdata) 1078 return ibc->kdata[idx]; 1079 return p->ib.ptr[idx]; 1080 } 1081 1082 1083 struct radeon_cs_packet { 1084 unsigned idx; 1085 unsigned type; 1086 unsigned reg; 1087 unsigned opcode; 1088 int count; 1089 unsigned one_reg_wr; 1090 }; 1091 1092 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1093 struct radeon_cs_packet *pkt, 1094 unsigned idx, unsigned reg); 1095 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1096 struct radeon_cs_packet *pkt); 1097 1098 1099 /* 1100 * AGP 1101 */ 1102 int radeon_agp_init(struct radeon_device *rdev); 1103 void radeon_agp_resume(struct radeon_device *rdev); 1104 void radeon_agp_suspend(struct radeon_device *rdev); 1105 void radeon_agp_fini(struct radeon_device *rdev); 1106 1107 1108 /* 1109 * Writeback 1110 */ 1111 struct radeon_wb { 1112 struct radeon_bo *wb_obj; 1113 volatile uint32_t *wb; 1114 uint64_t gpu_addr; 1115 bool enabled; 1116 bool use_event; 1117 }; 1118 1119 #define RADEON_WB_SCRATCH_OFFSET 0 1120 #define RADEON_WB_RING0_NEXT_RPTR 256 1121 #define RADEON_WB_CP_RPTR_OFFSET 1024 1122 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1123 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1124 #define R600_WB_DMA_RPTR_OFFSET 1792 1125 #define R600_WB_IH_WPTR_OFFSET 2048 1126 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1127 #define R600_WB_EVENT_OFFSET 3072 1128 #define CIK_WB_CP1_WPTR_OFFSET 3328 1129 #define CIK_WB_CP2_WPTR_OFFSET 3584 1130 1131 /** 1132 * struct radeon_pm - power management datas 1133 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1134 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1135 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1136 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1137 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1138 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1139 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1140 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1141 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1142 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1143 * @needed_bandwidth: current bandwidth needs 1144 * 1145 * It keeps track of various data needed to take powermanagement decision. 1146 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1147 * Equation between gpu/memory clock and available bandwidth is hw dependent 1148 * (type of memory, bus size, efficiency, ...) 1149 */ 1150 1151 enum radeon_pm_method { 1152 PM_METHOD_PROFILE, 1153 PM_METHOD_DYNPM, 1154 PM_METHOD_DPM, 1155 }; 1156 1157 enum radeon_dynpm_state { 1158 DYNPM_STATE_DISABLED, 1159 DYNPM_STATE_MINIMUM, 1160 DYNPM_STATE_PAUSED, 1161 DYNPM_STATE_ACTIVE, 1162 DYNPM_STATE_SUSPENDED, 1163 }; 1164 enum radeon_dynpm_action { 1165 DYNPM_ACTION_NONE, 1166 DYNPM_ACTION_MINIMUM, 1167 DYNPM_ACTION_DOWNCLOCK, 1168 DYNPM_ACTION_UPCLOCK, 1169 DYNPM_ACTION_DEFAULT 1170 }; 1171 1172 enum radeon_voltage_type { 1173 VOLTAGE_NONE = 0, 1174 VOLTAGE_GPIO, 1175 VOLTAGE_VDDC, 1176 VOLTAGE_SW 1177 }; 1178 1179 enum radeon_pm_state_type { 1180 /* not used for dpm */ 1181 POWER_STATE_TYPE_DEFAULT, 1182 POWER_STATE_TYPE_POWERSAVE, 1183 /* user selectable states */ 1184 POWER_STATE_TYPE_BATTERY, 1185 POWER_STATE_TYPE_BALANCED, 1186 POWER_STATE_TYPE_PERFORMANCE, 1187 /* internal states */ 1188 POWER_STATE_TYPE_INTERNAL_UVD, 1189 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1190 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1191 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1192 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1193 POWER_STATE_TYPE_INTERNAL_BOOT, 1194 POWER_STATE_TYPE_INTERNAL_THERMAL, 1195 POWER_STATE_TYPE_INTERNAL_ACPI, 1196 POWER_STATE_TYPE_INTERNAL_ULV, 1197 POWER_STATE_TYPE_INTERNAL_3DPERF, 1198 }; 1199 1200 enum radeon_pm_profile_type { 1201 PM_PROFILE_DEFAULT, 1202 PM_PROFILE_AUTO, 1203 PM_PROFILE_LOW, 1204 PM_PROFILE_MID, 1205 PM_PROFILE_HIGH, 1206 }; 1207 1208 #define PM_PROFILE_DEFAULT_IDX 0 1209 #define PM_PROFILE_LOW_SH_IDX 1 1210 #define PM_PROFILE_MID_SH_IDX 2 1211 #define PM_PROFILE_HIGH_SH_IDX 3 1212 #define PM_PROFILE_LOW_MH_IDX 4 1213 #define PM_PROFILE_MID_MH_IDX 5 1214 #define PM_PROFILE_HIGH_MH_IDX 6 1215 #define PM_PROFILE_MAX 7 1216 1217 struct radeon_pm_profile { 1218 int dpms_off_ps_idx; 1219 int dpms_on_ps_idx; 1220 int dpms_off_cm_idx; 1221 int dpms_on_cm_idx; 1222 }; 1223 1224 enum radeon_int_thermal_type { 1225 THERMAL_TYPE_NONE, 1226 THERMAL_TYPE_EXTERNAL, 1227 THERMAL_TYPE_EXTERNAL_GPIO, 1228 THERMAL_TYPE_RV6XX, 1229 THERMAL_TYPE_RV770, 1230 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1231 THERMAL_TYPE_EVERGREEN, 1232 THERMAL_TYPE_SUMO, 1233 THERMAL_TYPE_NI, 1234 THERMAL_TYPE_SI, 1235 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1236 THERMAL_TYPE_CI, 1237 THERMAL_TYPE_KV, 1238 }; 1239 1240 struct radeon_voltage { 1241 enum radeon_voltage_type type; 1242 /* gpio voltage */ 1243 struct radeon_gpio_rec gpio; 1244 u32 delay; /* delay in usec from voltage drop to sclk change */ 1245 bool active_high; /* voltage drop is active when bit is high */ 1246 /* VDDC voltage */ 1247 u8 vddc_id; /* index into vddc voltage table */ 1248 u8 vddci_id; /* index into vddci voltage table */ 1249 bool vddci_enabled; 1250 /* r6xx+ sw */ 1251 u16 voltage; 1252 /* evergreen+ vddci */ 1253 u16 vddci; 1254 }; 1255 1256 /* clock mode flags */ 1257 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1258 1259 struct radeon_pm_clock_info { 1260 /* memory clock */ 1261 u32 mclk; 1262 /* engine clock */ 1263 u32 sclk; 1264 /* voltage info */ 1265 struct radeon_voltage voltage; 1266 /* standardized clock flags */ 1267 u32 flags; 1268 }; 1269 1270 /* state flags */ 1271 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1272 1273 struct radeon_power_state { 1274 enum radeon_pm_state_type type; 1275 struct radeon_pm_clock_info *clock_info; 1276 /* number of valid clock modes in this power state */ 1277 int num_clock_modes; 1278 struct radeon_pm_clock_info *default_clock_mode; 1279 /* standardized state flags */ 1280 u32 flags; 1281 u32 misc; /* vbios specific flags */ 1282 u32 misc2; /* vbios specific flags */ 1283 int pcie_lanes; /* pcie lanes */ 1284 }; 1285 1286 /* 1287 * Some modes are overclocked by very low value, accept them 1288 */ 1289 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1290 1291 enum radeon_dpm_auto_throttle_src { 1292 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1293 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1294 }; 1295 1296 enum radeon_dpm_event_src { 1297 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1298 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1299 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1300 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1301 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1302 }; 1303 1304 #define RADEON_MAX_VCE_LEVELS 6 1305 1306 enum radeon_vce_level { 1307 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1308 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1309 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1310 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1311 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1312 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1313 }; 1314 1315 struct radeon_ps { 1316 u32 caps; /* vbios flags */ 1317 u32 class; /* vbios flags */ 1318 u32 class2; /* vbios flags */ 1319 /* UVD clocks */ 1320 u32 vclk; 1321 u32 dclk; 1322 /* VCE clocks */ 1323 u32 evclk; 1324 u32 ecclk; 1325 bool vce_active; 1326 enum radeon_vce_level vce_level; 1327 /* asic priv */ 1328 void *ps_priv; 1329 }; 1330 1331 struct radeon_dpm_thermal { 1332 /* thermal interrupt work */ 1333 struct work_struct work; 1334 /* low temperature threshold */ 1335 int min_temp; 1336 /* high temperature threshold */ 1337 int max_temp; 1338 /* was interrupt low to high or high to low */ 1339 bool high_to_low; 1340 }; 1341 1342 enum radeon_clk_action 1343 { 1344 RADEON_SCLK_UP = 1, 1345 RADEON_SCLK_DOWN 1346 }; 1347 1348 struct radeon_blacklist_clocks 1349 { 1350 u32 sclk; 1351 u32 mclk; 1352 enum radeon_clk_action action; 1353 }; 1354 1355 struct radeon_clock_and_voltage_limits { 1356 u32 sclk; 1357 u32 mclk; 1358 u16 vddc; 1359 u16 vddci; 1360 }; 1361 1362 struct radeon_clock_array { 1363 u32 count; 1364 u32 *values; 1365 }; 1366 1367 struct radeon_clock_voltage_dependency_entry { 1368 u32 clk; 1369 u16 v; 1370 }; 1371 1372 struct radeon_clock_voltage_dependency_table { 1373 u32 count; 1374 struct radeon_clock_voltage_dependency_entry *entries; 1375 }; 1376 1377 union radeon_cac_leakage_entry { 1378 struct { 1379 u16 vddc; 1380 u32 leakage; 1381 }; 1382 struct { 1383 u16 vddc1; 1384 u16 vddc2; 1385 u16 vddc3; 1386 }; 1387 }; 1388 1389 struct radeon_cac_leakage_table { 1390 u32 count; 1391 union radeon_cac_leakage_entry *entries; 1392 }; 1393 1394 struct radeon_phase_shedding_limits_entry { 1395 u16 voltage; 1396 u32 sclk; 1397 u32 mclk; 1398 }; 1399 1400 struct radeon_phase_shedding_limits_table { 1401 u32 count; 1402 struct radeon_phase_shedding_limits_entry *entries; 1403 }; 1404 1405 struct radeon_uvd_clock_voltage_dependency_entry { 1406 u32 vclk; 1407 u32 dclk; 1408 u16 v; 1409 }; 1410 1411 struct radeon_uvd_clock_voltage_dependency_table { 1412 u8 count; 1413 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1414 }; 1415 1416 struct radeon_vce_clock_voltage_dependency_entry { 1417 u32 ecclk; 1418 u32 evclk; 1419 u16 v; 1420 }; 1421 1422 struct radeon_vce_clock_voltage_dependency_table { 1423 u8 count; 1424 struct radeon_vce_clock_voltage_dependency_entry *entries; 1425 }; 1426 1427 struct radeon_ppm_table { 1428 u8 ppm_design; 1429 u16 cpu_core_number; 1430 u32 platform_tdp; 1431 u32 small_ac_platform_tdp; 1432 u32 platform_tdc; 1433 u32 small_ac_platform_tdc; 1434 u32 apu_tdp; 1435 u32 dgpu_tdp; 1436 u32 dgpu_ulv_power; 1437 u32 tj_max; 1438 }; 1439 1440 struct radeon_cac_tdp_table { 1441 u16 tdp; 1442 u16 configurable_tdp; 1443 u16 tdc; 1444 u16 battery_power_limit; 1445 u16 small_power_limit; 1446 u16 low_cac_leakage; 1447 u16 high_cac_leakage; 1448 u16 maximum_power_delivery_limit; 1449 }; 1450 1451 struct radeon_dpm_dynamic_state { 1452 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1453 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1454 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1455 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1456 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1457 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1458 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1459 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1460 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1461 struct radeon_clock_array valid_sclk_values; 1462 struct radeon_clock_array valid_mclk_values; 1463 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1464 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1465 u32 mclk_sclk_ratio; 1466 u32 sclk_mclk_delta; 1467 u16 vddc_vddci_delta; 1468 u16 min_vddc_for_pcie_gen2; 1469 struct radeon_cac_leakage_table cac_leakage_table; 1470 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1471 struct radeon_ppm_table *ppm_table; 1472 struct radeon_cac_tdp_table *cac_tdp_table; 1473 }; 1474 1475 struct radeon_dpm_fan { 1476 u16 t_min; 1477 u16 t_med; 1478 u16 t_high; 1479 u16 pwm_min; 1480 u16 pwm_med; 1481 u16 pwm_high; 1482 u8 t_hyst; 1483 u32 cycle_delay; 1484 u16 t_max; 1485 bool ucode_fan_control; 1486 }; 1487 1488 enum radeon_pcie_gen { 1489 RADEON_PCIE_GEN1 = 0, 1490 RADEON_PCIE_GEN2 = 1, 1491 RADEON_PCIE_GEN3 = 2, 1492 RADEON_PCIE_GEN_INVALID = 0xffff 1493 }; 1494 1495 enum radeon_dpm_forced_level { 1496 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1497 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1498 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1499 }; 1500 1501 struct radeon_vce_state { 1502 /* vce clocks */ 1503 u32 evclk; 1504 u32 ecclk; 1505 /* gpu clocks */ 1506 u32 sclk; 1507 u32 mclk; 1508 u8 clk_idx; 1509 u8 pstate; 1510 }; 1511 1512 struct radeon_dpm { 1513 struct radeon_ps *ps; 1514 /* number of valid power states */ 1515 int num_ps; 1516 /* current power state that is active */ 1517 struct radeon_ps *current_ps; 1518 /* requested power state */ 1519 struct radeon_ps *requested_ps; 1520 /* boot up power state */ 1521 struct radeon_ps *boot_ps; 1522 /* default uvd power state */ 1523 struct radeon_ps *uvd_ps; 1524 /* vce requirements */ 1525 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1526 enum radeon_vce_level vce_level; 1527 enum radeon_pm_state_type state; 1528 enum radeon_pm_state_type user_state; 1529 u32 platform_caps; 1530 u32 voltage_response_time; 1531 u32 backbias_response_time; 1532 void *priv; 1533 u32 new_active_crtcs; 1534 int new_active_crtc_count; 1535 u32 current_active_crtcs; 1536 int current_active_crtc_count; 1537 struct radeon_dpm_dynamic_state dyn_state; 1538 struct radeon_dpm_fan fan; 1539 u32 tdp_limit; 1540 u32 near_tdp_limit; 1541 u32 near_tdp_limit_adjusted; 1542 u32 sq_ramping_threshold; 1543 u32 cac_leakage; 1544 u16 tdp_od_limit; 1545 u32 tdp_adjustment; 1546 u16 load_line_slope; 1547 bool power_control; 1548 bool ac_power; 1549 /* special states active */ 1550 bool thermal_active; 1551 bool uvd_active; 1552 bool vce_active; 1553 /* thermal handling */ 1554 struct radeon_dpm_thermal thermal; 1555 /* forced levels */ 1556 enum radeon_dpm_forced_level forced_level; 1557 /* track UVD streams */ 1558 unsigned sd; 1559 unsigned hd; 1560 }; 1561 1562 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1563 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1564 1565 struct radeon_pm { 1566 struct mutex mutex; 1567 /* write locked while reprogramming mclk */ 1568 struct rw_semaphore mclk_lock; 1569 u32 active_crtcs; 1570 int active_crtc_count; 1571 int req_vblank; 1572 bool vblank_sync; 1573 fixed20_12 max_bandwidth; 1574 fixed20_12 igp_sideport_mclk; 1575 fixed20_12 igp_system_mclk; 1576 fixed20_12 igp_ht_link_clk; 1577 fixed20_12 igp_ht_link_width; 1578 fixed20_12 k8_bandwidth; 1579 fixed20_12 sideport_bandwidth; 1580 fixed20_12 ht_bandwidth; 1581 fixed20_12 core_bandwidth; 1582 fixed20_12 sclk; 1583 fixed20_12 mclk; 1584 fixed20_12 needed_bandwidth; 1585 struct radeon_power_state *power_state; 1586 /* number of valid power states */ 1587 int num_power_states; 1588 int current_power_state_index; 1589 int current_clock_mode_index; 1590 int requested_power_state_index; 1591 int requested_clock_mode_index; 1592 int default_power_state_index; 1593 u32 current_sclk; 1594 u32 current_mclk; 1595 u16 current_vddc; 1596 u16 current_vddci; 1597 u32 default_sclk; 1598 u32 default_mclk; 1599 u16 default_vddc; 1600 u16 default_vddci; 1601 struct radeon_i2c_chan *i2c_bus; 1602 /* selected pm method */ 1603 enum radeon_pm_method pm_method; 1604 /* dynpm power management */ 1605 struct delayed_work dynpm_idle_work; 1606 enum radeon_dynpm_state dynpm_state; 1607 enum radeon_dynpm_action dynpm_planned_action; 1608 unsigned long dynpm_action_timeout; 1609 bool dynpm_can_upclock; 1610 bool dynpm_can_downclock; 1611 /* profile-based power management */ 1612 enum radeon_pm_profile_type profile; 1613 int profile_index; 1614 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1615 /* internal thermal controller on rv6xx+ */ 1616 enum radeon_int_thermal_type int_thermal_type; 1617 struct device *int_hwmon_dev; 1618 /* dpm */ 1619 bool dpm_enabled; 1620 struct radeon_dpm dpm; 1621 }; 1622 1623 int radeon_pm_get_type_index(struct radeon_device *rdev, 1624 enum radeon_pm_state_type ps_type, 1625 int instance); 1626 /* 1627 * UVD 1628 */ 1629 #define RADEON_MAX_UVD_HANDLES 10 1630 #define RADEON_UVD_STACK_SIZE (1024*1024) 1631 #define RADEON_UVD_HEAP_SIZE (1024*1024) 1632 1633 struct radeon_uvd { 1634 struct radeon_bo *vcpu_bo; 1635 void *cpu_addr; 1636 uint64_t gpu_addr; 1637 void *saved_bo; 1638 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1639 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1640 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1641 struct delayed_work idle_work; 1642 }; 1643 1644 int radeon_uvd_init(struct radeon_device *rdev); 1645 void radeon_uvd_fini(struct radeon_device *rdev); 1646 int radeon_uvd_suspend(struct radeon_device *rdev); 1647 int radeon_uvd_resume(struct radeon_device *rdev); 1648 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1649 uint32_t handle, struct radeon_fence **fence); 1650 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1651 uint32_t handle, struct radeon_fence **fence); 1652 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1653 uint32_t allowed_domains); 1654 void radeon_uvd_free_handles(struct radeon_device *rdev, 1655 struct drm_file *filp); 1656 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1657 void radeon_uvd_note_usage(struct radeon_device *rdev); 1658 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1659 unsigned vclk, unsigned dclk, 1660 unsigned vco_min, unsigned vco_max, 1661 unsigned fb_factor, unsigned fb_mask, 1662 unsigned pd_min, unsigned pd_max, 1663 unsigned pd_even, 1664 unsigned *optimal_fb_div, 1665 unsigned *optimal_vclk_div, 1666 unsigned *optimal_dclk_div); 1667 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1668 unsigned cg_upll_func_cntl); 1669 1670 /* 1671 * VCE 1672 */ 1673 #define RADEON_MAX_VCE_HANDLES 16 1674 #define RADEON_VCE_STACK_SIZE (1024*1024) 1675 #define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1676 1677 struct radeon_vce { 1678 struct radeon_bo *vcpu_bo; 1679 uint64_t gpu_addr; 1680 unsigned fw_version; 1681 unsigned fb_version; 1682 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1683 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1684 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1685 struct delayed_work idle_work; 1686 }; 1687 1688 int radeon_vce_init(struct radeon_device *rdev); 1689 void radeon_vce_fini(struct radeon_device *rdev); 1690 int radeon_vce_suspend(struct radeon_device *rdev); 1691 int radeon_vce_resume(struct radeon_device *rdev); 1692 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1693 uint32_t handle, struct radeon_fence **fence); 1694 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1695 uint32_t handle, struct radeon_fence **fence); 1696 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1697 void radeon_vce_note_usage(struct radeon_device *rdev); 1698 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1699 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1700 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1701 struct radeon_ring *ring, 1702 struct radeon_semaphore *semaphore, 1703 bool emit_wait); 1704 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1705 void radeon_vce_fence_emit(struct radeon_device *rdev, 1706 struct radeon_fence *fence); 1707 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1708 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1709 1710 struct r600_audio_pin { 1711 int channels; 1712 int rate; 1713 int bits_per_sample; 1714 u8 status_bits; 1715 u8 category_code; 1716 u32 offset; 1717 bool connected; 1718 u32 id; 1719 }; 1720 1721 struct r600_audio { 1722 bool enabled; 1723 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1724 int num_pins; 1725 }; 1726 1727 /* 1728 * Benchmarking 1729 */ 1730 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1731 1732 1733 /* 1734 * Testing 1735 */ 1736 void radeon_test_moves(struct radeon_device *rdev); 1737 void radeon_test_ring_sync(struct radeon_device *rdev, 1738 struct radeon_ring *cpA, 1739 struct radeon_ring *cpB); 1740 void radeon_test_syncing(struct radeon_device *rdev); 1741 1742 /* 1743 * MMU Notifier 1744 */ 1745 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1746 void radeon_mn_unregister(struct radeon_bo *bo); 1747 1748 /* 1749 * Debugfs 1750 */ 1751 struct radeon_debugfs { 1752 struct drm_info_list *files; 1753 unsigned num_files; 1754 }; 1755 1756 int radeon_debugfs_add_files(struct radeon_device *rdev, 1757 struct drm_info_list *files, 1758 unsigned nfiles); 1759 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1760 1761 /* 1762 * ASIC ring specific functions. 1763 */ 1764 struct radeon_asic_ring { 1765 /* ring read/write ptr handling */ 1766 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1767 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1768 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1769 1770 /* validating and patching of IBs */ 1771 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1772 int (*cs_parse)(struct radeon_cs_parser *p); 1773 1774 /* command emmit functions */ 1775 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1776 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1777 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1778 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1779 struct radeon_semaphore *semaphore, bool emit_wait); 1780 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1781 1782 /* testing functions */ 1783 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1784 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1785 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1786 1787 /* deprecated */ 1788 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1789 }; 1790 1791 /* 1792 * ASIC specific functions. 1793 */ 1794 struct radeon_asic { 1795 int (*init)(struct radeon_device *rdev); 1796 void (*fini)(struct radeon_device *rdev); 1797 int (*resume)(struct radeon_device *rdev); 1798 int (*suspend)(struct radeon_device *rdev); 1799 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1800 int (*asic_reset)(struct radeon_device *rdev); 1801 /* Flush the HDP cache via MMIO */ 1802 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1803 /* check if 3D engine is idle */ 1804 bool (*gui_idle)(struct radeon_device *rdev); 1805 /* wait for mc_idle */ 1806 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1807 /* get the reference clock */ 1808 u32 (*get_xclk)(struct radeon_device *rdev); 1809 /* get the gpu clock counter */ 1810 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1811 /* gart */ 1812 struct { 1813 void (*tlb_flush)(struct radeon_device *rdev); 1814 void (*set_page)(struct radeon_device *rdev, unsigned i, 1815 uint64_t addr, uint32_t flags); 1816 } gart; 1817 struct { 1818 int (*init)(struct radeon_device *rdev); 1819 void (*fini)(struct radeon_device *rdev); 1820 void (*copy_pages)(struct radeon_device *rdev, 1821 struct radeon_ib *ib, 1822 uint64_t pe, uint64_t src, 1823 unsigned count); 1824 void (*write_pages)(struct radeon_device *rdev, 1825 struct radeon_ib *ib, 1826 uint64_t pe, 1827 uint64_t addr, unsigned count, 1828 uint32_t incr, uint32_t flags); 1829 void (*set_pages)(struct radeon_device *rdev, 1830 struct radeon_ib *ib, 1831 uint64_t pe, 1832 uint64_t addr, unsigned count, 1833 uint32_t incr, uint32_t flags); 1834 void (*pad_ib)(struct radeon_ib *ib); 1835 } vm; 1836 /* ring specific callbacks */ 1837 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1838 /* irqs */ 1839 struct { 1840 int (*set)(struct radeon_device *rdev); 1841 int (*process)(struct radeon_device *rdev); 1842 } irq; 1843 /* displays */ 1844 struct { 1845 /* display watermarks */ 1846 void (*bandwidth_update)(struct radeon_device *rdev); 1847 /* get frame count */ 1848 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1849 /* wait for vblank */ 1850 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1851 /* set backlight level */ 1852 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1853 /* get backlight level */ 1854 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1855 /* audio callbacks */ 1856 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1857 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1858 } display; 1859 /* copy functions for bo handling */ 1860 struct { 1861 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1862 uint64_t src_offset, 1863 uint64_t dst_offset, 1864 unsigned num_gpu_pages, 1865 struct reservation_object *resv); 1866 u32 blit_ring_index; 1867 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1868 uint64_t src_offset, 1869 uint64_t dst_offset, 1870 unsigned num_gpu_pages, 1871 struct reservation_object *resv); 1872 u32 dma_ring_index; 1873 /* method used for bo copy */ 1874 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1875 uint64_t src_offset, 1876 uint64_t dst_offset, 1877 unsigned num_gpu_pages, 1878 struct reservation_object *resv); 1879 /* ring used for bo copies */ 1880 u32 copy_ring_index; 1881 } copy; 1882 /* surfaces */ 1883 struct { 1884 int (*set_reg)(struct radeon_device *rdev, int reg, 1885 uint32_t tiling_flags, uint32_t pitch, 1886 uint32_t offset, uint32_t obj_size); 1887 void (*clear_reg)(struct radeon_device *rdev, int reg); 1888 } surface; 1889 /* hotplug detect */ 1890 struct { 1891 void (*init)(struct radeon_device *rdev); 1892 void (*fini)(struct radeon_device *rdev); 1893 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1894 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1895 } hpd; 1896 /* static power management */ 1897 struct { 1898 void (*misc)(struct radeon_device *rdev); 1899 void (*prepare)(struct radeon_device *rdev); 1900 void (*finish)(struct radeon_device *rdev); 1901 void (*init_profile)(struct radeon_device *rdev); 1902 void (*get_dynpm_state)(struct radeon_device *rdev); 1903 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1904 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1905 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1906 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1907 int (*get_pcie_lanes)(struct radeon_device *rdev); 1908 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1909 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1910 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1911 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1912 int (*get_temperature)(struct radeon_device *rdev); 1913 } pm; 1914 /* dynamic power management */ 1915 struct { 1916 int (*init)(struct radeon_device *rdev); 1917 void (*setup_asic)(struct radeon_device *rdev); 1918 int (*enable)(struct radeon_device *rdev); 1919 int (*late_enable)(struct radeon_device *rdev); 1920 void (*disable)(struct radeon_device *rdev); 1921 int (*pre_set_power_state)(struct radeon_device *rdev); 1922 int (*set_power_state)(struct radeon_device *rdev); 1923 void (*post_set_power_state)(struct radeon_device *rdev); 1924 void (*display_configuration_changed)(struct radeon_device *rdev); 1925 void (*fini)(struct radeon_device *rdev); 1926 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1927 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1928 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1929 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1930 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1931 bool (*vblank_too_short)(struct radeon_device *rdev); 1932 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1933 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1934 } dpm; 1935 /* pageflipping */ 1936 struct { 1937 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1938 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1939 } pflip; 1940 }; 1941 1942 /* 1943 * Asic structures 1944 */ 1945 struct r100_asic { 1946 const unsigned *reg_safe_bm; 1947 unsigned reg_safe_bm_size; 1948 u32 hdp_cntl; 1949 }; 1950 1951 struct r300_asic { 1952 const unsigned *reg_safe_bm; 1953 unsigned reg_safe_bm_size; 1954 u32 resync_scratch; 1955 u32 hdp_cntl; 1956 }; 1957 1958 struct r600_asic { 1959 unsigned max_pipes; 1960 unsigned max_tile_pipes; 1961 unsigned max_simds; 1962 unsigned max_backends; 1963 unsigned max_gprs; 1964 unsigned max_threads; 1965 unsigned max_stack_entries; 1966 unsigned max_hw_contexts; 1967 unsigned max_gs_threads; 1968 unsigned sx_max_export_size; 1969 unsigned sx_max_export_pos_size; 1970 unsigned sx_max_export_smx_size; 1971 unsigned sq_num_cf_insts; 1972 unsigned tiling_nbanks; 1973 unsigned tiling_npipes; 1974 unsigned tiling_group_size; 1975 unsigned tile_config; 1976 unsigned backend_map; 1977 unsigned active_simds; 1978 }; 1979 1980 struct rv770_asic { 1981 unsigned max_pipes; 1982 unsigned max_tile_pipes; 1983 unsigned max_simds; 1984 unsigned max_backends; 1985 unsigned max_gprs; 1986 unsigned max_threads; 1987 unsigned max_stack_entries; 1988 unsigned max_hw_contexts; 1989 unsigned max_gs_threads; 1990 unsigned sx_max_export_size; 1991 unsigned sx_max_export_pos_size; 1992 unsigned sx_max_export_smx_size; 1993 unsigned sq_num_cf_insts; 1994 unsigned sx_num_of_sets; 1995 unsigned sc_prim_fifo_size; 1996 unsigned sc_hiz_tile_fifo_size; 1997 unsigned sc_earlyz_tile_fifo_fize; 1998 unsigned tiling_nbanks; 1999 unsigned tiling_npipes; 2000 unsigned tiling_group_size; 2001 unsigned tile_config; 2002 unsigned backend_map; 2003 unsigned active_simds; 2004 }; 2005 2006 struct evergreen_asic { 2007 unsigned num_ses; 2008 unsigned max_pipes; 2009 unsigned max_tile_pipes; 2010 unsigned max_simds; 2011 unsigned max_backends; 2012 unsigned max_gprs; 2013 unsigned max_threads; 2014 unsigned max_stack_entries; 2015 unsigned max_hw_contexts; 2016 unsigned max_gs_threads; 2017 unsigned sx_max_export_size; 2018 unsigned sx_max_export_pos_size; 2019 unsigned sx_max_export_smx_size; 2020 unsigned sq_num_cf_insts; 2021 unsigned sx_num_of_sets; 2022 unsigned sc_prim_fifo_size; 2023 unsigned sc_hiz_tile_fifo_size; 2024 unsigned sc_earlyz_tile_fifo_size; 2025 unsigned tiling_nbanks; 2026 unsigned tiling_npipes; 2027 unsigned tiling_group_size; 2028 unsigned tile_config; 2029 unsigned backend_map; 2030 unsigned active_simds; 2031 }; 2032 2033 struct cayman_asic { 2034 unsigned max_shader_engines; 2035 unsigned max_pipes_per_simd; 2036 unsigned max_tile_pipes; 2037 unsigned max_simds_per_se; 2038 unsigned max_backends_per_se; 2039 unsigned max_texture_channel_caches; 2040 unsigned max_gprs; 2041 unsigned max_threads; 2042 unsigned max_gs_threads; 2043 unsigned max_stack_entries; 2044 unsigned sx_num_of_sets; 2045 unsigned sx_max_export_size; 2046 unsigned sx_max_export_pos_size; 2047 unsigned sx_max_export_smx_size; 2048 unsigned max_hw_contexts; 2049 unsigned sq_num_cf_insts; 2050 unsigned sc_prim_fifo_size; 2051 unsigned sc_hiz_tile_fifo_size; 2052 unsigned sc_earlyz_tile_fifo_size; 2053 2054 unsigned num_shader_engines; 2055 unsigned num_shader_pipes_per_simd; 2056 unsigned num_tile_pipes; 2057 unsigned num_simds_per_se; 2058 unsigned num_backends_per_se; 2059 unsigned backend_disable_mask_per_asic; 2060 unsigned backend_map; 2061 unsigned num_texture_channel_caches; 2062 unsigned mem_max_burst_length_bytes; 2063 unsigned mem_row_size_in_kb; 2064 unsigned shader_engine_tile_size; 2065 unsigned num_gpus; 2066 unsigned multi_gpu_tile_size; 2067 2068 unsigned tile_config; 2069 unsigned active_simds; 2070 }; 2071 2072 struct si_asic { 2073 unsigned max_shader_engines; 2074 unsigned max_tile_pipes; 2075 unsigned max_cu_per_sh; 2076 unsigned max_sh_per_se; 2077 unsigned max_backends_per_se; 2078 unsigned max_texture_channel_caches; 2079 unsigned max_gprs; 2080 unsigned max_gs_threads; 2081 unsigned max_hw_contexts; 2082 unsigned sc_prim_fifo_size_frontend; 2083 unsigned sc_prim_fifo_size_backend; 2084 unsigned sc_hiz_tile_fifo_size; 2085 unsigned sc_earlyz_tile_fifo_size; 2086 2087 unsigned num_tile_pipes; 2088 unsigned backend_enable_mask; 2089 unsigned backend_disable_mask_per_asic; 2090 unsigned backend_map; 2091 unsigned num_texture_channel_caches; 2092 unsigned mem_max_burst_length_bytes; 2093 unsigned mem_row_size_in_kb; 2094 unsigned shader_engine_tile_size; 2095 unsigned num_gpus; 2096 unsigned multi_gpu_tile_size; 2097 2098 unsigned tile_config; 2099 uint32_t tile_mode_array[32]; 2100 uint32_t active_cus; 2101 }; 2102 2103 struct cik_asic { 2104 unsigned max_shader_engines; 2105 unsigned max_tile_pipes; 2106 unsigned max_cu_per_sh; 2107 unsigned max_sh_per_se; 2108 unsigned max_backends_per_se; 2109 unsigned max_texture_channel_caches; 2110 unsigned max_gprs; 2111 unsigned max_gs_threads; 2112 unsigned max_hw_contexts; 2113 unsigned sc_prim_fifo_size_frontend; 2114 unsigned sc_prim_fifo_size_backend; 2115 unsigned sc_hiz_tile_fifo_size; 2116 unsigned sc_earlyz_tile_fifo_size; 2117 2118 unsigned num_tile_pipes; 2119 unsigned backend_enable_mask; 2120 unsigned backend_disable_mask_per_asic; 2121 unsigned backend_map; 2122 unsigned num_texture_channel_caches; 2123 unsigned mem_max_burst_length_bytes; 2124 unsigned mem_row_size_in_kb; 2125 unsigned shader_engine_tile_size; 2126 unsigned num_gpus; 2127 unsigned multi_gpu_tile_size; 2128 2129 unsigned tile_config; 2130 uint32_t tile_mode_array[32]; 2131 uint32_t macrotile_mode_array[16]; 2132 uint32_t active_cus; 2133 }; 2134 2135 union radeon_asic_config { 2136 struct r300_asic r300; 2137 struct r100_asic r100; 2138 struct r600_asic r600; 2139 struct rv770_asic rv770; 2140 struct evergreen_asic evergreen; 2141 struct cayman_asic cayman; 2142 struct si_asic si; 2143 struct cik_asic cik; 2144 }; 2145 2146 /* 2147 * asic initizalization from radeon_asic.c 2148 */ 2149 void radeon_agp_disable(struct radeon_device *rdev); 2150 int radeon_asic_init(struct radeon_device *rdev); 2151 2152 2153 /* 2154 * IOCTL. 2155 */ 2156 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2157 struct drm_file *filp); 2158 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2159 struct drm_file *filp); 2160 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2161 struct drm_file *filp); 2162 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2163 struct drm_file *file_priv); 2164 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2165 struct drm_file *file_priv); 2166 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2167 struct drm_file *file_priv); 2168 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2169 struct drm_file *file_priv); 2170 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2171 struct drm_file *filp); 2172 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2173 struct drm_file *filp); 2174 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2175 struct drm_file *filp); 2176 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2177 struct drm_file *filp); 2178 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2179 struct drm_file *filp); 2180 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2181 struct drm_file *filp); 2182 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2183 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2184 struct drm_file *filp); 2185 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2186 struct drm_file *filp); 2187 2188 /* VRAM scratch page for HDP bug, default vram page */ 2189 struct r600_vram_scratch { 2190 struct radeon_bo *robj; 2191 volatile uint32_t *ptr; 2192 u64 gpu_addr; 2193 }; 2194 2195 /* 2196 * ACPI 2197 */ 2198 struct radeon_atif_notification_cfg { 2199 bool enabled; 2200 int command_code; 2201 }; 2202 2203 struct radeon_atif_notifications { 2204 bool display_switch; 2205 bool expansion_mode_change; 2206 bool thermal_state; 2207 bool forced_power_state; 2208 bool system_power_state; 2209 bool display_conf_change; 2210 bool px_gfx_switch; 2211 bool brightness_change; 2212 bool dgpu_display_event; 2213 }; 2214 2215 struct radeon_atif_functions { 2216 bool system_params; 2217 bool sbios_requests; 2218 bool select_active_disp; 2219 bool lid_state; 2220 bool get_tv_standard; 2221 bool set_tv_standard; 2222 bool get_panel_expansion_mode; 2223 bool set_panel_expansion_mode; 2224 bool temperature_change; 2225 bool graphics_device_types; 2226 }; 2227 2228 struct radeon_atif { 2229 struct radeon_atif_notifications notifications; 2230 struct radeon_atif_functions functions; 2231 struct radeon_atif_notification_cfg notification_cfg; 2232 struct radeon_encoder *encoder_for_bl; 2233 }; 2234 2235 struct radeon_atcs_functions { 2236 bool get_ext_state; 2237 bool pcie_perf_req; 2238 bool pcie_dev_rdy; 2239 bool pcie_bus_width; 2240 }; 2241 2242 struct radeon_atcs { 2243 struct radeon_atcs_functions functions; 2244 }; 2245 2246 /* 2247 * Core structure, functions and helpers. 2248 */ 2249 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2250 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2251 2252 struct radeon_device { 2253 struct device *dev; 2254 struct drm_device *ddev; 2255 struct pci_dev *pdev; 2256 struct rw_semaphore exclusive_lock; 2257 /* ASIC */ 2258 union radeon_asic_config config; 2259 enum radeon_family family; 2260 unsigned long flags; 2261 int usec_timeout; 2262 enum radeon_pll_errata pll_errata; 2263 int num_gb_pipes; 2264 int num_z_pipes; 2265 int disp_priority; 2266 /* BIOS */ 2267 uint8_t *bios; 2268 bool is_atom_bios; 2269 uint16_t bios_header_start; 2270 struct radeon_bo *stollen_vga_memory; 2271 /* Register mmio */ 2272 resource_size_t rmmio_base; 2273 resource_size_t rmmio_size; 2274 /* protects concurrent MM_INDEX/DATA based register access */ 2275 spinlock_t mmio_idx_lock; 2276 /* protects concurrent SMC based register access */ 2277 spinlock_t smc_idx_lock; 2278 /* protects concurrent PLL register access */ 2279 spinlock_t pll_idx_lock; 2280 /* protects concurrent MC register access */ 2281 spinlock_t mc_idx_lock; 2282 /* protects concurrent PCIE register access */ 2283 spinlock_t pcie_idx_lock; 2284 /* protects concurrent PCIE_PORT register access */ 2285 spinlock_t pciep_idx_lock; 2286 /* protects concurrent PIF register access */ 2287 spinlock_t pif_idx_lock; 2288 /* protects concurrent CG register access */ 2289 spinlock_t cg_idx_lock; 2290 /* protects concurrent UVD register access */ 2291 spinlock_t uvd_idx_lock; 2292 /* protects concurrent RCU register access */ 2293 spinlock_t rcu_idx_lock; 2294 /* protects concurrent DIDT register access */ 2295 spinlock_t didt_idx_lock; 2296 /* protects concurrent ENDPOINT (audio) register access */ 2297 spinlock_t end_idx_lock; 2298 void __iomem *rmmio; 2299 radeon_rreg_t mc_rreg; 2300 radeon_wreg_t mc_wreg; 2301 radeon_rreg_t pll_rreg; 2302 radeon_wreg_t pll_wreg; 2303 uint32_t pcie_reg_mask; 2304 radeon_rreg_t pciep_rreg; 2305 radeon_wreg_t pciep_wreg; 2306 /* io port */ 2307 void __iomem *rio_mem; 2308 resource_size_t rio_mem_size; 2309 struct radeon_clock clock; 2310 struct radeon_mc mc; 2311 struct radeon_gart gart; 2312 struct radeon_mode_info mode_info; 2313 struct radeon_scratch scratch; 2314 struct radeon_doorbell doorbell; 2315 struct radeon_mman mman; 2316 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2317 wait_queue_head_t fence_queue; 2318 unsigned fence_context; 2319 struct mutex ring_lock; 2320 struct radeon_ring ring[RADEON_NUM_RINGS]; 2321 bool ib_pool_ready; 2322 struct radeon_sa_manager ring_tmp_bo; 2323 struct radeon_irq irq; 2324 struct radeon_asic *asic; 2325 struct radeon_gem gem; 2326 struct radeon_pm pm; 2327 struct radeon_uvd uvd; 2328 struct radeon_vce vce; 2329 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2330 struct radeon_wb wb; 2331 struct radeon_dummy_page dummy_page; 2332 bool shutdown; 2333 bool suspend; 2334 bool need_dma32; 2335 bool accel_working; 2336 bool fastfb_working; /* IGP feature*/ 2337 bool needs_reset, in_reset; 2338 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2339 const struct firmware *me_fw; /* all family ME firmware */ 2340 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2341 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2342 const struct firmware *mc_fw; /* NI MC firmware */ 2343 const struct firmware *ce_fw; /* SI CE firmware */ 2344 const struct firmware *mec_fw; /* CIK MEC firmware */ 2345 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2346 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2347 const struct firmware *smc_fw; /* SMC firmware */ 2348 const struct firmware *uvd_fw; /* UVD firmware */ 2349 const struct firmware *vce_fw; /* VCE firmware */ 2350 bool new_fw; 2351 struct r600_vram_scratch vram_scratch; 2352 int msi_enabled; /* msi enabled */ 2353 struct r600_ih ih; /* r6/700 interrupt ring */ 2354 struct radeon_rlc rlc; 2355 struct radeon_mec mec; 2356 struct work_struct hotplug_work; 2357 struct work_struct audio_work; 2358 int num_crtc; /* number of crtcs */ 2359 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2360 bool has_uvd; 2361 struct r600_audio audio; /* audio stuff */ 2362 struct notifier_block acpi_nb; 2363 /* only one userspace can use Hyperz features or CMASK at a time */ 2364 struct drm_file *hyperz_filp; 2365 struct drm_file *cmask_filp; 2366 /* i2c buses */ 2367 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2368 /* debugfs */ 2369 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2370 unsigned debugfs_count; 2371 /* virtual memory */ 2372 struct radeon_vm_manager vm_manager; 2373 struct mutex gpu_clock_mutex; 2374 /* memory stats */ 2375 atomic64_t vram_usage; 2376 atomic64_t gtt_usage; 2377 atomic64_t num_bytes_moved; 2378 /* ACPI interface */ 2379 struct radeon_atif atif; 2380 struct radeon_atcs atcs; 2381 /* srbm instance registers */ 2382 struct mutex srbm_mutex; 2383 /* clock, powergating flags */ 2384 u32 cg_flags; 2385 u32 pg_flags; 2386 2387 struct dev_pm_domain vga_pm_domain; 2388 bool have_disp_power_ref; 2389 u32 px_quirk_flags; 2390 2391 /* tracking pinned memory */ 2392 u64 vram_pin_size; 2393 u64 gart_pin_size; 2394 2395 struct mutex mn_lock; 2396 DECLARE_HASHTABLE(mn_hash, 7); 2397 }; 2398 2399 bool radeon_is_px(struct drm_device *dev); 2400 int radeon_device_init(struct radeon_device *rdev, 2401 struct drm_device *ddev, 2402 struct pci_dev *pdev, 2403 uint32_t flags); 2404 void radeon_device_fini(struct radeon_device *rdev); 2405 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2406 2407 #define RADEON_MIN_MMIO_SIZE 0x10000 2408 2409 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2410 bool always_indirect) 2411 { 2412 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2413 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2414 return readl(((void __iomem *)rdev->rmmio) + reg); 2415 else { 2416 unsigned long flags; 2417 uint32_t ret; 2418 2419 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 2420 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 2421 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 2422 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 2423 2424 return ret; 2425 } 2426 } 2427 2428 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2429 bool always_indirect) 2430 { 2431 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2432 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2433 else { 2434 unsigned long flags; 2435 2436 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 2437 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 2438 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 2439 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 2440 } 2441 } 2442 2443 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2444 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2445 2446 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2447 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2448 2449 /* 2450 * Cast helper 2451 */ 2452 extern const struct fence_ops radeon_fence_ops; 2453 2454 static inline struct radeon_fence *to_radeon_fence(struct fence *f) 2455 { 2456 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2457 2458 if (__f->base.ops == &radeon_fence_ops) 2459 return __f; 2460 2461 return NULL; 2462 } 2463 2464 /* 2465 * Registers read & write functions. 2466 */ 2467 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2468 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2469 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2470 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2471 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2472 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2473 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2474 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2475 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2476 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2477 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2478 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2479 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2480 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2481 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2482 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2483 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2484 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2485 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2486 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2487 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2488 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2489 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2490 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2491 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2492 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2493 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2494 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2495 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2496 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2497 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2498 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2499 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2500 #define WREG32_P(reg, val, mask) \ 2501 do { \ 2502 uint32_t tmp_ = RREG32(reg); \ 2503 tmp_ &= (mask); \ 2504 tmp_ |= ((val) & ~(mask)); \ 2505 WREG32(reg, tmp_); \ 2506 } while (0) 2507 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2508 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2509 #define WREG32_PLL_P(reg, val, mask) \ 2510 do { \ 2511 uint32_t tmp_ = RREG32_PLL(reg); \ 2512 tmp_ &= (mask); \ 2513 tmp_ |= ((val) & ~(mask)); \ 2514 WREG32_PLL(reg, tmp_); \ 2515 } while (0) 2516 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2517 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2518 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2519 2520 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2521 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2522 2523 /* 2524 * Indirect registers accessor 2525 */ 2526 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2527 { 2528 unsigned long flags; 2529 uint32_t r; 2530 2531 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2532 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2533 r = RREG32(RADEON_PCIE_DATA); 2534 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2535 return r; 2536 } 2537 2538 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2539 { 2540 unsigned long flags; 2541 2542 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2543 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2544 WREG32(RADEON_PCIE_DATA, (v)); 2545 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2546 } 2547 2548 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2549 { 2550 unsigned long flags; 2551 u32 r; 2552 2553 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2554 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2555 r = RREG32(TN_SMC_IND_DATA_0); 2556 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2557 return r; 2558 } 2559 2560 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2561 { 2562 unsigned long flags; 2563 2564 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2565 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2566 WREG32(TN_SMC_IND_DATA_0, (v)); 2567 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2568 } 2569 2570 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2571 { 2572 unsigned long flags; 2573 u32 r; 2574 2575 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2576 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2577 r = RREG32(R600_RCU_DATA); 2578 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2579 return r; 2580 } 2581 2582 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2583 { 2584 unsigned long flags; 2585 2586 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2587 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2588 WREG32(R600_RCU_DATA, (v)); 2589 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2590 } 2591 2592 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2593 { 2594 unsigned long flags; 2595 u32 r; 2596 2597 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2598 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2599 r = RREG32(EVERGREEN_CG_IND_DATA); 2600 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2601 return r; 2602 } 2603 2604 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2605 { 2606 unsigned long flags; 2607 2608 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2609 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2610 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2611 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2612 } 2613 2614 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2615 { 2616 unsigned long flags; 2617 u32 r; 2618 2619 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2620 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2621 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2622 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2623 return r; 2624 } 2625 2626 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2627 { 2628 unsigned long flags; 2629 2630 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2631 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2632 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2633 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2634 } 2635 2636 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2637 { 2638 unsigned long flags; 2639 u32 r; 2640 2641 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2642 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2643 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2644 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2645 return r; 2646 } 2647 2648 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2649 { 2650 unsigned long flags; 2651 2652 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2653 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2654 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2655 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2656 } 2657 2658 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2659 { 2660 unsigned long flags; 2661 u32 r; 2662 2663 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2664 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2665 r = RREG32(R600_UVD_CTX_DATA); 2666 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2667 return r; 2668 } 2669 2670 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2671 { 2672 unsigned long flags; 2673 2674 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2675 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2676 WREG32(R600_UVD_CTX_DATA, (v)); 2677 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2678 } 2679 2680 2681 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2682 { 2683 unsigned long flags; 2684 u32 r; 2685 2686 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2687 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2688 r = RREG32(CIK_DIDT_IND_DATA); 2689 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2690 return r; 2691 } 2692 2693 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2694 { 2695 unsigned long flags; 2696 2697 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2698 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2699 WREG32(CIK_DIDT_IND_DATA, (v)); 2700 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2701 } 2702 2703 void r100_pll_errata_after_index(struct radeon_device *rdev); 2704 2705 2706 /* 2707 * ASICs helpers. 2708 */ 2709 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2710 (rdev->pdev->device == 0x5969)) 2711 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2712 (rdev->family == CHIP_RV200) || \ 2713 (rdev->family == CHIP_RS100) || \ 2714 (rdev->family == CHIP_RS200) || \ 2715 (rdev->family == CHIP_RV250) || \ 2716 (rdev->family == CHIP_RV280) || \ 2717 (rdev->family == CHIP_RS300)) 2718 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2719 (rdev->family == CHIP_RV350) || \ 2720 (rdev->family == CHIP_R350) || \ 2721 (rdev->family == CHIP_RV380) || \ 2722 (rdev->family == CHIP_R420) || \ 2723 (rdev->family == CHIP_R423) || \ 2724 (rdev->family == CHIP_RV410) || \ 2725 (rdev->family == CHIP_RS400) || \ 2726 (rdev->family == CHIP_RS480)) 2727 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2728 (rdev->ddev->pdev->device == 0x9443) || \ 2729 (rdev->ddev->pdev->device == 0x944B) || \ 2730 (rdev->ddev->pdev->device == 0x9506) || \ 2731 (rdev->ddev->pdev->device == 0x9509) || \ 2732 (rdev->ddev->pdev->device == 0x950F) || \ 2733 (rdev->ddev->pdev->device == 0x689C) || \ 2734 (rdev->ddev->pdev->device == 0x689D)) 2735 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2736 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2737 (rdev->family == CHIP_RS690) || \ 2738 (rdev->family == CHIP_RS740) || \ 2739 (rdev->family >= CHIP_R600)) 2740 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2741 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2742 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2743 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2744 (rdev->flags & RADEON_IS_IGP)) 2745 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2746 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2747 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2748 (rdev->flags & RADEON_IS_IGP)) 2749 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2750 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2751 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2752 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2753 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2754 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2755 (rdev->family == CHIP_MULLINS)) 2756 2757 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2758 (rdev->ddev->pdev->device == 0x6850) || \ 2759 (rdev->ddev->pdev->device == 0x6858) || \ 2760 (rdev->ddev->pdev->device == 0x6859) || \ 2761 (rdev->ddev->pdev->device == 0x6840) || \ 2762 (rdev->ddev->pdev->device == 0x6841) || \ 2763 (rdev->ddev->pdev->device == 0x6842) || \ 2764 (rdev->ddev->pdev->device == 0x6843)) 2765 2766 /* 2767 * BIOS helpers. 2768 */ 2769 #define RBIOS8(i) (rdev->bios[i]) 2770 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2771 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2772 2773 int radeon_combios_init(struct radeon_device *rdev); 2774 void radeon_combios_fini(struct radeon_device *rdev); 2775 int radeon_atombios_init(struct radeon_device *rdev); 2776 void radeon_atombios_fini(struct radeon_device *rdev); 2777 2778 2779 /* 2780 * RING helpers. 2781 */ 2782 2783 /** 2784 * radeon_ring_write - write a value to the ring 2785 * 2786 * @ring: radeon_ring structure holding ring information 2787 * @v: dword (dw) value to write 2788 * 2789 * Write a value to the requested ring buffer (all asics). 2790 */ 2791 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2792 { 2793 if (ring->count_dw <= 0) 2794 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2795 2796 ring->ring[ring->wptr++] = v; 2797 ring->wptr &= ring->ptr_mask; 2798 ring->count_dw--; 2799 ring->ring_free_dw--; 2800 } 2801 2802 /* 2803 * ASICs macro. 2804 */ 2805 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2806 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2807 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2808 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2809 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2810 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2811 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2812 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2813 #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) 2814 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2815 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2816 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2817 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2818 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2819 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2820 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2821 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2822 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2823 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2824 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2825 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2826 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2827 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2828 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2829 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2830 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2831 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2832 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2833 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2834 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2835 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2836 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2837 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2838 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2839 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2840 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2841 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2842 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2843 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2844 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2845 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2846 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2847 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2848 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2849 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2850 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2851 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2852 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2853 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2854 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2855 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2856 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2857 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2858 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2859 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2860 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2861 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2862 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2863 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2864 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2865 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2866 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2867 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2868 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2869 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2870 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2871 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2872 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2873 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2874 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2875 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2876 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2877 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2878 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2879 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2880 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2881 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2882 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2883 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2884 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2885 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2886 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2887 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2888 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2889 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2890 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2891 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2892 2893 /* Common functions */ 2894 /* AGP */ 2895 extern int radeon_gpu_reset(struct radeon_device *rdev); 2896 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2897 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2898 extern void radeon_agp_disable(struct radeon_device *rdev); 2899 extern int radeon_modeset_init(struct radeon_device *rdev); 2900 extern void radeon_modeset_fini(struct radeon_device *rdev); 2901 extern bool radeon_card_posted(struct radeon_device *rdev); 2902 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2903 extern void radeon_update_display_priority(struct radeon_device *rdev); 2904 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2905 extern void radeon_scratch_init(struct radeon_device *rdev); 2906 extern void radeon_wb_fini(struct radeon_device *rdev); 2907 extern int radeon_wb_init(struct radeon_device *rdev); 2908 extern void radeon_wb_disable(struct radeon_device *rdev); 2909 extern void radeon_surface_init(struct radeon_device *rdev); 2910 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2911 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2912 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2913 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2914 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2915 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2916 uint32_t flags); 2917 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2918 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2919 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2920 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2921 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2922 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2923 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2924 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2925 const u32 *registers, 2926 const u32 array_size); 2927 2928 /* 2929 * vm 2930 */ 2931 int radeon_vm_manager_init(struct radeon_device *rdev); 2932 void radeon_vm_manager_fini(struct radeon_device *rdev); 2933 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2934 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2935 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2936 struct radeon_vm *vm, 2937 struct list_head *head); 2938 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2939 struct radeon_vm *vm, int ring); 2940 void radeon_vm_flush(struct radeon_device *rdev, 2941 struct radeon_vm *vm, 2942 int ring); 2943 void radeon_vm_fence(struct radeon_device *rdev, 2944 struct radeon_vm *vm, 2945 struct radeon_fence *fence); 2946 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2947 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2948 struct radeon_vm *vm); 2949 int radeon_vm_clear_freed(struct radeon_device *rdev, 2950 struct radeon_vm *vm); 2951 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2952 struct radeon_vm *vm); 2953 int radeon_vm_bo_update(struct radeon_device *rdev, 2954 struct radeon_bo_va *bo_va, 2955 struct ttm_mem_reg *mem); 2956 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2957 struct radeon_bo *bo); 2958 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2959 struct radeon_bo *bo); 2960 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2961 struct radeon_vm *vm, 2962 struct radeon_bo *bo); 2963 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2964 struct radeon_bo_va *bo_va, 2965 uint64_t offset, 2966 uint32_t flags); 2967 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2968 struct radeon_bo_va *bo_va); 2969 2970 /* audio */ 2971 void r600_audio_update_hdmi(struct work_struct *work); 2972 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2973 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2974 void r600_audio_enable(struct radeon_device *rdev, 2975 struct r600_audio_pin *pin, 2976 bool enable); 2977 void dce6_audio_enable(struct radeon_device *rdev, 2978 struct r600_audio_pin *pin, 2979 bool enable); 2980 2981 /* 2982 * R600 vram scratch functions 2983 */ 2984 int r600_vram_scratch_init(struct radeon_device *rdev); 2985 void r600_vram_scratch_fini(struct radeon_device *rdev); 2986 2987 /* 2988 * r600 cs checking helper 2989 */ 2990 unsigned r600_mip_minify(unsigned size, unsigned level); 2991 bool r600_fmt_is_valid_color(u32 format); 2992 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2993 int r600_fmt_get_blocksize(u32 format); 2994 int r600_fmt_get_nblocksx(u32 format, u32 w); 2995 int r600_fmt_get_nblocksy(u32 format, u32 h); 2996 2997 /* 2998 * r600 functions used by radeon_encoder.c 2999 */ 3000 struct radeon_hdmi_acr { 3001 u32 clock; 3002 3003 int n_32khz; 3004 int cts_32khz; 3005 3006 int n_44_1khz; 3007 int cts_44_1khz; 3008 3009 int n_48khz; 3010 int cts_48khz; 3011 3012 }; 3013 3014 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 3015 3016 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 3017 u32 tiling_pipe_num, 3018 u32 max_rb_num, 3019 u32 total_max_rb_num, 3020 u32 enabled_rb_mask); 3021 3022 /* 3023 * evergreen functions used by radeon_encoder.c 3024 */ 3025 3026 extern int ni_init_microcode(struct radeon_device *rdev); 3027 extern int ni_mc_load_microcode(struct radeon_device *rdev); 3028 3029 /* radeon_acpi.c */ 3030 #if defined(CONFIG_ACPI) 3031 extern int radeon_acpi_init(struct radeon_device *rdev); 3032 extern void radeon_acpi_fini(struct radeon_device *rdev); 3033 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 3034 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 3035 u8 perf_req, bool advertise); 3036 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 3037 #else 3038 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 3039 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 3040 #endif 3041 3042 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3043 struct radeon_cs_packet *pkt, 3044 unsigned idx); 3045 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3046 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3047 struct radeon_cs_packet *pkt); 3048 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3049 struct radeon_cs_reloc **cs_reloc, 3050 int nomm); 3051 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3052 uint32_t *vline_start_end, 3053 uint32_t *vline_status); 3054 3055 #include "radeon_object.h" 3056 3057 #endif 3058