1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #ifndef R600D_H 28 #define R600D_H 29 30 #define CP_PACKET2 0x80000000 31 #define PACKET2_PAD_SHIFT 0 32 #define PACKET2_PAD_MASK (0x3fffffff << 0) 33 34 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 35 36 #define R6XX_MAX_SH_GPRS 256 37 #define R6XX_MAX_TEMP_GPRS 16 38 #define R6XX_MAX_SH_THREADS 256 39 #define R6XX_MAX_SH_STACK_ENTRIES 4096 40 #define R6XX_MAX_BACKENDS 8 41 #define R6XX_MAX_BACKENDS_MASK 0xff 42 #define R6XX_MAX_SIMDS 8 43 #define R6XX_MAX_SIMDS_MASK 0xff 44 #define R6XX_MAX_PIPES 8 45 #define R6XX_MAX_PIPES_MASK 0xff 46 47 /* PTE flags */ 48 #define PTE_VALID (1 << 0) 49 #define PTE_SYSTEM (1 << 1) 50 #define PTE_SNOOPED (1 << 2) 51 #define PTE_READABLE (1 << 5) 52 #define PTE_WRITEABLE (1 << 6) 53 54 /* tiling bits */ 55 #define ARRAY_LINEAR_GENERAL 0x00000000 56 #define ARRAY_LINEAR_ALIGNED 0x00000001 57 #define ARRAY_1D_TILED_THIN1 0x00000002 58 #define ARRAY_2D_TILED_THIN1 0x00000004 59 60 /* Registers */ 61 #define ARB_POP 0x2418 62 #define ENABLE_TC128 (1 << 30) 63 #define ARB_GDEC_RD_CNTL 0x246C 64 65 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 66 #define CC_RB_BACKEND_DISABLE 0x98F4 67 #define BACKEND_DISABLE(x) ((x) << 16) 68 69 #define R_028808_CB_COLOR_CONTROL 0x28808 70 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) 71 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) 72 #define C_028808_SPECIAL_OP 0xFFFFFF8F 73 #define V_028808_SPECIAL_NORMAL 0x00 74 #define V_028808_SPECIAL_DISABLE 0x01 75 #define V_028808_SPECIAL_RESOLVE_BOX 0x07 76 77 #define CB_COLOR0_BASE 0x28040 78 #define CB_COLOR1_BASE 0x28044 79 #define CB_COLOR2_BASE 0x28048 80 #define CB_COLOR3_BASE 0x2804C 81 #define CB_COLOR4_BASE 0x28050 82 #define CB_COLOR5_BASE 0x28054 83 #define CB_COLOR6_BASE 0x28058 84 #define CB_COLOR7_BASE 0x2805C 85 #define CB_COLOR7_FRAG 0x280FC 86 87 #define CB_COLOR0_SIZE 0x28060 88 #define CB_COLOR0_VIEW 0x28080 89 #define R_028080_CB_COLOR0_VIEW 0x028080 90 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) 91 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) 92 #define C_028080_SLICE_START 0xFFFFF800 93 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) 94 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 95 #define C_028080_SLICE_MAX 0xFF001FFF 96 #define R_028084_CB_COLOR1_VIEW 0x028084 97 #define R_028088_CB_COLOR2_VIEW 0x028088 98 #define R_02808C_CB_COLOR3_VIEW 0x02808C 99 #define R_028090_CB_COLOR4_VIEW 0x028090 100 #define R_028094_CB_COLOR5_VIEW 0x028094 101 #define R_028098_CB_COLOR6_VIEW 0x028098 102 #define R_02809C_CB_COLOR7_VIEW 0x02809C 103 #define R_028100_CB_COLOR0_MASK 0x028100 104 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) 105 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) 106 #define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 107 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) 108 #define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) 109 #define C_028100_FMASK_TILE_MAX 0x00000FFF 110 #define R_028104_CB_COLOR1_MASK 0x028104 111 #define R_028108_CB_COLOR2_MASK 0x028108 112 #define R_02810C_CB_COLOR3_MASK 0x02810C 113 #define R_028110_CB_COLOR4_MASK 0x028110 114 #define R_028114_CB_COLOR5_MASK 0x028114 115 #define R_028118_CB_COLOR6_MASK 0x028118 116 #define R_02811C_CB_COLOR7_MASK 0x02811C 117 #define CB_COLOR0_INFO 0x280a0 118 # define CB_FORMAT(x) ((x) << 2) 119 # define CB_ARRAY_MODE(x) ((x) << 8) 120 # define CB_SOURCE_FORMAT(x) ((x) << 27) 121 # define CB_SF_EXPORT_FULL 0 122 # define CB_SF_EXPORT_NORM 1 123 #define CB_COLOR0_TILE 0x280c0 124 #define CB_COLOR0_FRAG 0x280e0 125 #define CB_COLOR0_MASK 0x28100 126 127 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 128 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 129 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 130 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 131 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 132 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 133 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 134 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 135 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 136 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 137 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 138 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 139 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 140 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 141 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 142 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 143 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 144 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 145 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 146 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 147 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 148 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 149 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 150 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 151 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 152 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 153 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 154 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 155 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 156 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 157 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 158 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 159 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 160 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 161 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 162 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 163 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 164 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 165 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 166 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 167 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 168 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 169 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 170 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 171 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 172 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 173 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 174 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 175 176 #define CONFIG_MEMSIZE 0x5428 177 #define CONFIG_CNTL 0x5424 178 #define CP_STALLED_STAT1 0x8674 179 #define CP_STALLED_STAT2 0x8678 180 #define CP_BUSY_STAT 0x867C 181 #define CP_STAT 0x8680 182 #define CP_COHER_BASE 0x85F8 183 #define CP_DEBUG 0xC1FC 184 #define R_0086D8_CP_ME_CNTL 0x86D8 185 #define S_0086D8_CP_PFP_HALT(x) (((x) & 1)<<26) 186 #define C_0086D8_CP_PFP_HALT(x) ((x) & 0xFBFFFFFF) 187 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 188 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 189 #define CP_ME_RAM_DATA 0xC160 190 #define CP_ME_RAM_RADDR 0xC158 191 #define CP_ME_RAM_WADDR 0xC15C 192 #define CP_MEQ_THRESHOLDS 0x8764 193 #define MEQ_END(x) ((x) << 16) 194 #define ROQ_END(x) ((x) << 24) 195 #define CP_PERFMON_CNTL 0x87FC 196 #define CP_PFP_UCODE_ADDR 0xC150 197 #define CP_PFP_UCODE_DATA 0xC154 198 #define CP_QUEUE_THRESHOLDS 0x8760 199 #define ROQ_IB1_START(x) ((x) << 0) 200 #define ROQ_IB2_START(x) ((x) << 8) 201 #define CP_RB_BASE 0xC100 202 #define CP_RB_CNTL 0xC104 203 #define RB_BUFSZ(x) ((x) << 0) 204 #define RB_BLKSZ(x) ((x) << 8) 205 #define RB_NO_UPDATE (1 << 27) 206 #define RB_RPTR_WR_ENA (1 << 31) 207 #define BUF_SWAP_32BIT (2 << 16) 208 #define CP_RB_RPTR 0x8700 209 #define CP_RB_RPTR_ADDR 0xC10C 210 #define RB_RPTR_SWAP(x) ((x) << 0) 211 #define CP_RB_RPTR_ADDR_HI 0xC110 212 #define CP_RB_RPTR_WR 0xC108 213 #define CP_RB_WPTR 0xC114 214 #define CP_RB_WPTR_ADDR 0xC118 215 #define CP_RB_WPTR_ADDR_HI 0xC11C 216 #define CP_RB_WPTR_DELAY 0x8704 217 #define CP_ROQ_IB1_STAT 0x8784 218 #define CP_ROQ_IB2_STAT 0x8788 219 #define CP_SEM_WAIT_TIMER 0x85BC 220 221 #define DB_DEBUG 0x9830 222 #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 223 #define DB_DEPTH_BASE 0x2800C 224 #define DB_HTILE_DATA_BASE 0x28014 225 #define DB_HTILE_SURFACE 0x28D24 226 #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) 227 #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 228 #define C_028D24_HTILE_WIDTH 0xFFFFFFFE 229 #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 230 #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 231 #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD 232 #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) 233 #define DB_WATERMARKS 0x9838 234 #define DEPTH_FREE(x) ((x) << 0) 235 #define DEPTH_FLUSH(x) ((x) << 5) 236 #define DEPTH_PENDING_FREE(x) ((x) << 15) 237 #define DEPTH_CACHELINE_FREE(x) ((x) << 20) 238 239 #define DCP_TILING_CONFIG 0x6CA0 240 #define PIPE_TILING(x) ((x) << 1) 241 #define BANK_TILING(x) ((x) << 4) 242 #define GROUP_SIZE(x) ((x) << 6) 243 #define ROW_TILING(x) ((x) << 8) 244 #define BANK_SWAPS(x) ((x) << 11) 245 #define SAMPLE_SPLIT(x) ((x) << 14) 246 #define BACKEND_MAP(x) ((x) << 16) 247 248 #define GB_TILING_CONFIG 0x98F0 249 #define PIPE_TILING__SHIFT 1 250 #define PIPE_TILING__MASK 0x0000000e 251 252 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 253 #define INACTIVE_QD_PIPES(x) ((x) << 8) 254 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 255 #define INACTIVE_SIMDS(x) ((x) << 16) 256 #define INACTIVE_SIMDS_MASK 0x00FF0000 257 258 #define SQ_CONFIG 0x8c00 259 # define VC_ENABLE (1 << 0) 260 # define EXPORT_SRC_C (1 << 1) 261 # define DX9_CONSTS (1 << 2) 262 # define ALU_INST_PREFER_VECTOR (1 << 3) 263 # define DX10_CLAMP (1 << 4) 264 # define CLAUSE_SEQ_PRIO(x) ((x) << 8) 265 # define PS_PRIO(x) ((x) << 24) 266 # define VS_PRIO(x) ((x) << 26) 267 # define GS_PRIO(x) ((x) << 28) 268 # define ES_PRIO(x) ((x) << 30) 269 #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 270 # define NUM_PS_GPRS(x) ((x) << 0) 271 # define NUM_VS_GPRS(x) ((x) << 16) 272 # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 273 #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 274 # define NUM_GS_GPRS(x) ((x) << 0) 275 # define NUM_ES_GPRS(x) ((x) << 16) 276 #define SQ_THREAD_RESOURCE_MGMT 0x8c0c 277 # define NUM_PS_THREADS(x) ((x) << 0) 278 # define NUM_VS_THREADS(x) ((x) << 8) 279 # define NUM_GS_THREADS(x) ((x) << 16) 280 # define NUM_ES_THREADS(x) ((x) << 24) 281 #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 282 # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 283 # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 284 #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 285 # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 286 # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 287 #define SQ_ESGS_RING_BASE 0x8c40 288 #define SQ_GSVS_RING_BASE 0x8c48 289 #define SQ_ESTMP_RING_BASE 0x8c50 290 #define SQ_GSTMP_RING_BASE 0x8c58 291 #define SQ_VSTMP_RING_BASE 0x8c60 292 #define SQ_PSTMP_RING_BASE 0x8c68 293 #define SQ_FBUF_RING_BASE 0x8c70 294 #define SQ_REDUC_RING_BASE 0x8c78 295 296 #define GRBM_CNTL 0x8000 297 # define GRBM_READ_TIMEOUT(x) ((x) << 0) 298 #define GRBM_STATUS 0x8010 299 #define CMDFIFO_AVAIL_MASK 0x0000001F 300 #define GUI_ACTIVE (1<<31) 301 #define GRBM_STATUS2 0x8014 302 #define GRBM_SOFT_RESET 0x8020 303 #define SOFT_RESET_CP (1<<0) 304 305 #define CG_THERMAL_STATUS 0x7F4 306 #define ASIC_T(x) ((x) << 0) 307 #define ASIC_T_MASK 0x1FF 308 #define ASIC_T_SHIFT 0 309 310 #define HDP_HOST_PATH_CNTL 0x2C00 311 #define HDP_NONSURFACE_BASE 0x2C04 312 #define HDP_NONSURFACE_INFO 0x2C08 313 #define HDP_NONSURFACE_SIZE 0x2C0C 314 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 315 #define HDP_TILING_CONFIG 0x2F3C 316 #define HDP_DEBUG1 0x2F34 317 318 #define MC_VM_AGP_TOP 0x2184 319 #define MC_VM_AGP_BOT 0x2188 320 #define MC_VM_AGP_BASE 0x218C 321 #define MC_VM_FB_LOCATION 0x2180 322 #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 323 #define ENABLE_L1_TLB (1 << 0) 324 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 325 #define ENABLE_L1_STRICT_ORDERING (1 << 2) 326 #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 327 #define SYSTEM_ACCESS_MODE_SHIFT 6 328 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 329 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 330 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 331 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 332 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 333 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 334 #define ENABLE_SEMAPHORE_MODE (1 << 10) 335 #define ENABLE_WAIT_L2_QUERY (1 << 11) 336 #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 337 #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 338 #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 339 #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 340 #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 341 #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 342 #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 343 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 344 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 345 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 346 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 347 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 348 #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 349 #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 350 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 351 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 352 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 353 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 354 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 355 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 356 #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 357 #define LOGICAL_PAGE_NUMBER_SHIFT 0 358 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 359 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 360 361 #define PA_CL_ENHANCE 0x8A14 362 #define CLIP_VTX_REORDER_ENA (1 << 0) 363 #define NUM_CLIP_SEQ(x) ((x) << 1) 364 #define PA_SC_AA_CONFIG 0x28C04 365 #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 366 #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 367 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 368 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 369 #define S0_X(x) ((x) << 0) 370 #define S0_Y(x) ((x) << 4) 371 #define S1_X(x) ((x) << 8) 372 #define S1_Y(x) ((x) << 12) 373 #define S2_X(x) ((x) << 16) 374 #define S2_Y(x) ((x) << 20) 375 #define S3_X(x) ((x) << 24) 376 #define S3_Y(x) ((x) << 28) 377 #define S4_X(x) ((x) << 0) 378 #define S4_Y(x) ((x) << 4) 379 #define S5_X(x) ((x) << 8) 380 #define S5_Y(x) ((x) << 12) 381 #define S6_X(x) ((x) << 16) 382 #define S6_Y(x) ((x) << 20) 383 #define S7_X(x) ((x) << 24) 384 #define S7_Y(x) ((x) << 28) 385 #define PA_SC_CLIPRECT_RULE 0x2820c 386 #define PA_SC_ENHANCE 0x8BF0 387 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 388 #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 389 #define PA_SC_LINE_STIPPLE 0x28A0C 390 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 391 #define PA_SC_MODE_CNTL 0x28A4C 392 #define PA_SC_MULTI_CHIP_CNTL 0x8B20 393 394 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 395 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 396 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 397 398 #define PCIE_PORT_INDEX 0x0038 399 #define PCIE_PORT_DATA 0x003C 400 401 #define CHMAP 0x2004 402 #define NOOFCHAN_SHIFT 12 403 #define NOOFCHAN_MASK 0x00003000 404 405 #define RAMCFG 0x2408 406 #define NOOFBANK_SHIFT 0 407 #define NOOFBANK_MASK 0x00000001 408 #define NOOFRANK_SHIFT 1 409 #define NOOFRANK_MASK 0x00000002 410 #define NOOFROWS_SHIFT 2 411 #define NOOFROWS_MASK 0x0000001C 412 #define NOOFCOLS_SHIFT 5 413 #define NOOFCOLS_MASK 0x00000060 414 #define CHANSIZE_SHIFT 7 415 #define CHANSIZE_MASK 0x00000080 416 #define BURSTLENGTH_SHIFT 8 417 #define BURSTLENGTH_MASK 0x00000100 418 #define CHANSIZE_OVERRIDE (1 << 10) 419 420 #define SCRATCH_REG0 0x8500 421 #define SCRATCH_REG1 0x8504 422 #define SCRATCH_REG2 0x8508 423 #define SCRATCH_REG3 0x850C 424 #define SCRATCH_REG4 0x8510 425 #define SCRATCH_REG5 0x8514 426 #define SCRATCH_REG6 0x8518 427 #define SCRATCH_REG7 0x851C 428 #define SCRATCH_UMSK 0x8540 429 #define SCRATCH_ADDR 0x8544 430 431 #define SPI_CONFIG_CNTL 0x9100 432 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 433 #define DISABLE_INTERP_1 (1 << 5) 434 #define SPI_CONFIG_CNTL_1 0x913C 435 #define VTX_DONE_DELAY(x) ((x) << 0) 436 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 437 #define SPI_INPUT_Z 0x286D8 438 #define SPI_PS_IN_CONTROL_0 0x286CC 439 #define NUM_INTERP(x) ((x)<<0) 440 #define POSITION_ENA (1<<8) 441 #define POSITION_CENTROID (1<<9) 442 #define POSITION_ADDR(x) ((x)<<10) 443 #define PARAM_GEN(x) ((x)<<15) 444 #define PARAM_GEN_ADDR(x) ((x)<<19) 445 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 446 #define PERSP_GRADIENT_ENA (1<<28) 447 #define LINEAR_GRADIENT_ENA (1<<29) 448 #define POSITION_SAMPLE (1<<30) 449 #define BARYC_AT_SAMPLE_ENA (1<<31) 450 #define SPI_PS_IN_CONTROL_1 0x286D0 451 #define GEN_INDEX_PIX (1<<0) 452 #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 453 #define FRONT_FACE_ENA (1<<8) 454 #define FRONT_FACE_CHAN(x) ((x)<<9) 455 #define FRONT_FACE_ALL_BITS (1<<11) 456 #define FRONT_FACE_ADDR(x) ((x)<<12) 457 #define FOG_ADDR(x) ((x)<<17) 458 #define FIXED_PT_POSITION_ENA (1<<24) 459 #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 460 461 #define SQ_MS_FIFO_SIZES 0x8CF0 462 #define CACHE_FIFO_SIZE(x) ((x) << 0) 463 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 464 #define DONE_FIFO_HIWATER(x) ((x) << 16) 465 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 466 #define SQ_PGM_START_ES 0x28880 467 #define SQ_PGM_START_FS 0x28894 468 #define SQ_PGM_START_GS 0x2886C 469 #define SQ_PGM_START_PS 0x28840 470 #define SQ_PGM_RESOURCES_PS 0x28850 471 #define SQ_PGM_EXPORTS_PS 0x28854 472 #define SQ_PGM_CF_OFFSET_PS 0x288cc 473 #define SQ_PGM_START_VS 0x28858 474 #define SQ_PGM_RESOURCES_VS 0x28868 475 #define SQ_PGM_CF_OFFSET_VS 0x288d0 476 477 #define SQ_VTX_CONSTANT_WORD0_0 0x30000 478 #define SQ_VTX_CONSTANT_WORD1_0 0x30004 479 #define SQ_VTX_CONSTANT_WORD2_0 0x30008 480 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 481 # define SQ_VTXC_STRIDE(x) ((x) << 8) 482 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 483 # define SQ_ENDIAN_NONE 0 484 # define SQ_ENDIAN_8IN16 1 485 # define SQ_ENDIAN_8IN32 2 486 #define SQ_VTX_CONSTANT_WORD3_0 0x3000c 487 #define SQ_VTX_CONSTANT_WORD6_0 0x38018 488 #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 489 #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 490 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 491 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 492 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 493 #define SQ_TEX_VTX_VALID_BUFFER 0x3 494 495 496 #define SX_MISC 0x28350 497 #define SX_MEMORY_EXPORT_BASE 0x9010 498 #define SX_DEBUG_1 0x9054 499 #define SMX_EVENT_RELEASE (1 << 0) 500 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 501 502 #define TA_CNTL_AUX 0x9508 503 #define DISABLE_CUBE_WRAP (1 << 0) 504 #define DISABLE_CUBE_ANISO (1 << 1) 505 #define SYNC_GRADIENT (1 << 24) 506 #define SYNC_WALKER (1 << 25) 507 #define SYNC_ALIGNER (1 << 26) 508 #define BILINEAR_PRECISION_6_BIT (0 << 31) 509 #define BILINEAR_PRECISION_8_BIT (1 << 31) 510 511 #define TC_CNTL 0x9608 512 #define TC_L2_SIZE(x) ((x)<<5) 513 #define L2_DISABLE_LATE_HIT (1<<9) 514 515 #define VC_ENHANCE 0x9714 516 517 #define VGT_CACHE_INVALIDATION 0x88C4 518 #define CACHE_INVALIDATION(x) ((x)<<0) 519 #define VC_ONLY 0 520 #define TC_ONLY 1 521 #define VC_AND_TC 2 522 #define VGT_DMA_BASE 0x287E8 523 #define VGT_DMA_BASE_HI 0x287E4 524 #define VGT_ES_PER_GS 0x88CC 525 #define VGT_GS_PER_ES 0x88C8 526 #define VGT_GS_PER_VS 0x88E8 527 #define VGT_GS_VERTEX_REUSE 0x88D4 528 #define VGT_PRIMITIVE_TYPE 0x8958 529 #define VGT_NUM_INSTANCES 0x8974 530 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 531 #define DEALLOC_DIST_MASK 0x0000007F 532 #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 533 #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 534 #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 535 #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 536 #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 537 #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 538 #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 539 #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 540 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 541 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 542 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 543 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 544 #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 545 #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 546 #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 547 #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 548 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 549 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 550 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 551 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 552 553 #define VGT_STRMOUT_EN 0x28AB0 554 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 555 #define VTX_REUSE_DEPTH_MASK 0x000000FF 556 #define VGT_EVENT_INITIATOR 0x28a90 557 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 558 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 559 560 #define VM_CONTEXT0_CNTL 0x1410 561 #define ENABLE_CONTEXT (1 << 0) 562 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 563 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 564 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 565 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 566 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 567 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 568 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 569 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 570 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 571 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 572 #define RESPONSE_TYPE_MASK 0x000000F0 573 #define RESPONSE_TYPE_SHIFT 4 574 #define VM_L2_CNTL 0x1400 575 #define ENABLE_L2_CACHE (1 << 0) 576 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 577 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 578 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 579 #define VM_L2_CNTL2 0x1404 580 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 581 #define INVALIDATE_L2_CACHE (1 << 1) 582 #define VM_L2_CNTL3 0x1408 583 #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 584 #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 585 #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 586 #define VM_L2_STATUS 0x140C 587 #define L2_BUSY (1 << 0) 588 589 #define WAIT_UNTIL 0x8040 590 #define WAIT_2D_IDLE_bit (1 << 14) 591 #define WAIT_3D_IDLE_bit (1 << 15) 592 #define WAIT_2D_IDLECLEAN_bit (1 << 16) 593 #define WAIT_3D_IDLECLEAN_bit (1 << 17) 594 595 /* async DMA */ 596 #define DMA_TILING_CONFIG 0x3ec4 597 #define DMA_CONFIG 0x3e4c 598 599 #define DMA_RB_CNTL 0xd000 600 # define DMA_RB_ENABLE (1 << 0) 601 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 602 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 603 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 604 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 605 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 606 #define DMA_RB_BASE 0xd004 607 #define DMA_RB_RPTR 0xd008 608 #define DMA_RB_WPTR 0xd00c 609 610 #define DMA_RB_RPTR_ADDR_HI 0xd01c 611 #define DMA_RB_RPTR_ADDR_LO 0xd020 612 613 #define DMA_IB_CNTL 0xd024 614 # define DMA_IB_ENABLE (1 << 0) 615 # define DMA_IB_SWAP_ENABLE (1 << 4) 616 #define DMA_IB_RPTR 0xd028 617 #define DMA_CNTL 0xd02c 618 # define TRAP_ENABLE (1 << 0) 619 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 620 # define SEM_WAIT_INT_ENABLE (1 << 2) 621 # define DATA_SWAP_ENABLE (1 << 3) 622 # define FENCE_SWAP_ENABLE (1 << 4) 623 # define CTXEMPTY_INT_ENABLE (1 << 28) 624 #define DMA_STATUS_REG 0xd034 625 # define DMA_IDLE (1 << 0) 626 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 627 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 628 #define DMA_MODE 0xd0bc 629 630 /* async DMA packets */ 631 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 632 (((t) & 0x1) << 23) | \ 633 (((s) & 0x1) << 22) | \ 634 (((n) & 0xFFFF) << 0)) 635 /* async DMA Packet types */ 636 #define DMA_PACKET_WRITE 0x2 637 #define DMA_PACKET_COPY 0x3 638 #define DMA_PACKET_INDIRECT_BUFFER 0x4 639 #define DMA_PACKET_SEMAPHORE 0x5 640 #define DMA_PACKET_FENCE 0x6 641 #define DMA_PACKET_TRAP 0x7 642 #define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */ 643 #define DMA_PACKET_NOP 0xf 644 645 #define IH_RB_CNTL 0x3e00 646 # define IH_RB_ENABLE (1 << 0) 647 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 648 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 649 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 650 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 651 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 652 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 653 #define IH_RB_BASE 0x3e04 654 #define IH_RB_RPTR 0x3e08 655 #define IH_RB_WPTR 0x3e0c 656 # define RB_OVERFLOW (1 << 0) 657 # define WPTR_OFFSET_MASK 0x3fffc 658 #define IH_RB_WPTR_ADDR_HI 0x3e10 659 #define IH_RB_WPTR_ADDR_LO 0x3e14 660 #define IH_CNTL 0x3e18 661 # define ENABLE_INTR (1 << 0) 662 # define IH_MC_SWAP(x) ((x) << 1) 663 # define IH_MC_SWAP_NONE 0 664 # define IH_MC_SWAP_16BIT 1 665 # define IH_MC_SWAP_32BIT 2 666 # define IH_MC_SWAP_64BIT 3 667 # define RPTR_REARM (1 << 4) 668 # define MC_WRREQ_CREDIT(x) ((x) << 15) 669 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 670 671 #define RLC_CNTL 0x3f00 672 # define RLC_ENABLE (1 << 0) 673 #define RLC_HB_BASE 0x3f10 674 #define RLC_HB_CNTL 0x3f0c 675 #define RLC_HB_RPTR 0x3f20 676 #define RLC_HB_WPTR 0x3f1c 677 #define RLC_HB_WPTR_LSB_ADDR 0x3f14 678 #define RLC_HB_WPTR_MSB_ADDR 0x3f18 679 #define RLC_GPU_CLOCK_COUNT_LSB 0x3f38 680 #define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c 681 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40 682 #define RLC_MC_CNTL 0x3f44 683 #define RLC_UCODE_CNTL 0x3f48 684 #define RLC_UCODE_ADDR 0x3f2c 685 #define RLC_UCODE_DATA 0x3f30 686 687 #define SRBM_SOFT_RESET 0xe60 688 # define SOFT_RESET_DMA (1 << 12) 689 # define SOFT_RESET_RLC (1 << 13) 690 # define SOFT_RESET_UVD (1 << 18) 691 # define RV770_SOFT_RESET_DMA (1 << 20) 692 693 #define CP_INT_CNTL 0xc124 694 # define CNTX_BUSY_INT_ENABLE (1 << 19) 695 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 696 # define SCRATCH_INT_ENABLE (1 << 25) 697 # define TIME_STAMP_INT_ENABLE (1 << 26) 698 # define IB2_INT_ENABLE (1 << 29) 699 # define IB1_INT_ENABLE (1 << 30) 700 # define RB_INT_ENABLE (1 << 31) 701 #define CP_INT_STATUS 0xc128 702 # define SCRATCH_INT_STAT (1 << 25) 703 # define TIME_STAMP_INT_STAT (1 << 26) 704 # define IB2_INT_STAT (1 << 29) 705 # define IB1_INT_STAT (1 << 30) 706 # define RB_INT_STAT (1 << 31) 707 708 #define GRBM_INT_CNTL 0x8060 709 # define RDERR_INT_ENABLE (1 << 0) 710 # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) 711 # define GUI_IDLE_INT_ENABLE (1 << 19) 712 713 #define INTERRUPT_CNTL 0x5468 714 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 715 # define IH_DUMMY_RD_EN (1 << 1) 716 # define IH_REQ_NONSNOOP_EN (1 << 3) 717 # define GEN_IH_INT_EN (1 << 8) 718 #define INTERRUPT_CNTL2 0x546c 719 720 #define D1MODE_VBLANK_STATUS 0x6534 721 #define D2MODE_VBLANK_STATUS 0x6d34 722 # define DxMODE_VBLANK_OCCURRED (1 << 0) 723 # define DxMODE_VBLANK_ACK (1 << 4) 724 # define DxMODE_VBLANK_STAT (1 << 12) 725 # define DxMODE_VBLANK_INTERRUPT (1 << 16) 726 # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) 727 #define D1MODE_VLINE_STATUS 0x653c 728 #define D2MODE_VLINE_STATUS 0x6d3c 729 # define DxMODE_VLINE_OCCURRED (1 << 0) 730 # define DxMODE_VLINE_ACK (1 << 4) 731 # define DxMODE_VLINE_STAT (1 << 12) 732 # define DxMODE_VLINE_INTERRUPT (1 << 16) 733 # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) 734 #define DxMODE_INT_MASK 0x6540 735 # define D1MODE_VBLANK_INT_MASK (1 << 0) 736 # define D1MODE_VLINE_INT_MASK (1 << 4) 737 # define D2MODE_VBLANK_INT_MASK (1 << 8) 738 # define D2MODE_VLINE_INT_MASK (1 << 12) 739 #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc 740 # define DC_HPD1_INTERRUPT (1 << 18) 741 # define DC_HPD2_INTERRUPT (1 << 19) 742 #define DISP_INTERRUPT_STATUS 0x7edc 743 # define LB_D1_VLINE_INTERRUPT (1 << 2) 744 # define LB_D2_VLINE_INTERRUPT (1 << 3) 745 # define LB_D1_VBLANK_INTERRUPT (1 << 4) 746 # define LB_D2_VBLANK_INTERRUPT (1 << 5) 747 # define DACA_AUTODETECT_INTERRUPT (1 << 16) 748 # define DACB_AUTODETECT_INTERRUPT (1 << 17) 749 # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) 750 # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) 751 # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) 752 # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) 753 #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 754 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 755 # define DC_HPD4_INTERRUPT (1 << 14) 756 # define DC_HPD4_RX_INTERRUPT (1 << 15) 757 # define DC_HPD3_INTERRUPT (1 << 28) 758 # define DC_HPD1_RX_INTERRUPT (1 << 29) 759 # define DC_HPD2_RX_INTERRUPT (1 << 30) 760 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec 761 # define DC_HPD3_RX_INTERRUPT (1 << 0) 762 # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) 763 # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) 764 # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) 765 # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) 766 # define AUX1_SW_DONE_INTERRUPT (1 << 5) 767 # define AUX1_LS_DONE_INTERRUPT (1 << 6) 768 # define AUX2_SW_DONE_INTERRUPT (1 << 7) 769 # define AUX2_LS_DONE_INTERRUPT (1 << 8) 770 # define AUX3_SW_DONE_INTERRUPT (1 << 9) 771 # define AUX3_LS_DONE_INTERRUPT (1 << 10) 772 # define AUX4_SW_DONE_INTERRUPT (1 << 11) 773 # define AUX4_LS_DONE_INTERRUPT (1 << 12) 774 # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) 775 # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) 776 /* DCE 3.2 */ 777 # define AUX5_SW_DONE_INTERRUPT (1 << 15) 778 # define AUX5_LS_DONE_INTERRUPT (1 << 16) 779 # define AUX6_SW_DONE_INTERRUPT (1 << 17) 780 # define AUX6_LS_DONE_INTERRUPT (1 << 18) 781 # define DC_HPD5_INTERRUPT (1 << 19) 782 # define DC_HPD5_RX_INTERRUPT (1 << 20) 783 # define DC_HPD6_INTERRUPT (1 << 21) 784 # define DC_HPD6_RX_INTERRUPT (1 << 22) 785 786 #define DACA_AUTO_DETECT_CONTROL 0x7828 787 #define DACB_AUTO_DETECT_CONTROL 0x7a28 788 #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 789 #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 790 # define DACx_AUTODETECT_MODE(x) ((x) << 0) 791 # define DACx_AUTODETECT_MODE_NONE 0 792 # define DACx_AUTODETECT_MODE_CONNECT 1 793 # define DACx_AUTODETECT_MODE_DISCONNECT 2 794 # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) 795 /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ 796 # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) 797 798 #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 799 #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 800 #define DACA_AUTODETECT_INT_CONTROL 0x7838 801 #define DACB_AUTODETECT_INT_CONTROL 0x7a38 802 # define DACx_AUTODETECT_ACK (1 << 0) 803 # define DACx_AUTODETECT_INT_ENABLE (1 << 16) 804 805 #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 806 #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 807 #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 808 # define DC_HOT_PLUG_DETECTx_EN (1 << 0) 809 810 #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 811 #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 812 #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 813 # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) 814 # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) 815 816 /* DCE 3.0 */ 817 #define DC_HPD1_INT_STATUS 0x7d00 818 #define DC_HPD2_INT_STATUS 0x7d0c 819 #define DC_HPD3_INT_STATUS 0x7d18 820 #define DC_HPD4_INT_STATUS 0x7d24 821 /* DCE 3.2 */ 822 #define DC_HPD5_INT_STATUS 0x7dc0 823 #define DC_HPD6_INT_STATUS 0x7df4 824 # define DC_HPDx_INT_STATUS (1 << 0) 825 # define DC_HPDx_SENSE (1 << 1) 826 # define DC_HPDx_RX_INT_STATUS (1 << 8) 827 828 #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 829 #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 830 #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c 831 # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) 832 # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) 833 # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) 834 /* DCE 3.0 */ 835 #define DC_HPD1_INT_CONTROL 0x7d04 836 #define DC_HPD2_INT_CONTROL 0x7d10 837 #define DC_HPD3_INT_CONTROL 0x7d1c 838 #define DC_HPD4_INT_CONTROL 0x7d28 839 /* DCE 3.2 */ 840 #define DC_HPD5_INT_CONTROL 0x7dc4 841 #define DC_HPD6_INT_CONTROL 0x7df8 842 # define DC_HPDx_INT_ACK (1 << 0) 843 # define DC_HPDx_INT_POLARITY (1 << 8) 844 # define DC_HPDx_INT_EN (1 << 16) 845 # define DC_HPDx_RX_INT_ACK (1 << 20) 846 # define DC_HPDx_RX_INT_EN (1 << 24) 847 848 /* DCE 3.0 */ 849 #define DC_HPD1_CONTROL 0x7d08 850 #define DC_HPD2_CONTROL 0x7d14 851 #define DC_HPD3_CONTROL 0x7d20 852 #define DC_HPD4_CONTROL 0x7d2c 853 /* DCE 3.2 */ 854 #define DC_HPD5_CONTROL 0x7dc8 855 #define DC_HPD6_CONTROL 0x7dfc 856 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 857 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 858 /* DCE 3.2 */ 859 # define DC_HPDx_EN (1 << 28) 860 861 #define D1GRPH_INTERRUPT_STATUS 0x6158 862 #define D2GRPH_INTERRUPT_STATUS 0x6958 863 # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) 864 # define DxGRPH_PFLIP_INT_CLEAR (1 << 8) 865 #define D1GRPH_INTERRUPT_CONTROL 0x615c 866 #define D2GRPH_INTERRUPT_CONTROL 0x695c 867 # define DxGRPH_PFLIP_INT_MASK (1 << 0) 868 # define DxGRPH_PFLIP_INT_TYPE (1 << 8) 869 870 /* PCIE link stuff */ 871 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 872 # define LC_POINT_7_PLUS_EN (1 << 6) 873 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 874 # define LC_LINK_WIDTH_SHIFT 0 875 # define LC_LINK_WIDTH_MASK 0x7 876 # define LC_LINK_WIDTH_X0 0 877 # define LC_LINK_WIDTH_X1 1 878 # define LC_LINK_WIDTH_X2 2 879 # define LC_LINK_WIDTH_X4 3 880 # define LC_LINK_WIDTH_X8 4 881 # define LC_LINK_WIDTH_X16 6 882 # define LC_LINK_WIDTH_RD_SHIFT 4 883 # define LC_LINK_WIDTH_RD_MASK 0x70 884 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 885 # define LC_RECONFIG_NOW (1 << 8) 886 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 887 # define LC_RENEGOTIATE_EN (1 << 10) 888 # define LC_SHORT_RECONFIG_EN (1 << 11) 889 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 890 # define LC_UPCONFIGURE_DIS (1 << 13) 891 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 892 # define LC_GEN2_EN_STRAP (1 << 0) 893 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 894 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 895 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 896 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 897 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 898 # define LC_CURRENT_DATA_RATE (1 << 11) 899 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 900 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 901 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 902 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 903 #define MM_CFGREGS_CNTL 0x544c 904 # define MM_WR_TO_CFG_EN (1 << 3) 905 #define LINK_CNTL2 0x88 /* F0 */ 906 # define TARGET_LINK_SPEED_MASK (0xf << 0) 907 # define SELECTABLE_DEEMPHASIS (1 << 6) 908 909 /* Audio clocks DCE 2.0/3.0 */ 910 #define AUDIO_DTO 0x7340 911 # define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0) 912 # define AUDIO_DTO_MODULE(x) (((x) & 0xffff) << 16) 913 914 /* Audio clocks DCE 3.2 */ 915 #define DCCG_AUDIO_DTO0_PHASE 0x0514 916 #define DCCG_AUDIO_DTO0_MODULE 0x0518 917 #define DCCG_AUDIO_DTO0_LOAD 0x051c 918 # define DTO_LOAD (1 << 31) 919 #define DCCG_AUDIO_DTO0_CNTL 0x0520 920 921 #define DCCG_AUDIO_DTO1_PHASE 0x0524 922 #define DCCG_AUDIO_DTO1_MODULE 0x0528 923 #define DCCG_AUDIO_DTO1_LOAD 0x052c 924 #define DCCG_AUDIO_DTO1_CNTL 0x0530 925 926 #define DCCG_AUDIO_DTO_SELECT 0x0534 927 928 /* digital blocks */ 929 #define TMDSA_CNTL 0x7880 930 # define TMDSA_HDMI_EN (1 << 2) 931 #define LVTMA_CNTL 0x7a80 932 # define LVTMA_HDMI_EN (1 << 2) 933 #define DDIA_CNTL 0x7200 934 # define DDIA_HDMI_EN (1 << 2) 935 #define DIG0_CNTL 0x75a0 936 # define DIG_MODE(x) (((x) & 7) << 8) 937 # define DIG_MODE_DP 0 938 # define DIG_MODE_LVDS 1 939 # define DIG_MODE_TMDS_DVI 2 940 # define DIG_MODE_TMDS_HDMI 3 941 # define DIG_MODE_SDVO 4 942 #define DIG1_CNTL 0x79a0 943 944 /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one 945 * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly 946 * different due to the new DIG blocks, but also have 2 instances. 947 * DCE 3.0 HDMI blocks are part of each DIG encoder. 948 */ 949 950 /* rs6xx/rs740/r6xx/dce3 */ 951 #define HDMI0_CONTROL 0x7400 952 /* rs6xx/rs740/r6xx */ 953 # define HDMI0_ENABLE (1 << 0) 954 # define HDMI0_STREAM(x) (((x) & 3) << 2) 955 # define HDMI0_STREAM_TMDSA 0 956 # define HDMI0_STREAM_LVTMA 1 957 # define HDMI0_STREAM_DVOA 2 958 # define HDMI0_STREAM_DDIA 3 959 /* rs6xx/r6xx/dce3 */ 960 # define HDMI0_ERROR_ACK (1 << 8) 961 # define HDMI0_ERROR_MASK (1 << 9) 962 #define HDMI0_STATUS 0x7404 963 # define HDMI0_ACTIVE_AVMUTE (1 << 0) 964 # define HDMI0_AUDIO_ENABLE (1 << 4) 965 # define HDMI0_AZ_FORMAT_WTRIG (1 << 28) 966 # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) 967 #define HDMI0_AUDIO_PACKET_CONTROL 0x7408 968 # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) 969 # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 970 # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) 971 # define HDMI0_AUDIO_TEST_EN (1 << 12) 972 # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 973 # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) 974 # define HDMI0_60958_CS_UPDATE (1 << 26) 975 # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) 976 # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) 977 #define HDMI0_AUDIO_CRC_CONTROL 0x740c 978 # define HDMI0_AUDIO_CRC_EN (1 << 0) 979 #define HDMI0_VBI_PACKET_CONTROL 0x7410 980 # define HDMI0_NULL_SEND (1 << 0) 981 # define HDMI0_GC_SEND (1 << 4) 982 # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 983 #define HDMI0_INFOFRAME_CONTROL0 0x7414 984 # define HDMI0_AVI_INFO_SEND (1 << 0) 985 # define HDMI0_AVI_INFO_CONT (1 << 1) 986 # define HDMI0_AUDIO_INFO_SEND (1 << 4) 987 # define HDMI0_AUDIO_INFO_CONT (1 << 5) 988 # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ 989 # define HDMI0_AUDIO_INFO_UPDATE (1 << 7) 990 # define HDMI0_MPEG_INFO_SEND (1 << 8) 991 # define HDMI0_MPEG_INFO_CONT (1 << 9) 992 # define HDMI0_MPEG_INFO_UPDATE (1 << 10) 993 #define HDMI0_INFOFRAME_CONTROL1 0x7418 994 # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 995 # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 996 # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 997 #define HDMI0_GENERIC_PACKET_CONTROL 0x741c 998 # define HDMI0_GENERIC0_SEND (1 << 0) 999 # define HDMI0_GENERIC0_CONT (1 << 1) 1000 # define HDMI0_GENERIC0_UPDATE (1 << 2) 1001 # define HDMI0_GENERIC1_SEND (1 << 4) 1002 # define HDMI0_GENERIC1_CONT (1 << 5) 1003 # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 1004 # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 1005 #define HDMI0_GC 0x7428 1006 # define HDMI0_GC_AVMUTE (1 << 0) 1007 #define HDMI0_AVI_INFO0 0x7454 1008 # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1009 # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) 1010 # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10) 1011 # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12) 1012 # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13) 1013 # define HDMI0_AVI_INFO_Y_RGB 0 1014 # define HDMI0_AVI_INFO_Y_YCBCR422 1 1015 # define HDMI0_AVI_INFO_Y_YCBCR444 2 1016 # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 1017 # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16) 1018 # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20) 1019 # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22) 1020 # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 1021 # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24) 1022 # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 1023 #define HDMI0_AVI_INFO1 0x7458 1024 # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 1025 # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 1026 # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 1027 #define HDMI0_AVI_INFO2 0x745c 1028 # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 1029 # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 1030 #define HDMI0_AVI_INFO3 0x7460 1031 # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 1032 # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24) 1033 #define HDMI0_MPEG_INFO0 0x7464 1034 # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1035 # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 1036 # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 1037 # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 1038 #define HDMI0_MPEG_INFO1 0x7468 1039 # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 1040 # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8) 1041 # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12) 1042 #define HDMI0_GENERIC0_HDR 0x746c 1043 #define HDMI0_GENERIC0_0 0x7470 1044 #define HDMI0_GENERIC0_1 0x7474 1045 #define HDMI0_GENERIC0_2 0x7478 1046 #define HDMI0_GENERIC0_3 0x747c 1047 #define HDMI0_GENERIC0_4 0x7480 1048 #define HDMI0_GENERIC0_5 0x7484 1049 #define HDMI0_GENERIC0_6 0x7488 1050 #define HDMI0_GENERIC1_HDR 0x748c 1051 #define HDMI0_GENERIC1_0 0x7490 1052 #define HDMI0_GENERIC1_1 0x7494 1053 #define HDMI0_GENERIC1_2 0x7498 1054 #define HDMI0_GENERIC1_3 0x749c 1055 #define HDMI0_GENERIC1_4 0x74a0 1056 #define HDMI0_GENERIC1_5 0x74a4 1057 #define HDMI0_GENERIC1_6 0x74a8 1058 #define HDMI0_ACR_32_0 0x74ac 1059 # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 1060 #define HDMI0_ACR_32_1 0x74b0 1061 # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) 1062 #define HDMI0_ACR_44_0 0x74b4 1063 # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 1064 #define HDMI0_ACR_44_1 0x74b8 1065 # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) 1066 #define HDMI0_ACR_48_0 0x74bc 1067 # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 1068 #define HDMI0_ACR_48_1 0x74c0 1069 # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) 1070 #define HDMI0_ACR_STATUS_0 0x74c4 1071 #define HDMI0_ACR_STATUS_1 0x74c8 1072 #define HDMI0_AUDIO_INFO0 0x74cc 1073 # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1074 # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) 1075 #define HDMI0_AUDIO_INFO1 0x74d0 1076 # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 1077 # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 1078 # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 1079 # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 1080 #define HDMI0_60958_0 0x74d4 1081 # define HDMI0_60958_CS_A(x) (((x) & 1) << 0) 1082 # define HDMI0_60958_CS_B(x) (((x) & 1) << 1) 1083 # define HDMI0_60958_CS_C(x) (((x) & 1) << 2) 1084 # define HDMI0_60958_CS_D(x) (((x) & 3) << 3) 1085 # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) 1086 # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 1087 # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 1088 # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 1089 # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 1090 # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 1091 #define HDMI0_60958_1 0x74d8 1092 # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 1093 # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 1094 # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) 1095 # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) 1096 # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 1097 #define HDMI0_ACR_PACKET_CONTROL 0x74dc 1098 # define HDMI0_ACR_SEND (1 << 0) 1099 # define HDMI0_ACR_CONT (1 << 1) 1100 # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) 1101 # define HDMI0_ACR_HW 0 1102 # define HDMI0_ACR_32 1 1103 # define HDMI0_ACR_44 2 1104 # define HDMI0_ACR_48 3 1105 # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 1106 # define HDMI0_ACR_AUTO_SEND (1 << 12) 1107 #define HDMI0_RAMP_CONTROL0 0x74e0 1108 # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 1109 #define HDMI0_RAMP_CONTROL1 0x74e4 1110 # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 1111 #define HDMI0_RAMP_CONTROL2 0x74e8 1112 # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 1113 #define HDMI0_RAMP_CONTROL3 0x74ec 1114 # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 1115 /* HDMI0_60958_2 is r7xx only */ 1116 #define HDMI0_60958_2 0x74f0 1117 # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 1118 # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 1119 # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 1120 # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 1121 # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 1122 # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 1123 /* r6xx only; second instance starts at 0x7700 */ 1124 #define HDMI1_CONTROL 0x7700 1125 #define HDMI1_STATUS 0x7704 1126 #define HDMI1_AUDIO_PACKET_CONTROL 0x7708 1127 /* DCE3; second instance starts at 0x7800 NOT 0x7700 */ 1128 #define DCE3_HDMI1_CONTROL 0x7800 1129 #define DCE3_HDMI1_STATUS 0x7804 1130 #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808 1131 /* DCE3.2 (for interrupts) */ 1132 #define AFMT_STATUS 0x7600 1133 # define AFMT_AUDIO_ENABLE (1 << 4) 1134 # define AFMT_AZ_FORMAT_WTRIG (1 << 28) 1135 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 1136 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 1137 #define AFMT_AUDIO_PACKET_CONTROL 0x7604 1138 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 1139 # define AFMT_AUDIO_TEST_EN (1 << 12) 1140 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 1141 # define AFMT_60958_CS_UPDATE (1 << 26) 1142 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 1143 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 1144 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 1145 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 1146 1147 /* Power management */ 1148 #define CG_SPLL_FUNC_CNTL 0x600 1149 # define SPLL_RESET (1 << 0) 1150 # define SPLL_SLEEP (1 << 1) 1151 # define SPLL_REF_DIV(x) ((x) << 2) 1152 # define SPLL_REF_DIV_MASK (7 << 2) 1153 # define SPLL_FB_DIV(x) ((x) << 5) 1154 # define SPLL_FB_DIV_MASK (0xff << 5) 1155 # define SPLL_PULSEEN (1 << 13) 1156 # define SPLL_PULSENUM(x) ((x) << 14) 1157 # define SPLL_PULSENUM_MASK (3 << 14) 1158 # define SPLL_SW_HILEN(x) ((x) << 16) 1159 # define SPLL_SW_HILEN_MASK (0xf << 16) 1160 # define SPLL_SW_LOLEN(x) ((x) << 20) 1161 # define SPLL_SW_LOLEN_MASK (0xf << 20) 1162 # define SPLL_DIVEN (1 << 24) 1163 # define SPLL_BYPASS_EN (1 << 25) 1164 # define SPLL_CHG_STATUS (1 << 29) 1165 # define SPLL_CTLREQ (1 << 30) 1166 # define SPLL_CTLACK (1 << 31) 1167 1168 #define GENERAL_PWRMGT 0x618 1169 # define GLOBAL_PWRMGT_EN (1 << 0) 1170 # define STATIC_PM_EN (1 << 1) 1171 # define MOBILE_SU (1 << 2) 1172 # define THERMAL_PROTECTION_DIS (1 << 3) 1173 # define THERMAL_PROTECTION_TYPE (1 << 4) 1174 # define ENABLE_GEN2PCIE (1 << 5) 1175 # define SW_GPIO_INDEX(x) ((x) << 6) 1176 # define SW_GPIO_INDEX_MASK (3 << 6) 1177 # define LOW_VOLT_D2_ACPI (1 << 8) 1178 # define LOW_VOLT_D3_ACPI (1 << 9) 1179 # define VOLT_PWRMGT_EN (1 << 10) 1180 #define CG_TPC 0x61c 1181 # define TPCC(x) ((x) << 0) 1182 # define TPCC_MASK (0x7fffff << 0) 1183 # define TPU(x) ((x) << 23) 1184 # define TPU_MASK (0x1f << 23) 1185 #define SCLK_PWRMGT_CNTL 0x620 1186 # define SCLK_PWRMGT_OFF (1 << 0) 1187 # define SCLK_TURNOFF (1 << 1) 1188 # define SPLL_TURNOFF (1 << 2) 1189 # define SU_SCLK_USE_BCLK (1 << 3) 1190 # define DYNAMIC_GFX_ISLAND_PWR_DOWN (1 << 4) 1191 # define DYNAMIC_GFX_ISLAND_PWR_LP (1 << 5) 1192 # define CLK_TURN_ON_STAGGER (1 << 6) 1193 # define CLK_TURN_OFF_STAGGER (1 << 7) 1194 # define FIR_FORCE_TREND_SEL (1 << 8) 1195 # define FIR_TREND_MODE (1 << 9) 1196 # define DYN_GFX_CLK_OFF_EN (1 << 10) 1197 # define VDDC3D_TURNOFF_D1 (1 << 11) 1198 # define VDDC3D_TURNOFF_D2 (1 << 12) 1199 # define VDDC3D_TURNOFF_D3 (1 << 13) 1200 # define SPLL_TURNOFF_D2 (1 << 14) 1201 # define SCLK_LOW_D1 (1 << 15) 1202 # define DYN_GFX_CLK_OFF_MC_EN (1 << 16) 1203 #define MCLK_PWRMGT_CNTL 0x624 1204 # define MPLL_PWRMGT_OFF (1 << 0) 1205 # define YCLK_TURNOFF (1 << 1) 1206 # define MPLL_TURNOFF (1 << 2) 1207 # define SU_MCLK_USE_BCLK (1 << 3) 1208 # define DLL_READY (1 << 4) 1209 # define MC_BUSY (1 << 5) 1210 # define MC_INT_CNTL (1 << 7) 1211 # define MRDCKA_SLEEP (1 << 8) 1212 # define MRDCKB_SLEEP (1 << 9) 1213 # define MRDCKC_SLEEP (1 << 10) 1214 # define MRDCKD_SLEEP (1 << 11) 1215 # define MRDCKE_SLEEP (1 << 12) 1216 # define MRDCKF_SLEEP (1 << 13) 1217 # define MRDCKG_SLEEP (1 << 14) 1218 # define MRDCKH_SLEEP (1 << 15) 1219 # define MRDCKA_RESET (1 << 16) 1220 # define MRDCKB_RESET (1 << 17) 1221 # define MRDCKC_RESET (1 << 18) 1222 # define MRDCKD_RESET (1 << 19) 1223 # define MRDCKE_RESET (1 << 20) 1224 # define MRDCKF_RESET (1 << 21) 1225 # define MRDCKG_RESET (1 << 22) 1226 # define MRDCKH_RESET (1 << 23) 1227 # define DLL_READY_READ (1 << 24) 1228 # define USE_DISPLAY_GAP (1 << 25) 1229 # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 1230 # define USE_DISPLAY_GAP_CTXSW (1 << 27) 1231 # define MPLL_TURNOFF_D2 (1 << 28) 1232 # define USE_DISPLAY_URGENT_CTXSW (1 << 29) 1233 1234 #define MPLL_TIME 0x634 1235 # define MPLL_LOCK_TIME(x) ((x) << 0) 1236 # define MPLL_LOCK_TIME_MASK (0xffff << 0) 1237 # define MPLL_RESET_TIME(x) ((x) << 16) 1238 # define MPLL_RESET_TIME_MASK (0xffff << 16) 1239 1240 #define SCLK_FREQ_SETTING_STEP_0_PART1 0x648 1241 # define STEP_0_SPLL_POST_DIV(x) ((x) << 0) 1242 # define STEP_0_SPLL_POST_DIV_MASK (0xff << 0) 1243 # define STEP_0_SPLL_FB_DIV(x) ((x) << 8) 1244 # define STEP_0_SPLL_FB_DIV_MASK (0xff << 8) 1245 # define STEP_0_SPLL_REF_DIV(x) ((x) << 16) 1246 # define STEP_0_SPLL_REF_DIV_MASK (7 << 16) 1247 # define STEP_0_SPLL_STEP_TIME(x) ((x) << 19) 1248 # define STEP_0_SPLL_STEP_TIME_MASK (0x1fff << 19) 1249 #define SCLK_FREQ_SETTING_STEP_0_PART2 0x64c 1250 # define STEP_0_PULSE_HIGH_CNT(x) ((x) << 0) 1251 # define STEP_0_PULSE_HIGH_CNT_MASK (0x1ff << 0) 1252 # define STEP_0_POST_DIV_EN (1 << 9) 1253 # define STEP_0_SPLL_STEP_ENABLE (1 << 30) 1254 # define STEP_0_SPLL_ENTRY_VALID (1 << 31) 1255 1256 #define VID_RT 0x6f8 1257 # define VID_CRT(x) ((x) << 0) 1258 # define VID_CRT_MASK (0x1fff << 0) 1259 # define VID_CRTU(x) ((x) << 13) 1260 # define VID_CRTU_MASK (7 << 13) 1261 # define SSTU(x) ((x) << 16) 1262 # define SSTU_MASK (7 << 16) 1263 #define CTXSW_PROFILE_INDEX 0x6fc 1264 # define CTXSW_FREQ_VIDS_CFG_INDEX(x) ((x) << 0) 1265 # define CTXSW_FREQ_VIDS_CFG_INDEX_MASK (3 << 0) 1266 # define CTXSW_FREQ_VIDS_CFG_INDEX_SHIFT 0 1267 # define CTXSW_FREQ_MCLK_CFG_INDEX(x) ((x) << 2) 1268 # define CTXSW_FREQ_MCLK_CFG_INDEX_MASK (3 << 2) 1269 # define CTXSW_FREQ_MCLK_CFG_INDEX_SHIFT 2 1270 # define CTXSW_FREQ_SCLK_CFG_INDEX(x) ((x) << 4) 1271 # define CTXSW_FREQ_SCLK_CFG_INDEX_MASK (0x1f << 4) 1272 # define CTXSW_FREQ_SCLK_CFG_INDEX_SHIFT 4 1273 # define CTXSW_FREQ_STATE_SPLL_RESET_EN (1 << 9) 1274 # define CTXSW_FREQ_STATE_ENABLE (1 << 10) 1275 # define CTXSW_FREQ_DISPLAY_WATERMARK (1 << 11) 1276 # define CTXSW_FREQ_GEN2PCIE_VOLT (1 << 12) 1277 1278 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c 1279 # define TARGET_PROFILE_INDEX_MASK (3 << 0) 1280 # define TARGET_PROFILE_INDEX_SHIFT 0 1281 # define CURRENT_PROFILE_INDEX_MASK (3 << 2) 1282 # define CURRENT_PROFILE_INDEX_SHIFT 2 1283 # define DYN_PWR_ENTER_INDEX(x) ((x) << 4) 1284 # define DYN_PWR_ENTER_INDEX_MASK (3 << 4) 1285 # define DYN_PWR_ENTER_INDEX_SHIFT 4 1286 # define CURR_MCLK_INDEX_MASK (3 << 6) 1287 # define CURR_MCLK_INDEX_SHIFT 6 1288 # define CURR_SCLK_INDEX_MASK (0x1f << 8) 1289 # define CURR_SCLK_INDEX_SHIFT 8 1290 # define CURR_VID_INDEX_MASK (3 << 13) 1291 # define CURR_VID_INDEX_SHIFT 13 1292 1293 #define LOWER_GPIO_ENABLE 0x710 1294 #define UPPER_GPIO_ENABLE 0x714 1295 #define CTXSW_VID_LOWER_GPIO_CNTL 0x718 1296 1297 #define VID_UPPER_GPIO_CNTL 0x740 1298 #define CG_CTX_CGTT3D_R 0x744 1299 # define PHC(x) ((x) << 0) 1300 # define PHC_MASK (0x1ff << 0) 1301 # define SDC(x) ((x) << 9) 1302 # define SDC_MASK (0x3fff << 9) 1303 #define CG_VDDC3D_OOR 0x748 1304 # define SU(x) ((x) << 23) 1305 # define SU_MASK (0xf << 23) 1306 #define CG_FTV 0x74c 1307 #define CG_FFCT_0 0x750 1308 # define UTC_0(x) ((x) << 0) 1309 # define UTC_0_MASK (0x3ff << 0) 1310 # define DTC_0(x) ((x) << 10) 1311 # define DTC_0_MASK (0x3ff << 10) 1312 1313 #define CG_BSP 0x78c 1314 # define BSP(x) ((x) << 0) 1315 # define BSP_MASK (0xffff << 0) 1316 # define BSU(x) ((x) << 16) 1317 # define BSU_MASK (0xf << 16) 1318 #define CG_RT 0x790 1319 # define FLS(x) ((x) << 0) 1320 # define FLS_MASK (0xffff << 0) 1321 # define FMS(x) ((x) << 16) 1322 # define FMS_MASK (0xffff << 16) 1323 #define CG_LT 0x794 1324 # define FHS(x) ((x) << 0) 1325 # define FHS_MASK (0xffff << 0) 1326 #define CG_GIT 0x798 1327 # define CG_GICST(x) ((x) << 0) 1328 # define CG_GICST_MASK (0xffff << 0) 1329 # define CG_GIPOT(x) ((x) << 16) 1330 # define CG_GIPOT_MASK (0xffff << 16) 1331 1332 #define CG_SSP 0x7a8 1333 # define CG_SST(x) ((x) << 0) 1334 # define CG_SST_MASK (0xffff << 0) 1335 # define CG_SSTU(x) ((x) << 16) 1336 # define CG_SSTU_MASK (0xf << 16) 1337 1338 #define CG_RLC_REQ_AND_RSP 0x7c4 1339 # define RLC_CG_REQ_TYPE_MASK 0xf 1340 # define RLC_CG_REQ_TYPE_SHIFT 0 1341 # define CG_RLC_RSP_TYPE_MASK 0xf0 1342 # define CG_RLC_RSP_TYPE_SHIFT 4 1343 1344 #define CG_FC_T 0x7cc 1345 # define FC_T(x) ((x) << 0) 1346 # define FC_T_MASK (0xffff << 0) 1347 # define FC_TU(x) ((x) << 16) 1348 # define FC_TU_MASK (0x1f << 16) 1349 1350 #define GPIOPAD_MASK 0x1798 1351 #define GPIOPAD_A 0x179c 1352 #define GPIOPAD_EN 0x17a0 1353 1354 #define GRBM_PWR_CNTL 0x800c 1355 # define REQ_TYPE_MASK 0xf 1356 # define REQ_TYPE_SHIFT 0 1357 # define RSP_TYPE_MASK 0xf0 1358 # define RSP_TYPE_SHIFT 4 1359 1360 /* 1361 * UVD 1362 */ 1363 #define UVD_SEMA_ADDR_LOW 0xef00 1364 #define UVD_SEMA_ADDR_HIGH 0xef04 1365 #define UVD_SEMA_CMD 0xef08 1366 1367 #define UVD_GPCOM_VCPU_CMD 0xef0c 1368 #define UVD_GPCOM_VCPU_DATA0 0xef10 1369 #define UVD_GPCOM_VCPU_DATA1 0xef14 1370 #define UVD_ENGINE_CNTL 0xef18 1371 1372 #define UVD_SEMA_CNTL 0xf400 1373 #define UVD_RB_ARB_CTRL 0xf480 1374 1375 #define UVD_LMI_EXT40_ADDR 0xf498 1376 #define UVD_CGC_GATE 0xf4a8 1377 #define UVD_LMI_CTRL2 0xf4f4 1378 #define UVD_MASTINT_EN 0xf500 1379 #define UVD_LMI_ADDR_EXT 0xf594 1380 #define UVD_LMI_CTRL 0xf598 1381 #define UVD_LMI_SWAP_CNTL 0xf5b4 1382 #define UVD_MP_SWAP_CNTL 0xf5bC 1383 #define UVD_MPC_CNTL 0xf5dC 1384 #define UVD_MPC_SET_MUXA0 0xf5e4 1385 #define UVD_MPC_SET_MUXA1 0xf5e8 1386 #define UVD_MPC_SET_MUXB0 0xf5eC 1387 #define UVD_MPC_SET_MUXB1 0xf5f0 1388 #define UVD_MPC_SET_MUX 0xf5f4 1389 #define UVD_MPC_SET_ALU 0xf5f8 1390 1391 #define UVD_VCPU_CNTL 0xf660 1392 #define UVD_SOFT_RESET 0xf680 1393 #define RBC_SOFT_RESET (1<<0) 1394 #define LBSI_SOFT_RESET (1<<1) 1395 #define LMI_SOFT_RESET (1<<2) 1396 #define VCPU_SOFT_RESET (1<<3) 1397 #define CSM_SOFT_RESET (1<<5) 1398 #define CXW_SOFT_RESET (1<<6) 1399 #define TAP_SOFT_RESET (1<<7) 1400 #define LMI_UMC_SOFT_RESET (1<<13) 1401 #define UVD_RBC_IB_BASE 0xf684 1402 #define UVD_RBC_IB_SIZE 0xf688 1403 #define UVD_RBC_RB_BASE 0xf68c 1404 #define UVD_RBC_RB_RPTR 0xf690 1405 #define UVD_RBC_RB_WPTR 0xf694 1406 #define UVD_RBC_RB_WPTR_CNTL 0xf698 1407 1408 #define UVD_STATUS 0xf6bc 1409 1410 #define UVD_SEMA_TIMEOUT_STATUS 0xf6c0 1411 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0xf6c4 1412 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0xf6c8 1413 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0xf6cc 1414 1415 #define UVD_RBC_RB_CNTL 0xf6a4 1416 #define UVD_RBC_RB_RPTR_ADDR 0xf6a8 1417 1418 #define UVD_CONTEXT_ID 0xf6f4 1419 1420 # define UPLL_CTLREQ_MASK 0x00000008 1421 # define UPLL_CTLACK_MASK 0x40000000 1422 # define UPLL_CTLACK2_MASK 0x80000000 1423 1424 /* 1425 * PM4 1426 */ 1427 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1428 (((reg) >> 2) & 0xFFFF) | \ 1429 ((n) & 0x3FFF) << 16) 1430 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1431 (((op) & 0xFF) << 8) | \ 1432 ((n) & 0x3FFF) << 16) 1433 1434 /* Packet 3 types */ 1435 #define PACKET3_NOP 0x10 1436 #define PACKET3_INDIRECT_BUFFER_END 0x17 1437 #define PACKET3_SET_PREDICATION 0x20 1438 #define PACKET3_REG_RMW 0x21 1439 #define PACKET3_COND_EXEC 0x22 1440 #define PACKET3_PRED_EXEC 0x23 1441 #define PACKET3_START_3D_CMDBUF 0x24 1442 #define PACKET3_DRAW_INDEX_2 0x27 1443 #define PACKET3_CONTEXT_CONTROL 0x28 1444 #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 1445 #define PACKET3_INDEX_TYPE 0x2A 1446 #define PACKET3_DRAW_INDEX 0x2B 1447 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1448 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1449 #define PACKET3_NUM_INSTANCES 0x2F 1450 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1451 #define PACKET3_INDIRECT_BUFFER_MP 0x38 1452 #define PACKET3_MEM_SEMAPHORE 0x39 1453 # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 1454 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1455 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1456 #define PACKET3_MPEG_INDEX 0x3A 1457 #define PACKET3_COPY_DW 0x3B 1458 #define PACKET3_WAIT_REG_MEM 0x3C 1459 #define PACKET3_MEM_WRITE 0x3D 1460 #define PACKET3_INDIRECT_BUFFER 0x32 1461 #define PACKET3_CP_DMA 0x41 1462 /* 1. header 1463 * 2. SRC_ADDR_LO [31:0] 1464 * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0] 1465 * 4. DST_ADDR_LO [31:0] 1466 * 5. DST_ADDR_HI [7:0] 1467 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1468 */ 1469 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1470 /* COMMAND */ 1471 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1472 /* 0 - none 1473 * 1 - 8 in 16 1474 * 2 - 8 in 32 1475 * 3 - 8 in 64 1476 */ 1477 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1478 /* 0 - none 1479 * 1 - 8 in 16 1480 * 2 - 8 in 32 1481 * 3 - 8 in 64 1482 */ 1483 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1484 /* 0 - memory 1485 * 1 - register 1486 */ 1487 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1488 /* 0 - memory 1489 * 1 - register 1490 */ 1491 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1492 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1493 #define PACKET3_SURFACE_SYNC 0x43 1494 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1495 # define PACKET3_TC_ACTION_ENA (1 << 23) 1496 # define PACKET3_VC_ACTION_ENA (1 << 24) 1497 # define PACKET3_CB_ACTION_ENA (1 << 25) 1498 # define PACKET3_DB_ACTION_ENA (1 << 26) 1499 # define PACKET3_SH_ACTION_ENA (1 << 27) 1500 # define PACKET3_SMX_ACTION_ENA (1 << 28) 1501 #define PACKET3_ME_INITIALIZE 0x44 1502 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1503 #define PACKET3_COND_WRITE 0x45 1504 #define PACKET3_EVENT_WRITE 0x46 1505 #define EVENT_TYPE(x) ((x) << 0) 1506 #define EVENT_INDEX(x) ((x) << 8) 1507 /* 0 - any non-TS event 1508 * 1 - ZPASS_DONE 1509 * 2 - SAMPLE_PIPELINESTAT 1510 * 3 - SAMPLE_STREAMOUTSTAT* 1511 * 4 - *S_PARTIAL_FLUSH 1512 * 5 - TS events 1513 */ 1514 #define PACKET3_EVENT_WRITE_EOP 0x47 1515 #define DATA_SEL(x) ((x) << 29) 1516 /* 0 - discard 1517 * 1 - send low 32bit data 1518 * 2 - send 64bit data 1519 * 3 - send 64bit counter value 1520 */ 1521 #define INT_SEL(x) ((x) << 24) 1522 /* 0 - none 1523 * 1 - interrupt only (DATA_SEL = 0) 1524 * 2 - interrupt when data write is confirmed 1525 */ 1526 #define PACKET3_ONE_REG_WRITE 0x57 1527 #define PACKET3_SET_CONFIG_REG 0x68 1528 #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 1529 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1530 #define PACKET3_SET_CONTEXT_REG 0x69 1531 #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 1532 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1533 #define PACKET3_SET_ALU_CONST 0x6A 1534 #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 1535 #define PACKET3_SET_ALU_CONST_END 0x00032000 1536 #define PACKET3_SET_BOOL_CONST 0x6B 1537 #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 1538 #define PACKET3_SET_BOOL_CONST_END 0x00040000 1539 #define PACKET3_SET_LOOP_CONST 0x6C 1540 #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 1541 #define PACKET3_SET_LOOP_CONST_END 0x0003e380 1542 #define PACKET3_SET_RESOURCE 0x6D 1543 #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 1544 #define PACKET3_SET_RESOURCE_END 0x0003c000 1545 #define PACKET3_SET_SAMPLER 0x6E 1546 #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 1547 #define PACKET3_SET_SAMPLER_END 0x0003cff0 1548 #define PACKET3_SET_CTL_CONST 0x6F 1549 #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 1550 #define PACKET3_SET_CTL_CONST_END 0x0003e200 1551 #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ 1552 #define PACKET3_SURFACE_BASE_UPDATE 0x73 1553 1554 #define R_000011_K8_FB_LOCATION 0x11 1555 #define R_000012_MC_MISC_UMA_CNTL 0x12 1556 #define G_000012_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) 1557 #define R_0028F8_MC_INDEX 0x28F8 1558 #define S_0028F8_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) 1559 #define C_0028F8_MC_IND_ADDR 0xFFFFFE00 1560 #define S_0028F8_MC_IND_WR_EN(x) (((x) & 0x1) << 9) 1561 #define R_0028FC_MC_DATA 0x28FC 1562 1563 #define R_008020_GRBM_SOFT_RESET 0x8020 1564 #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 1565 #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 1566 #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 1567 #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 1568 #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 1569 #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 1570 #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 1571 #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 1572 #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 1573 #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 1574 #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 1575 #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 1576 #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 1577 #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 1578 #define R_008010_GRBM_STATUS 0x8010 1579 #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 1580 #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 1581 #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 1582 #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 1583 #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 1584 #define S_008010_VC_BUSY(x) (((x) & 1) << 11) 1585 #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 1586 #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 1587 #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 1588 #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 1589 #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 1590 #define S_008010_TC_BUSY(x) (((x) & 1) << 19) 1591 #define S_008010_SX_BUSY(x) (((x) & 1) << 20) 1592 #define S_008010_SH_BUSY(x) (((x) & 1) << 21) 1593 #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 1594 #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 1595 #define S_008010_SC_BUSY(x) (((x) & 1) << 24) 1596 #define S_008010_PA_BUSY(x) (((x) & 1) << 25) 1597 #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 1598 #define S_008010_CR_BUSY(x) (((x) & 1) << 27) 1599 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 1600 #define S_008010_CP_BUSY(x) (((x) & 1) << 29) 1601 #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 1602 #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 1603 #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 1604 #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 1605 #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 1606 #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 1607 #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 1608 #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 1609 #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 1610 #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 1611 #define G_008010_TA_BUSY(x) (((x) >> 14) & 1) 1612 #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 1613 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 1614 #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 1615 #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 1616 #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 1617 #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 1618 #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 1619 #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 1620 #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 1621 #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 1622 #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 1623 #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 1624 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 1625 #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 1626 #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 1627 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 1628 #define R_008014_GRBM_STATUS2 0x8014 1629 #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 1630 #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 1631 #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 1632 #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 1633 #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 1634 #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 1635 #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 1636 #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 1637 #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 1638 #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 1639 #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 1640 #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 1641 #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 1642 #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 1643 #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 1644 #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 1645 #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 1646 #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 1647 #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 1648 #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 1649 #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 1650 #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 1651 #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 1652 #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 1653 #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 1654 #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 1655 #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 1656 #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 1657 #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 1658 #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 1659 #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 1660 #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 1661 #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 1662 #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 1663 #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 1664 #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 1665 #define R_000E50_SRBM_STATUS 0x0E50 1666 #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 1667 #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 1668 #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 1669 #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 1670 #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 1671 #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 1672 #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 1673 #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 1674 #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 1675 #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 1676 #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 1677 #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 1678 #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 1679 #define G_000E50_IH_BUSY(x) (((x) >> 17) & 1) 1680 #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 1681 #define R_000E60_SRBM_SOFT_RESET 0x0E60 1682 #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 1683 #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 1684 #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 1685 #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 1686 #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 1687 #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 1688 #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 1689 #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 1690 #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 1691 #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 1692 #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 1693 #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 1694 #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 1695 #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 1696 1697 #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 1698 1699 #define R_028C04_PA_SC_AA_CONFIG 0x028C04 1700 #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) 1701 #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) 1702 #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC 1703 #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) 1704 #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) 1705 #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF 1706 #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) 1707 #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) 1708 #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF 1709 #define R_0280E0_CB_COLOR0_FRAG 0x0280E0 1710 #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1711 #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1712 #define C_0280E0_BASE_256B 0x00000000 1713 #define R_0280E4_CB_COLOR1_FRAG 0x0280E4 1714 #define R_0280E8_CB_COLOR2_FRAG 0x0280E8 1715 #define R_0280EC_CB_COLOR3_FRAG 0x0280EC 1716 #define R_0280F0_CB_COLOR4_FRAG 0x0280F0 1717 #define R_0280F4_CB_COLOR5_FRAG 0x0280F4 1718 #define R_0280F8_CB_COLOR6_FRAG 0x0280F8 1719 #define R_0280FC_CB_COLOR7_FRAG 0x0280FC 1720 #define R_0280C0_CB_COLOR0_TILE 0x0280C0 1721 #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1722 #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1723 #define C_0280C0_BASE_256B 0x00000000 1724 #define R_0280C4_CB_COLOR1_TILE 0x0280C4 1725 #define R_0280C8_CB_COLOR2_TILE 0x0280C8 1726 #define R_0280CC_CB_COLOR3_TILE 0x0280CC 1727 #define R_0280D0_CB_COLOR4_TILE 0x0280D0 1728 #define R_0280D4_CB_COLOR5_TILE 0x0280D4 1729 #define R_0280D8_CB_COLOR6_TILE 0x0280D8 1730 #define R_0280DC_CB_COLOR7_TILE 0x0280DC 1731 #define R_0280A0_CB_COLOR0_INFO 0x0280A0 1732 #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) 1733 #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) 1734 #define C_0280A0_ENDIAN 0xFFFFFFFC 1735 #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) 1736 #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) 1737 #define C_0280A0_FORMAT 0xFFFFFF03 1738 #define V_0280A0_COLOR_INVALID 0x00000000 1739 #define V_0280A0_COLOR_8 0x00000001 1740 #define V_0280A0_COLOR_4_4 0x00000002 1741 #define V_0280A0_COLOR_3_3_2 0x00000003 1742 #define V_0280A0_COLOR_16 0x00000005 1743 #define V_0280A0_COLOR_16_FLOAT 0x00000006 1744 #define V_0280A0_COLOR_8_8 0x00000007 1745 #define V_0280A0_COLOR_5_6_5 0x00000008 1746 #define V_0280A0_COLOR_6_5_5 0x00000009 1747 #define V_0280A0_COLOR_1_5_5_5 0x0000000A 1748 #define V_0280A0_COLOR_4_4_4_4 0x0000000B 1749 #define V_0280A0_COLOR_5_5_5_1 0x0000000C 1750 #define V_0280A0_COLOR_32 0x0000000D 1751 #define V_0280A0_COLOR_32_FLOAT 0x0000000E 1752 #define V_0280A0_COLOR_16_16 0x0000000F 1753 #define V_0280A0_COLOR_16_16_FLOAT 0x00000010 1754 #define V_0280A0_COLOR_8_24 0x00000011 1755 #define V_0280A0_COLOR_8_24_FLOAT 0x00000012 1756 #define V_0280A0_COLOR_24_8 0x00000013 1757 #define V_0280A0_COLOR_24_8_FLOAT 0x00000014 1758 #define V_0280A0_COLOR_10_11_11 0x00000015 1759 #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 1760 #define V_0280A0_COLOR_11_11_10 0x00000017 1761 #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 1762 #define V_0280A0_COLOR_2_10_10_10 0x00000019 1763 #define V_0280A0_COLOR_8_8_8_8 0x0000001A 1764 #define V_0280A0_COLOR_10_10_10_2 0x0000001B 1765 #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C 1766 #define V_0280A0_COLOR_32_32 0x0000001D 1767 #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E 1768 #define V_0280A0_COLOR_16_16_16_16 0x0000001F 1769 #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 1770 #define V_0280A0_COLOR_32_32_32_32 0x00000022 1771 #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 1772 #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) 1773 #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1774 #define C_0280A0_ARRAY_MODE 0xFFFFF0FF 1775 #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 1776 #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 1777 #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 1778 #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 1779 #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1780 #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1781 #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF 1782 #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) 1783 #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) 1784 #define C_0280A0_READ_SIZE 0xFFFF7FFF 1785 #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) 1786 #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) 1787 #define C_0280A0_COMP_SWAP 0xFFFCFFFF 1788 #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1789 #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1790 #define C_0280A0_TILE_MODE 0xFFF3FFFF 1791 #define V_0280A0_TILE_DISABLE 0 1792 #define V_0280A0_CLEAR_ENABLE 1 1793 #define V_0280A0_FRAG_ENABLE 2 1794 #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1795 #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1796 #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1797 #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) 1798 #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) 1799 #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF 1800 #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) 1801 #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) 1802 #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF 1803 #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) 1804 #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) 1805 #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF 1806 #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) 1807 #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) 1808 #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF 1809 #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) 1810 #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) 1811 #define C_0280A0_ROUND_MODE 0xFDFFFFFF 1812 #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) 1813 #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1814 #define C_0280A0_TILE_COMPACT 0xFBFFFFFF 1815 #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) 1816 #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) 1817 #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF 1818 #define R_0280A4_CB_COLOR1_INFO 0x0280A4 1819 #define R_0280A8_CB_COLOR2_INFO 0x0280A8 1820 #define R_0280AC_CB_COLOR3_INFO 0x0280AC 1821 #define R_0280B0_CB_COLOR4_INFO 0x0280B0 1822 #define R_0280B4_CB_COLOR5_INFO 0x0280B4 1823 #define R_0280B8_CB_COLOR6_INFO 0x0280B8 1824 #define R_0280BC_CB_COLOR7_INFO 0x0280BC 1825 #define R_028060_CB_COLOR0_SIZE 0x028060 1826 #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1827 #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1828 #define C_028060_PITCH_TILE_MAX 0xFFFFFC00 1829 #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1830 #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1831 #define C_028060_SLICE_TILE_MAX 0xC00003FF 1832 #define R_028064_CB_COLOR1_SIZE 0x028064 1833 #define R_028068_CB_COLOR2_SIZE 0x028068 1834 #define R_02806C_CB_COLOR3_SIZE 0x02806C 1835 #define R_028070_CB_COLOR4_SIZE 0x028070 1836 #define R_028074_CB_COLOR5_SIZE 0x028074 1837 #define R_028078_CB_COLOR6_SIZE 0x028078 1838 #define R_02807C_CB_COLOR7_SIZE 0x02807C 1839 #define R_028238_CB_TARGET_MASK 0x028238 1840 #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) 1841 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) 1842 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0 1843 #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) 1844 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) 1845 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F 1846 #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) 1847 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) 1848 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF 1849 #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) 1850 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) 1851 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF 1852 #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) 1853 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) 1854 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF 1855 #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) 1856 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) 1857 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF 1858 #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) 1859 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) 1860 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF 1861 #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) 1862 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) 1863 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF 1864 #define R_02823C_CB_SHADER_MASK 0x02823C 1865 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) 1866 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) 1867 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 1868 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) 1869 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) 1870 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F 1871 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) 1872 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) 1873 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF 1874 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) 1875 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) 1876 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF 1877 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) 1878 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) 1879 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF 1880 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) 1881 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) 1882 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF 1883 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) 1884 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) 1885 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF 1886 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) 1887 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) 1888 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF 1889 #define R_028AB0_VGT_STRMOUT_EN 0x028AB0 1890 #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) 1891 #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) 1892 #define C_028AB0_STREAMOUT 0xFFFFFFFE 1893 #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 1894 #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) 1895 #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) 1896 #define C_028B20_BUFFER_0_EN 0xFFFFFFFE 1897 #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) 1898 #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) 1899 #define C_028B20_BUFFER_1_EN 0xFFFFFFFD 1900 #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) 1901 #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) 1902 #define C_028B20_BUFFER_2_EN 0xFFFFFFFB 1903 #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) 1904 #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) 1905 #define C_028B20_BUFFER_3_EN 0xFFFFFFF7 1906 #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1907 #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1908 #define C_028B20_SIZE 0x00000000 1909 #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 1910 #define S_038000_DIM(x) (((x) & 0x7) << 0) 1911 #define G_038000_DIM(x) (((x) >> 0) & 0x7) 1912 #define C_038000_DIM 0xFFFFFFF8 1913 #define V_038000_SQ_TEX_DIM_1D 0x00000000 1914 #define V_038000_SQ_TEX_DIM_2D 0x00000001 1915 #define V_038000_SQ_TEX_DIM_3D 0x00000002 1916 #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 1917 #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1918 #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1919 #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 1920 #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1921 #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) 1922 #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) 1923 #define C_038000_TILE_MODE 0xFFFFFF87 1924 #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 1925 #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 1926 #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 1927 #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 1928 #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) 1929 #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) 1930 #define C_038000_TILE_TYPE 0xFFFFFF7F 1931 #define S_038000_PITCH(x) (((x) & 0x7FF) << 8) 1932 #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) 1933 #define C_038000_PITCH 0xFFF800FF 1934 #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) 1935 #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) 1936 #define C_038000_TEX_WIDTH 0x0007FFFF 1937 #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 1938 #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) 1939 #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) 1940 #define C_038004_TEX_HEIGHT 0xFFFFE000 1941 #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) 1942 #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) 1943 #define C_038004_TEX_DEPTH 0xFC001FFF 1944 #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) 1945 #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) 1946 #define C_038004_DATA_FORMAT 0x03FFFFFF 1947 #define V_038004_COLOR_INVALID 0x00000000 1948 #define V_038004_COLOR_8 0x00000001 1949 #define V_038004_COLOR_4_4 0x00000002 1950 #define V_038004_COLOR_3_3_2 0x00000003 1951 #define V_038004_COLOR_16 0x00000005 1952 #define V_038004_COLOR_16_FLOAT 0x00000006 1953 #define V_038004_COLOR_8_8 0x00000007 1954 #define V_038004_COLOR_5_6_5 0x00000008 1955 #define V_038004_COLOR_6_5_5 0x00000009 1956 #define V_038004_COLOR_1_5_5_5 0x0000000A 1957 #define V_038004_COLOR_4_4_4_4 0x0000000B 1958 #define V_038004_COLOR_5_5_5_1 0x0000000C 1959 #define V_038004_COLOR_32 0x0000000D 1960 #define V_038004_COLOR_32_FLOAT 0x0000000E 1961 #define V_038004_COLOR_16_16 0x0000000F 1962 #define V_038004_COLOR_16_16_FLOAT 0x00000010 1963 #define V_038004_COLOR_8_24 0x00000011 1964 #define V_038004_COLOR_8_24_FLOAT 0x00000012 1965 #define V_038004_COLOR_24_8 0x00000013 1966 #define V_038004_COLOR_24_8_FLOAT 0x00000014 1967 #define V_038004_COLOR_10_11_11 0x00000015 1968 #define V_038004_COLOR_10_11_11_FLOAT 0x00000016 1969 #define V_038004_COLOR_11_11_10 0x00000017 1970 #define V_038004_COLOR_11_11_10_FLOAT 0x00000018 1971 #define V_038004_COLOR_2_10_10_10 0x00000019 1972 #define V_038004_COLOR_8_8_8_8 0x0000001A 1973 #define V_038004_COLOR_10_10_10_2 0x0000001B 1974 #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C 1975 #define V_038004_COLOR_32_32 0x0000001D 1976 #define V_038004_COLOR_32_32_FLOAT 0x0000001E 1977 #define V_038004_COLOR_16_16_16_16 0x0000001F 1978 #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 1979 #define V_038004_COLOR_32_32_32_32 0x00000022 1980 #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 1981 #define V_038004_FMT_1 0x00000025 1982 #define V_038004_FMT_GB_GR 0x00000027 1983 #define V_038004_FMT_BG_RG 0x00000028 1984 #define V_038004_FMT_32_AS_8 0x00000029 1985 #define V_038004_FMT_32_AS_8_8 0x0000002A 1986 #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B 1987 #define V_038004_FMT_8_8_8 0x0000002C 1988 #define V_038004_FMT_16_16_16 0x0000002D 1989 #define V_038004_FMT_16_16_16_FLOAT 0x0000002E 1990 #define V_038004_FMT_32_32_32 0x0000002F 1991 #define V_038004_FMT_32_32_32_FLOAT 0x00000030 1992 #define V_038004_FMT_BC1 0x00000031 1993 #define V_038004_FMT_BC2 0x00000032 1994 #define V_038004_FMT_BC3 0x00000033 1995 #define V_038004_FMT_BC4 0x00000034 1996 #define V_038004_FMT_BC5 0x00000035 1997 #define V_038004_FMT_BC6 0x00000036 1998 #define V_038004_FMT_BC7 0x00000037 1999 #define V_038004_FMT_32_AS_32_32_32_32 0x00000038 2000 #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 2001 #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 2002 #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 2003 #define C_038010_FORMAT_COMP_X 0xFFFFFFFC 2004 #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 2005 #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 2006 #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 2007 #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 2008 #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 2009 #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF 2010 #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 2011 #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 2012 #define C_038010_FORMAT_COMP_W 0xFFFFFF3F 2013 #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 2014 #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 2015 #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF 2016 #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 2017 #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 2018 #define C_038010_SRF_MODE_ALL 0xFFFFFBFF 2019 #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 2020 #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 2021 #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF 2022 #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 2023 #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 2024 #define C_038010_ENDIAN_SWAP 0xFFFFCFFF 2025 #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) 2026 #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) 2027 #define C_038010_REQUEST_SIZE 0xFFFF3FFF 2028 #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) 2029 #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) 2030 #define C_038010_DST_SEL_X 0xFFF8FFFF 2031 #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) 2032 #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 2033 #define C_038010_DST_SEL_Y 0xFFC7FFFF 2034 #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) 2035 #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 2036 #define C_038010_DST_SEL_Z 0xFE3FFFFF 2037 #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) 2038 #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) 2039 #define C_038010_DST_SEL_W 0xF1FFFFFF 2040 # define SQ_SEL_X 0 2041 # define SQ_SEL_Y 1 2042 # define SQ_SEL_Z 2 2043 # define SQ_SEL_W 3 2044 # define SQ_SEL_0 4 2045 # define SQ_SEL_1 5 2046 #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) 2047 #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 2048 #define C_038010_BASE_LEVEL 0x0FFFFFFF 2049 #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 2050 #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) 2051 #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 2052 #define C_038014_LAST_LEVEL 0xFFFFFFF0 2053 #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 2054 #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 2055 #define C_038014_BASE_ARRAY 0xFFFE000F 2056 #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 2057 #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 2058 #define C_038014_LAST_ARRAY 0xC001FFFF 2059 #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 2060 #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2061 #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2062 #define C_0288A8_ITEMSIZE 0xFFFF8000 2063 #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 2064 #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2065 #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2066 #define C_008C44_MEM_SIZE 0x00000000 2067 #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 2068 #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2069 #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2070 #define C_0288B0_ITEMSIZE 0xFFFF8000 2071 #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 2072 #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2073 #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2074 #define C_008C54_MEM_SIZE 0x00000000 2075 #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 2076 #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2077 #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2078 #define C_0288C0_ITEMSIZE 0xFFFF8000 2079 #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 2080 #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2081 #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2082 #define C_008C74_MEM_SIZE 0x00000000 2083 #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 2084 #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2085 #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2086 #define C_0288B4_ITEMSIZE 0xFFFF8000 2087 #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C 2088 #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2089 #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2090 #define C_008C5C_MEM_SIZE 0x00000000 2091 #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC 2092 #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2093 #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2094 #define C_0288AC_ITEMSIZE 0xFFFF8000 2095 #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C 2096 #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2097 #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2098 #define C_008C4C_MEM_SIZE 0x00000000 2099 #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC 2100 #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2101 #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2102 #define C_0288BC_ITEMSIZE 0xFFFF8000 2103 #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C 2104 #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2105 #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2106 #define C_008C6C_MEM_SIZE 0x00000000 2107 #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 2108 #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2109 #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2110 #define C_0288C4_ITEMSIZE 0xFFFF8000 2111 #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C 2112 #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2113 #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2114 #define C_008C7C_MEM_SIZE 0x00000000 2115 #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 2116 #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2117 #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2118 #define C_0288B8_ITEMSIZE 0xFFFF8000 2119 #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 2120 #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 2121 #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 2122 #define C_008C64_MEM_SIZE 0x00000000 2123 #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 2124 #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 2125 #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 2126 #define C_0288C8_ITEMSIZE 0xFFFF8000 2127 #define R_028010_DB_DEPTH_INFO 0x028010 2128 #define S_028010_FORMAT(x) (((x) & 0x7) << 0) 2129 #define G_028010_FORMAT(x) (((x) >> 0) & 0x7) 2130 #define C_028010_FORMAT 0xFFFFFFF8 2131 #define V_028010_DEPTH_INVALID 0x00000000 2132 #define V_028010_DEPTH_16 0x00000001 2133 #define V_028010_DEPTH_X8_24 0x00000002 2134 #define V_028010_DEPTH_8_24 0x00000003 2135 #define V_028010_DEPTH_X8_24_FLOAT 0x00000004 2136 #define V_028010_DEPTH_8_24_FLOAT 0x00000005 2137 #define V_028010_DEPTH_32_FLOAT 0x00000006 2138 #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 2139 #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) 2140 #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) 2141 #define C_028010_READ_SIZE 0xFFFFFFF7 2142 #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) 2143 #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) 2144 #define C_028010_ARRAY_MODE 0xFFF87FFF 2145 #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 2146 #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 2147 #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) 2148 #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) 2149 #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF 2150 #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) 2151 #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) 2152 #define C_028010_TILE_COMPACT 0xFBFFFFFF 2153 #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 2154 #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 2155 #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF 2156 #define R_028000_DB_DEPTH_SIZE 0x028000 2157 #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 2158 #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 2159 #define C_028000_PITCH_TILE_MAX 0xFFFFFC00 2160 #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 2161 #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 2162 #define C_028000_SLICE_TILE_MAX 0xC00003FF 2163 #define R_028004_DB_DEPTH_VIEW 0x028004 2164 #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) 2165 #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) 2166 #define C_028004_SLICE_START 0xFFFFF800 2167 #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) 2168 #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 2169 #define C_028004_SLICE_MAX 0xFF001FFF 2170 #define R_028800_DB_DEPTH_CONTROL 0x028800 2171 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 2172 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 2173 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE 2174 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 2175 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 2176 #define C_028800_Z_ENABLE 0xFFFFFFFD 2177 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 2178 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 2179 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 2180 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 2181 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 2182 #define C_028800_ZFUNC 0xFFFFFF8F 2183 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 2184 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 2185 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 2186 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 2187 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 2188 #define C_028800_STENCILFUNC 0xFFFFF8FF 2189 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 2190 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 2191 #define C_028800_STENCILFAIL 0xFFFFC7FF 2192 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 2193 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 2194 #define C_028800_STENCILZPASS 0xFFFE3FFF 2195 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 2196 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 2197 #define C_028800_STENCILZFAIL 0xFFF1FFFF 2198 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 2199 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 2200 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF 2201 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 2202 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 2203 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF 2204 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 2205 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 2206 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF 2207 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 2208 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 2209 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 2210 2211 #endif 2212