1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2008 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * Copyright 2009 Jerome Glisse. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Authors: Dave Airlie 25771fe6b9SJerome Glisse * Alex Deucher 26771fe6b9SJerome Glisse * Jerome Glisse 27771fe6b9SJerome Glisse */ 28771fe6b9SJerome Glisse #include <linux/seq_file.h> 29771fe6b9SJerome Glisse #include "drmP.h" 30771fe6b9SJerome Glisse #include "drm.h" 31771fe6b9SJerome Glisse #include "radeon_drm.h" 32771fe6b9SJerome Glisse #include "radeon_reg.h" 33771fe6b9SJerome Glisse #include "radeon.h" 34e6990375SDaniel Vetter #include "radeon_asic.h" 353ce0a23dSJerome Glisse #include "r100d.h" 36d4550907SJerome Glisse #include "rs100d.h" 37d4550907SJerome Glisse #include "rv200d.h" 38d4550907SJerome Glisse #include "rv250d.h" 393ce0a23dSJerome Glisse 4070967ab9SBen Hutchings #include <linux/firmware.h> 4170967ab9SBen Hutchings #include <linux/platform_device.h> 4270967ab9SBen Hutchings 43551ebd83SDave Airlie #include "r100_reg_safe.h" 44551ebd83SDave Airlie #include "rn50_reg_safe.h" 45551ebd83SDave Airlie 4670967ab9SBen Hutchings /* Firmware Names */ 4770967ab9SBen Hutchings #define FIRMWARE_R100 "radeon/R100_cp.bin" 4870967ab9SBen Hutchings #define FIRMWARE_R200 "radeon/R200_cp.bin" 4970967ab9SBen Hutchings #define FIRMWARE_R300 "radeon/R300_cp.bin" 5070967ab9SBen Hutchings #define FIRMWARE_R420 "radeon/R420_cp.bin" 5170967ab9SBen Hutchings #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 5270967ab9SBen Hutchings #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 5370967ab9SBen Hutchings #define FIRMWARE_R520 "radeon/R520_cp.bin" 5470967ab9SBen Hutchings 5570967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R100); 5670967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R200); 5770967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R300); 5870967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R420); 5970967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_RS690); 6070967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_RS600); 6170967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R520); 62771fe6b9SJerome Glisse 63551ebd83SDave Airlie #include "r100_track.h" 64551ebd83SDave Airlie 65771fe6b9SJerome Glisse /* This files gather functions specifics to: 66771fe6b9SJerome Glisse * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 67771fe6b9SJerome Glisse */ 68771fe6b9SJerome Glisse 6905a05c50SAlex Deucher /* hpd for digital panel detect/disconnect */ 7005a05c50SAlex Deucher bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 7105a05c50SAlex Deucher { 7205a05c50SAlex Deucher bool connected = false; 7305a05c50SAlex Deucher 7405a05c50SAlex Deucher switch (hpd) { 7505a05c50SAlex Deucher case RADEON_HPD_1: 7605a05c50SAlex Deucher if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 7705a05c50SAlex Deucher connected = true; 7805a05c50SAlex Deucher break; 7905a05c50SAlex Deucher case RADEON_HPD_2: 8005a05c50SAlex Deucher if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 8105a05c50SAlex Deucher connected = true; 8205a05c50SAlex Deucher break; 8305a05c50SAlex Deucher default: 8405a05c50SAlex Deucher break; 8505a05c50SAlex Deucher } 8605a05c50SAlex Deucher return connected; 8705a05c50SAlex Deucher } 8805a05c50SAlex Deucher 8905a05c50SAlex Deucher void r100_hpd_set_polarity(struct radeon_device *rdev, 9005a05c50SAlex Deucher enum radeon_hpd_id hpd) 9105a05c50SAlex Deucher { 9205a05c50SAlex Deucher u32 tmp; 9305a05c50SAlex Deucher bool connected = r100_hpd_sense(rdev, hpd); 9405a05c50SAlex Deucher 9505a05c50SAlex Deucher switch (hpd) { 9605a05c50SAlex Deucher case RADEON_HPD_1: 9705a05c50SAlex Deucher tmp = RREG32(RADEON_FP_GEN_CNTL); 9805a05c50SAlex Deucher if (connected) 9905a05c50SAlex Deucher tmp &= ~RADEON_FP_DETECT_INT_POL; 10005a05c50SAlex Deucher else 10105a05c50SAlex Deucher tmp |= RADEON_FP_DETECT_INT_POL; 10205a05c50SAlex Deucher WREG32(RADEON_FP_GEN_CNTL, tmp); 10305a05c50SAlex Deucher break; 10405a05c50SAlex Deucher case RADEON_HPD_2: 10505a05c50SAlex Deucher tmp = RREG32(RADEON_FP2_GEN_CNTL); 10605a05c50SAlex Deucher if (connected) 10705a05c50SAlex Deucher tmp &= ~RADEON_FP2_DETECT_INT_POL; 10805a05c50SAlex Deucher else 10905a05c50SAlex Deucher tmp |= RADEON_FP2_DETECT_INT_POL; 11005a05c50SAlex Deucher WREG32(RADEON_FP2_GEN_CNTL, tmp); 11105a05c50SAlex Deucher break; 11205a05c50SAlex Deucher default: 11305a05c50SAlex Deucher break; 11405a05c50SAlex Deucher } 11505a05c50SAlex Deucher } 11605a05c50SAlex Deucher 11705a05c50SAlex Deucher void r100_hpd_init(struct radeon_device *rdev) 11805a05c50SAlex Deucher { 11905a05c50SAlex Deucher struct drm_device *dev = rdev->ddev; 12005a05c50SAlex Deucher struct drm_connector *connector; 12105a05c50SAlex Deucher 12205a05c50SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 12305a05c50SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 12405a05c50SAlex Deucher switch (radeon_connector->hpd.hpd) { 12505a05c50SAlex Deucher case RADEON_HPD_1: 12605a05c50SAlex Deucher rdev->irq.hpd[0] = true; 12705a05c50SAlex Deucher break; 12805a05c50SAlex Deucher case RADEON_HPD_2: 12905a05c50SAlex Deucher rdev->irq.hpd[1] = true; 13005a05c50SAlex Deucher break; 13105a05c50SAlex Deucher default: 13205a05c50SAlex Deucher break; 13305a05c50SAlex Deucher } 13405a05c50SAlex Deucher } 135003e69f9SJerome Glisse if (rdev->irq.installed) 13605a05c50SAlex Deucher r100_irq_set(rdev); 13705a05c50SAlex Deucher } 13805a05c50SAlex Deucher 13905a05c50SAlex Deucher void r100_hpd_fini(struct radeon_device *rdev) 14005a05c50SAlex Deucher { 14105a05c50SAlex Deucher struct drm_device *dev = rdev->ddev; 14205a05c50SAlex Deucher struct drm_connector *connector; 14305a05c50SAlex Deucher 14405a05c50SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 14505a05c50SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 14605a05c50SAlex Deucher switch (radeon_connector->hpd.hpd) { 14705a05c50SAlex Deucher case RADEON_HPD_1: 14805a05c50SAlex Deucher rdev->irq.hpd[0] = false; 14905a05c50SAlex Deucher break; 15005a05c50SAlex Deucher case RADEON_HPD_2: 15105a05c50SAlex Deucher rdev->irq.hpd[1] = false; 15205a05c50SAlex Deucher break; 15305a05c50SAlex Deucher default: 15405a05c50SAlex Deucher break; 15505a05c50SAlex Deucher } 15605a05c50SAlex Deucher } 15705a05c50SAlex Deucher } 15805a05c50SAlex Deucher 159771fe6b9SJerome Glisse /* 160771fe6b9SJerome Glisse * PCI GART 161771fe6b9SJerome Glisse */ 162771fe6b9SJerome Glisse void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 163771fe6b9SJerome Glisse { 164771fe6b9SJerome Glisse /* TODO: can we do somethings here ? */ 165771fe6b9SJerome Glisse /* It seems hw only cache one entry so we should discard this 166771fe6b9SJerome Glisse * entry otherwise if first GPU GART read hit this entry it 167771fe6b9SJerome Glisse * could end up in wrong address. */ 168771fe6b9SJerome Glisse } 169771fe6b9SJerome Glisse 1704aac0473SJerome Glisse int r100_pci_gart_init(struct radeon_device *rdev) 1714aac0473SJerome Glisse { 1724aac0473SJerome Glisse int r; 1734aac0473SJerome Glisse 1744aac0473SJerome Glisse if (rdev->gart.table.ram.ptr) { 1754aac0473SJerome Glisse WARN(1, "R100 PCI GART already initialized.\n"); 1764aac0473SJerome Glisse return 0; 1774aac0473SJerome Glisse } 1784aac0473SJerome Glisse /* Initialize common gart structure */ 1794aac0473SJerome Glisse r = radeon_gart_init(rdev); 1804aac0473SJerome Glisse if (r) 1814aac0473SJerome Glisse return r; 1824aac0473SJerome Glisse rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 1834aac0473SJerome Glisse rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 1844aac0473SJerome Glisse rdev->asic->gart_set_page = &r100_pci_gart_set_page; 1854aac0473SJerome Glisse return radeon_gart_table_ram_alloc(rdev); 1864aac0473SJerome Glisse } 1874aac0473SJerome Glisse 18817e15b0cSDave Airlie /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 18917e15b0cSDave Airlie void r100_enable_bm(struct radeon_device *rdev) 19017e15b0cSDave Airlie { 19117e15b0cSDave Airlie uint32_t tmp; 19217e15b0cSDave Airlie /* Enable bus mastering */ 19317e15b0cSDave Airlie tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 19417e15b0cSDave Airlie WREG32(RADEON_BUS_CNTL, tmp); 19517e15b0cSDave Airlie } 19617e15b0cSDave Airlie 197771fe6b9SJerome Glisse int r100_pci_gart_enable(struct radeon_device *rdev) 198771fe6b9SJerome Glisse { 199771fe6b9SJerome Glisse uint32_t tmp; 200771fe6b9SJerome Glisse 20182568565SDave Airlie radeon_gart_restore(rdev); 202771fe6b9SJerome Glisse /* discard memory request outside of configured range */ 203771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 204771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp); 205771fe6b9SJerome Glisse /* set address range for PCI address translate */ 206d594e46aSJerome Glisse WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 207d594e46aSJerome Glisse WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 208771fe6b9SJerome Glisse /* set PCI GART page-table base address */ 209771fe6b9SJerome Glisse WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 210771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 211771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp); 212771fe6b9SJerome Glisse r100_pci_gart_tlb_flush(rdev); 213771fe6b9SJerome Glisse rdev->gart.ready = true; 214771fe6b9SJerome Glisse return 0; 215771fe6b9SJerome Glisse } 216771fe6b9SJerome Glisse 217771fe6b9SJerome Glisse void r100_pci_gart_disable(struct radeon_device *rdev) 218771fe6b9SJerome Glisse { 219771fe6b9SJerome Glisse uint32_t tmp; 220771fe6b9SJerome Glisse 221771fe6b9SJerome Glisse /* discard memory request outside of configured range */ 222771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 223771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 224771fe6b9SJerome Glisse WREG32(RADEON_AIC_LO_ADDR, 0); 225771fe6b9SJerome Glisse WREG32(RADEON_AIC_HI_ADDR, 0); 226771fe6b9SJerome Glisse } 227771fe6b9SJerome Glisse 228771fe6b9SJerome Glisse int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 229771fe6b9SJerome Glisse { 230771fe6b9SJerome Glisse if (i < 0 || i > rdev->gart.num_gpu_pages) { 231771fe6b9SJerome Glisse return -EINVAL; 232771fe6b9SJerome Glisse } 233ed10f95dSDave Airlie rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr)); 234771fe6b9SJerome Glisse return 0; 235771fe6b9SJerome Glisse } 236771fe6b9SJerome Glisse 2374aac0473SJerome Glisse void r100_pci_gart_fini(struct radeon_device *rdev) 238771fe6b9SJerome Glisse { 239f9274562SJerome Glisse radeon_gart_fini(rdev); 240771fe6b9SJerome Glisse r100_pci_gart_disable(rdev); 2414aac0473SJerome Glisse radeon_gart_table_ram_free(rdev); 242771fe6b9SJerome Glisse } 243771fe6b9SJerome Glisse 2447ed220d7SMichel Dänzer int r100_irq_set(struct radeon_device *rdev) 2457ed220d7SMichel Dänzer { 2467ed220d7SMichel Dänzer uint32_t tmp = 0; 2477ed220d7SMichel Dänzer 248003e69f9SJerome Glisse if (!rdev->irq.installed) { 249003e69f9SJerome Glisse WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); 250003e69f9SJerome Glisse WREG32(R_000040_GEN_INT_CNTL, 0); 251003e69f9SJerome Glisse return -EINVAL; 252003e69f9SJerome Glisse } 2537ed220d7SMichel Dänzer if (rdev->irq.sw_int) { 2547ed220d7SMichel Dänzer tmp |= RADEON_SW_INT_ENABLE; 2557ed220d7SMichel Dänzer } 2567ed220d7SMichel Dänzer if (rdev->irq.crtc_vblank_int[0]) { 2577ed220d7SMichel Dänzer tmp |= RADEON_CRTC_VBLANK_MASK; 2587ed220d7SMichel Dänzer } 2597ed220d7SMichel Dänzer if (rdev->irq.crtc_vblank_int[1]) { 2607ed220d7SMichel Dänzer tmp |= RADEON_CRTC2_VBLANK_MASK; 2617ed220d7SMichel Dänzer } 26205a05c50SAlex Deucher if (rdev->irq.hpd[0]) { 26305a05c50SAlex Deucher tmp |= RADEON_FP_DETECT_MASK; 26405a05c50SAlex Deucher } 26505a05c50SAlex Deucher if (rdev->irq.hpd[1]) { 26605a05c50SAlex Deucher tmp |= RADEON_FP2_DETECT_MASK; 26705a05c50SAlex Deucher } 2687ed220d7SMichel Dänzer WREG32(RADEON_GEN_INT_CNTL, tmp); 2697ed220d7SMichel Dänzer return 0; 2707ed220d7SMichel Dänzer } 2717ed220d7SMichel Dänzer 2729f022ddfSJerome Glisse void r100_irq_disable(struct radeon_device *rdev) 2739f022ddfSJerome Glisse { 2749f022ddfSJerome Glisse u32 tmp; 2759f022ddfSJerome Glisse 2769f022ddfSJerome Glisse WREG32(R_000040_GEN_INT_CNTL, 0); 2779f022ddfSJerome Glisse /* Wait and acknowledge irq */ 2789f022ddfSJerome Glisse mdelay(1); 2799f022ddfSJerome Glisse tmp = RREG32(R_000044_GEN_INT_STATUS); 2809f022ddfSJerome Glisse WREG32(R_000044_GEN_INT_STATUS, tmp); 2819f022ddfSJerome Glisse } 2829f022ddfSJerome Glisse 2837ed220d7SMichel Dänzer static inline uint32_t r100_irq_ack(struct radeon_device *rdev) 2847ed220d7SMichel Dänzer { 2857ed220d7SMichel Dänzer uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 28605a05c50SAlex Deucher uint32_t irq_mask = RADEON_SW_INT_TEST | 28705a05c50SAlex Deucher RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 28805a05c50SAlex Deucher RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 2897ed220d7SMichel Dänzer 2907ed220d7SMichel Dänzer if (irqs) { 2917ed220d7SMichel Dänzer WREG32(RADEON_GEN_INT_STATUS, irqs); 2927ed220d7SMichel Dänzer } 2937ed220d7SMichel Dänzer return irqs & irq_mask; 2947ed220d7SMichel Dänzer } 2957ed220d7SMichel Dänzer 2967ed220d7SMichel Dänzer int r100_irq_process(struct radeon_device *rdev) 2977ed220d7SMichel Dänzer { 2983e5cb98dSAlex Deucher uint32_t status, msi_rearm; 299d4877cf2SAlex Deucher bool queue_hotplug = false; 3007ed220d7SMichel Dänzer 3017ed220d7SMichel Dänzer status = r100_irq_ack(rdev); 3027ed220d7SMichel Dänzer if (!status) { 3037ed220d7SMichel Dänzer return IRQ_NONE; 3047ed220d7SMichel Dänzer } 305a513c184SJerome Glisse if (rdev->shutdown) { 306a513c184SJerome Glisse return IRQ_NONE; 307a513c184SJerome Glisse } 3087ed220d7SMichel Dänzer while (status) { 3097ed220d7SMichel Dänzer /* SW interrupt */ 3107ed220d7SMichel Dänzer if (status & RADEON_SW_INT_TEST) { 3117ed220d7SMichel Dänzer radeon_fence_process(rdev); 3127ed220d7SMichel Dänzer } 3137ed220d7SMichel Dänzer /* Vertical blank interrupts */ 3147ed220d7SMichel Dänzer if (status & RADEON_CRTC_VBLANK_STAT) { 3157ed220d7SMichel Dänzer drm_handle_vblank(rdev->ddev, 0); 316839461d3SRafał Miłecki rdev->pm.vblank_sync = true; 31773a6d3fcSRafał Miłecki wake_up(&rdev->irq.vblank_queue); 3187ed220d7SMichel Dänzer } 3197ed220d7SMichel Dänzer if (status & RADEON_CRTC2_VBLANK_STAT) { 3207ed220d7SMichel Dänzer drm_handle_vblank(rdev->ddev, 1); 321839461d3SRafał Miłecki rdev->pm.vblank_sync = true; 32273a6d3fcSRafał Miłecki wake_up(&rdev->irq.vblank_queue); 3237ed220d7SMichel Dänzer } 32405a05c50SAlex Deucher if (status & RADEON_FP_DETECT_STAT) { 325d4877cf2SAlex Deucher queue_hotplug = true; 326d4877cf2SAlex Deucher DRM_DEBUG("HPD1\n"); 32705a05c50SAlex Deucher } 32805a05c50SAlex Deucher if (status & RADEON_FP2_DETECT_STAT) { 329d4877cf2SAlex Deucher queue_hotplug = true; 330d4877cf2SAlex Deucher DRM_DEBUG("HPD2\n"); 33105a05c50SAlex Deucher } 3327ed220d7SMichel Dänzer status = r100_irq_ack(rdev); 3337ed220d7SMichel Dänzer } 334d4877cf2SAlex Deucher if (queue_hotplug) 335d4877cf2SAlex Deucher queue_work(rdev->wq, &rdev->hotplug_work); 3363e5cb98dSAlex Deucher if (rdev->msi_enabled) { 3373e5cb98dSAlex Deucher switch (rdev->family) { 3383e5cb98dSAlex Deucher case CHIP_RS400: 3393e5cb98dSAlex Deucher case CHIP_RS480: 3403e5cb98dSAlex Deucher msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 3413e5cb98dSAlex Deucher WREG32(RADEON_AIC_CNTL, msi_rearm); 3423e5cb98dSAlex Deucher WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 3433e5cb98dSAlex Deucher break; 3443e5cb98dSAlex Deucher default: 3453e5cb98dSAlex Deucher msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; 3463e5cb98dSAlex Deucher WREG32(RADEON_MSI_REARM_EN, msi_rearm); 3473e5cb98dSAlex Deucher WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); 3483e5cb98dSAlex Deucher break; 3493e5cb98dSAlex Deucher } 3503e5cb98dSAlex Deucher } 3517ed220d7SMichel Dänzer return IRQ_HANDLED; 3527ed220d7SMichel Dänzer } 3537ed220d7SMichel Dänzer 3547ed220d7SMichel Dänzer u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 3557ed220d7SMichel Dänzer { 3567ed220d7SMichel Dänzer if (crtc == 0) 3577ed220d7SMichel Dänzer return RREG32(RADEON_CRTC_CRNT_FRAME); 3587ed220d7SMichel Dänzer else 3597ed220d7SMichel Dänzer return RREG32(RADEON_CRTC2_CRNT_FRAME); 3607ed220d7SMichel Dänzer } 3617ed220d7SMichel Dänzer 3629e5b2af7SPauli Nieminen /* Who ever call radeon_fence_emit should call ring_lock and ask 3639e5b2af7SPauli Nieminen * for enough space (today caller are ib schedule and buffer move) */ 364771fe6b9SJerome Glisse void r100_fence_ring_emit(struct radeon_device *rdev, 365771fe6b9SJerome Glisse struct radeon_fence *fence) 366771fe6b9SJerome Glisse { 3679e5b2af7SPauli Nieminen /* We have to make sure that caches are flushed before 3689e5b2af7SPauli Nieminen * CPU might read something from VRAM. */ 3699e5b2af7SPauli Nieminen radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 3709e5b2af7SPauli Nieminen radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL); 3719e5b2af7SPauli Nieminen radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 3729e5b2af7SPauli Nieminen radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); 373771fe6b9SJerome Glisse /* Wait until IDLE & CLEAN */ 3744612dc97SAlex Deucher radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 3754612dc97SAlex Deucher radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 376cafe6609SJerome Glisse radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 377cafe6609SJerome Glisse radeon_ring_write(rdev, rdev->config.r100.hdp_cntl | 378cafe6609SJerome Glisse RADEON_HDP_READ_BUFFER_INVALIDATE); 379cafe6609SJerome Glisse radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 380cafe6609SJerome Glisse radeon_ring_write(rdev, rdev->config.r100.hdp_cntl); 381771fe6b9SJerome Glisse /* Emit fence sequence & fire IRQ */ 382771fe6b9SJerome Glisse radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 383771fe6b9SJerome Glisse radeon_ring_write(rdev, fence->seq); 384771fe6b9SJerome Glisse radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 385771fe6b9SJerome Glisse radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 386771fe6b9SJerome Glisse } 387771fe6b9SJerome Glisse 388771fe6b9SJerome Glisse int r100_wb_init(struct radeon_device *rdev) 389771fe6b9SJerome Glisse { 390771fe6b9SJerome Glisse int r; 391771fe6b9SJerome Glisse 392771fe6b9SJerome Glisse if (rdev->wb.wb_obj == NULL) { 3934c788679SJerome Glisse r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, 394771fe6b9SJerome Glisse RADEON_GEM_DOMAIN_GTT, 3954c788679SJerome Glisse &rdev->wb.wb_obj); 396771fe6b9SJerome Glisse if (r) { 3974c788679SJerome Glisse dev_err(rdev->dev, "(%d) create WB buffer failed\n", r); 398771fe6b9SJerome Glisse return r; 399771fe6b9SJerome Glisse } 4004c788679SJerome Glisse r = radeon_bo_reserve(rdev->wb.wb_obj, false); 4014c788679SJerome Glisse if (unlikely(r != 0)) 4024c788679SJerome Glisse return r; 4034c788679SJerome Glisse r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 404771fe6b9SJerome Glisse &rdev->wb.gpu_addr); 405771fe6b9SJerome Glisse if (r) { 4064c788679SJerome Glisse dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r); 4074c788679SJerome Glisse radeon_bo_unreserve(rdev->wb.wb_obj); 408771fe6b9SJerome Glisse return r; 409771fe6b9SJerome Glisse } 4104c788679SJerome Glisse r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 4114c788679SJerome Glisse radeon_bo_unreserve(rdev->wb.wb_obj); 412771fe6b9SJerome Glisse if (r) { 4134c788679SJerome Glisse dev_err(rdev->dev, "(%d) map WB buffer failed\n", r); 414771fe6b9SJerome Glisse return r; 415771fe6b9SJerome Glisse } 416771fe6b9SJerome Glisse } 4179f022ddfSJerome Glisse WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr); 4189f022ddfSJerome Glisse WREG32(R_00070C_CP_RB_RPTR_ADDR, 4199f022ddfSJerome Glisse S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2)); 4209f022ddfSJerome Glisse WREG32(R_000770_SCRATCH_UMSK, 0xff); 421771fe6b9SJerome Glisse return 0; 422771fe6b9SJerome Glisse } 423771fe6b9SJerome Glisse 4249f022ddfSJerome Glisse void r100_wb_disable(struct radeon_device *rdev) 4259f022ddfSJerome Glisse { 4269f022ddfSJerome Glisse WREG32(R_000770_SCRATCH_UMSK, 0); 4279f022ddfSJerome Glisse } 4289f022ddfSJerome Glisse 429771fe6b9SJerome Glisse void r100_wb_fini(struct radeon_device *rdev) 430771fe6b9SJerome Glisse { 4314c788679SJerome Glisse int r; 4324c788679SJerome Glisse 4339f022ddfSJerome Glisse r100_wb_disable(rdev); 434771fe6b9SJerome Glisse if (rdev->wb.wb_obj) { 4354c788679SJerome Glisse r = radeon_bo_reserve(rdev->wb.wb_obj, false); 4364c788679SJerome Glisse if (unlikely(r != 0)) { 4374c788679SJerome Glisse dev_err(rdev->dev, "(%d) can't finish WB\n", r); 4384c788679SJerome Glisse return; 4394c788679SJerome Glisse } 4404c788679SJerome Glisse radeon_bo_kunmap(rdev->wb.wb_obj); 4414c788679SJerome Glisse radeon_bo_unpin(rdev->wb.wb_obj); 4424c788679SJerome Glisse radeon_bo_unreserve(rdev->wb.wb_obj); 4434c788679SJerome Glisse radeon_bo_unref(&rdev->wb.wb_obj); 444771fe6b9SJerome Glisse rdev->wb.wb = NULL; 445771fe6b9SJerome Glisse rdev->wb.wb_obj = NULL; 446771fe6b9SJerome Glisse } 447771fe6b9SJerome Glisse } 448771fe6b9SJerome Glisse 449771fe6b9SJerome Glisse int r100_copy_blit(struct radeon_device *rdev, 450771fe6b9SJerome Glisse uint64_t src_offset, 451771fe6b9SJerome Glisse uint64_t dst_offset, 452771fe6b9SJerome Glisse unsigned num_pages, 453771fe6b9SJerome Glisse struct radeon_fence *fence) 454771fe6b9SJerome Glisse { 455771fe6b9SJerome Glisse uint32_t cur_pages; 456771fe6b9SJerome Glisse uint32_t stride_bytes = PAGE_SIZE; 457771fe6b9SJerome Glisse uint32_t pitch; 458771fe6b9SJerome Glisse uint32_t stride_pixels; 459771fe6b9SJerome Glisse unsigned ndw; 460771fe6b9SJerome Glisse int num_loops; 461771fe6b9SJerome Glisse int r = 0; 462771fe6b9SJerome Glisse 463771fe6b9SJerome Glisse /* radeon limited to 16k stride */ 464771fe6b9SJerome Glisse stride_bytes &= 0x3fff; 465771fe6b9SJerome Glisse /* radeon pitch is /64 */ 466771fe6b9SJerome Glisse pitch = stride_bytes / 64; 467771fe6b9SJerome Glisse stride_pixels = stride_bytes / 4; 468771fe6b9SJerome Glisse num_loops = DIV_ROUND_UP(num_pages, 8191); 469771fe6b9SJerome Glisse 470771fe6b9SJerome Glisse /* Ask for enough room for blit + flush + fence */ 471771fe6b9SJerome Glisse ndw = 64 + (10 * num_loops); 472771fe6b9SJerome Glisse r = radeon_ring_lock(rdev, ndw); 473771fe6b9SJerome Glisse if (r) { 474771fe6b9SJerome Glisse DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 475771fe6b9SJerome Glisse return -EINVAL; 476771fe6b9SJerome Glisse } 477771fe6b9SJerome Glisse while (num_pages > 0) { 478771fe6b9SJerome Glisse cur_pages = num_pages; 479771fe6b9SJerome Glisse if (cur_pages > 8191) { 480771fe6b9SJerome Glisse cur_pages = 8191; 481771fe6b9SJerome Glisse } 482771fe6b9SJerome Glisse num_pages -= cur_pages; 483771fe6b9SJerome Glisse 484771fe6b9SJerome Glisse /* pages are in Y direction - height 485771fe6b9SJerome Glisse page width in X direction - width */ 486771fe6b9SJerome Glisse radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8)); 487771fe6b9SJerome Glisse radeon_ring_write(rdev, 488771fe6b9SJerome Glisse RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 489771fe6b9SJerome Glisse RADEON_GMC_DST_PITCH_OFFSET_CNTL | 490771fe6b9SJerome Glisse RADEON_GMC_SRC_CLIPPING | 491771fe6b9SJerome Glisse RADEON_GMC_DST_CLIPPING | 492771fe6b9SJerome Glisse RADEON_GMC_BRUSH_NONE | 493771fe6b9SJerome Glisse (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 494771fe6b9SJerome Glisse RADEON_GMC_SRC_DATATYPE_COLOR | 495771fe6b9SJerome Glisse RADEON_ROP3_S | 496771fe6b9SJerome Glisse RADEON_DP_SRC_SOURCE_MEMORY | 497771fe6b9SJerome Glisse RADEON_GMC_CLR_CMP_CNTL_DIS | 498771fe6b9SJerome Glisse RADEON_GMC_WR_MSK_DIS); 499771fe6b9SJerome Glisse radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10)); 500771fe6b9SJerome Glisse radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10)); 501771fe6b9SJerome Glisse radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 502771fe6b9SJerome Glisse radeon_ring_write(rdev, 0); 503771fe6b9SJerome Glisse radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 504771fe6b9SJerome Glisse radeon_ring_write(rdev, num_pages); 505771fe6b9SJerome Glisse radeon_ring_write(rdev, num_pages); 506771fe6b9SJerome Glisse radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); 507771fe6b9SJerome Glisse } 508771fe6b9SJerome Glisse radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 509771fe6b9SJerome Glisse radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); 510771fe6b9SJerome Glisse radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 511771fe6b9SJerome Glisse radeon_ring_write(rdev, 512771fe6b9SJerome Glisse RADEON_WAIT_2D_IDLECLEAN | 513771fe6b9SJerome Glisse RADEON_WAIT_HOST_IDLECLEAN | 514771fe6b9SJerome Glisse RADEON_WAIT_DMA_GUI_IDLE); 515771fe6b9SJerome Glisse if (fence) { 516771fe6b9SJerome Glisse r = radeon_fence_emit(rdev, fence); 517771fe6b9SJerome Glisse } 518771fe6b9SJerome Glisse radeon_ring_unlock_commit(rdev); 519771fe6b9SJerome Glisse return r; 520771fe6b9SJerome Glisse } 521771fe6b9SJerome Glisse 52245600232SJerome Glisse static int r100_cp_wait_for_idle(struct radeon_device *rdev) 52345600232SJerome Glisse { 52445600232SJerome Glisse unsigned i; 52545600232SJerome Glisse u32 tmp; 52645600232SJerome Glisse 52745600232SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 52845600232SJerome Glisse tmp = RREG32(R_000E40_RBBM_STATUS); 52945600232SJerome Glisse if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 53045600232SJerome Glisse return 0; 53145600232SJerome Glisse } 53245600232SJerome Glisse udelay(1); 53345600232SJerome Glisse } 53445600232SJerome Glisse return -1; 53545600232SJerome Glisse } 53645600232SJerome Glisse 537771fe6b9SJerome Glisse void r100_ring_start(struct radeon_device *rdev) 538771fe6b9SJerome Glisse { 539771fe6b9SJerome Glisse int r; 540771fe6b9SJerome Glisse 541771fe6b9SJerome Glisse r = radeon_ring_lock(rdev, 2); 542771fe6b9SJerome Glisse if (r) { 543771fe6b9SJerome Glisse return; 544771fe6b9SJerome Glisse } 545771fe6b9SJerome Glisse radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 546771fe6b9SJerome Glisse radeon_ring_write(rdev, 547771fe6b9SJerome Glisse RADEON_ISYNC_ANY2D_IDLE3D | 548771fe6b9SJerome Glisse RADEON_ISYNC_ANY3D_IDLE2D | 549771fe6b9SJerome Glisse RADEON_ISYNC_WAIT_IDLEGUI | 550771fe6b9SJerome Glisse RADEON_ISYNC_CPSCRATCH_IDLEGUI); 551771fe6b9SJerome Glisse radeon_ring_unlock_commit(rdev); 552771fe6b9SJerome Glisse } 553771fe6b9SJerome Glisse 55470967ab9SBen Hutchings 55570967ab9SBen Hutchings /* Load the microcode for the CP */ 55670967ab9SBen Hutchings static int r100_cp_init_microcode(struct radeon_device *rdev) 557771fe6b9SJerome Glisse { 55870967ab9SBen Hutchings struct platform_device *pdev; 55970967ab9SBen Hutchings const char *fw_name = NULL; 56070967ab9SBen Hutchings int err; 561771fe6b9SJerome Glisse 56270967ab9SBen Hutchings DRM_DEBUG("\n"); 56370967ab9SBen Hutchings 56470967ab9SBen Hutchings pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 56570967ab9SBen Hutchings err = IS_ERR(pdev); 56670967ab9SBen Hutchings if (err) { 56770967ab9SBen Hutchings printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 56870967ab9SBen Hutchings return -EINVAL; 569771fe6b9SJerome Glisse } 570771fe6b9SJerome Glisse if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 571771fe6b9SJerome Glisse (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 572771fe6b9SJerome Glisse (rdev->family == CHIP_RS200)) { 573771fe6b9SJerome Glisse DRM_INFO("Loading R100 Microcode\n"); 57470967ab9SBen Hutchings fw_name = FIRMWARE_R100; 575771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_R200) || 576771fe6b9SJerome Glisse (rdev->family == CHIP_RV250) || 577771fe6b9SJerome Glisse (rdev->family == CHIP_RV280) || 578771fe6b9SJerome Glisse (rdev->family == CHIP_RS300)) { 579771fe6b9SJerome Glisse DRM_INFO("Loading R200 Microcode\n"); 58070967ab9SBen Hutchings fw_name = FIRMWARE_R200; 581771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_R300) || 582771fe6b9SJerome Glisse (rdev->family == CHIP_R350) || 583771fe6b9SJerome Glisse (rdev->family == CHIP_RV350) || 584771fe6b9SJerome Glisse (rdev->family == CHIP_RV380) || 585771fe6b9SJerome Glisse (rdev->family == CHIP_RS400) || 586771fe6b9SJerome Glisse (rdev->family == CHIP_RS480)) { 587771fe6b9SJerome Glisse DRM_INFO("Loading R300 Microcode\n"); 58870967ab9SBen Hutchings fw_name = FIRMWARE_R300; 589771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_R420) || 590771fe6b9SJerome Glisse (rdev->family == CHIP_R423) || 591771fe6b9SJerome Glisse (rdev->family == CHIP_RV410)) { 592771fe6b9SJerome Glisse DRM_INFO("Loading R400 Microcode\n"); 59370967ab9SBen Hutchings fw_name = FIRMWARE_R420; 594771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_RS690) || 595771fe6b9SJerome Glisse (rdev->family == CHIP_RS740)) { 596771fe6b9SJerome Glisse DRM_INFO("Loading RS690/RS740 Microcode\n"); 59770967ab9SBen Hutchings fw_name = FIRMWARE_RS690; 598771fe6b9SJerome Glisse } else if (rdev->family == CHIP_RS600) { 599771fe6b9SJerome Glisse DRM_INFO("Loading RS600 Microcode\n"); 60070967ab9SBen Hutchings fw_name = FIRMWARE_RS600; 601771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_RV515) || 602771fe6b9SJerome Glisse (rdev->family == CHIP_R520) || 603771fe6b9SJerome Glisse (rdev->family == CHIP_RV530) || 604771fe6b9SJerome Glisse (rdev->family == CHIP_R580) || 605771fe6b9SJerome Glisse (rdev->family == CHIP_RV560) || 606771fe6b9SJerome Glisse (rdev->family == CHIP_RV570)) { 607771fe6b9SJerome Glisse DRM_INFO("Loading R500 Microcode\n"); 60870967ab9SBen Hutchings fw_name = FIRMWARE_R520; 60970967ab9SBen Hutchings } 61070967ab9SBen Hutchings 6113ce0a23dSJerome Glisse err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 61270967ab9SBen Hutchings platform_device_unregister(pdev); 61370967ab9SBen Hutchings if (err) { 61470967ab9SBen Hutchings printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", 61570967ab9SBen Hutchings fw_name); 6163ce0a23dSJerome Glisse } else if (rdev->me_fw->size % 8) { 61770967ab9SBen Hutchings printk(KERN_ERR 61870967ab9SBen Hutchings "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 6193ce0a23dSJerome Glisse rdev->me_fw->size, fw_name); 62070967ab9SBen Hutchings err = -EINVAL; 6213ce0a23dSJerome Glisse release_firmware(rdev->me_fw); 6223ce0a23dSJerome Glisse rdev->me_fw = NULL; 62370967ab9SBen Hutchings } 62470967ab9SBen Hutchings return err; 62570967ab9SBen Hutchings } 626d4550907SJerome Glisse 62770967ab9SBen Hutchings static void r100_cp_load_microcode(struct radeon_device *rdev) 62870967ab9SBen Hutchings { 62970967ab9SBen Hutchings const __be32 *fw_data; 63070967ab9SBen Hutchings int i, size; 63170967ab9SBen Hutchings 63270967ab9SBen Hutchings if (r100_gui_wait_for_idle(rdev)) { 63370967ab9SBen Hutchings printk(KERN_WARNING "Failed to wait GUI idle while " 63470967ab9SBen Hutchings "programming pipes. Bad things might happen.\n"); 63570967ab9SBen Hutchings } 63670967ab9SBen Hutchings 6373ce0a23dSJerome Glisse if (rdev->me_fw) { 6383ce0a23dSJerome Glisse size = rdev->me_fw->size / 4; 6393ce0a23dSJerome Glisse fw_data = (const __be32 *)&rdev->me_fw->data[0]; 64070967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_ADDR, 0); 64170967ab9SBen Hutchings for (i = 0; i < size; i += 2) { 64270967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_DATAH, 64370967ab9SBen Hutchings be32_to_cpup(&fw_data[i])); 64470967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_DATAL, 64570967ab9SBen Hutchings be32_to_cpup(&fw_data[i + 1])); 646771fe6b9SJerome Glisse } 647771fe6b9SJerome Glisse } 648771fe6b9SJerome Glisse } 649771fe6b9SJerome Glisse 650771fe6b9SJerome Glisse int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 651771fe6b9SJerome Glisse { 652771fe6b9SJerome Glisse unsigned rb_bufsz; 653771fe6b9SJerome Glisse unsigned rb_blksz; 654771fe6b9SJerome Glisse unsigned max_fetch; 655771fe6b9SJerome Glisse unsigned pre_write_timer; 656771fe6b9SJerome Glisse unsigned pre_write_limit; 657771fe6b9SJerome Glisse unsigned indirect2_start; 658771fe6b9SJerome Glisse unsigned indirect1_start; 659771fe6b9SJerome Glisse uint32_t tmp; 660771fe6b9SJerome Glisse int r; 661771fe6b9SJerome Glisse 662771fe6b9SJerome Glisse if (r100_debugfs_cp_init(rdev)) { 663771fe6b9SJerome Glisse DRM_ERROR("Failed to register debugfs file for CP !\n"); 664771fe6b9SJerome Glisse } 6653ce0a23dSJerome Glisse if (!rdev->me_fw) { 66670967ab9SBen Hutchings r = r100_cp_init_microcode(rdev); 66770967ab9SBen Hutchings if (r) { 66870967ab9SBen Hutchings DRM_ERROR("Failed to load firmware!\n"); 66970967ab9SBen Hutchings return r; 67070967ab9SBen Hutchings } 67170967ab9SBen Hutchings } 67270967ab9SBen Hutchings 673771fe6b9SJerome Glisse /* Align ring size */ 674771fe6b9SJerome Glisse rb_bufsz = drm_order(ring_size / 8); 675771fe6b9SJerome Glisse ring_size = (1 << (rb_bufsz + 1)) * 4; 676771fe6b9SJerome Glisse r100_cp_load_microcode(rdev); 677771fe6b9SJerome Glisse r = radeon_ring_init(rdev, ring_size); 678771fe6b9SJerome Glisse if (r) { 679771fe6b9SJerome Glisse return r; 680771fe6b9SJerome Glisse } 681771fe6b9SJerome Glisse /* Each time the cp read 1024 bytes (16 dword/quadword) update 682771fe6b9SJerome Glisse * the rptr copy in system ram */ 683771fe6b9SJerome Glisse rb_blksz = 9; 684771fe6b9SJerome Glisse /* cp will read 128bytes at a time (4 dwords) */ 685771fe6b9SJerome Glisse max_fetch = 1; 686771fe6b9SJerome Glisse rdev->cp.align_mask = 16 - 1; 687771fe6b9SJerome Glisse /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 688771fe6b9SJerome Glisse pre_write_timer = 64; 689771fe6b9SJerome Glisse /* Force CP_RB_WPTR write if written more than one time before the 690771fe6b9SJerome Glisse * delay expire 691771fe6b9SJerome Glisse */ 692771fe6b9SJerome Glisse pre_write_limit = 0; 693771fe6b9SJerome Glisse /* Setup the cp cache like this (cache size is 96 dwords) : 694771fe6b9SJerome Glisse * RING 0 to 15 695771fe6b9SJerome Glisse * INDIRECT1 16 to 79 696771fe6b9SJerome Glisse * INDIRECT2 80 to 95 697771fe6b9SJerome Glisse * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 698771fe6b9SJerome Glisse * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 699771fe6b9SJerome Glisse * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 700771fe6b9SJerome Glisse * Idea being that most of the gpu cmd will be through indirect1 buffer 701771fe6b9SJerome Glisse * so it gets the bigger cache. 702771fe6b9SJerome Glisse */ 703771fe6b9SJerome Glisse indirect2_start = 80; 704771fe6b9SJerome Glisse indirect1_start = 16; 705771fe6b9SJerome Glisse /* cp setup */ 706771fe6b9SJerome Glisse WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 707d6f28938SAlex Deucher tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 708771fe6b9SJerome Glisse REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 709771fe6b9SJerome Glisse REG_SET(RADEON_MAX_FETCH, max_fetch) | 710771fe6b9SJerome Glisse RADEON_RB_NO_UPDATE); 711d6f28938SAlex Deucher #ifdef __BIG_ENDIAN 712d6f28938SAlex Deucher tmp |= RADEON_BUF_SWAP_32BIT; 713d6f28938SAlex Deucher #endif 714d6f28938SAlex Deucher WREG32(RADEON_CP_RB_CNTL, tmp); 715d6f28938SAlex Deucher 716771fe6b9SJerome Glisse /* Set ring address */ 717771fe6b9SJerome Glisse DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); 718771fe6b9SJerome Glisse WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); 719771fe6b9SJerome Glisse /* Force read & write ptr to 0 */ 720771fe6b9SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 721771fe6b9SJerome Glisse WREG32(RADEON_CP_RB_RPTR_WR, 0); 722771fe6b9SJerome Glisse WREG32(RADEON_CP_RB_WPTR, 0); 723771fe6b9SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp); 724771fe6b9SJerome Glisse udelay(10); 725771fe6b9SJerome Glisse rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 726771fe6b9SJerome Glisse rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); 7279e5786bdSDave Airlie /* protect against crazy HW on resume */ 7289e5786bdSDave Airlie rdev->cp.wptr &= rdev->cp.ptr_mask; 729771fe6b9SJerome Glisse /* Set cp mode to bus mastering & enable cp*/ 730771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_MODE, 731771fe6b9SJerome Glisse REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 732771fe6b9SJerome Glisse REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 733771fe6b9SJerome Glisse WREG32(0x718, 0); 734771fe6b9SJerome Glisse WREG32(0x744, 0x00004D4D); 735771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 736771fe6b9SJerome Glisse radeon_ring_start(rdev); 737771fe6b9SJerome Glisse r = radeon_ring_test(rdev); 738771fe6b9SJerome Glisse if (r) { 739771fe6b9SJerome Glisse DRM_ERROR("radeon: cp isn't working (%d).\n", r); 740771fe6b9SJerome Glisse return r; 741771fe6b9SJerome Glisse } 742771fe6b9SJerome Glisse rdev->cp.ready = true; 743771fe6b9SJerome Glisse return 0; 744771fe6b9SJerome Glisse } 745771fe6b9SJerome Glisse 746771fe6b9SJerome Glisse void r100_cp_fini(struct radeon_device *rdev) 747771fe6b9SJerome Glisse { 74845600232SJerome Glisse if (r100_cp_wait_for_idle(rdev)) { 74945600232SJerome Glisse DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 75045600232SJerome Glisse } 751771fe6b9SJerome Glisse /* Disable ring */ 752a18d7ea1SJerome Glisse r100_cp_disable(rdev); 753771fe6b9SJerome Glisse radeon_ring_fini(rdev); 754771fe6b9SJerome Glisse DRM_INFO("radeon: cp finalized\n"); 755771fe6b9SJerome Glisse } 756771fe6b9SJerome Glisse 757771fe6b9SJerome Glisse void r100_cp_disable(struct radeon_device *rdev) 758771fe6b9SJerome Glisse { 759771fe6b9SJerome Glisse /* Disable ring */ 760771fe6b9SJerome Glisse rdev->cp.ready = false; 761771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_MODE, 0); 762771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, 0); 763771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 764771fe6b9SJerome Glisse printk(KERN_WARNING "Failed to wait GUI idle while " 765771fe6b9SJerome Glisse "programming pipes. Bad things might happen.\n"); 766771fe6b9SJerome Glisse } 767771fe6b9SJerome Glisse } 768771fe6b9SJerome Glisse 7693ce0a23dSJerome Glisse void r100_cp_commit(struct radeon_device *rdev) 7703ce0a23dSJerome Glisse { 7713ce0a23dSJerome Glisse WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 7723ce0a23dSJerome Glisse (void)RREG32(RADEON_CP_RB_WPTR); 7733ce0a23dSJerome Glisse } 7743ce0a23dSJerome Glisse 775771fe6b9SJerome Glisse 776771fe6b9SJerome Glisse /* 777771fe6b9SJerome Glisse * CS functions 778771fe6b9SJerome Glisse */ 779771fe6b9SJerome Glisse int r100_cs_parse_packet0(struct radeon_cs_parser *p, 780771fe6b9SJerome Glisse struct radeon_cs_packet *pkt, 781068a117cSJerome Glisse const unsigned *auth, unsigned n, 782771fe6b9SJerome Glisse radeon_packet0_check_t check) 783771fe6b9SJerome Glisse { 784771fe6b9SJerome Glisse unsigned reg; 785771fe6b9SJerome Glisse unsigned i, j, m; 786771fe6b9SJerome Glisse unsigned idx; 787771fe6b9SJerome Glisse int r; 788771fe6b9SJerome Glisse 789771fe6b9SJerome Glisse idx = pkt->idx + 1; 790771fe6b9SJerome Glisse reg = pkt->reg; 791068a117cSJerome Glisse /* Check that register fall into register range 792068a117cSJerome Glisse * determined by the number of entry (n) in the 793068a117cSJerome Glisse * safe register bitmap. 794068a117cSJerome Glisse */ 795771fe6b9SJerome Glisse if (pkt->one_reg_wr) { 796771fe6b9SJerome Glisse if ((reg >> 7) > n) { 797771fe6b9SJerome Glisse return -EINVAL; 798771fe6b9SJerome Glisse } 799771fe6b9SJerome Glisse } else { 800771fe6b9SJerome Glisse if (((reg + (pkt->count << 2)) >> 7) > n) { 801771fe6b9SJerome Glisse return -EINVAL; 802771fe6b9SJerome Glisse } 803771fe6b9SJerome Glisse } 804771fe6b9SJerome Glisse for (i = 0; i <= pkt->count; i++, idx++) { 805771fe6b9SJerome Glisse j = (reg >> 7); 806771fe6b9SJerome Glisse m = 1 << ((reg >> 2) & 31); 807771fe6b9SJerome Glisse if (auth[j] & m) { 808771fe6b9SJerome Glisse r = check(p, pkt, idx, reg); 809771fe6b9SJerome Glisse if (r) { 810771fe6b9SJerome Glisse return r; 811771fe6b9SJerome Glisse } 812771fe6b9SJerome Glisse } 813771fe6b9SJerome Glisse if (pkt->one_reg_wr) { 814771fe6b9SJerome Glisse if (!(auth[j] & m)) { 815771fe6b9SJerome Glisse break; 816771fe6b9SJerome Glisse } 817771fe6b9SJerome Glisse } else { 818771fe6b9SJerome Glisse reg += 4; 819771fe6b9SJerome Glisse } 820771fe6b9SJerome Glisse } 821771fe6b9SJerome Glisse return 0; 822771fe6b9SJerome Glisse } 823771fe6b9SJerome Glisse 824771fe6b9SJerome Glisse void r100_cs_dump_packet(struct radeon_cs_parser *p, 825771fe6b9SJerome Glisse struct radeon_cs_packet *pkt) 826771fe6b9SJerome Glisse { 827771fe6b9SJerome Glisse volatile uint32_t *ib; 828771fe6b9SJerome Glisse unsigned i; 829771fe6b9SJerome Glisse unsigned idx; 830771fe6b9SJerome Glisse 831771fe6b9SJerome Glisse ib = p->ib->ptr; 832771fe6b9SJerome Glisse idx = pkt->idx; 833771fe6b9SJerome Glisse for (i = 0; i <= (pkt->count + 1); i++, idx++) { 834771fe6b9SJerome Glisse DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 835771fe6b9SJerome Glisse } 836771fe6b9SJerome Glisse } 837771fe6b9SJerome Glisse 838771fe6b9SJerome Glisse /** 839771fe6b9SJerome Glisse * r100_cs_packet_parse() - parse cp packet and point ib index to next packet 840771fe6b9SJerome Glisse * @parser: parser structure holding parsing context. 841771fe6b9SJerome Glisse * @pkt: where to store packet informations 842771fe6b9SJerome Glisse * 843771fe6b9SJerome Glisse * Assume that chunk_ib_index is properly set. Will return -EINVAL 844771fe6b9SJerome Glisse * if packet is bigger than remaining ib size. or if packets is unknown. 845771fe6b9SJerome Glisse **/ 846771fe6b9SJerome Glisse int r100_cs_packet_parse(struct radeon_cs_parser *p, 847771fe6b9SJerome Glisse struct radeon_cs_packet *pkt, 848771fe6b9SJerome Glisse unsigned idx) 849771fe6b9SJerome Glisse { 850771fe6b9SJerome Glisse struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 851fa99239cSRoel Kluin uint32_t header; 852771fe6b9SJerome Glisse 853771fe6b9SJerome Glisse if (idx >= ib_chunk->length_dw) { 854771fe6b9SJerome Glisse DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 855771fe6b9SJerome Glisse idx, ib_chunk->length_dw); 856771fe6b9SJerome Glisse return -EINVAL; 857771fe6b9SJerome Glisse } 858513bcb46SDave Airlie header = radeon_get_ib_value(p, idx); 859771fe6b9SJerome Glisse pkt->idx = idx; 860771fe6b9SJerome Glisse pkt->type = CP_PACKET_GET_TYPE(header); 861771fe6b9SJerome Glisse pkt->count = CP_PACKET_GET_COUNT(header); 862771fe6b9SJerome Glisse switch (pkt->type) { 863771fe6b9SJerome Glisse case PACKET_TYPE0: 864771fe6b9SJerome Glisse pkt->reg = CP_PACKET0_GET_REG(header); 865771fe6b9SJerome Glisse pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); 866771fe6b9SJerome Glisse break; 867771fe6b9SJerome Glisse case PACKET_TYPE3: 868771fe6b9SJerome Glisse pkt->opcode = CP_PACKET3_GET_OPCODE(header); 869771fe6b9SJerome Glisse break; 870771fe6b9SJerome Glisse case PACKET_TYPE2: 871771fe6b9SJerome Glisse pkt->count = -1; 872771fe6b9SJerome Glisse break; 873771fe6b9SJerome Glisse default: 874771fe6b9SJerome Glisse DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 875771fe6b9SJerome Glisse return -EINVAL; 876771fe6b9SJerome Glisse } 877771fe6b9SJerome Glisse if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 878771fe6b9SJerome Glisse DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 879771fe6b9SJerome Glisse pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 880771fe6b9SJerome Glisse return -EINVAL; 881771fe6b9SJerome Glisse } 882771fe6b9SJerome Glisse return 0; 883771fe6b9SJerome Glisse } 884771fe6b9SJerome Glisse 885771fe6b9SJerome Glisse /** 886531369e6SDave Airlie * r100_cs_packet_next_vline() - parse userspace VLINE packet 887531369e6SDave Airlie * @parser: parser structure holding parsing context. 888531369e6SDave Airlie * 889531369e6SDave Airlie * Userspace sends a special sequence for VLINE waits. 890531369e6SDave Airlie * PACKET0 - VLINE_START_END + value 891531369e6SDave Airlie * PACKET0 - WAIT_UNTIL +_value 892531369e6SDave Airlie * RELOC (P3) - crtc_id in reloc. 893531369e6SDave Airlie * 894531369e6SDave Airlie * This function parses this and relocates the VLINE START END 895531369e6SDave Airlie * and WAIT UNTIL packets to the correct crtc. 896531369e6SDave Airlie * It also detects a switched off crtc and nulls out the 897531369e6SDave Airlie * wait in that case. 898531369e6SDave Airlie */ 899531369e6SDave Airlie int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 900531369e6SDave Airlie { 901531369e6SDave Airlie struct drm_mode_object *obj; 902531369e6SDave Airlie struct drm_crtc *crtc; 903531369e6SDave Airlie struct radeon_crtc *radeon_crtc; 904531369e6SDave Airlie struct radeon_cs_packet p3reloc, waitreloc; 905531369e6SDave Airlie int crtc_id; 906531369e6SDave Airlie int r; 907531369e6SDave Airlie uint32_t header, h_idx, reg; 908513bcb46SDave Airlie volatile uint32_t *ib; 909531369e6SDave Airlie 910513bcb46SDave Airlie ib = p->ib->ptr; 911531369e6SDave Airlie 912531369e6SDave Airlie /* parse the wait until */ 913531369e6SDave Airlie r = r100_cs_packet_parse(p, &waitreloc, p->idx); 914531369e6SDave Airlie if (r) 915531369e6SDave Airlie return r; 916531369e6SDave Airlie 917531369e6SDave Airlie /* check its a wait until and only 1 count */ 918531369e6SDave Airlie if (waitreloc.reg != RADEON_WAIT_UNTIL || 919531369e6SDave Airlie waitreloc.count != 0) { 920531369e6SDave Airlie DRM_ERROR("vline wait had illegal wait until segment\n"); 921531369e6SDave Airlie r = -EINVAL; 922531369e6SDave Airlie return r; 923531369e6SDave Airlie } 924531369e6SDave Airlie 925513bcb46SDave Airlie if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 926531369e6SDave Airlie DRM_ERROR("vline wait had illegal wait until\n"); 927531369e6SDave Airlie r = -EINVAL; 928531369e6SDave Airlie return r; 929531369e6SDave Airlie } 930531369e6SDave Airlie 931531369e6SDave Airlie /* jump over the NOP */ 93290ebd065SAlex Deucher r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 933531369e6SDave Airlie if (r) 934531369e6SDave Airlie return r; 935531369e6SDave Airlie 936531369e6SDave Airlie h_idx = p->idx - 2; 93790ebd065SAlex Deucher p->idx += waitreloc.count + 2; 93890ebd065SAlex Deucher p->idx += p3reloc.count + 2; 939531369e6SDave Airlie 940513bcb46SDave Airlie header = radeon_get_ib_value(p, h_idx); 941513bcb46SDave Airlie crtc_id = radeon_get_ib_value(p, h_idx + 5); 942d4ac6a05SDave Airlie reg = CP_PACKET0_GET_REG(header); 943531369e6SDave Airlie mutex_lock(&p->rdev->ddev->mode_config.mutex); 944531369e6SDave Airlie obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 945531369e6SDave Airlie if (!obj) { 946531369e6SDave Airlie DRM_ERROR("cannot find crtc %d\n", crtc_id); 947531369e6SDave Airlie r = -EINVAL; 948531369e6SDave Airlie goto out; 949531369e6SDave Airlie } 950531369e6SDave Airlie crtc = obj_to_crtc(obj); 951531369e6SDave Airlie radeon_crtc = to_radeon_crtc(crtc); 952531369e6SDave Airlie crtc_id = radeon_crtc->crtc_id; 953531369e6SDave Airlie 954531369e6SDave Airlie if (!crtc->enabled) { 955531369e6SDave Airlie /* if the CRTC isn't enabled - we need to nop out the wait until */ 956513bcb46SDave Airlie ib[h_idx + 2] = PACKET2(0); 957513bcb46SDave Airlie ib[h_idx + 3] = PACKET2(0); 958531369e6SDave Airlie } else if (crtc_id == 1) { 959531369e6SDave Airlie switch (reg) { 960531369e6SDave Airlie case AVIVO_D1MODE_VLINE_START_END: 96190ebd065SAlex Deucher header &= ~R300_CP_PACKET0_REG_MASK; 962531369e6SDave Airlie header |= AVIVO_D2MODE_VLINE_START_END >> 2; 963531369e6SDave Airlie break; 964531369e6SDave Airlie case RADEON_CRTC_GUI_TRIG_VLINE: 96590ebd065SAlex Deucher header &= ~R300_CP_PACKET0_REG_MASK; 966531369e6SDave Airlie header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 967531369e6SDave Airlie break; 968531369e6SDave Airlie default: 969531369e6SDave Airlie DRM_ERROR("unknown crtc reloc\n"); 970531369e6SDave Airlie r = -EINVAL; 971531369e6SDave Airlie goto out; 972531369e6SDave Airlie } 973513bcb46SDave Airlie ib[h_idx] = header; 974513bcb46SDave Airlie ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 975531369e6SDave Airlie } 976531369e6SDave Airlie out: 977531369e6SDave Airlie mutex_unlock(&p->rdev->ddev->mode_config.mutex); 978531369e6SDave Airlie return r; 979531369e6SDave Airlie } 980531369e6SDave Airlie 981531369e6SDave Airlie /** 982771fe6b9SJerome Glisse * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 983771fe6b9SJerome Glisse * @parser: parser structure holding parsing context. 984771fe6b9SJerome Glisse * @data: pointer to relocation data 985771fe6b9SJerome Glisse * @offset_start: starting offset 986771fe6b9SJerome Glisse * @offset_mask: offset mask (to align start offset on) 987771fe6b9SJerome Glisse * @reloc: reloc informations 988771fe6b9SJerome Glisse * 989771fe6b9SJerome Glisse * Check next packet is relocation packet3, do bo validation and compute 990771fe6b9SJerome Glisse * GPU offset using the provided start. 991771fe6b9SJerome Glisse **/ 992771fe6b9SJerome Glisse int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 993771fe6b9SJerome Glisse struct radeon_cs_reloc **cs_reloc) 994771fe6b9SJerome Glisse { 995771fe6b9SJerome Glisse struct radeon_cs_chunk *relocs_chunk; 996771fe6b9SJerome Glisse struct radeon_cs_packet p3reloc; 997771fe6b9SJerome Glisse unsigned idx; 998771fe6b9SJerome Glisse int r; 999771fe6b9SJerome Glisse 1000771fe6b9SJerome Glisse if (p->chunk_relocs_idx == -1) { 1001771fe6b9SJerome Glisse DRM_ERROR("No relocation chunk !\n"); 1002771fe6b9SJerome Glisse return -EINVAL; 1003771fe6b9SJerome Glisse } 1004771fe6b9SJerome Glisse *cs_reloc = NULL; 1005771fe6b9SJerome Glisse relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 1006771fe6b9SJerome Glisse r = r100_cs_packet_parse(p, &p3reloc, p->idx); 1007771fe6b9SJerome Glisse if (r) { 1008771fe6b9SJerome Glisse return r; 1009771fe6b9SJerome Glisse } 1010771fe6b9SJerome Glisse p->idx += p3reloc.count + 2; 1011771fe6b9SJerome Glisse if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 1012771fe6b9SJerome Glisse DRM_ERROR("No packet3 for relocation for packet at %d.\n", 1013771fe6b9SJerome Glisse p3reloc.idx); 1014771fe6b9SJerome Glisse r100_cs_dump_packet(p, &p3reloc); 1015771fe6b9SJerome Glisse return -EINVAL; 1016771fe6b9SJerome Glisse } 1017513bcb46SDave Airlie idx = radeon_get_ib_value(p, p3reloc.idx + 1); 1018771fe6b9SJerome Glisse if (idx >= relocs_chunk->length_dw) { 1019771fe6b9SJerome Glisse DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 1020771fe6b9SJerome Glisse idx, relocs_chunk->length_dw); 1021771fe6b9SJerome Glisse r100_cs_dump_packet(p, &p3reloc); 1022771fe6b9SJerome Glisse return -EINVAL; 1023771fe6b9SJerome Glisse } 1024771fe6b9SJerome Glisse /* FIXME: we assume reloc size is 4 dwords */ 1025771fe6b9SJerome Glisse *cs_reloc = p->relocs_ptr[(idx / 4)]; 1026771fe6b9SJerome Glisse return 0; 1027771fe6b9SJerome Glisse } 1028771fe6b9SJerome Glisse 1029551ebd83SDave Airlie static int r100_get_vtx_size(uint32_t vtx_fmt) 1030551ebd83SDave Airlie { 1031551ebd83SDave Airlie int vtx_size; 1032551ebd83SDave Airlie vtx_size = 2; 1033551ebd83SDave Airlie /* ordered according to bits in spec */ 1034551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1035551ebd83SDave Airlie vtx_size++; 1036551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1037551ebd83SDave Airlie vtx_size += 3; 1038551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1039551ebd83SDave Airlie vtx_size++; 1040551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1041551ebd83SDave Airlie vtx_size++; 1042551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1043551ebd83SDave Airlie vtx_size += 3; 1044551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1045551ebd83SDave Airlie vtx_size++; 1046551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1047551ebd83SDave Airlie vtx_size++; 1048551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1049551ebd83SDave Airlie vtx_size += 2; 1050551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1051551ebd83SDave Airlie vtx_size += 2; 1052551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1053551ebd83SDave Airlie vtx_size++; 1054551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1055551ebd83SDave Airlie vtx_size += 2; 1056551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1057551ebd83SDave Airlie vtx_size++; 1058551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1059551ebd83SDave Airlie vtx_size += 2; 1060551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1061551ebd83SDave Airlie vtx_size++; 1062551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1063551ebd83SDave Airlie vtx_size++; 1064551ebd83SDave Airlie /* blend weight */ 1065551ebd83SDave Airlie if (vtx_fmt & (0x7 << 15)) 1066551ebd83SDave Airlie vtx_size += (vtx_fmt >> 15) & 0x7; 1067551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1068551ebd83SDave Airlie vtx_size += 3; 1069551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1070551ebd83SDave Airlie vtx_size += 2; 1071551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1072551ebd83SDave Airlie vtx_size++; 1073551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1074551ebd83SDave Airlie vtx_size++; 1075551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1076551ebd83SDave Airlie vtx_size++; 1077551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1078551ebd83SDave Airlie vtx_size++; 1079551ebd83SDave Airlie return vtx_size; 1080551ebd83SDave Airlie } 1081551ebd83SDave Airlie 1082771fe6b9SJerome Glisse static int r100_packet0_check(struct radeon_cs_parser *p, 1083551ebd83SDave Airlie struct radeon_cs_packet *pkt, 1084551ebd83SDave Airlie unsigned idx, unsigned reg) 1085771fe6b9SJerome Glisse { 1086771fe6b9SJerome Glisse struct radeon_cs_reloc *reloc; 1087551ebd83SDave Airlie struct r100_cs_track *track; 1088771fe6b9SJerome Glisse volatile uint32_t *ib; 1089771fe6b9SJerome Glisse uint32_t tmp; 1090771fe6b9SJerome Glisse int r; 1091551ebd83SDave Airlie int i, face; 1092e024e110SDave Airlie u32 tile_flags = 0; 1093513bcb46SDave Airlie u32 idx_value; 1094771fe6b9SJerome Glisse 1095771fe6b9SJerome Glisse ib = p->ib->ptr; 1096551ebd83SDave Airlie track = (struct r100_cs_track *)p->track; 1097551ebd83SDave Airlie 1098513bcb46SDave Airlie idx_value = radeon_get_ib_value(p, idx); 1099513bcb46SDave Airlie 1100771fe6b9SJerome Glisse switch (reg) { 1101531369e6SDave Airlie case RADEON_CRTC_GUI_TRIG_VLINE: 1102531369e6SDave Airlie r = r100_cs_packet_parse_vline(p); 1103531369e6SDave Airlie if (r) { 1104531369e6SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1105531369e6SDave Airlie idx, reg); 1106531369e6SDave Airlie r100_cs_dump_packet(p, pkt); 1107531369e6SDave Airlie return r; 1108531369e6SDave Airlie } 1109531369e6SDave Airlie break; 1110771fe6b9SJerome Glisse /* FIXME: only allow PACKET3 blit? easier to check for out of 1111771fe6b9SJerome Glisse * range access */ 1112771fe6b9SJerome Glisse case RADEON_DST_PITCH_OFFSET: 1113771fe6b9SJerome Glisse case RADEON_SRC_PITCH_OFFSET: 1114551ebd83SDave Airlie r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1115551ebd83SDave Airlie if (r) 1116551ebd83SDave Airlie return r; 1117551ebd83SDave Airlie break; 1118551ebd83SDave Airlie case RADEON_RB3D_DEPTHOFFSET: 1119771fe6b9SJerome Glisse r = r100_cs_packet_next_reloc(p, &reloc); 1120771fe6b9SJerome Glisse if (r) { 1121771fe6b9SJerome Glisse DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1122771fe6b9SJerome Glisse idx, reg); 1123771fe6b9SJerome Glisse r100_cs_dump_packet(p, pkt); 1124771fe6b9SJerome Glisse return r; 1125771fe6b9SJerome Glisse } 1126551ebd83SDave Airlie track->zb.robj = reloc->robj; 1127513bcb46SDave Airlie track->zb.offset = idx_value; 1128513bcb46SDave Airlie ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1129771fe6b9SJerome Glisse break; 1130771fe6b9SJerome Glisse case RADEON_RB3D_COLOROFFSET: 1131551ebd83SDave Airlie r = r100_cs_packet_next_reloc(p, &reloc); 1132551ebd83SDave Airlie if (r) { 1133551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1134551ebd83SDave Airlie idx, reg); 1135551ebd83SDave Airlie r100_cs_dump_packet(p, pkt); 1136551ebd83SDave Airlie return r; 1137551ebd83SDave Airlie } 1138551ebd83SDave Airlie track->cb[0].robj = reloc->robj; 1139513bcb46SDave Airlie track->cb[0].offset = idx_value; 1140513bcb46SDave Airlie ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1141551ebd83SDave Airlie break; 1142771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_0: 1143771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_1: 1144771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_2: 1145551ebd83SDave Airlie i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1146771fe6b9SJerome Glisse r = r100_cs_packet_next_reloc(p, &reloc); 1147771fe6b9SJerome Glisse if (r) { 1148771fe6b9SJerome Glisse DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1149771fe6b9SJerome Glisse idx, reg); 1150771fe6b9SJerome Glisse r100_cs_dump_packet(p, pkt); 1151771fe6b9SJerome Glisse return r; 1152771fe6b9SJerome Glisse } 1153513bcb46SDave Airlie ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1154551ebd83SDave Airlie track->textures[i].robj = reloc->robj; 1155771fe6b9SJerome Glisse break; 1156551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_0: 1157551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_1: 1158551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_2: 1159551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_3: 1160551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_4: 1161551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1162551ebd83SDave Airlie r = r100_cs_packet_next_reloc(p, &reloc); 1163551ebd83SDave Airlie if (r) { 1164551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1165551ebd83SDave Airlie idx, reg); 1166551ebd83SDave Airlie r100_cs_dump_packet(p, pkt); 1167551ebd83SDave Airlie return r; 1168551ebd83SDave Airlie } 1169513bcb46SDave Airlie track->textures[0].cube_info[i].offset = idx_value; 1170513bcb46SDave Airlie ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1171551ebd83SDave Airlie track->textures[0].cube_info[i].robj = reloc->robj; 1172551ebd83SDave Airlie break; 1173551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_0: 1174551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_1: 1175551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_2: 1176551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_3: 1177551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_4: 1178551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1179551ebd83SDave Airlie r = r100_cs_packet_next_reloc(p, &reloc); 1180551ebd83SDave Airlie if (r) { 1181551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1182551ebd83SDave Airlie idx, reg); 1183551ebd83SDave Airlie r100_cs_dump_packet(p, pkt); 1184551ebd83SDave Airlie return r; 1185551ebd83SDave Airlie } 1186513bcb46SDave Airlie track->textures[1].cube_info[i].offset = idx_value; 1187513bcb46SDave Airlie ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1188551ebd83SDave Airlie track->textures[1].cube_info[i].robj = reloc->robj; 1189551ebd83SDave Airlie break; 1190551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_0: 1191551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_1: 1192551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_2: 1193551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_3: 1194551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_4: 1195551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1196551ebd83SDave Airlie r = r100_cs_packet_next_reloc(p, &reloc); 1197551ebd83SDave Airlie if (r) { 1198551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1199551ebd83SDave Airlie idx, reg); 1200551ebd83SDave Airlie r100_cs_dump_packet(p, pkt); 1201551ebd83SDave Airlie return r; 1202551ebd83SDave Airlie } 1203513bcb46SDave Airlie track->textures[2].cube_info[i].offset = idx_value; 1204513bcb46SDave Airlie ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1205551ebd83SDave Airlie track->textures[2].cube_info[i].robj = reloc->robj; 1206551ebd83SDave Airlie break; 1207551ebd83SDave Airlie case RADEON_RE_WIDTH_HEIGHT: 1208513bcb46SDave Airlie track->maxy = ((idx_value >> 16) & 0x7FF); 1209551ebd83SDave Airlie break; 1210e024e110SDave Airlie case RADEON_RB3D_COLORPITCH: 1211e024e110SDave Airlie r = r100_cs_packet_next_reloc(p, &reloc); 1212e024e110SDave Airlie if (r) { 1213e024e110SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1214e024e110SDave Airlie idx, reg); 1215e024e110SDave Airlie r100_cs_dump_packet(p, pkt); 1216e024e110SDave Airlie return r; 1217e024e110SDave Airlie } 1218e024e110SDave Airlie 1219e024e110SDave Airlie if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1220e024e110SDave Airlie tile_flags |= RADEON_COLOR_TILE_ENABLE; 1221e024e110SDave Airlie if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1222e024e110SDave Airlie tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1223e024e110SDave Airlie 1224513bcb46SDave Airlie tmp = idx_value & ~(0x7 << 16); 1225e024e110SDave Airlie tmp |= tile_flags; 1226e024e110SDave Airlie ib[idx] = tmp; 1227551ebd83SDave Airlie 1228513bcb46SDave Airlie track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1229551ebd83SDave Airlie break; 1230551ebd83SDave Airlie case RADEON_RB3D_DEPTHPITCH: 1231513bcb46SDave Airlie track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1232551ebd83SDave Airlie break; 1233551ebd83SDave Airlie case RADEON_RB3D_CNTL: 1234513bcb46SDave Airlie switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1235551ebd83SDave Airlie case 7: 1236551ebd83SDave Airlie case 8: 1237551ebd83SDave Airlie case 9: 1238551ebd83SDave Airlie case 11: 1239551ebd83SDave Airlie case 12: 1240551ebd83SDave Airlie track->cb[0].cpp = 1; 1241551ebd83SDave Airlie break; 1242551ebd83SDave Airlie case 3: 1243551ebd83SDave Airlie case 4: 1244551ebd83SDave Airlie case 15: 1245551ebd83SDave Airlie track->cb[0].cpp = 2; 1246551ebd83SDave Airlie break; 1247551ebd83SDave Airlie case 6: 1248551ebd83SDave Airlie track->cb[0].cpp = 4; 1249551ebd83SDave Airlie break; 1250551ebd83SDave Airlie default: 1251551ebd83SDave Airlie DRM_ERROR("Invalid color buffer format (%d) !\n", 1252513bcb46SDave Airlie ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1253551ebd83SDave Airlie return -EINVAL; 1254551ebd83SDave Airlie } 1255513bcb46SDave Airlie track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1256551ebd83SDave Airlie break; 1257551ebd83SDave Airlie case RADEON_RB3D_ZSTENCILCNTL: 1258513bcb46SDave Airlie switch (idx_value & 0xf) { 1259551ebd83SDave Airlie case 0: 1260551ebd83SDave Airlie track->zb.cpp = 2; 1261551ebd83SDave Airlie break; 1262551ebd83SDave Airlie case 2: 1263551ebd83SDave Airlie case 3: 1264551ebd83SDave Airlie case 4: 1265551ebd83SDave Airlie case 5: 1266551ebd83SDave Airlie case 9: 1267551ebd83SDave Airlie case 11: 1268551ebd83SDave Airlie track->zb.cpp = 4; 1269551ebd83SDave Airlie break; 1270551ebd83SDave Airlie default: 1271551ebd83SDave Airlie break; 1272551ebd83SDave Airlie } 1273e024e110SDave Airlie break; 127417782d99SDave Airlie case RADEON_RB3D_ZPASS_ADDR: 127517782d99SDave Airlie r = r100_cs_packet_next_reloc(p, &reloc); 127617782d99SDave Airlie if (r) { 127717782d99SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 127817782d99SDave Airlie idx, reg); 127917782d99SDave Airlie r100_cs_dump_packet(p, pkt); 128017782d99SDave Airlie return r; 128117782d99SDave Airlie } 1282513bcb46SDave Airlie ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 128317782d99SDave Airlie break; 1284551ebd83SDave Airlie case RADEON_PP_CNTL: 1285551ebd83SDave Airlie { 1286513bcb46SDave Airlie uint32_t temp = idx_value >> 4; 1287551ebd83SDave Airlie for (i = 0; i < track->num_texture; i++) 1288551ebd83SDave Airlie track->textures[i].enabled = !!(temp & (1 << i)); 1289551ebd83SDave Airlie } 1290551ebd83SDave Airlie break; 1291551ebd83SDave Airlie case RADEON_SE_VF_CNTL: 1292513bcb46SDave Airlie track->vap_vf_cntl = idx_value; 1293551ebd83SDave Airlie break; 1294551ebd83SDave Airlie case RADEON_SE_VTX_FMT: 1295513bcb46SDave Airlie track->vtx_size = r100_get_vtx_size(idx_value); 1296551ebd83SDave Airlie break; 1297551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_0: 1298551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_1: 1299551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_2: 1300551ebd83SDave Airlie i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1301513bcb46SDave Airlie track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1302513bcb46SDave Airlie track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1303551ebd83SDave Airlie break; 1304551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_0: 1305551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_1: 1306551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_2: 1307551ebd83SDave Airlie i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1308513bcb46SDave Airlie track->textures[i].pitch = idx_value + 32; 1309551ebd83SDave Airlie break; 1310551ebd83SDave Airlie case RADEON_PP_TXFILTER_0: 1311551ebd83SDave Airlie case RADEON_PP_TXFILTER_1: 1312551ebd83SDave Airlie case RADEON_PP_TXFILTER_2: 1313551ebd83SDave Airlie i = (reg - RADEON_PP_TXFILTER_0) / 24; 1314513bcb46SDave Airlie track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1315551ebd83SDave Airlie >> RADEON_MAX_MIP_LEVEL_SHIFT); 1316513bcb46SDave Airlie tmp = (idx_value >> 23) & 0x7; 1317551ebd83SDave Airlie if (tmp == 2 || tmp == 6) 1318551ebd83SDave Airlie track->textures[i].roundup_w = false; 1319513bcb46SDave Airlie tmp = (idx_value >> 27) & 0x7; 1320551ebd83SDave Airlie if (tmp == 2 || tmp == 6) 1321551ebd83SDave Airlie track->textures[i].roundup_h = false; 1322551ebd83SDave Airlie break; 1323551ebd83SDave Airlie case RADEON_PP_TXFORMAT_0: 1324551ebd83SDave Airlie case RADEON_PP_TXFORMAT_1: 1325551ebd83SDave Airlie case RADEON_PP_TXFORMAT_2: 1326551ebd83SDave Airlie i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1327513bcb46SDave Airlie if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1328551ebd83SDave Airlie track->textures[i].use_pitch = 1; 1329551ebd83SDave Airlie } else { 1330551ebd83SDave Airlie track->textures[i].use_pitch = 0; 1331513bcb46SDave Airlie track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1332513bcb46SDave Airlie track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1333551ebd83SDave Airlie } 1334513bcb46SDave Airlie if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1335551ebd83SDave Airlie track->textures[i].tex_coord_type = 2; 1336513bcb46SDave Airlie switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1337551ebd83SDave Airlie case RADEON_TXFORMAT_I8: 1338551ebd83SDave Airlie case RADEON_TXFORMAT_RGB332: 1339551ebd83SDave Airlie case RADEON_TXFORMAT_Y8: 1340551ebd83SDave Airlie track->textures[i].cpp = 1; 1341551ebd83SDave Airlie break; 1342551ebd83SDave Airlie case RADEON_TXFORMAT_AI88: 1343551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB1555: 1344551ebd83SDave Airlie case RADEON_TXFORMAT_RGB565: 1345551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB4444: 1346551ebd83SDave Airlie case RADEON_TXFORMAT_VYUY422: 1347551ebd83SDave Airlie case RADEON_TXFORMAT_YVYU422: 1348551ebd83SDave Airlie case RADEON_TXFORMAT_SHADOW16: 1349551ebd83SDave Airlie case RADEON_TXFORMAT_LDUDV655: 1350551ebd83SDave Airlie case RADEON_TXFORMAT_DUDV88: 1351551ebd83SDave Airlie track->textures[i].cpp = 2; 1352551ebd83SDave Airlie break; 1353551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB8888: 1354551ebd83SDave Airlie case RADEON_TXFORMAT_RGBA8888: 1355551ebd83SDave Airlie case RADEON_TXFORMAT_SHADOW32: 1356551ebd83SDave Airlie case RADEON_TXFORMAT_LDUDUV8888: 1357551ebd83SDave Airlie track->textures[i].cpp = 4; 1358551ebd83SDave Airlie break; 1359d785d78bSDave Airlie case RADEON_TXFORMAT_DXT1: 1360d785d78bSDave Airlie track->textures[i].cpp = 1; 1361d785d78bSDave Airlie track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1362d785d78bSDave Airlie break; 1363d785d78bSDave Airlie case RADEON_TXFORMAT_DXT23: 1364d785d78bSDave Airlie case RADEON_TXFORMAT_DXT45: 1365d785d78bSDave Airlie track->textures[i].cpp = 1; 1366d785d78bSDave Airlie track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1367d785d78bSDave Airlie break; 1368551ebd83SDave Airlie } 1369513bcb46SDave Airlie track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1370513bcb46SDave Airlie track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1371551ebd83SDave Airlie break; 1372551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_0: 1373551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_1: 1374551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_2: 1375513bcb46SDave Airlie tmp = idx_value; 1376551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1377551ebd83SDave Airlie for (face = 0; face < 4; face++) { 1378551ebd83SDave Airlie track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1379551ebd83SDave Airlie track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1380551ebd83SDave Airlie } 1381551ebd83SDave Airlie break; 1382771fe6b9SJerome Glisse default: 1383551ebd83SDave Airlie printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1384551ebd83SDave Airlie reg, idx); 1385551ebd83SDave Airlie return -EINVAL; 1386771fe6b9SJerome Glisse } 1387771fe6b9SJerome Glisse return 0; 1388771fe6b9SJerome Glisse } 1389771fe6b9SJerome Glisse 1390068a117cSJerome Glisse int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1391068a117cSJerome Glisse struct radeon_cs_packet *pkt, 13924c788679SJerome Glisse struct radeon_bo *robj) 1393068a117cSJerome Glisse { 1394068a117cSJerome Glisse unsigned idx; 1395513bcb46SDave Airlie u32 value; 1396068a117cSJerome Glisse idx = pkt->idx + 1; 1397513bcb46SDave Airlie value = radeon_get_ib_value(p, idx + 2); 13984c788679SJerome Glisse if ((value + 1) > radeon_bo_size(robj)) { 1399068a117cSJerome Glisse DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1400068a117cSJerome Glisse "(need %u have %lu) !\n", 1401513bcb46SDave Airlie value + 1, 14024c788679SJerome Glisse radeon_bo_size(robj)); 1403068a117cSJerome Glisse return -EINVAL; 1404068a117cSJerome Glisse } 1405068a117cSJerome Glisse return 0; 1406068a117cSJerome Glisse } 1407068a117cSJerome Glisse 1408771fe6b9SJerome Glisse static int r100_packet3_check(struct radeon_cs_parser *p, 1409771fe6b9SJerome Glisse struct radeon_cs_packet *pkt) 1410771fe6b9SJerome Glisse { 1411771fe6b9SJerome Glisse struct radeon_cs_reloc *reloc; 1412551ebd83SDave Airlie struct r100_cs_track *track; 1413771fe6b9SJerome Glisse unsigned idx; 1414771fe6b9SJerome Glisse volatile uint32_t *ib; 1415771fe6b9SJerome Glisse int r; 1416771fe6b9SJerome Glisse 1417771fe6b9SJerome Glisse ib = p->ib->ptr; 1418771fe6b9SJerome Glisse idx = pkt->idx + 1; 1419551ebd83SDave Airlie track = (struct r100_cs_track *)p->track; 1420771fe6b9SJerome Glisse switch (pkt->opcode) { 1421771fe6b9SJerome Glisse case PACKET3_3D_LOAD_VBPNTR: 1422513bcb46SDave Airlie r = r100_packet3_load_vbpntr(p, pkt, idx); 1423513bcb46SDave Airlie if (r) 1424771fe6b9SJerome Glisse return r; 1425771fe6b9SJerome Glisse break; 1426771fe6b9SJerome Glisse case PACKET3_INDX_BUFFER: 1427771fe6b9SJerome Glisse r = r100_cs_packet_next_reloc(p, &reloc); 1428771fe6b9SJerome Glisse if (r) { 1429771fe6b9SJerome Glisse DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1430771fe6b9SJerome Glisse r100_cs_dump_packet(p, pkt); 1431771fe6b9SJerome Glisse return r; 1432771fe6b9SJerome Glisse } 1433513bcb46SDave Airlie ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1434068a117cSJerome Glisse r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1435068a117cSJerome Glisse if (r) { 1436068a117cSJerome Glisse return r; 1437068a117cSJerome Glisse } 1438771fe6b9SJerome Glisse break; 1439771fe6b9SJerome Glisse case 0x23: 1440771fe6b9SJerome Glisse /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1441771fe6b9SJerome Glisse r = r100_cs_packet_next_reloc(p, &reloc); 1442771fe6b9SJerome Glisse if (r) { 1443771fe6b9SJerome Glisse DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1444771fe6b9SJerome Glisse r100_cs_dump_packet(p, pkt); 1445771fe6b9SJerome Glisse return r; 1446771fe6b9SJerome Glisse } 1447513bcb46SDave Airlie ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1448551ebd83SDave Airlie track->num_arrays = 1; 1449513bcb46SDave Airlie track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1450551ebd83SDave Airlie 1451551ebd83SDave Airlie track->arrays[0].robj = reloc->robj; 1452551ebd83SDave Airlie track->arrays[0].esize = track->vtx_size; 1453551ebd83SDave Airlie 1454513bcb46SDave Airlie track->max_indx = radeon_get_ib_value(p, idx+1); 1455551ebd83SDave Airlie 1456513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1457551ebd83SDave Airlie track->immd_dwords = pkt->count - 1; 1458551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1459551ebd83SDave Airlie if (r) 1460551ebd83SDave Airlie return r; 1461771fe6b9SJerome Glisse break; 1462771fe6b9SJerome Glisse case PACKET3_3D_DRAW_IMMD: 1463513bcb46SDave Airlie if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1464551ebd83SDave Airlie DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1465551ebd83SDave Airlie return -EINVAL; 1466551ebd83SDave Airlie } 1467cf57fc7aSAlex Deucher track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1468513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1469551ebd83SDave Airlie track->immd_dwords = pkt->count - 1; 1470551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1471551ebd83SDave Airlie if (r) 1472551ebd83SDave Airlie return r; 1473551ebd83SDave Airlie break; 1474771fe6b9SJerome Glisse /* triggers drawing using in-packet vertex data */ 1475771fe6b9SJerome Glisse case PACKET3_3D_DRAW_IMMD_2: 1476513bcb46SDave Airlie if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1477551ebd83SDave Airlie DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1478551ebd83SDave Airlie return -EINVAL; 1479551ebd83SDave Airlie } 1480513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1481551ebd83SDave Airlie track->immd_dwords = pkt->count; 1482551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1483551ebd83SDave Airlie if (r) 1484551ebd83SDave Airlie return r; 1485551ebd83SDave Airlie break; 1486771fe6b9SJerome Glisse /* triggers drawing using in-packet vertex data */ 1487771fe6b9SJerome Glisse case PACKET3_3D_DRAW_VBUF_2: 1488513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1489551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1490551ebd83SDave Airlie if (r) 1491551ebd83SDave Airlie return r; 1492551ebd83SDave Airlie break; 1493771fe6b9SJerome Glisse /* triggers drawing of vertex buffers setup elsewhere */ 1494771fe6b9SJerome Glisse case PACKET3_3D_DRAW_INDX_2: 1495513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1496551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1497551ebd83SDave Airlie if (r) 1498551ebd83SDave Airlie return r; 1499551ebd83SDave Airlie break; 1500771fe6b9SJerome Glisse /* triggers drawing using indices to vertex buffer */ 1501771fe6b9SJerome Glisse case PACKET3_3D_DRAW_VBUF: 1502513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1503551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1504551ebd83SDave Airlie if (r) 1505551ebd83SDave Airlie return r; 1506551ebd83SDave Airlie break; 1507771fe6b9SJerome Glisse /* triggers drawing of vertex buffers setup elsewhere */ 1508771fe6b9SJerome Glisse case PACKET3_3D_DRAW_INDX: 1509513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1510551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1511551ebd83SDave Airlie if (r) 1512551ebd83SDave Airlie return r; 1513551ebd83SDave Airlie break; 1514771fe6b9SJerome Glisse /* triggers drawing using indices to vertex buffer */ 1515771fe6b9SJerome Glisse case PACKET3_NOP: 1516771fe6b9SJerome Glisse break; 1517771fe6b9SJerome Glisse default: 1518771fe6b9SJerome Glisse DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1519771fe6b9SJerome Glisse return -EINVAL; 1520771fe6b9SJerome Glisse } 1521771fe6b9SJerome Glisse return 0; 1522771fe6b9SJerome Glisse } 1523771fe6b9SJerome Glisse 1524771fe6b9SJerome Glisse int r100_cs_parse(struct radeon_cs_parser *p) 1525771fe6b9SJerome Glisse { 1526771fe6b9SJerome Glisse struct radeon_cs_packet pkt; 15279f022ddfSJerome Glisse struct r100_cs_track *track; 1528771fe6b9SJerome Glisse int r; 1529771fe6b9SJerome Glisse 15309f022ddfSJerome Glisse track = kzalloc(sizeof(*track), GFP_KERNEL); 15319f022ddfSJerome Glisse r100_cs_track_clear(p->rdev, track); 15329f022ddfSJerome Glisse p->track = track; 1533771fe6b9SJerome Glisse do { 1534771fe6b9SJerome Glisse r = r100_cs_packet_parse(p, &pkt, p->idx); 1535771fe6b9SJerome Glisse if (r) { 1536771fe6b9SJerome Glisse return r; 1537771fe6b9SJerome Glisse } 1538771fe6b9SJerome Glisse p->idx += pkt.count + 2; 1539771fe6b9SJerome Glisse switch (pkt.type) { 1540771fe6b9SJerome Glisse case PACKET_TYPE0: 1541551ebd83SDave Airlie if (p->rdev->family >= CHIP_R200) 1542551ebd83SDave Airlie r = r100_cs_parse_packet0(p, &pkt, 1543551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm, 1544551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm_size, 1545551ebd83SDave Airlie &r200_packet0_check); 1546551ebd83SDave Airlie else 1547551ebd83SDave Airlie r = r100_cs_parse_packet0(p, &pkt, 1548551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm, 1549551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm_size, 1550551ebd83SDave Airlie &r100_packet0_check); 1551771fe6b9SJerome Glisse break; 1552771fe6b9SJerome Glisse case PACKET_TYPE2: 1553771fe6b9SJerome Glisse break; 1554771fe6b9SJerome Glisse case PACKET_TYPE3: 1555771fe6b9SJerome Glisse r = r100_packet3_check(p, &pkt); 1556771fe6b9SJerome Glisse break; 1557771fe6b9SJerome Glisse default: 1558771fe6b9SJerome Glisse DRM_ERROR("Unknown packet type %d !\n", 1559771fe6b9SJerome Glisse pkt.type); 1560771fe6b9SJerome Glisse return -EINVAL; 1561771fe6b9SJerome Glisse } 1562771fe6b9SJerome Glisse if (r) { 1563771fe6b9SJerome Glisse return r; 1564771fe6b9SJerome Glisse } 1565771fe6b9SJerome Glisse } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1566771fe6b9SJerome Glisse return 0; 1567771fe6b9SJerome Glisse } 1568771fe6b9SJerome Glisse 1569771fe6b9SJerome Glisse 1570771fe6b9SJerome Glisse /* 1571771fe6b9SJerome Glisse * Global GPU functions 1572771fe6b9SJerome Glisse */ 1573771fe6b9SJerome Glisse void r100_errata(struct radeon_device *rdev) 1574771fe6b9SJerome Glisse { 1575771fe6b9SJerome Glisse rdev->pll_errata = 0; 1576771fe6b9SJerome Glisse 1577771fe6b9SJerome Glisse if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 1578771fe6b9SJerome Glisse rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 1579771fe6b9SJerome Glisse } 1580771fe6b9SJerome Glisse 1581771fe6b9SJerome Glisse if (rdev->family == CHIP_RV100 || 1582771fe6b9SJerome Glisse rdev->family == CHIP_RS100 || 1583771fe6b9SJerome Glisse rdev->family == CHIP_RS200) { 1584771fe6b9SJerome Glisse rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 1585771fe6b9SJerome Glisse } 1586771fe6b9SJerome Glisse } 1587771fe6b9SJerome Glisse 1588771fe6b9SJerome Glisse /* Wait for vertical sync on primary CRTC */ 1589771fe6b9SJerome Glisse void r100_gpu_wait_for_vsync(struct radeon_device *rdev) 1590771fe6b9SJerome Glisse { 1591771fe6b9SJerome Glisse uint32_t crtc_gen_cntl, tmp; 1592771fe6b9SJerome Glisse int i; 1593771fe6b9SJerome Glisse 1594771fe6b9SJerome Glisse crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 1595771fe6b9SJerome Glisse if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 1596771fe6b9SJerome Glisse !(crtc_gen_cntl & RADEON_CRTC_EN)) { 1597771fe6b9SJerome Glisse return; 1598771fe6b9SJerome Glisse } 1599771fe6b9SJerome Glisse /* Clear the CRTC_VBLANK_SAVE bit */ 1600771fe6b9SJerome Glisse WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 1601771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 1602771fe6b9SJerome Glisse tmp = RREG32(RADEON_CRTC_STATUS); 1603771fe6b9SJerome Glisse if (tmp & RADEON_CRTC_VBLANK_SAVE) { 1604771fe6b9SJerome Glisse return; 1605771fe6b9SJerome Glisse } 1606771fe6b9SJerome Glisse DRM_UDELAY(1); 1607771fe6b9SJerome Glisse } 1608771fe6b9SJerome Glisse } 1609771fe6b9SJerome Glisse 1610771fe6b9SJerome Glisse /* Wait for vertical sync on secondary CRTC */ 1611771fe6b9SJerome Glisse void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) 1612771fe6b9SJerome Glisse { 1613771fe6b9SJerome Glisse uint32_t crtc2_gen_cntl, tmp; 1614771fe6b9SJerome Glisse int i; 1615771fe6b9SJerome Glisse 1616771fe6b9SJerome Glisse crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1617771fe6b9SJerome Glisse if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 1618771fe6b9SJerome Glisse !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 1619771fe6b9SJerome Glisse return; 1620771fe6b9SJerome Glisse 1621771fe6b9SJerome Glisse /* Clear the CRTC_VBLANK_SAVE bit */ 1622771fe6b9SJerome Glisse WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 1623771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 1624771fe6b9SJerome Glisse tmp = RREG32(RADEON_CRTC2_STATUS); 1625771fe6b9SJerome Glisse if (tmp & RADEON_CRTC2_VBLANK_SAVE) { 1626771fe6b9SJerome Glisse return; 1627771fe6b9SJerome Glisse } 1628771fe6b9SJerome Glisse DRM_UDELAY(1); 1629771fe6b9SJerome Glisse } 1630771fe6b9SJerome Glisse } 1631771fe6b9SJerome Glisse 1632771fe6b9SJerome Glisse int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 1633771fe6b9SJerome Glisse { 1634771fe6b9SJerome Glisse unsigned i; 1635771fe6b9SJerome Glisse uint32_t tmp; 1636771fe6b9SJerome Glisse 1637771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 1638771fe6b9SJerome Glisse tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 1639771fe6b9SJerome Glisse if (tmp >= n) { 1640771fe6b9SJerome Glisse return 0; 1641771fe6b9SJerome Glisse } 1642771fe6b9SJerome Glisse DRM_UDELAY(1); 1643771fe6b9SJerome Glisse } 1644771fe6b9SJerome Glisse return -1; 1645771fe6b9SJerome Glisse } 1646771fe6b9SJerome Glisse 1647771fe6b9SJerome Glisse int r100_gui_wait_for_idle(struct radeon_device *rdev) 1648771fe6b9SJerome Glisse { 1649771fe6b9SJerome Glisse unsigned i; 1650771fe6b9SJerome Glisse uint32_t tmp; 1651771fe6b9SJerome Glisse 1652771fe6b9SJerome Glisse if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 1653771fe6b9SJerome Glisse printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 1654771fe6b9SJerome Glisse " Bad things might happen.\n"); 1655771fe6b9SJerome Glisse } 1656771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 1657771fe6b9SJerome Glisse tmp = RREG32(RADEON_RBBM_STATUS); 16584612dc97SAlex Deucher if (!(tmp & RADEON_RBBM_ACTIVE)) { 1659771fe6b9SJerome Glisse return 0; 1660771fe6b9SJerome Glisse } 1661771fe6b9SJerome Glisse DRM_UDELAY(1); 1662771fe6b9SJerome Glisse } 1663771fe6b9SJerome Glisse return -1; 1664771fe6b9SJerome Glisse } 1665771fe6b9SJerome Glisse 1666771fe6b9SJerome Glisse int r100_mc_wait_for_idle(struct radeon_device *rdev) 1667771fe6b9SJerome Glisse { 1668771fe6b9SJerome Glisse unsigned i; 1669771fe6b9SJerome Glisse uint32_t tmp; 1670771fe6b9SJerome Glisse 1671771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 1672771fe6b9SJerome Glisse /* read MC_STATUS */ 16734612dc97SAlex Deucher tmp = RREG32(RADEON_MC_STATUS); 16744612dc97SAlex Deucher if (tmp & RADEON_MC_IDLE) { 1675771fe6b9SJerome Glisse return 0; 1676771fe6b9SJerome Glisse } 1677771fe6b9SJerome Glisse DRM_UDELAY(1); 1678771fe6b9SJerome Glisse } 1679771fe6b9SJerome Glisse return -1; 1680771fe6b9SJerome Glisse } 1681771fe6b9SJerome Glisse 1682225758d8SJerome Glisse void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp) 1683225758d8SJerome Glisse { 1684225758d8SJerome Glisse lockup->last_cp_rptr = cp->rptr; 1685225758d8SJerome Glisse lockup->last_jiffies = jiffies; 1686225758d8SJerome Glisse } 1687225758d8SJerome Glisse 1688225758d8SJerome Glisse /** 1689225758d8SJerome Glisse * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information 1690225758d8SJerome Glisse * @rdev: radeon device structure 1691225758d8SJerome Glisse * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations 1692225758d8SJerome Glisse * @cp: radeon_cp structure holding CP information 1693225758d8SJerome Glisse * 1694225758d8SJerome Glisse * We don't need to initialize the lockup tracking information as we will either 1695225758d8SJerome Glisse * have CP rptr to a different value of jiffies wrap around which will force 1696225758d8SJerome Glisse * initialization of the lockup tracking informations. 1697225758d8SJerome Glisse * 1698225758d8SJerome Glisse * A possible false positivie is if we get call after while and last_cp_rptr == 1699225758d8SJerome Glisse * the current CP rptr, even if it's unlikely it might happen. To avoid this 1700225758d8SJerome Glisse * if the elapsed time since last call is bigger than 2 second than we return 1701225758d8SJerome Glisse * false and update the tracking information. Due to this the caller must call 1702225758d8SJerome Glisse * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported 1703225758d8SJerome Glisse * the fencing code should be cautious about that. 1704225758d8SJerome Glisse * 1705225758d8SJerome Glisse * Caller should write to the ring to force CP to do something so we don't get 1706225758d8SJerome Glisse * false positive when CP is just gived nothing to do. 1707225758d8SJerome Glisse * 1708225758d8SJerome Glisse **/ 1709225758d8SJerome Glisse bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp) 1710225758d8SJerome Glisse { 1711225758d8SJerome Glisse unsigned long cjiffies, elapsed; 1712225758d8SJerome Glisse 1713225758d8SJerome Glisse cjiffies = jiffies; 1714225758d8SJerome Glisse if (!time_after(cjiffies, lockup->last_jiffies)) { 1715225758d8SJerome Glisse /* likely a wrap around */ 1716225758d8SJerome Glisse lockup->last_cp_rptr = cp->rptr; 1717225758d8SJerome Glisse lockup->last_jiffies = jiffies; 1718225758d8SJerome Glisse return false; 1719225758d8SJerome Glisse } 1720225758d8SJerome Glisse if (cp->rptr != lockup->last_cp_rptr) { 1721225758d8SJerome Glisse /* CP is still working no lockup */ 1722225758d8SJerome Glisse lockup->last_cp_rptr = cp->rptr; 1723225758d8SJerome Glisse lockup->last_jiffies = jiffies; 1724225758d8SJerome Glisse return false; 1725225758d8SJerome Glisse } 1726225758d8SJerome Glisse elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); 1727225758d8SJerome Glisse if (elapsed >= 3000) { 1728225758d8SJerome Glisse /* very likely the improbable case where current 1729225758d8SJerome Glisse * rptr is equal to last recorded, a while ago, rptr 1730225758d8SJerome Glisse * this is more likely a false positive update tracking 1731225758d8SJerome Glisse * information which should force us to be recall at 1732225758d8SJerome Glisse * latter point 1733225758d8SJerome Glisse */ 1734225758d8SJerome Glisse lockup->last_cp_rptr = cp->rptr; 1735225758d8SJerome Glisse lockup->last_jiffies = jiffies; 1736225758d8SJerome Glisse return false; 1737225758d8SJerome Glisse } 1738225758d8SJerome Glisse if (elapsed >= 1000) { 1739225758d8SJerome Glisse dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); 1740225758d8SJerome Glisse return true; 1741225758d8SJerome Glisse } 1742225758d8SJerome Glisse /* give a chance to the GPU ... */ 1743225758d8SJerome Glisse return false; 1744225758d8SJerome Glisse } 1745225758d8SJerome Glisse 1746225758d8SJerome Glisse bool r100_gpu_is_lockup(struct radeon_device *rdev) 1747225758d8SJerome Glisse { 1748225758d8SJerome Glisse u32 rbbm_status; 1749225758d8SJerome Glisse int r; 1750225758d8SJerome Glisse 1751225758d8SJerome Glisse rbbm_status = RREG32(R_000E40_RBBM_STATUS); 1752225758d8SJerome Glisse if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 1753225758d8SJerome Glisse r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp); 1754225758d8SJerome Glisse return false; 1755225758d8SJerome Glisse } 1756225758d8SJerome Glisse /* force CP activities */ 1757225758d8SJerome Glisse r = radeon_ring_lock(rdev, 2); 1758225758d8SJerome Glisse if (!r) { 1759225758d8SJerome Glisse /* PACKET2 NOP */ 1760225758d8SJerome Glisse radeon_ring_write(rdev, 0x80000000); 1761225758d8SJerome Glisse radeon_ring_write(rdev, 0x80000000); 1762225758d8SJerome Glisse radeon_ring_unlock_commit(rdev); 1763225758d8SJerome Glisse } 1764225758d8SJerome Glisse rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 1765225758d8SJerome Glisse return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp); 1766225758d8SJerome Glisse } 1767225758d8SJerome Glisse 1768*90aca4d2SJerome Glisse void r100_bm_disable(struct radeon_device *rdev) 1769*90aca4d2SJerome Glisse { 1770*90aca4d2SJerome Glisse u32 tmp; 1771*90aca4d2SJerome Glisse 1772*90aca4d2SJerome Glisse /* disable bus mastering */ 1773*90aca4d2SJerome Glisse tmp = RREG32(R_000030_BUS_CNTL); 1774*90aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 1775*90aca4d2SJerome Glisse mdelay(1); 1776*90aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 1777*90aca4d2SJerome Glisse mdelay(1); 1778*90aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 1779*90aca4d2SJerome Glisse tmp = RREG32(RADEON_BUS_CNTL); 1780*90aca4d2SJerome Glisse mdelay(1); 1781*90aca4d2SJerome Glisse pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp); 1782*90aca4d2SJerome Glisse pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB); 1783*90aca4d2SJerome Glisse mdelay(1); 1784*90aca4d2SJerome Glisse } 1785*90aca4d2SJerome Glisse 1786a2d07b74SJerome Glisse int r100_asic_reset(struct radeon_device *rdev) 1787771fe6b9SJerome Glisse { 1788*90aca4d2SJerome Glisse struct r100_mc_save save; 1789*90aca4d2SJerome Glisse u32 status, tmp; 1790771fe6b9SJerome Glisse 1791*90aca4d2SJerome Glisse r100_mc_stop(rdev, &save); 1792*90aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 1793*90aca4d2SJerome Glisse if (!G_000E40_GUI_ACTIVE(status)) { 1794*90aca4d2SJerome Glisse return 0; 1795771fe6b9SJerome Glisse } 1796*90aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 1797*90aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 1798*90aca4d2SJerome Glisse /* stop CP */ 1799*90aca4d2SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, 0); 1800*90aca4d2SJerome Glisse tmp = RREG32(RADEON_CP_RB_CNTL); 1801*90aca4d2SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 1802*90aca4d2SJerome Glisse WREG32(RADEON_CP_RB_RPTR_WR, 0); 1803*90aca4d2SJerome Glisse WREG32(RADEON_CP_RB_WPTR, 0); 1804*90aca4d2SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp); 1805*90aca4d2SJerome Glisse /* save PCI state */ 1806*90aca4d2SJerome Glisse pci_save_state(rdev->pdev); 1807*90aca4d2SJerome Glisse /* disable bus mastering */ 1808*90aca4d2SJerome Glisse r100_bm_disable(rdev); 1809*90aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 1810*90aca4d2SJerome Glisse S_0000F0_SOFT_RESET_RE(1) | 1811*90aca4d2SJerome Glisse S_0000F0_SOFT_RESET_PP(1) | 1812*90aca4d2SJerome Glisse S_0000F0_SOFT_RESET_RB(1)); 1813*90aca4d2SJerome Glisse RREG32(R_0000F0_RBBM_SOFT_RESET); 1814*90aca4d2SJerome Glisse mdelay(500); 1815*90aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 1816*90aca4d2SJerome Glisse mdelay(1); 1817*90aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 1818*90aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 1819771fe6b9SJerome Glisse /* reset CP */ 1820*90aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 1821*90aca4d2SJerome Glisse RREG32(R_0000F0_RBBM_SOFT_RESET); 1822*90aca4d2SJerome Glisse mdelay(500); 1823*90aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 1824*90aca4d2SJerome Glisse mdelay(1); 1825*90aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 1826*90aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 1827*90aca4d2SJerome Glisse /* restore PCI & busmastering */ 1828*90aca4d2SJerome Glisse pci_restore_state(rdev->pdev); 1829*90aca4d2SJerome Glisse r100_enable_bm(rdev); 1830771fe6b9SJerome Glisse /* Check if GPU is idle */ 1831*90aca4d2SJerome Glisse if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 1832*90aca4d2SJerome Glisse G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 1833*90aca4d2SJerome Glisse dev_err(rdev->dev, "failed to reset GPU\n"); 1834*90aca4d2SJerome Glisse rdev->gpu_lockup = true; 1835771fe6b9SJerome Glisse return -1; 1836771fe6b9SJerome Glisse } 1837*90aca4d2SJerome Glisse r100_mc_resume(rdev, &save); 1838*90aca4d2SJerome Glisse dev_info(rdev->dev, "GPU reset succeed\n"); 1839771fe6b9SJerome Glisse return 0; 1840771fe6b9SJerome Glisse } 1841771fe6b9SJerome Glisse 184292cde00cSAlex Deucher void r100_set_common_regs(struct radeon_device *rdev) 184392cde00cSAlex Deucher { 18442739d49cSAlex Deucher struct drm_device *dev = rdev->ddev; 18452739d49cSAlex Deucher bool force_dac2 = false; 1846d668046cSDave Airlie u32 tmp; 18472739d49cSAlex Deucher 184892cde00cSAlex Deucher /* set these so they don't interfere with anything */ 184992cde00cSAlex Deucher WREG32(RADEON_OV0_SCALE_CNTL, 0); 185092cde00cSAlex Deucher WREG32(RADEON_SUBPIC_CNTL, 0); 185192cde00cSAlex Deucher WREG32(RADEON_VIPH_CONTROL, 0); 185292cde00cSAlex Deucher WREG32(RADEON_I2C_CNTL_1, 0); 185392cde00cSAlex Deucher WREG32(RADEON_DVI_I2C_CNTL_1, 0); 185492cde00cSAlex Deucher WREG32(RADEON_CAP0_TRIG_CNTL, 0); 185592cde00cSAlex Deucher WREG32(RADEON_CAP1_TRIG_CNTL, 0); 18562739d49cSAlex Deucher 18572739d49cSAlex Deucher /* always set up dac2 on rn50 and some rv100 as lots 18582739d49cSAlex Deucher * of servers seem to wire it up to a VGA port but 18592739d49cSAlex Deucher * don't report it in the bios connector 18602739d49cSAlex Deucher * table. 18612739d49cSAlex Deucher */ 18622739d49cSAlex Deucher switch (dev->pdev->device) { 18632739d49cSAlex Deucher /* RN50 */ 18642739d49cSAlex Deucher case 0x515e: 18652739d49cSAlex Deucher case 0x5969: 18662739d49cSAlex Deucher force_dac2 = true; 18672739d49cSAlex Deucher break; 18682739d49cSAlex Deucher /* RV100*/ 18692739d49cSAlex Deucher case 0x5159: 18702739d49cSAlex Deucher case 0x515a: 18712739d49cSAlex Deucher /* DELL triple head servers */ 18722739d49cSAlex Deucher if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 18732739d49cSAlex Deucher ((dev->pdev->subsystem_device == 0x016c) || 18742739d49cSAlex Deucher (dev->pdev->subsystem_device == 0x016d) || 18752739d49cSAlex Deucher (dev->pdev->subsystem_device == 0x016e) || 18762739d49cSAlex Deucher (dev->pdev->subsystem_device == 0x016f) || 18772739d49cSAlex Deucher (dev->pdev->subsystem_device == 0x0170) || 18782739d49cSAlex Deucher (dev->pdev->subsystem_device == 0x017d) || 18792739d49cSAlex Deucher (dev->pdev->subsystem_device == 0x017e) || 18802739d49cSAlex Deucher (dev->pdev->subsystem_device == 0x0183) || 18812739d49cSAlex Deucher (dev->pdev->subsystem_device == 0x018a) || 18822739d49cSAlex Deucher (dev->pdev->subsystem_device == 0x019a))) 18832739d49cSAlex Deucher force_dac2 = true; 18842739d49cSAlex Deucher break; 18852739d49cSAlex Deucher } 18862739d49cSAlex Deucher 18872739d49cSAlex Deucher if (force_dac2) { 18882739d49cSAlex Deucher u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 18892739d49cSAlex Deucher u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 18902739d49cSAlex Deucher u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 18912739d49cSAlex Deucher 18922739d49cSAlex Deucher /* For CRT on DAC2, don't turn it on if BIOS didn't 18932739d49cSAlex Deucher enable it, even it's detected. 18942739d49cSAlex Deucher */ 18952739d49cSAlex Deucher 18962739d49cSAlex Deucher /* force it to crtc0 */ 18972739d49cSAlex Deucher dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 18982739d49cSAlex Deucher dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 18992739d49cSAlex Deucher disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 19002739d49cSAlex Deucher 19012739d49cSAlex Deucher /* set up the TV DAC */ 19022739d49cSAlex Deucher tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 19032739d49cSAlex Deucher RADEON_TV_DAC_STD_MASK | 19042739d49cSAlex Deucher RADEON_TV_DAC_RDACPD | 19052739d49cSAlex Deucher RADEON_TV_DAC_GDACPD | 19062739d49cSAlex Deucher RADEON_TV_DAC_BDACPD | 19072739d49cSAlex Deucher RADEON_TV_DAC_BGADJ_MASK | 19082739d49cSAlex Deucher RADEON_TV_DAC_DACADJ_MASK); 19092739d49cSAlex Deucher tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 19102739d49cSAlex Deucher RADEON_TV_DAC_NHOLD | 19112739d49cSAlex Deucher RADEON_TV_DAC_STD_PS2 | 19122739d49cSAlex Deucher (0x58 << 16)); 19132739d49cSAlex Deucher 19142739d49cSAlex Deucher WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 19152739d49cSAlex Deucher WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 19162739d49cSAlex Deucher WREG32(RADEON_DAC_CNTL2, dac2_cntl); 19172739d49cSAlex Deucher } 1918d668046cSDave Airlie 1919d668046cSDave Airlie /* switch PM block to ACPI mode */ 1920d668046cSDave Airlie tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 1921d668046cSDave Airlie tmp &= ~RADEON_PM_MODE_SEL; 1922d668046cSDave Airlie WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 1923d668046cSDave Airlie 192492cde00cSAlex Deucher } 1925771fe6b9SJerome Glisse 1926771fe6b9SJerome Glisse /* 1927771fe6b9SJerome Glisse * VRAM info 1928771fe6b9SJerome Glisse */ 1929771fe6b9SJerome Glisse static void r100_vram_get_type(struct radeon_device *rdev) 1930771fe6b9SJerome Glisse { 1931771fe6b9SJerome Glisse uint32_t tmp; 1932771fe6b9SJerome Glisse 1933771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = false; 1934771fe6b9SJerome Glisse if (rdev->flags & RADEON_IS_IGP) 1935771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 1936771fe6b9SJerome Glisse else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 1937771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 1938771fe6b9SJerome Glisse if ((rdev->family == CHIP_RV100) || 1939771fe6b9SJerome Glisse (rdev->family == CHIP_RS100) || 1940771fe6b9SJerome Glisse (rdev->family == CHIP_RS200)) { 1941771fe6b9SJerome Glisse tmp = RREG32(RADEON_MEM_CNTL); 1942771fe6b9SJerome Glisse if (tmp & RV100_HALF_MODE) { 1943771fe6b9SJerome Glisse rdev->mc.vram_width = 32; 1944771fe6b9SJerome Glisse } else { 1945771fe6b9SJerome Glisse rdev->mc.vram_width = 64; 1946771fe6b9SJerome Glisse } 1947771fe6b9SJerome Glisse if (rdev->flags & RADEON_SINGLE_CRTC) { 1948771fe6b9SJerome Glisse rdev->mc.vram_width /= 4; 1949771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 1950771fe6b9SJerome Glisse } 1951771fe6b9SJerome Glisse } else if (rdev->family <= CHIP_RV280) { 1952771fe6b9SJerome Glisse tmp = RREG32(RADEON_MEM_CNTL); 1953771fe6b9SJerome Glisse if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 1954771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 1955771fe6b9SJerome Glisse } else { 1956771fe6b9SJerome Glisse rdev->mc.vram_width = 64; 1957771fe6b9SJerome Glisse } 1958771fe6b9SJerome Glisse } else { 1959771fe6b9SJerome Glisse /* newer IGPs */ 1960771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 1961771fe6b9SJerome Glisse } 1962771fe6b9SJerome Glisse } 1963771fe6b9SJerome Glisse 19642a0f8918SDave Airlie static u32 r100_get_accessible_vram(struct radeon_device *rdev) 1965771fe6b9SJerome Glisse { 19662a0f8918SDave Airlie u32 aper_size; 19672a0f8918SDave Airlie u8 byte; 19682a0f8918SDave Airlie 19692a0f8918SDave Airlie aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 19702a0f8918SDave Airlie 19712a0f8918SDave Airlie /* Set HDP_APER_CNTL only on cards that are known not to be broken, 19722a0f8918SDave Airlie * that is has the 2nd generation multifunction PCI interface 19732a0f8918SDave Airlie */ 19742a0f8918SDave Airlie if (rdev->family == CHIP_RV280 || 19752a0f8918SDave Airlie rdev->family >= CHIP_RV350) { 19762a0f8918SDave Airlie WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 19772a0f8918SDave Airlie ~RADEON_HDP_APER_CNTL); 19782a0f8918SDave Airlie DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 19792a0f8918SDave Airlie return aper_size * 2; 19802a0f8918SDave Airlie } 19812a0f8918SDave Airlie 19822a0f8918SDave Airlie /* Older cards have all sorts of funny issues to deal with. First 19832a0f8918SDave Airlie * check if it's a multifunction card by reading the PCI config 19842a0f8918SDave Airlie * header type... Limit those to one aperture size 19852a0f8918SDave Airlie */ 19862a0f8918SDave Airlie pci_read_config_byte(rdev->pdev, 0xe, &byte); 19872a0f8918SDave Airlie if (byte & 0x80) { 19882a0f8918SDave Airlie DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 19892a0f8918SDave Airlie DRM_INFO("Limiting VRAM to one aperture\n"); 19902a0f8918SDave Airlie return aper_size; 19912a0f8918SDave Airlie } 19922a0f8918SDave Airlie 19932a0f8918SDave Airlie /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 19942a0f8918SDave Airlie * have set it up. We don't write this as it's broken on some ASICs but 19952a0f8918SDave Airlie * we expect the BIOS to have done the right thing (might be too optimistic...) 19962a0f8918SDave Airlie */ 19972a0f8918SDave Airlie if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 19982a0f8918SDave Airlie return aper_size * 2; 19992a0f8918SDave Airlie return aper_size; 20002a0f8918SDave Airlie } 20012a0f8918SDave Airlie 20022a0f8918SDave Airlie void r100_vram_init_sizes(struct radeon_device *rdev) 20032a0f8918SDave Airlie { 20042a0f8918SDave Airlie u64 config_aper_size; 20052a0f8918SDave Airlie 2006d594e46aSJerome Glisse /* work out accessible VRAM */ 2007d594e46aSJerome Glisse rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 2008d594e46aSJerome Glisse rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 200951e5fcd3SJerome Glisse rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 201051e5fcd3SJerome Glisse /* FIXME we don't use the second aperture yet when we could use it */ 201151e5fcd3SJerome Glisse if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 201251e5fcd3SJerome Glisse rdev->mc.visible_vram_size = rdev->mc.aper_size; 20132a0f8918SDave Airlie config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2014771fe6b9SJerome Glisse if (rdev->flags & RADEON_IS_IGP) { 2015771fe6b9SJerome Glisse uint32_t tom; 2016771fe6b9SJerome Glisse /* read NB_TOM to get the amount of ram stolen for the GPU */ 2017771fe6b9SJerome Glisse tom = RREG32(RADEON_NB_TOM); 20187a50f01aSDave Airlie rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 20197a50f01aSDave Airlie WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 20207a50f01aSDave Airlie rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2021771fe6b9SJerome Glisse } else { 20227a50f01aSDave Airlie rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2023771fe6b9SJerome Glisse /* Some production boards of m6 will report 0 2024771fe6b9SJerome Glisse * if it's 8 MB 2025771fe6b9SJerome Glisse */ 20267a50f01aSDave Airlie if (rdev->mc.real_vram_size == 0) { 20277a50f01aSDave Airlie rdev->mc.real_vram_size = 8192 * 1024; 20287a50f01aSDave Airlie WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2029771fe6b9SJerome Glisse } 20302a0f8918SDave Airlie /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2031d594e46aSJerome Glisse * Novell bug 204882 + along with lots of ubuntu ones 2032d594e46aSJerome Glisse */ 20337a50f01aSDave Airlie if (config_aper_size > rdev->mc.real_vram_size) 20347a50f01aSDave Airlie rdev->mc.mc_vram_size = config_aper_size; 20357a50f01aSDave Airlie else 20367a50f01aSDave Airlie rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2037771fe6b9SJerome Glisse } 2038d594e46aSJerome Glisse /* FIXME remove this once we support unmappable VRAM */ 2039d594e46aSJerome Glisse if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { 20407a50f01aSDave Airlie rdev->mc.mc_vram_size = rdev->mc.aper_size; 20417a50f01aSDave Airlie rdev->mc.real_vram_size = rdev->mc.aper_size; 20422a0f8918SDave Airlie } 2043d594e46aSJerome Glisse } 20442a0f8918SDave Airlie 204528d52043SDave Airlie void r100_vga_set_state(struct radeon_device *rdev, bool state) 204628d52043SDave Airlie { 204728d52043SDave Airlie uint32_t temp; 204828d52043SDave Airlie 204928d52043SDave Airlie temp = RREG32(RADEON_CONFIG_CNTL); 205028d52043SDave Airlie if (state == false) { 205128d52043SDave Airlie temp &= ~(1<<8); 205228d52043SDave Airlie temp |= (1<<9); 205328d52043SDave Airlie } else { 205428d52043SDave Airlie temp &= ~(1<<9); 205528d52043SDave Airlie } 205628d52043SDave Airlie WREG32(RADEON_CONFIG_CNTL, temp); 205728d52043SDave Airlie } 205828d52043SDave Airlie 2059d594e46aSJerome Glisse void r100_mc_init(struct radeon_device *rdev) 20602a0f8918SDave Airlie { 2061d594e46aSJerome Glisse u64 base; 20622a0f8918SDave Airlie 2063d594e46aSJerome Glisse r100_vram_get_type(rdev); 20642a0f8918SDave Airlie r100_vram_init_sizes(rdev); 2065d594e46aSJerome Glisse base = rdev->mc.aper_base; 2066d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_IGP) 2067d594e46aSJerome Glisse base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2068d594e46aSJerome Glisse radeon_vram_location(rdev, &rdev->mc, base); 2069d594e46aSJerome Glisse if (!(rdev->flags & RADEON_IS_AGP)) 2070d594e46aSJerome Glisse radeon_gtt_location(rdev, &rdev->mc); 2071f47299c5SAlex Deucher radeon_update_bandwidth_info(rdev); 2072771fe6b9SJerome Glisse } 2073771fe6b9SJerome Glisse 2074771fe6b9SJerome Glisse 2075771fe6b9SJerome Glisse /* 2076771fe6b9SJerome Glisse * Indirect registers accessor 2077771fe6b9SJerome Glisse */ 2078771fe6b9SJerome Glisse void r100_pll_errata_after_index(struct radeon_device *rdev) 2079771fe6b9SJerome Glisse { 2080771fe6b9SJerome Glisse if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) { 2081771fe6b9SJerome Glisse return; 2082771fe6b9SJerome Glisse } 2083771fe6b9SJerome Glisse (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2084771fe6b9SJerome Glisse (void)RREG32(RADEON_CRTC_GEN_CNTL); 2085771fe6b9SJerome Glisse } 2086771fe6b9SJerome Glisse 2087771fe6b9SJerome Glisse static void r100_pll_errata_after_data(struct radeon_device *rdev) 2088771fe6b9SJerome Glisse { 2089771fe6b9SJerome Glisse /* This workarounds is necessary on RV100, RS100 and RS200 chips 2090771fe6b9SJerome Glisse * or the chip could hang on a subsequent access 2091771fe6b9SJerome Glisse */ 2092771fe6b9SJerome Glisse if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2093771fe6b9SJerome Glisse udelay(5000); 2094771fe6b9SJerome Glisse } 2095771fe6b9SJerome Glisse 2096771fe6b9SJerome Glisse /* This function is required to workaround a hardware bug in some (all?) 2097771fe6b9SJerome Glisse * revisions of the R300. This workaround should be called after every 2098771fe6b9SJerome Glisse * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2099771fe6b9SJerome Glisse * may not be correct. 2100771fe6b9SJerome Glisse */ 2101771fe6b9SJerome Glisse if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2102771fe6b9SJerome Glisse uint32_t save, tmp; 2103771fe6b9SJerome Glisse 2104771fe6b9SJerome Glisse save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2105771fe6b9SJerome Glisse tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2106771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2107771fe6b9SJerome Glisse tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2108771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2109771fe6b9SJerome Glisse } 2110771fe6b9SJerome Glisse } 2111771fe6b9SJerome Glisse 2112771fe6b9SJerome Glisse uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2113771fe6b9SJerome Glisse { 2114771fe6b9SJerome Glisse uint32_t data; 2115771fe6b9SJerome Glisse 2116771fe6b9SJerome Glisse WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2117771fe6b9SJerome Glisse r100_pll_errata_after_index(rdev); 2118771fe6b9SJerome Glisse data = RREG32(RADEON_CLOCK_CNTL_DATA); 2119771fe6b9SJerome Glisse r100_pll_errata_after_data(rdev); 2120771fe6b9SJerome Glisse return data; 2121771fe6b9SJerome Glisse } 2122771fe6b9SJerome Glisse 2123771fe6b9SJerome Glisse void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2124771fe6b9SJerome Glisse { 2125771fe6b9SJerome Glisse WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2126771fe6b9SJerome Glisse r100_pll_errata_after_index(rdev); 2127771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_DATA, v); 2128771fe6b9SJerome Glisse r100_pll_errata_after_data(rdev); 2129771fe6b9SJerome Glisse } 2130771fe6b9SJerome Glisse 2131d4550907SJerome Glisse void r100_set_safe_registers(struct radeon_device *rdev) 2132068a117cSJerome Glisse { 2133551ebd83SDave Airlie if (ASIC_IS_RN50(rdev)) { 2134551ebd83SDave Airlie rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2135551ebd83SDave Airlie rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2136551ebd83SDave Airlie } else if (rdev->family < CHIP_R200) { 2137551ebd83SDave Airlie rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2138551ebd83SDave Airlie rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2139551ebd83SDave Airlie } else { 2140d4550907SJerome Glisse r200_set_safe_registers(rdev); 2141551ebd83SDave Airlie } 2142068a117cSJerome Glisse } 2143068a117cSJerome Glisse 2144771fe6b9SJerome Glisse /* 2145771fe6b9SJerome Glisse * Debugfs info 2146771fe6b9SJerome Glisse */ 2147771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 2148771fe6b9SJerome Glisse static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2149771fe6b9SJerome Glisse { 2150771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 2151771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 2152771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 2153771fe6b9SJerome Glisse uint32_t reg, value; 2154771fe6b9SJerome Glisse unsigned i; 2155771fe6b9SJerome Glisse 2156771fe6b9SJerome Glisse seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2157771fe6b9SJerome Glisse seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2158771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2159771fe6b9SJerome Glisse for (i = 0; i < 64; i++) { 2160771fe6b9SJerome Glisse WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2161771fe6b9SJerome Glisse reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2162771fe6b9SJerome Glisse WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2163771fe6b9SJerome Glisse value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2164771fe6b9SJerome Glisse seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2165771fe6b9SJerome Glisse } 2166771fe6b9SJerome Glisse return 0; 2167771fe6b9SJerome Glisse } 2168771fe6b9SJerome Glisse 2169771fe6b9SJerome Glisse static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2170771fe6b9SJerome Glisse { 2171771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 2172771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 2173771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 2174771fe6b9SJerome Glisse uint32_t rdp, wdp; 2175771fe6b9SJerome Glisse unsigned count, i, j; 2176771fe6b9SJerome Glisse 2177771fe6b9SJerome Glisse radeon_ring_free_size(rdev); 2178771fe6b9SJerome Glisse rdp = RREG32(RADEON_CP_RB_RPTR); 2179771fe6b9SJerome Glisse wdp = RREG32(RADEON_CP_RB_WPTR); 2180771fe6b9SJerome Glisse count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; 2181771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2182771fe6b9SJerome Glisse seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2183771fe6b9SJerome Glisse seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2184771fe6b9SJerome Glisse seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); 2185771fe6b9SJerome Glisse seq_printf(m, "%u dwords in ring\n", count); 2186771fe6b9SJerome Glisse for (j = 0; j <= count; j++) { 2187771fe6b9SJerome Glisse i = (rdp + j) & rdev->cp.ptr_mask; 2188771fe6b9SJerome Glisse seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); 2189771fe6b9SJerome Glisse } 2190771fe6b9SJerome Glisse return 0; 2191771fe6b9SJerome Glisse } 2192771fe6b9SJerome Glisse 2193771fe6b9SJerome Glisse 2194771fe6b9SJerome Glisse static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2195771fe6b9SJerome Glisse { 2196771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 2197771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 2198771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 2199771fe6b9SJerome Glisse uint32_t csq_stat, csq2_stat, tmp; 2200771fe6b9SJerome Glisse unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2201771fe6b9SJerome Glisse unsigned i; 2202771fe6b9SJerome Glisse 2203771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2204771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2205771fe6b9SJerome Glisse csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2206771fe6b9SJerome Glisse csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2207771fe6b9SJerome Glisse r_rptr = (csq_stat >> 0) & 0x3ff; 2208771fe6b9SJerome Glisse r_wptr = (csq_stat >> 10) & 0x3ff; 2209771fe6b9SJerome Glisse ib1_rptr = (csq_stat >> 20) & 0x3ff; 2210771fe6b9SJerome Glisse ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2211771fe6b9SJerome Glisse ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2212771fe6b9SJerome Glisse ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2213771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2214771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2215771fe6b9SJerome Glisse seq_printf(m, "Ring rptr %u\n", r_rptr); 2216771fe6b9SJerome Glisse seq_printf(m, "Ring wptr %u\n", r_wptr); 2217771fe6b9SJerome Glisse seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2218771fe6b9SJerome Glisse seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2219771fe6b9SJerome Glisse seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 2220771fe6b9SJerome Glisse seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 2221771fe6b9SJerome Glisse /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 2222771fe6b9SJerome Glisse * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 2223771fe6b9SJerome Glisse seq_printf(m, "Ring fifo:\n"); 2224771fe6b9SJerome Glisse for (i = 0; i < 256; i++) { 2225771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2226771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA); 2227771fe6b9SJerome Glisse seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 2228771fe6b9SJerome Glisse } 2229771fe6b9SJerome Glisse seq_printf(m, "Indirect1 fifo:\n"); 2230771fe6b9SJerome Glisse for (i = 256; i <= 512; i++) { 2231771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2232771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA); 2233771fe6b9SJerome Glisse seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 2234771fe6b9SJerome Glisse } 2235771fe6b9SJerome Glisse seq_printf(m, "Indirect2 fifo:\n"); 2236771fe6b9SJerome Glisse for (i = 640; i < ib1_wptr; i++) { 2237771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2238771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA); 2239771fe6b9SJerome Glisse seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 2240771fe6b9SJerome Glisse } 2241771fe6b9SJerome Glisse return 0; 2242771fe6b9SJerome Glisse } 2243771fe6b9SJerome Glisse 2244771fe6b9SJerome Glisse static int r100_debugfs_mc_info(struct seq_file *m, void *data) 2245771fe6b9SJerome Glisse { 2246771fe6b9SJerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 2247771fe6b9SJerome Glisse struct drm_device *dev = node->minor->dev; 2248771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 2249771fe6b9SJerome Glisse uint32_t tmp; 2250771fe6b9SJerome Glisse 2251771fe6b9SJerome Glisse tmp = RREG32(RADEON_CONFIG_MEMSIZE); 2252771fe6b9SJerome Glisse seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 2253771fe6b9SJerome Glisse tmp = RREG32(RADEON_MC_FB_LOCATION); 2254771fe6b9SJerome Glisse seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 2255771fe6b9SJerome Glisse tmp = RREG32(RADEON_BUS_CNTL); 2256771fe6b9SJerome Glisse seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 2257771fe6b9SJerome Glisse tmp = RREG32(RADEON_MC_AGP_LOCATION); 2258771fe6b9SJerome Glisse seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 2259771fe6b9SJerome Glisse tmp = RREG32(RADEON_AGP_BASE); 2260771fe6b9SJerome Glisse seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 2261771fe6b9SJerome Glisse tmp = RREG32(RADEON_HOST_PATH_CNTL); 2262771fe6b9SJerome Glisse seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 2263771fe6b9SJerome Glisse tmp = RREG32(0x01D0); 2264771fe6b9SJerome Glisse seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 2265771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_LO_ADDR); 2266771fe6b9SJerome Glisse seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 2267771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_HI_ADDR); 2268771fe6b9SJerome Glisse seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 2269771fe6b9SJerome Glisse tmp = RREG32(0x01E4); 2270771fe6b9SJerome Glisse seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 2271771fe6b9SJerome Glisse return 0; 2272771fe6b9SJerome Glisse } 2273771fe6b9SJerome Glisse 2274771fe6b9SJerome Glisse static struct drm_info_list r100_debugfs_rbbm_list[] = { 2275771fe6b9SJerome Glisse {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 2276771fe6b9SJerome Glisse }; 2277771fe6b9SJerome Glisse 2278771fe6b9SJerome Glisse static struct drm_info_list r100_debugfs_cp_list[] = { 2279771fe6b9SJerome Glisse {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 2280771fe6b9SJerome Glisse {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 2281771fe6b9SJerome Glisse }; 2282771fe6b9SJerome Glisse 2283771fe6b9SJerome Glisse static struct drm_info_list r100_debugfs_mc_info_list[] = { 2284771fe6b9SJerome Glisse {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 2285771fe6b9SJerome Glisse }; 2286771fe6b9SJerome Glisse #endif 2287771fe6b9SJerome Glisse 2288771fe6b9SJerome Glisse int r100_debugfs_rbbm_init(struct radeon_device *rdev) 2289771fe6b9SJerome Glisse { 2290771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 2291771fe6b9SJerome Glisse return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 2292771fe6b9SJerome Glisse #else 2293771fe6b9SJerome Glisse return 0; 2294771fe6b9SJerome Glisse #endif 2295771fe6b9SJerome Glisse } 2296771fe6b9SJerome Glisse 2297771fe6b9SJerome Glisse int r100_debugfs_cp_init(struct radeon_device *rdev) 2298771fe6b9SJerome Glisse { 2299771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 2300771fe6b9SJerome Glisse return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 2301771fe6b9SJerome Glisse #else 2302771fe6b9SJerome Glisse return 0; 2303771fe6b9SJerome Glisse #endif 2304771fe6b9SJerome Glisse } 2305771fe6b9SJerome Glisse 2306771fe6b9SJerome Glisse int r100_debugfs_mc_info_init(struct radeon_device *rdev) 2307771fe6b9SJerome Glisse { 2308771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 2309771fe6b9SJerome Glisse return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 2310771fe6b9SJerome Glisse #else 2311771fe6b9SJerome Glisse return 0; 2312771fe6b9SJerome Glisse #endif 2313771fe6b9SJerome Glisse } 2314e024e110SDave Airlie 2315e024e110SDave Airlie int r100_set_surface_reg(struct radeon_device *rdev, int reg, 2316e024e110SDave Airlie uint32_t tiling_flags, uint32_t pitch, 2317e024e110SDave Airlie uint32_t offset, uint32_t obj_size) 2318e024e110SDave Airlie { 2319e024e110SDave Airlie int surf_index = reg * 16; 2320e024e110SDave Airlie int flags = 0; 2321e024e110SDave Airlie 2322e024e110SDave Airlie /* r100/r200 divide by 16 */ 2323e024e110SDave Airlie if (rdev->family < CHIP_R300) 2324e024e110SDave Airlie flags = pitch / 16; 2325e024e110SDave Airlie else 2326e024e110SDave Airlie flags = pitch / 8; 2327e024e110SDave Airlie 2328e024e110SDave Airlie if (rdev->family <= CHIP_RS200) { 2329e024e110SDave Airlie if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2330e024e110SDave Airlie == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2331e024e110SDave Airlie flags |= RADEON_SURF_TILE_COLOR_BOTH; 2332e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MACRO) 2333e024e110SDave Airlie flags |= RADEON_SURF_TILE_COLOR_MACRO; 2334e024e110SDave Airlie } else if (rdev->family <= CHIP_RV280) { 2335e024e110SDave Airlie if (tiling_flags & (RADEON_TILING_MACRO)) 2336e024e110SDave Airlie flags |= R200_SURF_TILE_COLOR_MACRO; 2337e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MICRO) 2338e024e110SDave Airlie flags |= R200_SURF_TILE_COLOR_MICRO; 2339e024e110SDave Airlie } else { 2340e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MACRO) 2341e024e110SDave Airlie flags |= R300_SURF_TILE_MACRO; 2342e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MICRO) 2343e024e110SDave Airlie flags |= R300_SURF_TILE_MICRO; 2344e024e110SDave Airlie } 2345e024e110SDave Airlie 2346c88f9f0cSMichel Dänzer if (tiling_flags & RADEON_TILING_SWAP_16BIT) 2347c88f9f0cSMichel Dänzer flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 2348c88f9f0cSMichel Dänzer if (tiling_flags & RADEON_TILING_SWAP_32BIT) 2349c88f9f0cSMichel Dänzer flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 2350c88f9f0cSMichel Dänzer 2351e024e110SDave Airlie DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 2352e024e110SDave Airlie WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 2353e024e110SDave Airlie WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 2354e024e110SDave Airlie WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 2355e024e110SDave Airlie return 0; 2356e024e110SDave Airlie } 2357e024e110SDave Airlie 2358e024e110SDave Airlie void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 2359e024e110SDave Airlie { 2360e024e110SDave Airlie int surf_index = reg * 16; 2361e024e110SDave Airlie WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 2362e024e110SDave Airlie } 2363c93bb85bSJerome Glisse 2364c93bb85bSJerome Glisse void r100_bandwidth_update(struct radeon_device *rdev) 2365c93bb85bSJerome Glisse { 2366c93bb85bSJerome Glisse fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 2367c93bb85bSJerome Glisse fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 2368c93bb85bSJerome Glisse fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 2369c93bb85bSJerome Glisse uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 2370c93bb85bSJerome Glisse fixed20_12 memtcas_ff[8] = { 2371c93bb85bSJerome Glisse fixed_init(1), 2372c93bb85bSJerome Glisse fixed_init(2), 2373c93bb85bSJerome Glisse fixed_init(3), 2374c93bb85bSJerome Glisse fixed_init(0), 2375c93bb85bSJerome Glisse fixed_init_half(1), 2376c93bb85bSJerome Glisse fixed_init_half(2), 2377c93bb85bSJerome Glisse fixed_init(0), 2378c93bb85bSJerome Glisse }; 2379c93bb85bSJerome Glisse fixed20_12 memtcas_rs480_ff[8] = { 2380c93bb85bSJerome Glisse fixed_init(0), 2381c93bb85bSJerome Glisse fixed_init(1), 2382c93bb85bSJerome Glisse fixed_init(2), 2383c93bb85bSJerome Glisse fixed_init(3), 2384c93bb85bSJerome Glisse fixed_init(0), 2385c93bb85bSJerome Glisse fixed_init_half(1), 2386c93bb85bSJerome Glisse fixed_init_half(2), 2387c93bb85bSJerome Glisse fixed_init_half(3), 2388c93bb85bSJerome Glisse }; 2389c93bb85bSJerome Glisse fixed20_12 memtcas2_ff[8] = { 2390c93bb85bSJerome Glisse fixed_init(0), 2391c93bb85bSJerome Glisse fixed_init(1), 2392c93bb85bSJerome Glisse fixed_init(2), 2393c93bb85bSJerome Glisse fixed_init(3), 2394c93bb85bSJerome Glisse fixed_init(4), 2395c93bb85bSJerome Glisse fixed_init(5), 2396c93bb85bSJerome Glisse fixed_init(6), 2397c93bb85bSJerome Glisse fixed_init(7), 2398c93bb85bSJerome Glisse }; 2399c93bb85bSJerome Glisse fixed20_12 memtrbs[8] = { 2400c93bb85bSJerome Glisse fixed_init(1), 2401c93bb85bSJerome Glisse fixed_init_half(1), 2402c93bb85bSJerome Glisse fixed_init(2), 2403c93bb85bSJerome Glisse fixed_init_half(2), 2404c93bb85bSJerome Glisse fixed_init(3), 2405c93bb85bSJerome Glisse fixed_init_half(3), 2406c93bb85bSJerome Glisse fixed_init(4), 2407c93bb85bSJerome Glisse fixed_init_half(4) 2408c93bb85bSJerome Glisse }; 2409c93bb85bSJerome Glisse fixed20_12 memtrbs_r4xx[8] = { 2410c93bb85bSJerome Glisse fixed_init(4), 2411c93bb85bSJerome Glisse fixed_init(5), 2412c93bb85bSJerome Glisse fixed_init(6), 2413c93bb85bSJerome Glisse fixed_init(7), 2414c93bb85bSJerome Glisse fixed_init(8), 2415c93bb85bSJerome Glisse fixed_init(9), 2416c93bb85bSJerome Glisse fixed_init(10), 2417c93bb85bSJerome Glisse fixed_init(11) 2418c93bb85bSJerome Glisse }; 2419c93bb85bSJerome Glisse fixed20_12 min_mem_eff; 2420c93bb85bSJerome Glisse fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 2421c93bb85bSJerome Glisse fixed20_12 cur_latency_mclk, cur_latency_sclk; 2422c93bb85bSJerome Glisse fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 2423c93bb85bSJerome Glisse disp_drain_rate2, read_return_rate; 2424c93bb85bSJerome Glisse fixed20_12 time_disp1_drop_priority; 2425c93bb85bSJerome Glisse int c; 2426c93bb85bSJerome Glisse int cur_size = 16; /* in octawords */ 2427c93bb85bSJerome Glisse int critical_point = 0, critical_point2; 2428c93bb85bSJerome Glisse /* uint32_t read_return_rate, time_disp1_drop_priority; */ 2429c93bb85bSJerome Glisse int stop_req, max_stop_req; 2430c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 2431c93bb85bSJerome Glisse struct drm_display_mode *mode2 = NULL; 2432c93bb85bSJerome Glisse uint32_t pixel_bytes1 = 0; 2433c93bb85bSJerome Glisse uint32_t pixel_bytes2 = 0; 2434c93bb85bSJerome Glisse 2435f46c0120SAlex Deucher radeon_update_display_priority(rdev); 2436f46c0120SAlex Deucher 2437c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) { 2438c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[0]->base.mode; 2439c93bb85bSJerome Glisse pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 2440c93bb85bSJerome Glisse } 2441dfee5614SDave Airlie if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 2442c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) { 2443c93bb85bSJerome Glisse mode2 = &rdev->mode_info.crtcs[1]->base.mode; 2444c93bb85bSJerome Glisse pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; 2445c93bb85bSJerome Glisse } 2446dfee5614SDave Airlie } 2447c93bb85bSJerome Glisse 2448c93bb85bSJerome Glisse min_mem_eff.full = rfixed_const_8(0); 2449c93bb85bSJerome Glisse /* get modes */ 2450c93bb85bSJerome Glisse if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 2451c93bb85bSJerome Glisse uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 2452c93bb85bSJerome Glisse mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 2453c93bb85bSJerome Glisse mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 2454c93bb85bSJerome Glisse /* check crtc enables */ 2455c93bb85bSJerome Glisse if (mode2) 2456c93bb85bSJerome Glisse mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 2457c93bb85bSJerome Glisse if (mode1) 2458c93bb85bSJerome Glisse mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 2459c93bb85bSJerome Glisse WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 2460c93bb85bSJerome Glisse } 2461c93bb85bSJerome Glisse 2462c93bb85bSJerome Glisse /* 2463c93bb85bSJerome Glisse * determine is there is enough bw for current mode 2464c93bb85bSJerome Glisse */ 2465f47299c5SAlex Deucher sclk_ff = rdev->pm.sclk; 2466f47299c5SAlex Deucher mclk_ff = rdev->pm.mclk; 2467c93bb85bSJerome Glisse 2468c93bb85bSJerome Glisse temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 2469c93bb85bSJerome Glisse temp_ff.full = rfixed_const(temp); 2470c93bb85bSJerome Glisse mem_bw.full = rfixed_mul(mclk_ff, temp_ff); 2471c93bb85bSJerome Glisse 2472c93bb85bSJerome Glisse pix_clk.full = 0; 2473c93bb85bSJerome Glisse pix_clk2.full = 0; 2474c93bb85bSJerome Glisse peak_disp_bw.full = 0; 2475c93bb85bSJerome Glisse if (mode1) { 2476c93bb85bSJerome Glisse temp_ff.full = rfixed_const(1000); 2477c93bb85bSJerome Glisse pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ 2478c93bb85bSJerome Glisse pix_clk.full = rfixed_div(pix_clk, temp_ff); 2479c93bb85bSJerome Glisse temp_ff.full = rfixed_const(pixel_bytes1); 2480c93bb85bSJerome Glisse peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); 2481c93bb85bSJerome Glisse } 2482c93bb85bSJerome Glisse if (mode2) { 2483c93bb85bSJerome Glisse temp_ff.full = rfixed_const(1000); 2484c93bb85bSJerome Glisse pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ 2485c93bb85bSJerome Glisse pix_clk2.full = rfixed_div(pix_clk2, temp_ff); 2486c93bb85bSJerome Glisse temp_ff.full = rfixed_const(pixel_bytes2); 2487c93bb85bSJerome Glisse peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); 2488c93bb85bSJerome Glisse } 2489c93bb85bSJerome Glisse 2490c93bb85bSJerome Glisse mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); 2491c93bb85bSJerome Glisse if (peak_disp_bw.full >= mem_bw.full) { 2492c93bb85bSJerome Glisse DRM_ERROR("You may not have enough display bandwidth for current mode\n" 2493c93bb85bSJerome Glisse "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 2494c93bb85bSJerome Glisse } 2495c93bb85bSJerome Glisse 2496c93bb85bSJerome Glisse /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 2497c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_TIMING_CNTL); 2498c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 2499c93bb85bSJerome Glisse mem_trcd = ((temp >> 2) & 0x3) + 1; 2500c93bb85bSJerome Glisse mem_trp = ((temp & 0x3)) + 1; 2501c93bb85bSJerome Glisse mem_tras = ((temp & 0x70) >> 4) + 1; 2502c93bb85bSJerome Glisse } else if (rdev->family == CHIP_R300 || 2503c93bb85bSJerome Glisse rdev->family == CHIP_R350) { /* r300, r350 */ 2504c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 1; 2505c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 1; 2506c93bb85bSJerome Glisse mem_tras = ((temp >> 11) & 0xf) + 4; 2507c93bb85bSJerome Glisse } else if (rdev->family == CHIP_RV350 || 2508c93bb85bSJerome Glisse rdev->family <= CHIP_RV380) { 2509c93bb85bSJerome Glisse /* rv3x0 */ 2510c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 3; 2511c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 3; 2512c93bb85bSJerome Glisse mem_tras = ((temp >> 11) & 0xf) + 6; 2513c93bb85bSJerome Glisse } else if (rdev->family == CHIP_R420 || 2514c93bb85bSJerome Glisse rdev->family == CHIP_R423 || 2515c93bb85bSJerome Glisse rdev->family == CHIP_RV410) { 2516c93bb85bSJerome Glisse /* r4xx */ 2517c93bb85bSJerome Glisse mem_trcd = (temp & 0xf) + 3; 2518c93bb85bSJerome Glisse if (mem_trcd > 15) 2519c93bb85bSJerome Glisse mem_trcd = 15; 2520c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0xf) + 3; 2521c93bb85bSJerome Glisse if (mem_trp > 15) 2522c93bb85bSJerome Glisse mem_trp = 15; 2523c93bb85bSJerome Glisse mem_tras = ((temp >> 12) & 0x1f) + 6; 2524c93bb85bSJerome Glisse if (mem_tras > 31) 2525c93bb85bSJerome Glisse mem_tras = 31; 2526c93bb85bSJerome Glisse } else { /* RV200, R200 */ 2527c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 1; 2528c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 1; 2529c93bb85bSJerome Glisse mem_tras = ((temp >> 12) & 0xf) + 4; 2530c93bb85bSJerome Glisse } 2531c93bb85bSJerome Glisse /* convert to FF */ 2532c93bb85bSJerome Glisse trcd_ff.full = rfixed_const(mem_trcd); 2533c93bb85bSJerome Glisse trp_ff.full = rfixed_const(mem_trp); 2534c93bb85bSJerome Glisse tras_ff.full = rfixed_const(mem_tras); 2535c93bb85bSJerome Glisse 2536c93bb85bSJerome Glisse /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 2537c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2538c93bb85bSJerome Glisse data = (temp & (7 << 20)) >> 20; 2539c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 2540c93bb85bSJerome Glisse if (rdev->family == CHIP_RS480) /* don't think rs400 */ 2541c93bb85bSJerome Glisse tcas_ff = memtcas_rs480_ff[data]; 2542c93bb85bSJerome Glisse else 2543c93bb85bSJerome Glisse tcas_ff = memtcas_ff[data]; 2544c93bb85bSJerome Glisse } else 2545c93bb85bSJerome Glisse tcas_ff = memtcas2_ff[data]; 2546c93bb85bSJerome Glisse 2547c93bb85bSJerome Glisse if (rdev->family == CHIP_RS400 || 2548c93bb85bSJerome Glisse rdev->family == CHIP_RS480) { 2549c93bb85bSJerome Glisse /* extra cas latency stored in bits 23-25 0-4 clocks */ 2550c93bb85bSJerome Glisse data = (temp >> 23) & 0x7; 2551c93bb85bSJerome Glisse if (data < 5) 2552c93bb85bSJerome Glisse tcas_ff.full += rfixed_const(data); 2553c93bb85bSJerome Glisse } 2554c93bb85bSJerome Glisse 2555c93bb85bSJerome Glisse if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 2556c93bb85bSJerome Glisse /* on the R300, Tcas is included in Trbs. 2557c93bb85bSJerome Glisse */ 2558c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_CNTL); 2559c93bb85bSJerome Glisse data = (R300_MEM_NUM_CHANNELS_MASK & temp); 2560c93bb85bSJerome Glisse if (data == 1) { 2561c93bb85bSJerome Glisse if (R300_MEM_USE_CD_CH_ONLY & temp) { 2562c93bb85bSJerome Glisse temp = RREG32(R300_MC_IND_INDEX); 2563c93bb85bSJerome Glisse temp &= ~R300_MC_IND_ADDR_MASK; 2564c93bb85bSJerome Glisse temp |= R300_MC_READ_CNTL_CD_mcind; 2565c93bb85bSJerome Glisse WREG32(R300_MC_IND_INDEX, temp); 2566c93bb85bSJerome Glisse temp = RREG32(R300_MC_IND_DATA); 2567c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_C_MASK & temp); 2568c93bb85bSJerome Glisse } else { 2569c93bb85bSJerome Glisse temp = RREG32(R300_MC_READ_CNTL_AB); 2570c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2571c93bb85bSJerome Glisse } 2572c93bb85bSJerome Glisse } else { 2573c93bb85bSJerome Glisse temp = RREG32(R300_MC_READ_CNTL_AB); 2574c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2575c93bb85bSJerome Glisse } 2576c93bb85bSJerome Glisse if (rdev->family == CHIP_RV410 || 2577c93bb85bSJerome Glisse rdev->family == CHIP_R420 || 2578c93bb85bSJerome Glisse rdev->family == CHIP_R423) 2579c93bb85bSJerome Glisse trbs_ff = memtrbs_r4xx[data]; 2580c93bb85bSJerome Glisse else 2581c93bb85bSJerome Glisse trbs_ff = memtrbs[data]; 2582c93bb85bSJerome Glisse tcas_ff.full += trbs_ff.full; 2583c93bb85bSJerome Glisse } 2584c93bb85bSJerome Glisse 2585c93bb85bSJerome Glisse sclk_eff_ff.full = sclk_ff.full; 2586c93bb85bSJerome Glisse 2587c93bb85bSJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 2588c93bb85bSJerome Glisse fixed20_12 agpmode_ff; 2589c93bb85bSJerome Glisse agpmode_ff.full = rfixed_const(radeon_agpmode); 2590c93bb85bSJerome Glisse temp_ff.full = rfixed_const_666(16); 2591c93bb85bSJerome Glisse sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff); 2592c93bb85bSJerome Glisse } 2593c93bb85bSJerome Glisse /* TODO PCIE lanes may affect this - agpmode == 16?? */ 2594c93bb85bSJerome Glisse 2595c93bb85bSJerome Glisse if (ASIC_IS_R300(rdev)) { 2596c93bb85bSJerome Glisse sclk_delay_ff.full = rfixed_const(250); 2597c93bb85bSJerome Glisse } else { 2598c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) || 2599c93bb85bSJerome Glisse rdev->flags & RADEON_IS_IGP) { 2600c93bb85bSJerome Glisse if (rdev->mc.vram_is_ddr) 2601c93bb85bSJerome Glisse sclk_delay_ff.full = rfixed_const(41); 2602c93bb85bSJerome Glisse else 2603c93bb85bSJerome Glisse sclk_delay_ff.full = rfixed_const(33); 2604c93bb85bSJerome Glisse } else { 2605c93bb85bSJerome Glisse if (rdev->mc.vram_width == 128) 2606c93bb85bSJerome Glisse sclk_delay_ff.full = rfixed_const(57); 2607c93bb85bSJerome Glisse else 2608c93bb85bSJerome Glisse sclk_delay_ff.full = rfixed_const(41); 2609c93bb85bSJerome Glisse } 2610c93bb85bSJerome Glisse } 2611c93bb85bSJerome Glisse 2612c93bb85bSJerome Glisse mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff); 2613c93bb85bSJerome Glisse 2614c93bb85bSJerome Glisse if (rdev->mc.vram_is_ddr) { 2615c93bb85bSJerome Glisse if (rdev->mc.vram_width == 32) { 2616c93bb85bSJerome Glisse k1.full = rfixed_const(40); 2617c93bb85bSJerome Glisse c = 3; 2618c93bb85bSJerome Glisse } else { 2619c93bb85bSJerome Glisse k1.full = rfixed_const(20); 2620c93bb85bSJerome Glisse c = 1; 2621c93bb85bSJerome Glisse } 2622c93bb85bSJerome Glisse } else { 2623c93bb85bSJerome Glisse k1.full = rfixed_const(40); 2624c93bb85bSJerome Glisse c = 3; 2625c93bb85bSJerome Glisse } 2626c93bb85bSJerome Glisse 2627c93bb85bSJerome Glisse temp_ff.full = rfixed_const(2); 2628c93bb85bSJerome Glisse mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff); 2629c93bb85bSJerome Glisse temp_ff.full = rfixed_const(c); 2630c93bb85bSJerome Glisse mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff); 2631c93bb85bSJerome Glisse temp_ff.full = rfixed_const(4); 2632c93bb85bSJerome Glisse mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff); 2633c93bb85bSJerome Glisse mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff); 2634c93bb85bSJerome Glisse mc_latency_mclk.full += k1.full; 2635c93bb85bSJerome Glisse 2636c93bb85bSJerome Glisse mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff); 2637c93bb85bSJerome Glisse mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff); 2638c93bb85bSJerome Glisse 2639c93bb85bSJerome Glisse /* 2640c93bb85bSJerome Glisse HW cursor time assuming worst case of full size colour cursor. 2641c93bb85bSJerome Glisse */ 2642c93bb85bSJerome Glisse temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 2643c93bb85bSJerome Glisse temp_ff.full += trcd_ff.full; 2644c93bb85bSJerome Glisse if (temp_ff.full < tras_ff.full) 2645c93bb85bSJerome Glisse temp_ff.full = tras_ff.full; 2646c93bb85bSJerome Glisse cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff); 2647c93bb85bSJerome Glisse 2648c93bb85bSJerome Glisse temp_ff.full = rfixed_const(cur_size); 2649c93bb85bSJerome Glisse cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff); 2650c93bb85bSJerome Glisse /* 2651c93bb85bSJerome Glisse Find the total latency for the display data. 2652c93bb85bSJerome Glisse */ 2653b5fc9010SMichel Dänzer disp_latency_overhead.full = rfixed_const(8); 2654c93bb85bSJerome Glisse disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff); 2655c93bb85bSJerome Glisse mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 2656c93bb85bSJerome Glisse mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 2657c93bb85bSJerome Glisse 2658c93bb85bSJerome Glisse if (mc_latency_mclk.full > mc_latency_sclk.full) 2659c93bb85bSJerome Glisse disp_latency.full = mc_latency_mclk.full; 2660c93bb85bSJerome Glisse else 2661c93bb85bSJerome Glisse disp_latency.full = mc_latency_sclk.full; 2662c93bb85bSJerome Glisse 2663c93bb85bSJerome Glisse /* setup Max GRPH_STOP_REQ default value */ 2664c93bb85bSJerome Glisse if (ASIC_IS_RV100(rdev)) 2665c93bb85bSJerome Glisse max_stop_req = 0x5c; 2666c93bb85bSJerome Glisse else 2667c93bb85bSJerome Glisse max_stop_req = 0x7c; 2668c93bb85bSJerome Glisse 2669c93bb85bSJerome Glisse if (mode1) { 2670c93bb85bSJerome Glisse /* CRTC1 2671c93bb85bSJerome Glisse Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 2672c93bb85bSJerome Glisse GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 2673c93bb85bSJerome Glisse */ 2674c93bb85bSJerome Glisse stop_req = mode1->hdisplay * pixel_bytes1 / 16; 2675c93bb85bSJerome Glisse 2676c93bb85bSJerome Glisse if (stop_req > max_stop_req) 2677c93bb85bSJerome Glisse stop_req = max_stop_req; 2678c93bb85bSJerome Glisse 2679c93bb85bSJerome Glisse /* 2680c93bb85bSJerome Glisse Find the drain rate of the display buffer. 2681c93bb85bSJerome Glisse */ 2682c93bb85bSJerome Glisse temp_ff.full = rfixed_const((16/pixel_bytes1)); 2683c93bb85bSJerome Glisse disp_drain_rate.full = rfixed_div(pix_clk, temp_ff); 2684c93bb85bSJerome Glisse 2685c93bb85bSJerome Glisse /* 2686c93bb85bSJerome Glisse Find the critical point of the display buffer. 2687c93bb85bSJerome Glisse */ 2688c93bb85bSJerome Glisse crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency); 2689c93bb85bSJerome Glisse crit_point_ff.full += rfixed_const_half(0); 2690c93bb85bSJerome Glisse 2691c93bb85bSJerome Glisse critical_point = rfixed_trunc(crit_point_ff); 2692c93bb85bSJerome Glisse 2693c93bb85bSJerome Glisse if (rdev->disp_priority == 2) { 2694c93bb85bSJerome Glisse critical_point = 0; 2695c93bb85bSJerome Glisse } 2696c93bb85bSJerome Glisse 2697c93bb85bSJerome Glisse /* 2698c93bb85bSJerome Glisse The critical point should never be above max_stop_req-4. Setting 2699c93bb85bSJerome Glisse GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 2700c93bb85bSJerome Glisse */ 2701c93bb85bSJerome Glisse if (max_stop_req - critical_point < 4) 2702c93bb85bSJerome Glisse critical_point = 0; 2703c93bb85bSJerome Glisse 2704c93bb85bSJerome Glisse if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 2705c93bb85bSJerome Glisse /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 2706c93bb85bSJerome Glisse critical_point = 0x10; 2707c93bb85bSJerome Glisse } 2708c93bb85bSJerome Glisse 2709c93bb85bSJerome Glisse temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 2710c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 2711c93bb85bSJerome Glisse temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 2712c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_START_REQ_MASK); 2713c93bb85bSJerome Glisse if ((rdev->family == CHIP_R350) && 2714c93bb85bSJerome Glisse (stop_req > 0x15)) { 2715c93bb85bSJerome Glisse stop_req -= 0x10; 2716c93bb85bSJerome Glisse } 2717c93bb85bSJerome Glisse temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 2718c93bb85bSJerome Glisse temp |= RADEON_GRPH_BUFFER_SIZE; 2719c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 2720c93bb85bSJerome Glisse RADEON_GRPH_CRITICAL_AT_SOF | 2721c93bb85bSJerome Glisse RADEON_GRPH_STOP_CNTL); 2722c93bb85bSJerome Glisse /* 2723c93bb85bSJerome Glisse Write the result into the register. 2724c93bb85bSJerome Glisse */ 2725c93bb85bSJerome Glisse WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 2726c93bb85bSJerome Glisse (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 2727c93bb85bSJerome Glisse 2728c93bb85bSJerome Glisse #if 0 2729c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS400) || 2730c93bb85bSJerome Glisse (rdev->family == CHIP_RS480)) { 2731c93bb85bSJerome Glisse /* attempt to program RS400 disp regs correctly ??? */ 2732c93bb85bSJerome Glisse temp = RREG32(RS400_DISP1_REG_CNTL); 2733c93bb85bSJerome Glisse temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 2734c93bb85bSJerome Glisse RS400_DISP1_STOP_REQ_LEVEL_MASK); 2735c93bb85bSJerome Glisse WREG32(RS400_DISP1_REQ_CNTL1, (temp | 2736c93bb85bSJerome Glisse (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 2737c93bb85bSJerome Glisse (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 2738c93bb85bSJerome Glisse temp = RREG32(RS400_DMIF_MEM_CNTL1); 2739c93bb85bSJerome Glisse temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 2740c93bb85bSJerome Glisse RS400_DISP1_CRITICAL_POINT_STOP_MASK); 2741c93bb85bSJerome Glisse WREG32(RS400_DMIF_MEM_CNTL1, (temp | 2742c93bb85bSJerome Glisse (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 2743c93bb85bSJerome Glisse (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 2744c93bb85bSJerome Glisse } 2745c93bb85bSJerome Glisse #endif 2746c93bb85bSJerome Glisse 2747c93bb85bSJerome Glisse DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n", 2748c93bb85bSJerome Glisse /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 2749c93bb85bSJerome Glisse (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 2750c93bb85bSJerome Glisse } 2751c93bb85bSJerome Glisse 2752c93bb85bSJerome Glisse if (mode2) { 2753c93bb85bSJerome Glisse u32 grph2_cntl; 2754c93bb85bSJerome Glisse stop_req = mode2->hdisplay * pixel_bytes2 / 16; 2755c93bb85bSJerome Glisse 2756c93bb85bSJerome Glisse if (stop_req > max_stop_req) 2757c93bb85bSJerome Glisse stop_req = max_stop_req; 2758c93bb85bSJerome Glisse 2759c93bb85bSJerome Glisse /* 2760c93bb85bSJerome Glisse Find the drain rate of the display buffer. 2761c93bb85bSJerome Glisse */ 2762c93bb85bSJerome Glisse temp_ff.full = rfixed_const((16/pixel_bytes2)); 2763c93bb85bSJerome Glisse disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff); 2764c93bb85bSJerome Glisse 2765c93bb85bSJerome Glisse grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 2766c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 2767c93bb85bSJerome Glisse grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 2768c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 2769c93bb85bSJerome Glisse if ((rdev->family == CHIP_R350) && 2770c93bb85bSJerome Glisse (stop_req > 0x15)) { 2771c93bb85bSJerome Glisse stop_req -= 0x10; 2772c93bb85bSJerome Glisse } 2773c93bb85bSJerome Glisse grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 2774c93bb85bSJerome Glisse grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 2775c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 2776c93bb85bSJerome Glisse RADEON_GRPH_CRITICAL_AT_SOF | 2777c93bb85bSJerome Glisse RADEON_GRPH_STOP_CNTL); 2778c93bb85bSJerome Glisse 2779c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS100) || 2780c93bb85bSJerome Glisse (rdev->family == CHIP_RS200)) 2781c93bb85bSJerome Glisse critical_point2 = 0; 2782c93bb85bSJerome Glisse else { 2783c93bb85bSJerome Glisse temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 2784c93bb85bSJerome Glisse temp_ff.full = rfixed_const(temp); 2785c93bb85bSJerome Glisse temp_ff.full = rfixed_mul(mclk_ff, temp_ff); 2786c93bb85bSJerome Glisse if (sclk_ff.full < temp_ff.full) 2787c93bb85bSJerome Glisse temp_ff.full = sclk_ff.full; 2788c93bb85bSJerome Glisse 2789c93bb85bSJerome Glisse read_return_rate.full = temp_ff.full; 2790c93bb85bSJerome Glisse 2791c93bb85bSJerome Glisse if (mode1) { 2792c93bb85bSJerome Glisse temp_ff.full = read_return_rate.full - disp_drain_rate.full; 2793c93bb85bSJerome Glisse time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff); 2794c93bb85bSJerome Glisse } else { 2795c93bb85bSJerome Glisse time_disp1_drop_priority.full = 0; 2796c93bb85bSJerome Glisse } 2797c93bb85bSJerome Glisse crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 2798c93bb85bSJerome Glisse crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2); 2799c93bb85bSJerome Glisse crit_point_ff.full += rfixed_const_half(0); 2800c93bb85bSJerome Glisse 2801c93bb85bSJerome Glisse critical_point2 = rfixed_trunc(crit_point_ff); 2802c93bb85bSJerome Glisse 2803c93bb85bSJerome Glisse if (rdev->disp_priority == 2) { 2804c93bb85bSJerome Glisse critical_point2 = 0; 2805c93bb85bSJerome Glisse } 2806c93bb85bSJerome Glisse 2807c93bb85bSJerome Glisse if (max_stop_req - critical_point2 < 4) 2808c93bb85bSJerome Glisse critical_point2 = 0; 2809c93bb85bSJerome Glisse 2810c93bb85bSJerome Glisse } 2811c93bb85bSJerome Glisse 2812c93bb85bSJerome Glisse if (critical_point2 == 0 && rdev->family == CHIP_R300) { 2813c93bb85bSJerome Glisse /* some R300 cards have problem with this set to 0 */ 2814c93bb85bSJerome Glisse critical_point2 = 0x10; 2815c93bb85bSJerome Glisse } 2816c93bb85bSJerome Glisse 2817c93bb85bSJerome Glisse WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 2818c93bb85bSJerome Glisse (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 2819c93bb85bSJerome Glisse 2820c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS400) || 2821c93bb85bSJerome Glisse (rdev->family == CHIP_RS480)) { 2822c93bb85bSJerome Glisse #if 0 2823c93bb85bSJerome Glisse /* attempt to program RS400 disp2 regs correctly ??? */ 2824c93bb85bSJerome Glisse temp = RREG32(RS400_DISP2_REQ_CNTL1); 2825c93bb85bSJerome Glisse temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 2826c93bb85bSJerome Glisse RS400_DISP2_STOP_REQ_LEVEL_MASK); 2827c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL1, (temp | 2828c93bb85bSJerome Glisse (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 2829c93bb85bSJerome Glisse (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 2830c93bb85bSJerome Glisse temp = RREG32(RS400_DISP2_REQ_CNTL2); 2831c93bb85bSJerome Glisse temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 2832c93bb85bSJerome Glisse RS400_DISP2_CRITICAL_POINT_STOP_MASK); 2833c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL2, (temp | 2834c93bb85bSJerome Glisse (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 2835c93bb85bSJerome Glisse (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 2836c93bb85bSJerome Glisse #endif 2837c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 2838c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 2839c93bb85bSJerome Glisse WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 2840c93bb85bSJerome Glisse WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 2841c93bb85bSJerome Glisse } 2842c93bb85bSJerome Glisse 2843c93bb85bSJerome Glisse DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", 2844c93bb85bSJerome Glisse (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 2845c93bb85bSJerome Glisse } 2846c93bb85bSJerome Glisse } 2847551ebd83SDave Airlie 2848551ebd83SDave Airlie static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2849551ebd83SDave Airlie { 2850551ebd83SDave Airlie DRM_ERROR("pitch %d\n", t->pitch); 2851ceb776bcSMathias Fröhlich DRM_ERROR("use_pitch %d\n", t->use_pitch); 2852551ebd83SDave Airlie DRM_ERROR("width %d\n", t->width); 2853ceb776bcSMathias Fröhlich DRM_ERROR("width_11 %d\n", t->width_11); 2854551ebd83SDave Airlie DRM_ERROR("height %d\n", t->height); 2855ceb776bcSMathias Fröhlich DRM_ERROR("height_11 %d\n", t->height_11); 2856551ebd83SDave Airlie DRM_ERROR("num levels %d\n", t->num_levels); 2857551ebd83SDave Airlie DRM_ERROR("depth %d\n", t->txdepth); 2858551ebd83SDave Airlie DRM_ERROR("bpp %d\n", t->cpp); 2859551ebd83SDave Airlie DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2860551ebd83SDave Airlie DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2861551ebd83SDave Airlie DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2862d785d78bSDave Airlie DRM_ERROR("compress format %d\n", t->compress_format); 2863551ebd83SDave Airlie } 2864551ebd83SDave Airlie 2865551ebd83SDave Airlie static int r100_cs_track_cube(struct radeon_device *rdev, 2866551ebd83SDave Airlie struct r100_cs_track *track, unsigned idx) 2867551ebd83SDave Airlie { 2868551ebd83SDave Airlie unsigned face, w, h; 28694c788679SJerome Glisse struct radeon_bo *cube_robj; 2870551ebd83SDave Airlie unsigned long size; 2871551ebd83SDave Airlie 2872551ebd83SDave Airlie for (face = 0; face < 5; face++) { 2873551ebd83SDave Airlie cube_robj = track->textures[idx].cube_info[face].robj; 2874551ebd83SDave Airlie w = track->textures[idx].cube_info[face].width; 2875551ebd83SDave Airlie h = track->textures[idx].cube_info[face].height; 2876551ebd83SDave Airlie 2877551ebd83SDave Airlie size = w * h; 2878551ebd83SDave Airlie size *= track->textures[idx].cpp; 2879551ebd83SDave Airlie 2880551ebd83SDave Airlie size += track->textures[idx].cube_info[face].offset; 2881551ebd83SDave Airlie 28824c788679SJerome Glisse if (size > radeon_bo_size(cube_robj)) { 2883551ebd83SDave Airlie DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 28844c788679SJerome Glisse size, radeon_bo_size(cube_robj)); 2885551ebd83SDave Airlie r100_cs_track_texture_print(&track->textures[idx]); 2886551ebd83SDave Airlie return -1; 2887551ebd83SDave Airlie } 2888551ebd83SDave Airlie } 2889551ebd83SDave Airlie return 0; 2890551ebd83SDave Airlie } 2891551ebd83SDave Airlie 2892d785d78bSDave Airlie static int r100_track_compress_size(int compress_format, int w, int h) 2893d785d78bSDave Airlie { 2894d785d78bSDave Airlie int block_width, block_height, block_bytes; 2895d785d78bSDave Airlie int wblocks, hblocks; 2896d785d78bSDave Airlie int min_wblocks; 2897d785d78bSDave Airlie int sz; 2898d785d78bSDave Airlie 2899d785d78bSDave Airlie block_width = 4; 2900d785d78bSDave Airlie block_height = 4; 2901d785d78bSDave Airlie 2902d785d78bSDave Airlie switch (compress_format) { 2903d785d78bSDave Airlie case R100_TRACK_COMP_DXT1: 2904d785d78bSDave Airlie block_bytes = 8; 2905d785d78bSDave Airlie min_wblocks = 4; 2906d785d78bSDave Airlie break; 2907d785d78bSDave Airlie default: 2908d785d78bSDave Airlie case R100_TRACK_COMP_DXT35: 2909d785d78bSDave Airlie block_bytes = 16; 2910d785d78bSDave Airlie min_wblocks = 2; 2911d785d78bSDave Airlie break; 2912d785d78bSDave Airlie } 2913d785d78bSDave Airlie 2914d785d78bSDave Airlie hblocks = (h + block_height - 1) / block_height; 2915d785d78bSDave Airlie wblocks = (w + block_width - 1) / block_width; 2916d785d78bSDave Airlie if (wblocks < min_wblocks) 2917d785d78bSDave Airlie wblocks = min_wblocks; 2918d785d78bSDave Airlie sz = wblocks * hblocks * block_bytes; 2919d785d78bSDave Airlie return sz; 2920d785d78bSDave Airlie } 2921d785d78bSDave Airlie 2922551ebd83SDave Airlie static int r100_cs_track_texture_check(struct radeon_device *rdev, 2923551ebd83SDave Airlie struct r100_cs_track *track) 2924551ebd83SDave Airlie { 29254c788679SJerome Glisse struct radeon_bo *robj; 2926551ebd83SDave Airlie unsigned long size; 2927551ebd83SDave Airlie unsigned u, i, w, h; 2928551ebd83SDave Airlie int ret; 2929551ebd83SDave Airlie 2930551ebd83SDave Airlie for (u = 0; u < track->num_texture; u++) { 2931551ebd83SDave Airlie if (!track->textures[u].enabled) 2932551ebd83SDave Airlie continue; 2933551ebd83SDave Airlie robj = track->textures[u].robj; 2934551ebd83SDave Airlie if (robj == NULL) { 2935551ebd83SDave Airlie DRM_ERROR("No texture bound to unit %u\n", u); 2936551ebd83SDave Airlie return -EINVAL; 2937551ebd83SDave Airlie } 2938551ebd83SDave Airlie size = 0; 2939551ebd83SDave Airlie for (i = 0; i <= track->textures[u].num_levels; i++) { 2940551ebd83SDave Airlie if (track->textures[u].use_pitch) { 2941551ebd83SDave Airlie if (rdev->family < CHIP_R300) 2942551ebd83SDave Airlie w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2943551ebd83SDave Airlie else 2944551ebd83SDave Airlie w = track->textures[u].pitch / (1 << i); 2945551ebd83SDave Airlie } else { 2946ceb776bcSMathias Fröhlich w = track->textures[u].width; 2947551ebd83SDave Airlie if (rdev->family >= CHIP_RV515) 2948551ebd83SDave Airlie w |= track->textures[u].width_11; 2949ceb776bcSMathias Fröhlich w = w / (1 << i); 2950551ebd83SDave Airlie if (track->textures[u].roundup_w) 2951551ebd83SDave Airlie w = roundup_pow_of_two(w); 2952551ebd83SDave Airlie } 2953ceb776bcSMathias Fröhlich h = track->textures[u].height; 2954551ebd83SDave Airlie if (rdev->family >= CHIP_RV515) 2955551ebd83SDave Airlie h |= track->textures[u].height_11; 2956ceb776bcSMathias Fröhlich h = h / (1 << i); 2957551ebd83SDave Airlie if (track->textures[u].roundup_h) 2958551ebd83SDave Airlie h = roundup_pow_of_two(h); 2959d785d78bSDave Airlie if (track->textures[u].compress_format) { 2960d785d78bSDave Airlie 2961d785d78bSDave Airlie size += r100_track_compress_size(track->textures[u].compress_format, w, h); 2962d785d78bSDave Airlie /* compressed textures are block based */ 2963d785d78bSDave Airlie } else 2964551ebd83SDave Airlie size += w * h; 2965551ebd83SDave Airlie } 2966551ebd83SDave Airlie size *= track->textures[u].cpp; 2967d785d78bSDave Airlie 2968551ebd83SDave Airlie switch (track->textures[u].tex_coord_type) { 2969551ebd83SDave Airlie case 0: 2970551ebd83SDave Airlie break; 2971551ebd83SDave Airlie case 1: 2972551ebd83SDave Airlie size *= (1 << track->textures[u].txdepth); 2973551ebd83SDave Airlie break; 2974551ebd83SDave Airlie case 2: 2975551ebd83SDave Airlie if (track->separate_cube) { 2976551ebd83SDave Airlie ret = r100_cs_track_cube(rdev, track, u); 2977551ebd83SDave Airlie if (ret) 2978551ebd83SDave Airlie return ret; 2979551ebd83SDave Airlie } else 2980551ebd83SDave Airlie size *= 6; 2981551ebd83SDave Airlie break; 2982551ebd83SDave Airlie default: 2983551ebd83SDave Airlie DRM_ERROR("Invalid texture coordinate type %u for unit " 2984551ebd83SDave Airlie "%u\n", track->textures[u].tex_coord_type, u); 2985551ebd83SDave Airlie return -EINVAL; 2986551ebd83SDave Airlie } 29874c788679SJerome Glisse if (size > radeon_bo_size(robj)) { 2988551ebd83SDave Airlie DRM_ERROR("Texture of unit %u needs %lu bytes but is " 29894c788679SJerome Glisse "%lu\n", u, size, radeon_bo_size(robj)); 2990551ebd83SDave Airlie r100_cs_track_texture_print(&track->textures[u]); 2991551ebd83SDave Airlie return -EINVAL; 2992551ebd83SDave Airlie } 2993551ebd83SDave Airlie } 2994551ebd83SDave Airlie return 0; 2995551ebd83SDave Airlie } 2996551ebd83SDave Airlie 2997551ebd83SDave Airlie int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2998551ebd83SDave Airlie { 2999551ebd83SDave Airlie unsigned i; 3000551ebd83SDave Airlie unsigned long size; 3001551ebd83SDave Airlie unsigned prim_walk; 3002551ebd83SDave Airlie unsigned nverts; 3003551ebd83SDave Airlie 3004551ebd83SDave Airlie for (i = 0; i < track->num_cb; i++) { 3005551ebd83SDave Airlie if (track->cb[i].robj == NULL) { 300646c64d4bSMarek Olšák if (!(track->fastfill || track->color_channel_mask || 300746c64d4bSMarek Olšák track->blend_read_enable)) { 300846c64d4bSMarek Olšák continue; 300946c64d4bSMarek Olšák } 3010551ebd83SDave Airlie DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 3011551ebd83SDave Airlie return -EINVAL; 3012551ebd83SDave Airlie } 3013551ebd83SDave Airlie size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 3014551ebd83SDave Airlie size += track->cb[i].offset; 30154c788679SJerome Glisse if (size > radeon_bo_size(track->cb[i].robj)) { 3016551ebd83SDave Airlie DRM_ERROR("[drm] Buffer too small for color buffer %d " 3017551ebd83SDave Airlie "(need %lu have %lu) !\n", i, size, 30184c788679SJerome Glisse radeon_bo_size(track->cb[i].robj)); 3019551ebd83SDave Airlie DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 3020551ebd83SDave Airlie i, track->cb[i].pitch, track->cb[i].cpp, 3021551ebd83SDave Airlie track->cb[i].offset, track->maxy); 3022551ebd83SDave Airlie return -EINVAL; 3023551ebd83SDave Airlie } 3024551ebd83SDave Airlie } 3025551ebd83SDave Airlie if (track->z_enabled) { 3026551ebd83SDave Airlie if (track->zb.robj == NULL) { 3027551ebd83SDave Airlie DRM_ERROR("[drm] No buffer for z buffer !\n"); 3028551ebd83SDave Airlie return -EINVAL; 3029551ebd83SDave Airlie } 3030551ebd83SDave Airlie size = track->zb.pitch * track->zb.cpp * track->maxy; 3031551ebd83SDave Airlie size += track->zb.offset; 30324c788679SJerome Glisse if (size > radeon_bo_size(track->zb.robj)) { 3033551ebd83SDave Airlie DRM_ERROR("[drm] Buffer too small for z buffer " 3034551ebd83SDave Airlie "(need %lu have %lu) !\n", size, 30354c788679SJerome Glisse radeon_bo_size(track->zb.robj)); 3036551ebd83SDave Airlie DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 3037551ebd83SDave Airlie track->zb.pitch, track->zb.cpp, 3038551ebd83SDave Airlie track->zb.offset, track->maxy); 3039551ebd83SDave Airlie return -EINVAL; 3040551ebd83SDave Airlie } 3041551ebd83SDave Airlie } 3042551ebd83SDave Airlie prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 3043551ebd83SDave Airlie nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 3044551ebd83SDave Airlie switch (prim_walk) { 3045551ebd83SDave Airlie case 1: 3046551ebd83SDave Airlie for (i = 0; i < track->num_arrays; i++) { 3047551ebd83SDave Airlie size = track->arrays[i].esize * track->max_indx * 4; 3048551ebd83SDave Airlie if (track->arrays[i].robj == NULL) { 3049551ebd83SDave Airlie DRM_ERROR("(PW %u) Vertex array %u no buffer " 3050551ebd83SDave Airlie "bound\n", prim_walk, i); 3051551ebd83SDave Airlie return -EINVAL; 3052551ebd83SDave Airlie } 30534c788679SJerome Glisse if (size > radeon_bo_size(track->arrays[i].robj)) { 30544c788679SJerome Glisse dev_err(rdev->dev, "(PW %u) Vertex array %u " 30554c788679SJerome Glisse "need %lu dwords have %lu dwords\n", 30564c788679SJerome Glisse prim_walk, i, size >> 2, 30574c788679SJerome Glisse radeon_bo_size(track->arrays[i].robj) 30584c788679SJerome Glisse >> 2); 3059551ebd83SDave Airlie DRM_ERROR("Max indices %u\n", track->max_indx); 3060551ebd83SDave Airlie return -EINVAL; 3061551ebd83SDave Airlie } 3062551ebd83SDave Airlie } 3063551ebd83SDave Airlie break; 3064551ebd83SDave Airlie case 2: 3065551ebd83SDave Airlie for (i = 0; i < track->num_arrays; i++) { 3066551ebd83SDave Airlie size = track->arrays[i].esize * (nverts - 1) * 4; 3067551ebd83SDave Airlie if (track->arrays[i].robj == NULL) { 3068551ebd83SDave Airlie DRM_ERROR("(PW %u) Vertex array %u no buffer " 3069551ebd83SDave Airlie "bound\n", prim_walk, i); 3070551ebd83SDave Airlie return -EINVAL; 3071551ebd83SDave Airlie } 30724c788679SJerome Glisse if (size > radeon_bo_size(track->arrays[i].robj)) { 30734c788679SJerome Glisse dev_err(rdev->dev, "(PW %u) Vertex array %u " 30744c788679SJerome Glisse "need %lu dwords have %lu dwords\n", 30754c788679SJerome Glisse prim_walk, i, size >> 2, 30764c788679SJerome Glisse radeon_bo_size(track->arrays[i].robj) 30774c788679SJerome Glisse >> 2); 3078551ebd83SDave Airlie return -EINVAL; 3079551ebd83SDave Airlie } 3080551ebd83SDave Airlie } 3081551ebd83SDave Airlie break; 3082551ebd83SDave Airlie case 3: 3083551ebd83SDave Airlie size = track->vtx_size * nverts; 3084551ebd83SDave Airlie if (size != track->immd_dwords) { 3085551ebd83SDave Airlie DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 3086551ebd83SDave Airlie track->immd_dwords, size); 3087551ebd83SDave Airlie DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 3088551ebd83SDave Airlie nverts, track->vtx_size); 3089551ebd83SDave Airlie return -EINVAL; 3090551ebd83SDave Airlie } 3091551ebd83SDave Airlie break; 3092551ebd83SDave Airlie default: 3093551ebd83SDave Airlie DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 3094551ebd83SDave Airlie prim_walk); 3095551ebd83SDave Airlie return -EINVAL; 3096551ebd83SDave Airlie } 3097551ebd83SDave Airlie return r100_cs_track_texture_check(rdev, track); 3098551ebd83SDave Airlie } 3099551ebd83SDave Airlie 3100551ebd83SDave Airlie void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 3101551ebd83SDave Airlie { 3102551ebd83SDave Airlie unsigned i, face; 3103551ebd83SDave Airlie 3104551ebd83SDave Airlie if (rdev->family < CHIP_R300) { 3105551ebd83SDave Airlie track->num_cb = 1; 3106551ebd83SDave Airlie if (rdev->family <= CHIP_RS200) 3107551ebd83SDave Airlie track->num_texture = 3; 3108551ebd83SDave Airlie else 3109551ebd83SDave Airlie track->num_texture = 6; 3110551ebd83SDave Airlie track->maxy = 2048; 3111551ebd83SDave Airlie track->separate_cube = 1; 3112551ebd83SDave Airlie } else { 3113551ebd83SDave Airlie track->num_cb = 4; 3114551ebd83SDave Airlie track->num_texture = 16; 3115551ebd83SDave Airlie track->maxy = 4096; 3116551ebd83SDave Airlie track->separate_cube = 0; 3117551ebd83SDave Airlie } 3118551ebd83SDave Airlie 3119551ebd83SDave Airlie for (i = 0; i < track->num_cb; i++) { 3120551ebd83SDave Airlie track->cb[i].robj = NULL; 3121551ebd83SDave Airlie track->cb[i].pitch = 8192; 3122551ebd83SDave Airlie track->cb[i].cpp = 16; 3123551ebd83SDave Airlie track->cb[i].offset = 0; 3124551ebd83SDave Airlie } 3125551ebd83SDave Airlie track->z_enabled = true; 3126551ebd83SDave Airlie track->zb.robj = NULL; 3127551ebd83SDave Airlie track->zb.pitch = 8192; 3128551ebd83SDave Airlie track->zb.cpp = 4; 3129551ebd83SDave Airlie track->zb.offset = 0; 3130551ebd83SDave Airlie track->vtx_size = 0x7F; 3131551ebd83SDave Airlie track->immd_dwords = 0xFFFFFFFFUL; 3132551ebd83SDave Airlie track->num_arrays = 11; 3133551ebd83SDave Airlie track->max_indx = 0x00FFFFFFUL; 3134551ebd83SDave Airlie for (i = 0; i < track->num_arrays; i++) { 3135551ebd83SDave Airlie track->arrays[i].robj = NULL; 3136551ebd83SDave Airlie track->arrays[i].esize = 0x7F; 3137551ebd83SDave Airlie } 3138551ebd83SDave Airlie for (i = 0; i < track->num_texture; i++) { 3139d785d78bSDave Airlie track->textures[i].compress_format = R100_TRACK_COMP_NONE; 3140551ebd83SDave Airlie track->textures[i].pitch = 16536; 3141551ebd83SDave Airlie track->textures[i].width = 16536; 3142551ebd83SDave Airlie track->textures[i].height = 16536; 3143551ebd83SDave Airlie track->textures[i].width_11 = 1 << 11; 3144551ebd83SDave Airlie track->textures[i].height_11 = 1 << 11; 3145551ebd83SDave Airlie track->textures[i].num_levels = 12; 3146551ebd83SDave Airlie if (rdev->family <= CHIP_RS200) { 3147551ebd83SDave Airlie track->textures[i].tex_coord_type = 0; 3148551ebd83SDave Airlie track->textures[i].txdepth = 0; 3149551ebd83SDave Airlie } else { 3150551ebd83SDave Airlie track->textures[i].txdepth = 16; 3151551ebd83SDave Airlie track->textures[i].tex_coord_type = 1; 3152551ebd83SDave Airlie } 3153551ebd83SDave Airlie track->textures[i].cpp = 64; 3154551ebd83SDave Airlie track->textures[i].robj = NULL; 3155551ebd83SDave Airlie /* CS IB emission code makes sure texture unit are disabled */ 3156551ebd83SDave Airlie track->textures[i].enabled = false; 3157551ebd83SDave Airlie track->textures[i].roundup_w = true; 3158551ebd83SDave Airlie track->textures[i].roundup_h = true; 3159551ebd83SDave Airlie if (track->separate_cube) 3160551ebd83SDave Airlie for (face = 0; face < 5; face++) { 3161551ebd83SDave Airlie track->textures[i].cube_info[face].robj = NULL; 3162551ebd83SDave Airlie track->textures[i].cube_info[face].width = 16536; 3163551ebd83SDave Airlie track->textures[i].cube_info[face].height = 16536; 3164551ebd83SDave Airlie track->textures[i].cube_info[face].offset = 0; 3165551ebd83SDave Airlie } 3166551ebd83SDave Airlie } 3167551ebd83SDave Airlie } 31683ce0a23dSJerome Glisse 31693ce0a23dSJerome Glisse int r100_ring_test(struct radeon_device *rdev) 31703ce0a23dSJerome Glisse { 31713ce0a23dSJerome Glisse uint32_t scratch; 31723ce0a23dSJerome Glisse uint32_t tmp = 0; 31733ce0a23dSJerome Glisse unsigned i; 31743ce0a23dSJerome Glisse int r; 31753ce0a23dSJerome Glisse 31763ce0a23dSJerome Glisse r = radeon_scratch_get(rdev, &scratch); 31773ce0a23dSJerome Glisse if (r) { 31783ce0a23dSJerome Glisse DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 31793ce0a23dSJerome Glisse return r; 31803ce0a23dSJerome Glisse } 31813ce0a23dSJerome Glisse WREG32(scratch, 0xCAFEDEAD); 31823ce0a23dSJerome Glisse r = radeon_ring_lock(rdev, 2); 31833ce0a23dSJerome Glisse if (r) { 31843ce0a23dSJerome Glisse DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 31853ce0a23dSJerome Glisse radeon_scratch_free(rdev, scratch); 31863ce0a23dSJerome Glisse return r; 31873ce0a23dSJerome Glisse } 31883ce0a23dSJerome Glisse radeon_ring_write(rdev, PACKET0(scratch, 0)); 31893ce0a23dSJerome Glisse radeon_ring_write(rdev, 0xDEADBEEF); 31903ce0a23dSJerome Glisse radeon_ring_unlock_commit(rdev); 31913ce0a23dSJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 31923ce0a23dSJerome Glisse tmp = RREG32(scratch); 31933ce0a23dSJerome Glisse if (tmp == 0xDEADBEEF) { 31943ce0a23dSJerome Glisse break; 31953ce0a23dSJerome Glisse } 31963ce0a23dSJerome Glisse DRM_UDELAY(1); 31973ce0a23dSJerome Glisse } 31983ce0a23dSJerome Glisse if (i < rdev->usec_timeout) { 31993ce0a23dSJerome Glisse DRM_INFO("ring test succeeded in %d usecs\n", i); 32003ce0a23dSJerome Glisse } else { 32013ce0a23dSJerome Glisse DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", 32023ce0a23dSJerome Glisse scratch, tmp); 32033ce0a23dSJerome Glisse r = -EINVAL; 32043ce0a23dSJerome Glisse } 32053ce0a23dSJerome Glisse radeon_scratch_free(rdev, scratch); 32063ce0a23dSJerome Glisse return r; 32073ce0a23dSJerome Glisse } 32083ce0a23dSJerome Glisse 32093ce0a23dSJerome Glisse void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 32103ce0a23dSJerome Glisse { 32113ce0a23dSJerome Glisse radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); 32123ce0a23dSJerome Glisse radeon_ring_write(rdev, ib->gpu_addr); 32133ce0a23dSJerome Glisse radeon_ring_write(rdev, ib->length_dw); 32143ce0a23dSJerome Glisse } 32153ce0a23dSJerome Glisse 32163ce0a23dSJerome Glisse int r100_ib_test(struct radeon_device *rdev) 32173ce0a23dSJerome Glisse { 32183ce0a23dSJerome Glisse struct radeon_ib *ib; 32193ce0a23dSJerome Glisse uint32_t scratch; 32203ce0a23dSJerome Glisse uint32_t tmp = 0; 32213ce0a23dSJerome Glisse unsigned i; 32223ce0a23dSJerome Glisse int r; 32233ce0a23dSJerome Glisse 32243ce0a23dSJerome Glisse r = radeon_scratch_get(rdev, &scratch); 32253ce0a23dSJerome Glisse if (r) { 32263ce0a23dSJerome Glisse DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 32273ce0a23dSJerome Glisse return r; 32283ce0a23dSJerome Glisse } 32293ce0a23dSJerome Glisse WREG32(scratch, 0xCAFEDEAD); 32303ce0a23dSJerome Glisse r = radeon_ib_get(rdev, &ib); 32313ce0a23dSJerome Glisse if (r) { 32323ce0a23dSJerome Glisse return r; 32333ce0a23dSJerome Glisse } 32343ce0a23dSJerome Glisse ib->ptr[0] = PACKET0(scratch, 0); 32353ce0a23dSJerome Glisse ib->ptr[1] = 0xDEADBEEF; 32363ce0a23dSJerome Glisse ib->ptr[2] = PACKET2(0); 32373ce0a23dSJerome Glisse ib->ptr[3] = PACKET2(0); 32383ce0a23dSJerome Glisse ib->ptr[4] = PACKET2(0); 32393ce0a23dSJerome Glisse ib->ptr[5] = PACKET2(0); 32403ce0a23dSJerome Glisse ib->ptr[6] = PACKET2(0); 32413ce0a23dSJerome Glisse ib->ptr[7] = PACKET2(0); 32423ce0a23dSJerome Glisse ib->length_dw = 8; 32433ce0a23dSJerome Glisse r = radeon_ib_schedule(rdev, ib); 32443ce0a23dSJerome Glisse if (r) { 32453ce0a23dSJerome Glisse radeon_scratch_free(rdev, scratch); 32463ce0a23dSJerome Glisse radeon_ib_free(rdev, &ib); 32473ce0a23dSJerome Glisse return r; 32483ce0a23dSJerome Glisse } 32493ce0a23dSJerome Glisse r = radeon_fence_wait(ib->fence, false); 32503ce0a23dSJerome Glisse if (r) { 32513ce0a23dSJerome Glisse return r; 32523ce0a23dSJerome Glisse } 32533ce0a23dSJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 32543ce0a23dSJerome Glisse tmp = RREG32(scratch); 32553ce0a23dSJerome Glisse if (tmp == 0xDEADBEEF) { 32563ce0a23dSJerome Glisse break; 32573ce0a23dSJerome Glisse } 32583ce0a23dSJerome Glisse DRM_UDELAY(1); 32593ce0a23dSJerome Glisse } 32603ce0a23dSJerome Glisse if (i < rdev->usec_timeout) { 32613ce0a23dSJerome Glisse DRM_INFO("ib test succeeded in %u usecs\n", i); 32623ce0a23dSJerome Glisse } else { 32633ce0a23dSJerome Glisse DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", 32643ce0a23dSJerome Glisse scratch, tmp); 32653ce0a23dSJerome Glisse r = -EINVAL; 32663ce0a23dSJerome Glisse } 32673ce0a23dSJerome Glisse radeon_scratch_free(rdev, scratch); 32683ce0a23dSJerome Glisse radeon_ib_free(rdev, &ib); 32693ce0a23dSJerome Glisse return r; 32703ce0a23dSJerome Glisse } 32719f022ddfSJerome Glisse 32729f022ddfSJerome Glisse void r100_ib_fini(struct radeon_device *rdev) 32739f022ddfSJerome Glisse { 32749f022ddfSJerome Glisse radeon_ib_pool_fini(rdev); 32759f022ddfSJerome Glisse } 32769f022ddfSJerome Glisse 32779f022ddfSJerome Glisse int r100_ib_init(struct radeon_device *rdev) 32789f022ddfSJerome Glisse { 32799f022ddfSJerome Glisse int r; 32809f022ddfSJerome Glisse 32819f022ddfSJerome Glisse r = radeon_ib_pool_init(rdev); 32829f022ddfSJerome Glisse if (r) { 32839f022ddfSJerome Glisse dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r); 32849f022ddfSJerome Glisse r100_ib_fini(rdev); 32859f022ddfSJerome Glisse return r; 32869f022ddfSJerome Glisse } 32879f022ddfSJerome Glisse r = r100_ib_test(rdev); 32889f022ddfSJerome Glisse if (r) { 32899f022ddfSJerome Glisse dev_err(rdev->dev, "failled testing IB (%d).\n", r); 32909f022ddfSJerome Glisse r100_ib_fini(rdev); 32919f022ddfSJerome Glisse return r; 32929f022ddfSJerome Glisse } 32939f022ddfSJerome Glisse return 0; 32949f022ddfSJerome Glisse } 32959f022ddfSJerome Glisse 32969f022ddfSJerome Glisse void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 32979f022ddfSJerome Glisse { 32989f022ddfSJerome Glisse /* Shutdown CP we shouldn't need to do that but better be safe than 32999f022ddfSJerome Glisse * sorry 33009f022ddfSJerome Glisse */ 33019f022ddfSJerome Glisse rdev->cp.ready = false; 33029f022ddfSJerome Glisse WREG32(R_000740_CP_CSQ_CNTL, 0); 33039f022ddfSJerome Glisse 33049f022ddfSJerome Glisse /* Save few CRTC registers */ 3305ca6ffc64SJerome Glisse save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 33069f022ddfSJerome Glisse save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 33079f022ddfSJerome Glisse save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 33089f022ddfSJerome Glisse save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 33099f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 33109f022ddfSJerome Glisse save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 33119f022ddfSJerome Glisse save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 33129f022ddfSJerome Glisse } 33139f022ddfSJerome Glisse 33149f022ddfSJerome Glisse /* Disable VGA aperture access */ 3315ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 33169f022ddfSJerome Glisse /* Disable cursor, overlay, crtc */ 33179f022ddfSJerome Glisse WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 33189f022ddfSJerome Glisse WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 33199f022ddfSJerome Glisse S_000054_CRTC_DISPLAY_DIS(1)); 33209f022ddfSJerome Glisse WREG32(R_000050_CRTC_GEN_CNTL, 33219f022ddfSJerome Glisse (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 33229f022ddfSJerome Glisse S_000050_CRTC_DISP_REQ_EN_B(1)); 33239f022ddfSJerome Glisse WREG32(R_000420_OV0_SCALE_CNTL, 33249f022ddfSJerome Glisse C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 33259f022ddfSJerome Glisse WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 33269f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 33279f022ddfSJerome Glisse WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 33289f022ddfSJerome Glisse S_000360_CUR2_LOCK(1)); 33299f022ddfSJerome Glisse WREG32(R_0003F8_CRTC2_GEN_CNTL, 33309f022ddfSJerome Glisse (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 33319f022ddfSJerome Glisse S_0003F8_CRTC2_DISPLAY_DIS(1) | 33329f022ddfSJerome Glisse S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 33339f022ddfSJerome Glisse WREG32(R_000360_CUR2_OFFSET, 33349f022ddfSJerome Glisse C_000360_CUR2_LOCK & save->CUR2_OFFSET); 33359f022ddfSJerome Glisse } 33369f022ddfSJerome Glisse } 33379f022ddfSJerome Glisse 33389f022ddfSJerome Glisse void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 33399f022ddfSJerome Glisse { 33409f022ddfSJerome Glisse /* Update base address for crtc */ 3341d594e46aSJerome Glisse WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 33429f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3343d594e46aSJerome Glisse WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 33449f022ddfSJerome Glisse } 33459f022ddfSJerome Glisse /* Restore CRTC registers */ 3346ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 33479f022ddfSJerome Glisse WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 33489f022ddfSJerome Glisse WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 33499f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 33509f022ddfSJerome Glisse WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 33519f022ddfSJerome Glisse } 33529f022ddfSJerome Glisse } 3353ca6ffc64SJerome Glisse 3354ca6ffc64SJerome Glisse void r100_vga_render_disable(struct radeon_device *rdev) 3355ca6ffc64SJerome Glisse { 3356ca6ffc64SJerome Glisse u32 tmp; 3357ca6ffc64SJerome Glisse 3358ca6ffc64SJerome Glisse tmp = RREG8(R_0003C2_GENMO_WT); 3359ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3360ca6ffc64SJerome Glisse } 3361d4550907SJerome Glisse 3362d4550907SJerome Glisse static void r100_debugfs(struct radeon_device *rdev) 3363d4550907SJerome Glisse { 3364d4550907SJerome Glisse int r; 3365d4550907SJerome Glisse 3366d4550907SJerome Glisse r = r100_debugfs_mc_info_init(rdev); 3367d4550907SJerome Glisse if (r) 3368d4550907SJerome Glisse dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3369d4550907SJerome Glisse } 3370d4550907SJerome Glisse 3371d4550907SJerome Glisse static void r100_mc_program(struct radeon_device *rdev) 3372d4550907SJerome Glisse { 3373d4550907SJerome Glisse struct r100_mc_save save; 3374d4550907SJerome Glisse 3375d4550907SJerome Glisse /* Stops all mc clients */ 3376d4550907SJerome Glisse r100_mc_stop(rdev, &save); 3377d4550907SJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 3378d4550907SJerome Glisse WREG32(R_00014C_MC_AGP_LOCATION, 3379d4550907SJerome Glisse S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3380d4550907SJerome Glisse S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3381d4550907SJerome Glisse WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3382d4550907SJerome Glisse if (rdev->family > CHIP_RV200) 3383d4550907SJerome Glisse WREG32(R_00015C_AGP_BASE_2, 3384d4550907SJerome Glisse upper_32_bits(rdev->mc.agp_base) & 0xff); 3385d4550907SJerome Glisse } else { 3386d4550907SJerome Glisse WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3387d4550907SJerome Glisse WREG32(R_000170_AGP_BASE, 0); 3388d4550907SJerome Glisse if (rdev->family > CHIP_RV200) 3389d4550907SJerome Glisse WREG32(R_00015C_AGP_BASE_2, 0); 3390d4550907SJerome Glisse } 3391d4550907SJerome Glisse /* Wait for mc idle */ 3392d4550907SJerome Glisse if (r100_mc_wait_for_idle(rdev)) 3393d4550907SJerome Glisse dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3394d4550907SJerome Glisse /* Program MC, should be a 32bits limited address space */ 3395d4550907SJerome Glisse WREG32(R_000148_MC_FB_LOCATION, 3396d4550907SJerome Glisse S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3397d4550907SJerome Glisse S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3398d4550907SJerome Glisse r100_mc_resume(rdev, &save); 3399d4550907SJerome Glisse } 3400d4550907SJerome Glisse 3401d4550907SJerome Glisse void r100_clock_startup(struct radeon_device *rdev) 3402d4550907SJerome Glisse { 3403d4550907SJerome Glisse u32 tmp; 3404d4550907SJerome Glisse 3405d4550907SJerome Glisse if (radeon_dynclks != -1 && radeon_dynclks) 3406d4550907SJerome Glisse radeon_legacy_set_clock_gating(rdev, 1); 3407d4550907SJerome Glisse /* We need to force on some of the block */ 3408d4550907SJerome Glisse tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3409d4550907SJerome Glisse tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3410d4550907SJerome Glisse if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3411d4550907SJerome Glisse tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3412d4550907SJerome Glisse WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3413d4550907SJerome Glisse } 3414d4550907SJerome Glisse 3415d4550907SJerome Glisse static int r100_startup(struct radeon_device *rdev) 3416d4550907SJerome Glisse { 3417d4550907SJerome Glisse int r; 3418d4550907SJerome Glisse 341992cde00cSAlex Deucher /* set common regs */ 342092cde00cSAlex Deucher r100_set_common_regs(rdev); 342192cde00cSAlex Deucher /* program mc */ 3422d4550907SJerome Glisse r100_mc_program(rdev); 3423d4550907SJerome Glisse /* Resume clock */ 3424d4550907SJerome Glisse r100_clock_startup(rdev); 3425d4550907SJerome Glisse /* Initialize GPU configuration (# pipes, ...) */ 3426*90aca4d2SJerome Glisse // r100_gpu_init(rdev); 3427d4550907SJerome Glisse /* Initialize GART (initialize after TTM so we can allocate 3428d4550907SJerome Glisse * memory through TTM but finalize after TTM) */ 342917e15b0cSDave Airlie r100_enable_bm(rdev); 3430d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) { 3431d4550907SJerome Glisse r = r100_pci_gart_enable(rdev); 3432d4550907SJerome Glisse if (r) 3433d4550907SJerome Glisse return r; 3434d4550907SJerome Glisse } 3435d4550907SJerome Glisse /* Enable IRQ */ 3436d4550907SJerome Glisse r100_irq_set(rdev); 3437cafe6609SJerome Glisse rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3438d4550907SJerome Glisse /* 1M ring buffer */ 3439d4550907SJerome Glisse r = r100_cp_init(rdev, 1024 * 1024); 3440d4550907SJerome Glisse if (r) { 3441d4550907SJerome Glisse dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 3442d4550907SJerome Glisse return r; 3443d4550907SJerome Glisse } 3444d4550907SJerome Glisse r = r100_wb_init(rdev); 3445d4550907SJerome Glisse if (r) 3446d4550907SJerome Glisse dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 3447d4550907SJerome Glisse r = r100_ib_init(rdev); 3448d4550907SJerome Glisse if (r) { 3449d4550907SJerome Glisse dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 3450d4550907SJerome Glisse return r; 3451d4550907SJerome Glisse } 3452d4550907SJerome Glisse return 0; 3453d4550907SJerome Glisse } 3454d4550907SJerome Glisse 3455d4550907SJerome Glisse int r100_resume(struct radeon_device *rdev) 3456d4550907SJerome Glisse { 3457d4550907SJerome Glisse /* Make sur GART are not working */ 3458d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 3459d4550907SJerome Glisse r100_pci_gart_disable(rdev); 3460d4550907SJerome Glisse /* Resume clock before doing reset */ 3461d4550907SJerome Glisse r100_clock_startup(rdev); 3462d4550907SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3463a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 3464d4550907SJerome Glisse dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3465d4550907SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 3466d4550907SJerome Glisse RREG32(R_0007C0_CP_STAT)); 3467d4550907SJerome Glisse } 3468d4550907SJerome Glisse /* post */ 3469d4550907SJerome Glisse radeon_combios_asic_init(rdev->ddev); 3470d4550907SJerome Glisse /* Resume clock after posting */ 3471d4550907SJerome Glisse r100_clock_startup(rdev); 3472550e2d92SDave Airlie /* Initialize surface registers */ 3473550e2d92SDave Airlie radeon_surface_init(rdev); 3474d4550907SJerome Glisse return r100_startup(rdev); 3475d4550907SJerome Glisse } 3476d4550907SJerome Glisse 3477d4550907SJerome Glisse int r100_suspend(struct radeon_device *rdev) 3478d4550907SJerome Glisse { 3479d4550907SJerome Glisse r100_cp_disable(rdev); 3480d4550907SJerome Glisse r100_wb_disable(rdev); 3481d4550907SJerome Glisse r100_irq_disable(rdev); 3482d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 3483d4550907SJerome Glisse r100_pci_gart_disable(rdev); 3484d4550907SJerome Glisse return 0; 3485d4550907SJerome Glisse } 3486d4550907SJerome Glisse 3487d4550907SJerome Glisse void r100_fini(struct radeon_device *rdev) 3488d4550907SJerome Glisse { 348929fb52caSAlex Deucher radeon_pm_fini(rdev); 3490d4550907SJerome Glisse r100_cp_fini(rdev); 3491d4550907SJerome Glisse r100_wb_fini(rdev); 3492d4550907SJerome Glisse r100_ib_fini(rdev); 3493d4550907SJerome Glisse radeon_gem_fini(rdev); 3494d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 3495d4550907SJerome Glisse r100_pci_gart_fini(rdev); 3496d0269ed8SJerome Glisse radeon_agp_fini(rdev); 3497d4550907SJerome Glisse radeon_irq_kms_fini(rdev); 3498d4550907SJerome Glisse radeon_fence_driver_fini(rdev); 34994c788679SJerome Glisse radeon_bo_fini(rdev); 3500d4550907SJerome Glisse radeon_atombios_fini(rdev); 3501d4550907SJerome Glisse kfree(rdev->bios); 3502d4550907SJerome Glisse rdev->bios = NULL; 3503d4550907SJerome Glisse } 3504d4550907SJerome Glisse 3505d4550907SJerome Glisse int r100_init(struct radeon_device *rdev) 3506d4550907SJerome Glisse { 3507d4550907SJerome Glisse int r; 3508d4550907SJerome Glisse 3509d4550907SJerome Glisse /* Register debugfs file specific to this group of asics */ 3510d4550907SJerome Glisse r100_debugfs(rdev); 3511d4550907SJerome Glisse /* Disable VGA */ 3512d4550907SJerome Glisse r100_vga_render_disable(rdev); 3513d4550907SJerome Glisse /* Initialize scratch registers */ 3514d4550907SJerome Glisse radeon_scratch_init(rdev); 3515d4550907SJerome Glisse /* Initialize surface registers */ 3516d4550907SJerome Glisse radeon_surface_init(rdev); 3517d4550907SJerome Glisse /* TODO: disable VGA need to use VGA request */ 3518d4550907SJerome Glisse /* BIOS*/ 3519d4550907SJerome Glisse if (!radeon_get_bios(rdev)) { 3520d4550907SJerome Glisse if (ASIC_IS_AVIVO(rdev)) 3521d4550907SJerome Glisse return -EINVAL; 3522d4550907SJerome Glisse } 3523d4550907SJerome Glisse if (rdev->is_atom_bios) { 3524d4550907SJerome Glisse dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 3525d4550907SJerome Glisse return -EINVAL; 3526d4550907SJerome Glisse } else { 3527d4550907SJerome Glisse r = radeon_combios_init(rdev); 3528d4550907SJerome Glisse if (r) 3529d4550907SJerome Glisse return r; 3530d4550907SJerome Glisse } 3531d4550907SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3532a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 3533d4550907SJerome Glisse dev_warn(rdev->dev, 3534d4550907SJerome Glisse "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3535d4550907SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 3536d4550907SJerome Glisse RREG32(R_0007C0_CP_STAT)); 3537d4550907SJerome Glisse } 3538d4550907SJerome Glisse /* check if cards are posted or not */ 353972542d77SDave Airlie if (radeon_boot_test_post_card(rdev) == false) 354072542d77SDave Airlie return -EINVAL; 3541d4550907SJerome Glisse /* Set asic errata */ 3542d4550907SJerome Glisse r100_errata(rdev); 3543d4550907SJerome Glisse /* Initialize clocks */ 3544d4550907SJerome Glisse radeon_get_clock_info(rdev->ddev); 35456234077dSRafał Miłecki /* Initialize power management */ 35466234077dSRafał Miłecki radeon_pm_init(rdev); 3547d594e46aSJerome Glisse /* initialize AGP */ 3548d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 3549d594e46aSJerome Glisse r = radeon_agp_init(rdev); 3550d594e46aSJerome Glisse if (r) { 3551d594e46aSJerome Glisse radeon_agp_disable(rdev); 3552d594e46aSJerome Glisse } 3553d594e46aSJerome Glisse } 3554d594e46aSJerome Glisse /* initialize VRAM */ 3555d594e46aSJerome Glisse r100_mc_init(rdev); 3556d4550907SJerome Glisse /* Fence driver */ 3557d4550907SJerome Glisse r = radeon_fence_driver_init(rdev); 3558d4550907SJerome Glisse if (r) 3559d4550907SJerome Glisse return r; 3560d4550907SJerome Glisse r = radeon_irq_kms_init(rdev); 3561d4550907SJerome Glisse if (r) 3562d4550907SJerome Glisse return r; 3563d4550907SJerome Glisse /* Memory manager */ 35644c788679SJerome Glisse r = radeon_bo_init(rdev); 3565d4550907SJerome Glisse if (r) 3566d4550907SJerome Glisse return r; 3567d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) { 3568d4550907SJerome Glisse r = r100_pci_gart_init(rdev); 3569d4550907SJerome Glisse if (r) 3570d4550907SJerome Glisse return r; 3571d4550907SJerome Glisse } 3572d4550907SJerome Glisse r100_set_safe_registers(rdev); 3573d4550907SJerome Glisse rdev->accel_working = true; 3574d4550907SJerome Glisse r = r100_startup(rdev); 3575d4550907SJerome Glisse if (r) { 3576d4550907SJerome Glisse /* Somethings want wront with the accel init stop accel */ 3577d4550907SJerome Glisse dev_err(rdev->dev, "Disabling GPU acceleration\n"); 3578d4550907SJerome Glisse r100_cp_fini(rdev); 3579d4550907SJerome Glisse r100_wb_fini(rdev); 3580d4550907SJerome Glisse r100_ib_fini(rdev); 3581655efd3dSJerome Glisse radeon_irq_kms_fini(rdev); 3582d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 3583d4550907SJerome Glisse r100_pci_gart_fini(rdev); 3584d4550907SJerome Glisse rdev->accel_working = false; 3585d4550907SJerome Glisse } 3586d4550907SJerome Glisse return 0; 3587d4550907SJerome Glisse } 3588