1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2008 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * Copyright 2009 Jerome Glisse. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Authors: Dave Airlie 25771fe6b9SJerome Glisse * Alex Deucher 26771fe6b9SJerome Glisse * Jerome Glisse 27771fe6b9SJerome Glisse */ 28c182615fSSam Ravnborg 2970967ab9SBen Hutchings #include <linux/firmware.h> 30e0cd3608SPaul Gortmaker #include <linux/module.h> 312ef79416SThomas Zimmermann #include <linux/pci.h> 322ef79416SThomas Zimmermann #include <linux/seq_file.h> 332ef79416SThomas Zimmermann #include <linux/slab.h> 3470967ab9SBen Hutchings 35c182615fSSam Ravnborg #include <drm/drm_device.h> 36c182615fSSam Ravnborg #include <drm/drm_file.h> 37c182615fSSam Ravnborg #include <drm/drm_fourcc.h> 38c182615fSSam Ravnborg #include <drm/drm_vblank.h> 39c182615fSSam Ravnborg #include <drm/radeon_drm.h> 40c182615fSSam Ravnborg 41c182615fSSam Ravnborg #include "atom.h" 42551ebd83SDave Airlie #include "r100_reg_safe.h" 43c182615fSSam Ravnborg #include "r100d.h" 44c182615fSSam Ravnborg #include "radeon.h" 45c182615fSSam Ravnborg #include "radeon_asic.h" 46c182615fSSam Ravnborg #include "radeon_reg.h" 47551ebd83SDave Airlie #include "rn50_reg_safe.h" 48c182615fSSam Ravnborg #include "rs100d.h" 49c182615fSSam Ravnborg #include "rv200d.h" 50c182615fSSam Ravnborg #include "rv250d.h" 51551ebd83SDave Airlie 5270967ab9SBen Hutchings /* Firmware Names */ 5370967ab9SBen Hutchings #define FIRMWARE_R100 "radeon/R100_cp.bin" 5470967ab9SBen Hutchings #define FIRMWARE_R200 "radeon/R200_cp.bin" 5570967ab9SBen Hutchings #define FIRMWARE_R300 "radeon/R300_cp.bin" 5670967ab9SBen Hutchings #define FIRMWARE_R420 "radeon/R420_cp.bin" 5770967ab9SBen Hutchings #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 5870967ab9SBen Hutchings #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 5970967ab9SBen Hutchings #define FIRMWARE_R520 "radeon/R520_cp.bin" 6070967ab9SBen Hutchings 6170967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R100); 6270967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R200); 6370967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R300); 6470967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R420); 6570967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_RS690); 6670967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_RS600); 6770967ab9SBen Hutchings MODULE_FIRMWARE(FIRMWARE_R520); 68771fe6b9SJerome Glisse 69551ebd83SDave Airlie #include "r100_track.h" 70551ebd83SDave Airlie 7148ef779fSAlex Deucher /* This files gather functions specifics to: 7248ef779fSAlex Deucher * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 7348ef779fSAlex Deucher * and others in some cases. 7448ef779fSAlex Deucher */ 7548ef779fSAlex Deucher 762b48b968SAlex Deucher static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) 772b48b968SAlex Deucher { 782b48b968SAlex Deucher if (crtc == 0) { 792b48b968SAlex Deucher if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 802b48b968SAlex Deucher return true; 812b48b968SAlex Deucher else 822b48b968SAlex Deucher return false; 832b48b968SAlex Deucher } else { 842b48b968SAlex Deucher if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 852b48b968SAlex Deucher return true; 862b48b968SAlex Deucher else 872b48b968SAlex Deucher return false; 882b48b968SAlex Deucher } 892b48b968SAlex Deucher } 902b48b968SAlex Deucher 912b48b968SAlex Deucher static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) 922b48b968SAlex Deucher { 932b48b968SAlex Deucher u32 vline1, vline2; 942b48b968SAlex Deucher 952b48b968SAlex Deucher if (crtc == 0) { 962b48b968SAlex Deucher vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 972b48b968SAlex Deucher vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 982b48b968SAlex Deucher } else { 992b48b968SAlex Deucher vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1002b48b968SAlex Deucher vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1012b48b968SAlex Deucher } 1022b48b968SAlex Deucher if (vline1 != vline2) 1032b48b968SAlex Deucher return true; 1042b48b968SAlex Deucher else 1052b48b968SAlex Deucher return false; 1062b48b968SAlex Deucher } 1072b48b968SAlex Deucher 10848ef779fSAlex Deucher /** 10948ef779fSAlex Deucher * r100_wait_for_vblank - vblank wait asic callback. 11048ef779fSAlex Deucher * 11148ef779fSAlex Deucher * @rdev: radeon_device pointer 11248ef779fSAlex Deucher * @crtc: crtc to wait for vblank on 11348ef779fSAlex Deucher * 11448ef779fSAlex Deucher * Wait for vblank on the requested crtc (r1xx-r4xx). 11548ef779fSAlex Deucher */ 1163ae19b75SAlex Deucher void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 1173ae19b75SAlex Deucher { 1182b48b968SAlex Deucher unsigned i = 0; 1193ae19b75SAlex Deucher 12094f768fdSAlex Deucher if (crtc >= rdev->num_crtc) 12194f768fdSAlex Deucher return; 12294f768fdSAlex Deucher 12394f768fdSAlex Deucher if (crtc == 0) { 1242b48b968SAlex Deucher if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) 1252b48b968SAlex Deucher return; 1263ae19b75SAlex Deucher } else { 1272b48b968SAlex Deucher if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) 1282b48b968SAlex Deucher return; 1293ae19b75SAlex Deucher } 1302b48b968SAlex Deucher 1312b48b968SAlex Deucher /* depending on when we hit vblank, we may be close to active; if so, 1322b48b968SAlex Deucher * wait for another frame. 1332b48b968SAlex Deucher */ 1342b48b968SAlex Deucher while (r100_is_in_vblank(rdev, crtc)) { 1352b48b968SAlex Deucher if (i++ % 100 == 0) { 1362b48b968SAlex Deucher if (!r100_is_counter_moving(rdev, crtc)) 1373ae19b75SAlex Deucher break; 1383ae19b75SAlex Deucher } 1393ae19b75SAlex Deucher } 1402b48b968SAlex Deucher 1412b48b968SAlex Deucher while (!r100_is_in_vblank(rdev, crtc)) { 1422b48b968SAlex Deucher if (i++ % 100 == 0) { 1432b48b968SAlex Deucher if (!r100_is_counter_moving(rdev, crtc)) 1442b48b968SAlex Deucher break; 1452b48b968SAlex Deucher } 1463ae19b75SAlex Deucher } 1473ae19b75SAlex Deucher } 1483ae19b75SAlex Deucher 14948ef779fSAlex Deucher /** 15048ef779fSAlex Deucher * r100_page_flip - pageflip callback. 15148ef779fSAlex Deucher * 15248ef779fSAlex Deucher * @rdev: radeon_device pointer 15348ef779fSAlex Deucher * @crtc_id: crtc to cleanup pageflip on 15448ef779fSAlex Deucher * @crtc_base: new address of the crtc (GPU MC address) 1550d8357c2SLee Jones * @async: asynchronous flip 15648ef779fSAlex Deucher * 15748ef779fSAlex Deucher * Does the actual pageflip (r1xx-r4xx). 15848ef779fSAlex Deucher * During vblank we take the crtc lock and wait for the update_pending 15948ef779fSAlex Deucher * bit to go high, when it does, we release the lock, and allow the 16048ef779fSAlex Deucher * double buffered update to take place. 16148ef779fSAlex Deucher */ 162c63dd758SMichel Dänzer void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) 1636f34be50SAlex Deucher { 1646f34be50SAlex Deucher struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 1656f34be50SAlex Deucher u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 166f6496479SAlex Deucher int i; 1676f34be50SAlex Deucher 1686f34be50SAlex Deucher /* Lock the graphics update lock */ 1696f34be50SAlex Deucher /* update the scanout addresses */ 1706f34be50SAlex Deucher WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 1716f34be50SAlex Deucher 172acb32506SAlex Deucher /* Wait for update_pending to go high. */ 173f6496479SAlex Deucher for (i = 0; i < rdev->usec_timeout; i++) { 174f6496479SAlex Deucher if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 175f6496479SAlex Deucher break; 176f6496479SAlex Deucher udelay(1); 177f6496479SAlex Deucher } 178acb32506SAlex Deucher DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 1796f34be50SAlex Deucher 1806f34be50SAlex Deucher /* Unlock the lock, so double-buffering can take place inside vblank */ 1816f34be50SAlex Deucher tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 1826f34be50SAlex Deucher WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 1836f34be50SAlex Deucher 184157fa14dSChristian König } 185157fa14dSChristian König 186157fa14dSChristian König /** 187157fa14dSChristian König * r100_page_flip_pending - check if page flip is still pending 188157fa14dSChristian König * 189157fa14dSChristian König * @rdev: radeon_device pointer 190157fa14dSChristian König * @crtc_id: crtc to check 191157fa14dSChristian König * 192157fa14dSChristian König * Check if the last pagefilp is still pending (r1xx-r4xx). 193157fa14dSChristian König * Returns the current update pending status. 194157fa14dSChristian König */ 195157fa14dSChristian König bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id) 196157fa14dSChristian König { 197157fa14dSChristian König struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 198157fa14dSChristian König 1996f34be50SAlex Deucher /* Return current update_pending status: */ 200157fa14dSChristian König return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & 201157fa14dSChristian König RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET); 2026f34be50SAlex Deucher } 2036f34be50SAlex Deucher 20448ef779fSAlex Deucher /** 20548ef779fSAlex Deucher * r100_pm_get_dynpm_state - look up dynpm power state callback. 20648ef779fSAlex Deucher * 20748ef779fSAlex Deucher * @rdev: radeon_device pointer 20848ef779fSAlex Deucher * 20948ef779fSAlex Deucher * Look up the optimal power state based on the 21048ef779fSAlex Deucher * current state of the GPU (r1xx-r5xx). 21148ef779fSAlex Deucher * Used for dynpm only. 21248ef779fSAlex Deucher */ 213ce8f5370SAlex Deucher void r100_pm_get_dynpm_state(struct radeon_device *rdev) 214a48b9b4eSAlex Deucher { 215a48b9b4eSAlex Deucher int i; 216ce8f5370SAlex Deucher rdev->pm.dynpm_can_upclock = true; 217ce8f5370SAlex Deucher rdev->pm.dynpm_can_downclock = true; 218a48b9b4eSAlex Deucher 219ce8f5370SAlex Deucher switch (rdev->pm.dynpm_planned_action) { 220ce8f5370SAlex Deucher case DYNPM_ACTION_MINIMUM: 221a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = 0; 222ce8f5370SAlex Deucher rdev->pm.dynpm_can_downclock = false; 223a48b9b4eSAlex Deucher break; 224ce8f5370SAlex Deucher case DYNPM_ACTION_DOWNCLOCK: 225a48b9b4eSAlex Deucher if (rdev->pm.current_power_state_index == 0) { 226a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 227ce8f5370SAlex Deucher rdev->pm.dynpm_can_downclock = false; 228a48b9b4eSAlex Deucher } else { 229a48b9b4eSAlex Deucher if (rdev->pm.active_crtc_count > 1) { 230a48b9b4eSAlex Deucher for (i = 0; i < rdev->pm.num_power_states; i++) { 231d7311171SAlex Deucher if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 232a48b9b4eSAlex Deucher continue; 233a48b9b4eSAlex Deucher else if (i >= rdev->pm.current_power_state_index) { 234a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 235a48b9b4eSAlex Deucher break; 236a48b9b4eSAlex Deucher } else { 237a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = i; 238a48b9b4eSAlex Deucher break; 239a48b9b4eSAlex Deucher } 240a48b9b4eSAlex Deucher } 241a48b9b4eSAlex Deucher } else 242a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = 243a48b9b4eSAlex Deucher rdev->pm.current_power_state_index - 1; 244a48b9b4eSAlex Deucher } 245d7311171SAlex Deucher /* don't use the power state if crtcs are active and no display flag is set */ 246d7311171SAlex Deucher if ((rdev->pm.active_crtc_count > 0) && 247d7311171SAlex Deucher (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 248d7311171SAlex Deucher RADEON_PM_MODE_NO_DISPLAY)) { 249d7311171SAlex Deucher rdev->pm.requested_power_state_index++; 250d7311171SAlex Deucher } 251a48b9b4eSAlex Deucher break; 252ce8f5370SAlex Deucher case DYNPM_ACTION_UPCLOCK: 253a48b9b4eSAlex Deucher if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 254a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 255ce8f5370SAlex Deucher rdev->pm.dynpm_can_upclock = false; 256a48b9b4eSAlex Deucher } else { 257a48b9b4eSAlex Deucher if (rdev->pm.active_crtc_count > 1) { 258a48b9b4eSAlex Deucher for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 259d7311171SAlex Deucher if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 260a48b9b4eSAlex Deucher continue; 261a48b9b4eSAlex Deucher else if (i <= rdev->pm.current_power_state_index) { 262a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 263a48b9b4eSAlex Deucher break; 264a48b9b4eSAlex Deucher } else { 265a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = i; 266a48b9b4eSAlex Deucher break; 267a48b9b4eSAlex Deucher } 268a48b9b4eSAlex Deucher } 269a48b9b4eSAlex Deucher } else 270a48b9b4eSAlex Deucher rdev->pm.requested_power_state_index = 271a48b9b4eSAlex Deucher rdev->pm.current_power_state_index + 1; 272a48b9b4eSAlex Deucher } 273a48b9b4eSAlex Deucher break; 274ce8f5370SAlex Deucher case DYNPM_ACTION_DEFAULT: 27558e21dffSAlex Deucher rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 276ce8f5370SAlex Deucher rdev->pm.dynpm_can_upclock = false; 27758e21dffSAlex Deucher break; 278ce8f5370SAlex Deucher case DYNPM_ACTION_NONE: 279a48b9b4eSAlex Deucher default: 280a48b9b4eSAlex Deucher DRM_ERROR("Requested mode for not defined action\n"); 281a48b9b4eSAlex Deucher return; 282a48b9b4eSAlex Deucher } 283a48b9b4eSAlex Deucher /* only one clock mode per power state */ 284a48b9b4eSAlex Deucher rdev->pm.requested_clock_mode_index = 0; 285a48b9b4eSAlex Deucher 286d9fdaafbSDave Airlie DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 287a48b9b4eSAlex Deucher rdev->pm.power_state[rdev->pm.requested_power_state_index]. 288a48b9b4eSAlex Deucher clock_info[rdev->pm.requested_clock_mode_index].sclk, 289a48b9b4eSAlex Deucher rdev->pm.power_state[rdev->pm.requested_power_state_index]. 290a48b9b4eSAlex Deucher clock_info[rdev->pm.requested_clock_mode_index].mclk, 291a48b9b4eSAlex Deucher rdev->pm.power_state[rdev->pm.requested_power_state_index]. 29279daedc9SAlex Deucher pcie_lanes); 293a48b9b4eSAlex Deucher } 294a48b9b4eSAlex Deucher 29548ef779fSAlex Deucher /** 29648ef779fSAlex Deucher * r100_pm_init_profile - Initialize power profiles callback. 29748ef779fSAlex Deucher * 29848ef779fSAlex Deucher * @rdev: radeon_device pointer 29948ef779fSAlex Deucher * 30048ef779fSAlex Deucher * Initialize the power states used in profile mode 30148ef779fSAlex Deucher * (r1xx-r3xx). 30248ef779fSAlex Deucher * Used for profile mode only. 30348ef779fSAlex Deucher */ 304ce8f5370SAlex Deucher void r100_pm_init_profile(struct radeon_device *rdev) 305bae6b562SAlex Deucher { 306ce8f5370SAlex Deucher /* default */ 307ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 308ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 309ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 310ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 311ce8f5370SAlex Deucher /* low sh */ 312ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 313ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 314ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 315ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 316c9e75b21SAlex Deucher /* mid sh */ 317c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 318c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 319c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 320c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 321ce8f5370SAlex Deucher /* high sh */ 322ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 323ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 324ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 325ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 326ce8f5370SAlex Deucher /* low mh */ 327ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 328ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 329ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 330ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 331c9e75b21SAlex Deucher /* mid mh */ 332c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 333c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 334c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 335c9e75b21SAlex Deucher rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 336ce8f5370SAlex Deucher /* high mh */ 337ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 338ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 339ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 340ce8f5370SAlex Deucher rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 341bae6b562SAlex Deucher } 342bae6b562SAlex Deucher 34348ef779fSAlex Deucher /** 34448ef779fSAlex Deucher * r100_pm_misc - set additional pm hw parameters callback. 34548ef779fSAlex Deucher * 34648ef779fSAlex Deucher * @rdev: radeon_device pointer 34748ef779fSAlex Deucher * 34848ef779fSAlex Deucher * Set non-clock parameters associated with a power state 34948ef779fSAlex Deucher * (voltage, pcie lanes, etc.) (r1xx-r4xx). 35048ef779fSAlex Deucher */ 35149e02b73SAlex Deucher void r100_pm_misc(struct radeon_device *rdev) 35249e02b73SAlex Deucher { 35349e02b73SAlex Deucher int requested_index = rdev->pm.requested_power_state_index; 35449e02b73SAlex Deucher struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 35549e02b73SAlex Deucher struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 35649e02b73SAlex Deucher u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 35749e02b73SAlex Deucher 35849e02b73SAlex Deucher if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 35949e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 36049e02b73SAlex Deucher tmp = RREG32(voltage->gpio.reg); 36149e02b73SAlex Deucher if (voltage->active_high) 36249e02b73SAlex Deucher tmp |= voltage->gpio.mask; 36349e02b73SAlex Deucher else 36449e02b73SAlex Deucher tmp &= ~(voltage->gpio.mask); 36549e02b73SAlex Deucher WREG32(voltage->gpio.reg, tmp); 36649e02b73SAlex Deucher if (voltage->delay) 36749e02b73SAlex Deucher udelay(voltage->delay); 36849e02b73SAlex Deucher } else { 36949e02b73SAlex Deucher tmp = RREG32(voltage->gpio.reg); 37049e02b73SAlex Deucher if (voltage->active_high) 37149e02b73SAlex Deucher tmp &= ~voltage->gpio.mask; 37249e02b73SAlex Deucher else 37349e02b73SAlex Deucher tmp |= voltage->gpio.mask; 37449e02b73SAlex Deucher WREG32(voltage->gpio.reg, tmp); 37549e02b73SAlex Deucher if (voltage->delay) 37649e02b73SAlex Deucher udelay(voltage->delay); 37749e02b73SAlex Deucher } 37849e02b73SAlex Deucher } 37949e02b73SAlex Deucher 38049e02b73SAlex Deucher sclk_cntl = RREG32_PLL(SCLK_CNTL); 38149e02b73SAlex Deucher sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 38249e02b73SAlex Deucher sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 38349e02b73SAlex Deucher sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 38449e02b73SAlex Deucher sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 38549e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 38649e02b73SAlex Deucher sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 38749e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 38849e02b73SAlex Deucher sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 38949e02b73SAlex Deucher else 39049e02b73SAlex Deucher sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 39149e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 39249e02b73SAlex Deucher sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 39349e02b73SAlex Deucher else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 39449e02b73SAlex Deucher sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 39549e02b73SAlex Deucher } else 39649e02b73SAlex Deucher sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 39749e02b73SAlex Deucher 39849e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 39949e02b73SAlex Deucher sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 40049e02b73SAlex Deucher if (voltage->delay) { 40149e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DROP_SYNC; 40249e02b73SAlex Deucher switch (voltage->delay) { 40349e02b73SAlex Deucher case 33: 40449e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 40549e02b73SAlex Deucher break; 40649e02b73SAlex Deucher case 66: 40749e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 40849e02b73SAlex Deucher break; 40949e02b73SAlex Deucher case 99: 41049e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 41149e02b73SAlex Deucher break; 41249e02b73SAlex Deucher case 132: 41349e02b73SAlex Deucher sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 41449e02b73SAlex Deucher break; 41549e02b73SAlex Deucher } 41649e02b73SAlex Deucher } else 41749e02b73SAlex Deucher sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 41849e02b73SAlex Deucher } else 41949e02b73SAlex Deucher sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 42049e02b73SAlex Deucher 42149e02b73SAlex Deucher if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 42249e02b73SAlex Deucher sclk_cntl &= ~FORCE_HDP; 42349e02b73SAlex Deucher else 42449e02b73SAlex Deucher sclk_cntl |= FORCE_HDP; 42549e02b73SAlex Deucher 42649e02b73SAlex Deucher WREG32_PLL(SCLK_CNTL, sclk_cntl); 42749e02b73SAlex Deucher WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 42849e02b73SAlex Deucher WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 42949e02b73SAlex Deucher 43049e02b73SAlex Deucher /* set pcie lanes */ 43149e02b73SAlex Deucher if ((rdev->flags & RADEON_IS_PCIE) && 43249e02b73SAlex Deucher !(rdev->flags & RADEON_IS_IGP) && 433798bcf73SAlex Deucher rdev->asic->pm.set_pcie_lanes && 43449e02b73SAlex Deucher (ps->pcie_lanes != 43549e02b73SAlex Deucher rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 43649e02b73SAlex Deucher radeon_set_pcie_lanes(rdev, 43749e02b73SAlex Deucher ps->pcie_lanes); 438d9fdaafbSDave Airlie DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 43949e02b73SAlex Deucher } 44049e02b73SAlex Deucher } 44149e02b73SAlex Deucher 44248ef779fSAlex Deucher /** 44348ef779fSAlex Deucher * r100_pm_prepare - pre-power state change callback. 44448ef779fSAlex Deucher * 44548ef779fSAlex Deucher * @rdev: radeon_device pointer 44648ef779fSAlex Deucher * 44748ef779fSAlex Deucher * Prepare for a power state change (r1xx-r4xx). 44848ef779fSAlex Deucher */ 44949e02b73SAlex Deucher void r100_pm_prepare(struct radeon_device *rdev) 45049e02b73SAlex Deucher { 45149e02b73SAlex Deucher struct drm_device *ddev = rdev->ddev; 45249e02b73SAlex Deucher struct drm_crtc *crtc; 45349e02b73SAlex Deucher struct radeon_crtc *radeon_crtc; 45449e02b73SAlex Deucher u32 tmp; 45549e02b73SAlex Deucher 45649e02b73SAlex Deucher /* disable any active CRTCs */ 45749e02b73SAlex Deucher list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 45849e02b73SAlex Deucher radeon_crtc = to_radeon_crtc(crtc); 45949e02b73SAlex Deucher if (radeon_crtc->enabled) { 46049e02b73SAlex Deucher if (radeon_crtc->crtc_id) { 46149e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 46249e02b73SAlex Deucher tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 46349e02b73SAlex Deucher WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 46449e02b73SAlex Deucher } else { 46549e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC_GEN_CNTL); 46649e02b73SAlex Deucher tmp |= RADEON_CRTC_DISP_REQ_EN_B; 46749e02b73SAlex Deucher WREG32(RADEON_CRTC_GEN_CNTL, tmp); 46849e02b73SAlex Deucher } 46949e02b73SAlex Deucher } 47049e02b73SAlex Deucher } 47149e02b73SAlex Deucher } 47249e02b73SAlex Deucher 47348ef779fSAlex Deucher /** 47448ef779fSAlex Deucher * r100_pm_finish - post-power state change callback. 47548ef779fSAlex Deucher * 47648ef779fSAlex Deucher * @rdev: radeon_device pointer 47748ef779fSAlex Deucher * 47848ef779fSAlex Deucher * Clean up after a power state change (r1xx-r4xx). 47948ef779fSAlex Deucher */ 48049e02b73SAlex Deucher void r100_pm_finish(struct radeon_device *rdev) 48149e02b73SAlex Deucher { 48249e02b73SAlex Deucher struct drm_device *ddev = rdev->ddev; 48349e02b73SAlex Deucher struct drm_crtc *crtc; 48449e02b73SAlex Deucher struct radeon_crtc *radeon_crtc; 48549e02b73SAlex Deucher u32 tmp; 48649e02b73SAlex Deucher 48749e02b73SAlex Deucher /* enable any active CRTCs */ 48849e02b73SAlex Deucher list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 48949e02b73SAlex Deucher radeon_crtc = to_radeon_crtc(crtc); 49049e02b73SAlex Deucher if (radeon_crtc->enabled) { 49149e02b73SAlex Deucher if (radeon_crtc->crtc_id) { 49249e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 49349e02b73SAlex Deucher tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 49449e02b73SAlex Deucher WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 49549e02b73SAlex Deucher } else { 49649e02b73SAlex Deucher tmp = RREG32(RADEON_CRTC_GEN_CNTL); 49749e02b73SAlex Deucher tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 49849e02b73SAlex Deucher WREG32(RADEON_CRTC_GEN_CNTL, tmp); 49949e02b73SAlex Deucher } 50049e02b73SAlex Deucher } 50149e02b73SAlex Deucher } 50249e02b73SAlex Deucher } 50349e02b73SAlex Deucher 50448ef779fSAlex Deucher /** 50548ef779fSAlex Deucher * r100_gui_idle - gui idle callback. 50648ef779fSAlex Deucher * 50748ef779fSAlex Deucher * @rdev: radeon_device pointer 50848ef779fSAlex Deucher * 50948ef779fSAlex Deucher * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). 51048ef779fSAlex Deucher * Returns true if idle, false if not. 51148ef779fSAlex Deucher */ 512def9ba9cSAlex Deucher bool r100_gui_idle(struct radeon_device *rdev) 513def9ba9cSAlex Deucher { 514def9ba9cSAlex Deucher if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 515def9ba9cSAlex Deucher return false; 516def9ba9cSAlex Deucher else 517def9ba9cSAlex Deucher return true; 518def9ba9cSAlex Deucher } 519def9ba9cSAlex Deucher 52005a05c50SAlex Deucher /* hpd for digital panel detect/disconnect */ 52148ef779fSAlex Deucher /** 52248ef779fSAlex Deucher * r100_hpd_sense - hpd sense callback. 52348ef779fSAlex Deucher * 52448ef779fSAlex Deucher * @rdev: radeon_device pointer 52548ef779fSAlex Deucher * @hpd: hpd (hotplug detect) pin 52648ef779fSAlex Deucher * 52748ef779fSAlex Deucher * Checks if a digital monitor is connected (r1xx-r4xx). 52848ef779fSAlex Deucher * Returns true if connected, false if not connected. 52948ef779fSAlex Deucher */ 53005a05c50SAlex Deucher bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 53105a05c50SAlex Deucher { 53205a05c50SAlex Deucher bool connected = false; 53305a05c50SAlex Deucher 53405a05c50SAlex Deucher switch (hpd) { 53505a05c50SAlex Deucher case RADEON_HPD_1: 53605a05c50SAlex Deucher if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 53705a05c50SAlex Deucher connected = true; 53805a05c50SAlex Deucher break; 53905a05c50SAlex Deucher case RADEON_HPD_2: 54005a05c50SAlex Deucher if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 54105a05c50SAlex Deucher connected = true; 54205a05c50SAlex Deucher break; 54305a05c50SAlex Deucher default: 54405a05c50SAlex Deucher break; 54505a05c50SAlex Deucher } 54605a05c50SAlex Deucher return connected; 54705a05c50SAlex Deucher } 54805a05c50SAlex Deucher 54948ef779fSAlex Deucher /** 55048ef779fSAlex Deucher * r100_hpd_set_polarity - hpd set polarity callback. 55148ef779fSAlex Deucher * 55248ef779fSAlex Deucher * @rdev: radeon_device pointer 55348ef779fSAlex Deucher * @hpd: hpd (hotplug detect) pin 55448ef779fSAlex Deucher * 55548ef779fSAlex Deucher * Set the polarity of the hpd pin (r1xx-r4xx). 55648ef779fSAlex Deucher */ 55705a05c50SAlex Deucher void r100_hpd_set_polarity(struct radeon_device *rdev, 55805a05c50SAlex Deucher enum radeon_hpd_id hpd) 55905a05c50SAlex Deucher { 56005a05c50SAlex Deucher u32 tmp; 56105a05c50SAlex Deucher bool connected = r100_hpd_sense(rdev, hpd); 56205a05c50SAlex Deucher 56305a05c50SAlex Deucher switch (hpd) { 56405a05c50SAlex Deucher case RADEON_HPD_1: 56505a05c50SAlex Deucher tmp = RREG32(RADEON_FP_GEN_CNTL); 56605a05c50SAlex Deucher if (connected) 56705a05c50SAlex Deucher tmp &= ~RADEON_FP_DETECT_INT_POL; 56805a05c50SAlex Deucher else 56905a05c50SAlex Deucher tmp |= RADEON_FP_DETECT_INT_POL; 57005a05c50SAlex Deucher WREG32(RADEON_FP_GEN_CNTL, tmp); 57105a05c50SAlex Deucher break; 57205a05c50SAlex Deucher case RADEON_HPD_2: 57305a05c50SAlex Deucher tmp = RREG32(RADEON_FP2_GEN_CNTL); 57405a05c50SAlex Deucher if (connected) 57505a05c50SAlex Deucher tmp &= ~RADEON_FP2_DETECT_INT_POL; 57605a05c50SAlex Deucher else 57705a05c50SAlex Deucher tmp |= RADEON_FP2_DETECT_INT_POL; 57805a05c50SAlex Deucher WREG32(RADEON_FP2_GEN_CNTL, tmp); 57905a05c50SAlex Deucher break; 58005a05c50SAlex Deucher default: 58105a05c50SAlex Deucher break; 58205a05c50SAlex Deucher } 58305a05c50SAlex Deucher } 58405a05c50SAlex Deucher 58548ef779fSAlex Deucher /** 58648ef779fSAlex Deucher * r100_hpd_init - hpd setup callback. 58748ef779fSAlex Deucher * 58848ef779fSAlex Deucher * @rdev: radeon_device pointer 58948ef779fSAlex Deucher * 59048ef779fSAlex Deucher * Setup the hpd pins used by the card (r1xx-r4xx). 59148ef779fSAlex Deucher * Set the polarity, and enable the hpd interrupts. 59248ef779fSAlex Deucher */ 59305a05c50SAlex Deucher void r100_hpd_init(struct radeon_device *rdev) 59405a05c50SAlex Deucher { 59505a05c50SAlex Deucher struct drm_device *dev = rdev->ddev; 59605a05c50SAlex Deucher struct drm_connector *connector; 597fb98257aSChristian Koenig unsigned enable = 0; 59805a05c50SAlex Deucher 59905a05c50SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 60005a05c50SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 601b2c0cbd6SNicolai Stange if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 602fb98257aSChristian Koenig enable |= 1 << radeon_connector->hpd.hpd; 60364912e99SAlex Deucher radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 60405a05c50SAlex Deucher } 605fb98257aSChristian Koenig radeon_irq_kms_enable_hpd(rdev, enable); 60605a05c50SAlex Deucher } 60705a05c50SAlex Deucher 60848ef779fSAlex Deucher /** 60948ef779fSAlex Deucher * r100_hpd_fini - hpd tear down callback. 61048ef779fSAlex Deucher * 61148ef779fSAlex Deucher * @rdev: radeon_device pointer 61248ef779fSAlex Deucher * 61348ef779fSAlex Deucher * Tear down the hpd pins used by the card (r1xx-r4xx). 61448ef779fSAlex Deucher * Disable the hpd interrupts. 61548ef779fSAlex Deucher */ 61605a05c50SAlex Deucher void r100_hpd_fini(struct radeon_device *rdev) 61705a05c50SAlex Deucher { 61805a05c50SAlex Deucher struct drm_device *dev = rdev->ddev; 61905a05c50SAlex Deucher struct drm_connector *connector; 620fb98257aSChristian Koenig unsigned disable = 0; 62105a05c50SAlex Deucher 62205a05c50SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 62305a05c50SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 624b2c0cbd6SNicolai Stange if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 625fb98257aSChristian Koenig disable |= 1 << radeon_connector->hpd.hpd; 62605a05c50SAlex Deucher } 627fb98257aSChristian Koenig radeon_irq_kms_disable_hpd(rdev, disable); 62805a05c50SAlex Deucher } 62905a05c50SAlex Deucher 630771fe6b9SJerome Glisse /* 631771fe6b9SJerome Glisse * PCI GART 632771fe6b9SJerome Glisse */ 633771fe6b9SJerome Glisse void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 634771fe6b9SJerome Glisse { 635771fe6b9SJerome Glisse /* TODO: can we do somethings here ? */ 636771fe6b9SJerome Glisse /* It seems hw only cache one entry so we should discard this 637771fe6b9SJerome Glisse * entry otherwise if first GPU GART read hit this entry it 638771fe6b9SJerome Glisse * could end up in wrong address. */ 639771fe6b9SJerome Glisse } 640771fe6b9SJerome Glisse 6414aac0473SJerome Glisse int r100_pci_gart_init(struct radeon_device *rdev) 6424aac0473SJerome Glisse { 6434aac0473SJerome Glisse int r; 6444aac0473SJerome Glisse 645c9a1be96SJerome Glisse if (rdev->gart.ptr) { 646fce7d61bSJoe Perches WARN(1, "R100 PCI GART already initialized\n"); 6474aac0473SJerome Glisse return 0; 6484aac0473SJerome Glisse } 6494aac0473SJerome Glisse /* Initialize common gart structure */ 6504aac0473SJerome Glisse r = radeon_gart_init(rdev); 6514aac0473SJerome Glisse if (r) 6524aac0473SJerome Glisse return r; 6534aac0473SJerome Glisse rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 654c5b3b850SAlex Deucher rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 655cb658906SMichel Dänzer rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 656c5b3b850SAlex Deucher rdev->asic->gart.set_page = &r100_pci_gart_set_page; 6574aac0473SJerome Glisse return radeon_gart_table_ram_alloc(rdev); 6584aac0473SJerome Glisse } 6594aac0473SJerome Glisse 660771fe6b9SJerome Glisse int r100_pci_gart_enable(struct radeon_device *rdev) 661771fe6b9SJerome Glisse { 662771fe6b9SJerome Glisse uint32_t tmp; 663771fe6b9SJerome Glisse 664771fe6b9SJerome Glisse /* discard memory request outside of configured range */ 665771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 666771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp); 667771fe6b9SJerome Glisse /* set address range for PCI address translate */ 668d594e46aSJerome Glisse WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 669d594e46aSJerome Glisse WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 670771fe6b9SJerome Glisse /* set PCI GART page-table base address */ 671771fe6b9SJerome Glisse WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 672771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 673771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp); 674771fe6b9SJerome Glisse r100_pci_gart_tlb_flush(rdev); 67543caf451SMichel Dänzer DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 676fcf4de5aSTormod Volden (unsigned)(rdev->mc.gtt_size >> 20), 677fcf4de5aSTormod Volden (unsigned long long)rdev->gart.table_addr); 678771fe6b9SJerome Glisse rdev->gart.ready = true; 679771fe6b9SJerome Glisse return 0; 680771fe6b9SJerome Glisse } 681771fe6b9SJerome Glisse 682771fe6b9SJerome Glisse void r100_pci_gart_disable(struct radeon_device *rdev) 683771fe6b9SJerome Glisse { 684771fe6b9SJerome Glisse uint32_t tmp; 685771fe6b9SJerome Glisse 686771fe6b9SJerome Glisse /* discard memory request outside of configured range */ 687771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 688771fe6b9SJerome Glisse WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 689771fe6b9SJerome Glisse WREG32(RADEON_AIC_LO_ADDR, 0); 690771fe6b9SJerome Glisse WREG32(RADEON_AIC_HI_ADDR, 0); 691771fe6b9SJerome Glisse } 692771fe6b9SJerome Glisse 693cb658906SMichel Dänzer uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags) 694cb658906SMichel Dänzer { 695cb658906SMichel Dänzer return addr; 696cb658906SMichel Dänzer } 697cb658906SMichel Dänzer 6987f90fc96SChristian König void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 699cb658906SMichel Dänzer uint64_t entry) 700771fe6b9SJerome Glisse { 701c9a1be96SJerome Glisse u32 *gtt = rdev->gart.ptr; 702cb658906SMichel Dänzer gtt[i] = cpu_to_le32(lower_32_bits(entry)); 703771fe6b9SJerome Glisse } 704771fe6b9SJerome Glisse 7054aac0473SJerome Glisse void r100_pci_gart_fini(struct radeon_device *rdev) 706771fe6b9SJerome Glisse { 707f9274562SJerome Glisse radeon_gart_fini(rdev); 708771fe6b9SJerome Glisse r100_pci_gart_disable(rdev); 7094aac0473SJerome Glisse radeon_gart_table_ram_free(rdev); 710771fe6b9SJerome Glisse } 711771fe6b9SJerome Glisse 7127ed220d7SMichel Dänzer int r100_irq_set(struct radeon_device *rdev) 7137ed220d7SMichel Dänzer { 7147ed220d7SMichel Dänzer uint32_t tmp = 0; 7157ed220d7SMichel Dänzer 716003e69f9SJerome Glisse if (!rdev->irq.installed) { 717fce7d61bSJoe Perches WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 718003e69f9SJerome Glisse WREG32(R_000040_GEN_INT_CNTL, 0); 719003e69f9SJerome Glisse return -EINVAL; 720003e69f9SJerome Glisse } 721736fc37fSChristian Koenig if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 7227ed220d7SMichel Dänzer tmp |= RADEON_SW_INT_ENABLE; 7237ed220d7SMichel Dänzer } 7246f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[0] || 725736fc37fSChristian Koenig atomic_read(&rdev->irq.pflip[0])) { 7267ed220d7SMichel Dänzer tmp |= RADEON_CRTC_VBLANK_MASK; 7277ed220d7SMichel Dänzer } 7286f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[1] || 729736fc37fSChristian Koenig atomic_read(&rdev->irq.pflip[1])) { 7307ed220d7SMichel Dänzer tmp |= RADEON_CRTC2_VBLANK_MASK; 7317ed220d7SMichel Dänzer } 73205a05c50SAlex Deucher if (rdev->irq.hpd[0]) { 73305a05c50SAlex Deucher tmp |= RADEON_FP_DETECT_MASK; 73405a05c50SAlex Deucher } 73505a05c50SAlex Deucher if (rdev->irq.hpd[1]) { 73605a05c50SAlex Deucher tmp |= RADEON_FP2_DETECT_MASK; 73705a05c50SAlex Deucher } 7387ed220d7SMichel Dänzer WREG32(RADEON_GEN_INT_CNTL, tmp); 739f957063fSAlex Deucher 740f957063fSAlex Deucher /* read back to post the write */ 741f957063fSAlex Deucher RREG32(RADEON_GEN_INT_CNTL); 742f957063fSAlex Deucher 7437ed220d7SMichel Dänzer return 0; 7447ed220d7SMichel Dänzer } 7457ed220d7SMichel Dänzer 7469f022ddfSJerome Glisse void r100_irq_disable(struct radeon_device *rdev) 7479f022ddfSJerome Glisse { 7489f022ddfSJerome Glisse u32 tmp; 7499f022ddfSJerome Glisse 7509f022ddfSJerome Glisse WREG32(R_000040_GEN_INT_CNTL, 0); 7519f022ddfSJerome Glisse /* Wait and acknowledge irq */ 7529f022ddfSJerome Glisse mdelay(1); 7539f022ddfSJerome Glisse tmp = RREG32(R_000044_GEN_INT_STATUS); 7549f022ddfSJerome Glisse WREG32(R_000044_GEN_INT_STATUS, tmp); 7559f022ddfSJerome Glisse } 7569f022ddfSJerome Glisse 757cbdd4501SAndi Kleen static uint32_t r100_irq_ack(struct radeon_device *rdev) 7587ed220d7SMichel Dänzer { 7597ed220d7SMichel Dänzer uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 76005a05c50SAlex Deucher uint32_t irq_mask = RADEON_SW_INT_TEST | 76105a05c50SAlex Deucher RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 76205a05c50SAlex Deucher RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 7637ed220d7SMichel Dänzer 7647ed220d7SMichel Dänzer if (irqs) { 7657ed220d7SMichel Dänzer WREG32(RADEON_GEN_INT_STATUS, irqs); 7667ed220d7SMichel Dänzer } 7677ed220d7SMichel Dänzer return irqs & irq_mask; 7687ed220d7SMichel Dänzer } 7697ed220d7SMichel Dänzer 7707ed220d7SMichel Dänzer int r100_irq_process(struct radeon_device *rdev) 7717ed220d7SMichel Dänzer { 7723e5cb98dSAlex Deucher uint32_t status, msi_rearm; 773d4877cf2SAlex Deucher bool queue_hotplug = false; 7747ed220d7SMichel Dänzer 7757ed220d7SMichel Dänzer status = r100_irq_ack(rdev); 7767ed220d7SMichel Dänzer if (!status) { 7777ed220d7SMichel Dänzer return IRQ_NONE; 7787ed220d7SMichel Dänzer } 779a513c184SJerome Glisse if (rdev->shutdown) { 780a513c184SJerome Glisse return IRQ_NONE; 781a513c184SJerome Glisse } 7827ed220d7SMichel Dänzer while (status) { 7837ed220d7SMichel Dänzer /* SW interrupt */ 7847ed220d7SMichel Dänzer if (status & RADEON_SW_INT_TEST) { 7857465280cSAlex Deucher radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 7867ed220d7SMichel Dänzer } 7877ed220d7SMichel Dänzer /* Vertical blank interrupts */ 7887ed220d7SMichel Dänzer if (status & RADEON_CRTC_VBLANK_STAT) { 7896f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[0]) { 7907ed220d7SMichel Dänzer drm_handle_vblank(rdev->ddev, 0); 791839461d3SRafał Miłecki rdev->pm.vblank_sync = true; 79273a6d3fcSRafał Miłecki wake_up(&rdev->irq.vblank_queue); 7937ed220d7SMichel Dänzer } 794736fc37fSChristian Koenig if (atomic_read(&rdev->irq.pflip[0])) 7951a0e7918SChristian König radeon_crtc_handle_vblank(rdev, 0); 7966f34be50SAlex Deucher } 7977ed220d7SMichel Dänzer if (status & RADEON_CRTC2_VBLANK_STAT) { 7986f34be50SAlex Deucher if (rdev->irq.crtc_vblank_int[1]) { 7997ed220d7SMichel Dänzer drm_handle_vblank(rdev->ddev, 1); 800839461d3SRafał Miłecki rdev->pm.vblank_sync = true; 80173a6d3fcSRafał Miłecki wake_up(&rdev->irq.vblank_queue); 8027ed220d7SMichel Dänzer } 803736fc37fSChristian Koenig if (atomic_read(&rdev->irq.pflip[1])) 8041a0e7918SChristian König radeon_crtc_handle_vblank(rdev, 1); 8056f34be50SAlex Deucher } 80605a05c50SAlex Deucher if (status & RADEON_FP_DETECT_STAT) { 807d4877cf2SAlex Deucher queue_hotplug = true; 808d4877cf2SAlex Deucher DRM_DEBUG("HPD1\n"); 80905a05c50SAlex Deucher } 81005a05c50SAlex Deucher if (status & RADEON_FP2_DETECT_STAT) { 811d4877cf2SAlex Deucher queue_hotplug = true; 812d4877cf2SAlex Deucher DRM_DEBUG("HPD2\n"); 81305a05c50SAlex Deucher } 8147ed220d7SMichel Dänzer status = r100_irq_ack(rdev); 8157ed220d7SMichel Dänzer } 816d4877cf2SAlex Deucher if (queue_hotplug) 817cb5d4166SLyude schedule_delayed_work(&rdev->hotplug_work, 0); 8183e5cb98dSAlex Deucher if (rdev->msi_enabled) { 8193e5cb98dSAlex Deucher switch (rdev->family) { 8203e5cb98dSAlex Deucher case CHIP_RS400: 8213e5cb98dSAlex Deucher case CHIP_RS480: 8223e5cb98dSAlex Deucher msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 8233e5cb98dSAlex Deucher WREG32(RADEON_AIC_CNTL, msi_rearm); 8243e5cb98dSAlex Deucher WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 8253e5cb98dSAlex Deucher break; 8263e5cb98dSAlex Deucher default: 827b7f5b7deSAlex Deucher WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 8283e5cb98dSAlex Deucher break; 8293e5cb98dSAlex Deucher } 8303e5cb98dSAlex Deucher } 8317ed220d7SMichel Dänzer return IRQ_HANDLED; 8327ed220d7SMichel Dänzer } 8337ed220d7SMichel Dänzer 8347ed220d7SMichel Dänzer u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 8357ed220d7SMichel Dänzer { 8367ed220d7SMichel Dänzer if (crtc == 0) 8377ed220d7SMichel Dänzer return RREG32(RADEON_CRTC_CRNT_FRAME); 8387ed220d7SMichel Dänzer else 8397ed220d7SMichel Dänzer return RREG32(RADEON_CRTC2_CRNT_FRAME); 8407ed220d7SMichel Dänzer } 8417ed220d7SMichel Dänzer 842897eba82SMichel Dänzer /** 843897eba82SMichel Dänzer * r100_ring_hdp_flush - flush Host Data Path via the ring buffer 8440d8357c2SLee Jones * @rdev: radeon device structure 8450d8357c2SLee Jones * @ring: ring buffer struct for emitting packets 846897eba82SMichel Dänzer */ 847897eba82SMichel Dänzer static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring) 848897eba82SMichel Dänzer { 849897eba82SMichel Dänzer radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 850897eba82SMichel Dänzer radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 851897eba82SMichel Dänzer RADEON_HDP_READ_BUFFER_INVALIDATE); 852897eba82SMichel Dänzer radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 853897eba82SMichel Dänzer radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 854897eba82SMichel Dänzer } 855897eba82SMichel Dänzer 8569e5b2af7SPauli Nieminen /* Who ever call radeon_fence_emit should call ring_lock and ask 8579e5b2af7SPauli Nieminen * for enough space (today caller are ib schedule and buffer move) */ 858771fe6b9SJerome Glisse void r100_fence_ring_emit(struct radeon_device *rdev, 859771fe6b9SJerome Glisse struct radeon_fence *fence) 860771fe6b9SJerome Glisse { 861e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[fence->ring]; 8627b1f2485SChristian König 8639e5b2af7SPauli Nieminen /* We have to make sure that caches are flushed before 8649e5b2af7SPauli Nieminen * CPU might read something from VRAM. */ 865e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 866e32eb50dSChristian König radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 867e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 868e32eb50dSChristian König radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 869771fe6b9SJerome Glisse /* Wait until IDLE & CLEAN */ 870e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 871e32eb50dSChristian König radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 87272a9987eSMichel Dänzer r100_ring_hdp_flush(rdev, ring); 873771fe6b9SJerome Glisse /* Emit fence sequence & fire IRQ */ 874e32eb50dSChristian König radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 875e32eb50dSChristian König radeon_ring_write(ring, fence->seq); 876e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 877e32eb50dSChristian König radeon_ring_write(ring, RADEON_SW_INT_FIRE); 878771fe6b9SJerome Glisse } 879771fe6b9SJerome Glisse 8801654b817SChristian König bool r100_semaphore_ring_emit(struct radeon_device *rdev, 881e32eb50dSChristian König struct radeon_ring *ring, 88215d3332fSChristian König struct radeon_semaphore *semaphore, 8837b1f2485SChristian König bool emit_wait) 88415d3332fSChristian König { 88515d3332fSChristian König /* Unused on older asics, since we don't have semaphores or multiple rings */ 88615d3332fSChristian König BUG(); 8871654b817SChristian König return false; 88815d3332fSChristian König } 88915d3332fSChristian König 89057d20a43SChristian König struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, 891771fe6b9SJerome Glisse uint64_t src_offset, 892771fe6b9SJerome Glisse uint64_t dst_offset, 893003cefe0SAlex Deucher unsigned num_gpu_pages, 89452791eeeSChristian König struct dma_resv *resv) 895771fe6b9SJerome Glisse { 896e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 89757d20a43SChristian König struct radeon_fence *fence; 898771fe6b9SJerome Glisse uint32_t cur_pages; 899003cefe0SAlex Deucher uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 900771fe6b9SJerome Glisse uint32_t pitch; 901771fe6b9SJerome Glisse uint32_t stride_pixels; 902771fe6b9SJerome Glisse unsigned ndw; 903771fe6b9SJerome Glisse int num_loops; 904771fe6b9SJerome Glisse int r = 0; 905771fe6b9SJerome Glisse 906771fe6b9SJerome Glisse /* radeon limited to 16k stride */ 907771fe6b9SJerome Glisse stride_bytes &= 0x3fff; 908771fe6b9SJerome Glisse /* radeon pitch is /64 */ 909771fe6b9SJerome Glisse pitch = stride_bytes / 64; 910771fe6b9SJerome Glisse stride_pixels = stride_bytes / 4; 911003cefe0SAlex Deucher num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 912771fe6b9SJerome Glisse 913771fe6b9SJerome Glisse /* Ask for enough room for blit + flush + fence */ 914771fe6b9SJerome Glisse ndw = 64 + (10 * num_loops); 915e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, ndw); 916771fe6b9SJerome Glisse if (r) { 917771fe6b9SJerome Glisse DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 91857d20a43SChristian König return ERR_PTR(-EINVAL); 919771fe6b9SJerome Glisse } 920003cefe0SAlex Deucher while (num_gpu_pages > 0) { 921003cefe0SAlex Deucher cur_pages = num_gpu_pages; 922771fe6b9SJerome Glisse if (cur_pages > 8191) { 923771fe6b9SJerome Glisse cur_pages = 8191; 924771fe6b9SJerome Glisse } 925003cefe0SAlex Deucher num_gpu_pages -= cur_pages; 926771fe6b9SJerome Glisse 927771fe6b9SJerome Glisse /* pages are in Y direction - height 928771fe6b9SJerome Glisse page width in X direction - width */ 929e32eb50dSChristian König radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 930e32eb50dSChristian König radeon_ring_write(ring, 931771fe6b9SJerome Glisse RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 932771fe6b9SJerome Glisse RADEON_GMC_DST_PITCH_OFFSET_CNTL | 933771fe6b9SJerome Glisse RADEON_GMC_SRC_CLIPPING | 934771fe6b9SJerome Glisse RADEON_GMC_DST_CLIPPING | 935771fe6b9SJerome Glisse RADEON_GMC_BRUSH_NONE | 936771fe6b9SJerome Glisse (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 937771fe6b9SJerome Glisse RADEON_GMC_SRC_DATATYPE_COLOR | 938771fe6b9SJerome Glisse RADEON_ROP3_S | 939771fe6b9SJerome Glisse RADEON_DP_SRC_SOURCE_MEMORY | 940771fe6b9SJerome Glisse RADEON_GMC_CLR_CMP_CNTL_DIS | 941771fe6b9SJerome Glisse RADEON_GMC_WR_MSK_DIS); 942e32eb50dSChristian König radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 943e32eb50dSChristian König radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 944e32eb50dSChristian König radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 945e32eb50dSChristian König radeon_ring_write(ring, 0); 946e32eb50dSChristian König radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 947e32eb50dSChristian König radeon_ring_write(ring, num_gpu_pages); 948e32eb50dSChristian König radeon_ring_write(ring, num_gpu_pages); 949e32eb50dSChristian König radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 950771fe6b9SJerome Glisse } 951e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 952e32eb50dSChristian König radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 953e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 954e32eb50dSChristian König radeon_ring_write(ring, 955771fe6b9SJerome Glisse RADEON_WAIT_2D_IDLECLEAN | 956771fe6b9SJerome Glisse RADEON_WAIT_HOST_IDLECLEAN | 957771fe6b9SJerome Glisse RADEON_WAIT_DMA_GUI_IDLE); 95857d20a43SChristian König r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); 95957d20a43SChristian König if (r) { 96057d20a43SChristian König radeon_ring_unlock_undo(rdev, ring); 96157d20a43SChristian König return ERR_PTR(r); 962771fe6b9SJerome Glisse } 9631538a9e0SMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false); 96457d20a43SChristian König return fence; 965771fe6b9SJerome Glisse } 966771fe6b9SJerome Glisse 96745600232SJerome Glisse static int r100_cp_wait_for_idle(struct radeon_device *rdev) 96845600232SJerome Glisse { 96945600232SJerome Glisse unsigned i; 97045600232SJerome Glisse u32 tmp; 97145600232SJerome Glisse 97245600232SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 97345600232SJerome Glisse tmp = RREG32(R_000E40_RBBM_STATUS); 97445600232SJerome Glisse if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 97545600232SJerome Glisse return 0; 97645600232SJerome Glisse } 97745600232SJerome Glisse udelay(1); 97845600232SJerome Glisse } 97945600232SJerome Glisse return -1; 98045600232SJerome Glisse } 98145600232SJerome Glisse 982f712812eSAlex Deucher void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 983771fe6b9SJerome Glisse { 984771fe6b9SJerome Glisse int r; 985771fe6b9SJerome Glisse 986e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, 2); 987771fe6b9SJerome Glisse if (r) { 988771fe6b9SJerome Glisse return; 989771fe6b9SJerome Glisse } 990e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 991e32eb50dSChristian König radeon_ring_write(ring, 992771fe6b9SJerome Glisse RADEON_ISYNC_ANY2D_IDLE3D | 993771fe6b9SJerome Glisse RADEON_ISYNC_ANY3D_IDLE2D | 994771fe6b9SJerome Glisse RADEON_ISYNC_WAIT_IDLEGUI | 995771fe6b9SJerome Glisse RADEON_ISYNC_CPSCRATCH_IDLEGUI); 9961538a9e0SMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false); 997771fe6b9SJerome Glisse } 998771fe6b9SJerome Glisse 99970967ab9SBen Hutchings 100070967ab9SBen Hutchings /* Load the microcode for the CP */ 100170967ab9SBen Hutchings static int r100_cp_init_microcode(struct radeon_device *rdev) 1002771fe6b9SJerome Glisse { 100370967ab9SBen Hutchings const char *fw_name = NULL; 100470967ab9SBen Hutchings int err; 1005771fe6b9SJerome Glisse 1006d9fdaafbSDave Airlie DRM_DEBUG_KMS("\n"); 100770967ab9SBen Hutchings 1008771fe6b9SJerome Glisse if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 1009771fe6b9SJerome Glisse (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 1010771fe6b9SJerome Glisse (rdev->family == CHIP_RS200)) { 1011771fe6b9SJerome Glisse DRM_INFO("Loading R100 Microcode\n"); 101270967ab9SBen Hutchings fw_name = FIRMWARE_R100; 1013771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_R200) || 1014771fe6b9SJerome Glisse (rdev->family == CHIP_RV250) || 1015771fe6b9SJerome Glisse (rdev->family == CHIP_RV280) || 1016771fe6b9SJerome Glisse (rdev->family == CHIP_RS300)) { 1017771fe6b9SJerome Glisse DRM_INFO("Loading R200 Microcode\n"); 101870967ab9SBen Hutchings fw_name = FIRMWARE_R200; 1019771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_R300) || 1020771fe6b9SJerome Glisse (rdev->family == CHIP_R350) || 1021771fe6b9SJerome Glisse (rdev->family == CHIP_RV350) || 1022771fe6b9SJerome Glisse (rdev->family == CHIP_RV380) || 1023771fe6b9SJerome Glisse (rdev->family == CHIP_RS400) || 1024771fe6b9SJerome Glisse (rdev->family == CHIP_RS480)) { 1025771fe6b9SJerome Glisse DRM_INFO("Loading R300 Microcode\n"); 102670967ab9SBen Hutchings fw_name = FIRMWARE_R300; 1027771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_R420) || 1028771fe6b9SJerome Glisse (rdev->family == CHIP_R423) || 1029771fe6b9SJerome Glisse (rdev->family == CHIP_RV410)) { 1030771fe6b9SJerome Glisse DRM_INFO("Loading R400 Microcode\n"); 103170967ab9SBen Hutchings fw_name = FIRMWARE_R420; 1032771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_RS690) || 1033771fe6b9SJerome Glisse (rdev->family == CHIP_RS740)) { 1034771fe6b9SJerome Glisse DRM_INFO("Loading RS690/RS740 Microcode\n"); 103570967ab9SBen Hutchings fw_name = FIRMWARE_RS690; 1036771fe6b9SJerome Glisse } else if (rdev->family == CHIP_RS600) { 1037771fe6b9SJerome Glisse DRM_INFO("Loading RS600 Microcode\n"); 103870967ab9SBen Hutchings fw_name = FIRMWARE_RS600; 1039771fe6b9SJerome Glisse } else if ((rdev->family == CHIP_RV515) || 1040771fe6b9SJerome Glisse (rdev->family == CHIP_R520) || 1041771fe6b9SJerome Glisse (rdev->family == CHIP_RV530) || 1042771fe6b9SJerome Glisse (rdev->family == CHIP_R580) || 1043771fe6b9SJerome Glisse (rdev->family == CHIP_RV560) || 1044771fe6b9SJerome Glisse (rdev->family == CHIP_RV570)) { 1045771fe6b9SJerome Glisse DRM_INFO("Loading R500 Microcode\n"); 104670967ab9SBen Hutchings fw_name = FIRMWARE_R520; 104770967ab9SBen Hutchings } 104870967ab9SBen Hutchings 10490a168933SJerome Glisse err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 105070967ab9SBen Hutchings if (err) { 10517ca85295SJoe Perches pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name); 10523ce0a23dSJerome Glisse } else if (rdev->me_fw->size % 8) { 10537ca85295SJoe Perches pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n", 10543ce0a23dSJerome Glisse rdev->me_fw->size, fw_name); 105570967ab9SBen Hutchings err = -EINVAL; 10563ce0a23dSJerome Glisse release_firmware(rdev->me_fw); 10573ce0a23dSJerome Glisse rdev->me_fw = NULL; 105870967ab9SBen Hutchings } 105970967ab9SBen Hutchings return err; 106070967ab9SBen Hutchings } 1061d4550907SJerome Glisse 1062ea31bf69SAlex Deucher u32 r100_gfx_get_rptr(struct radeon_device *rdev, 1063ea31bf69SAlex Deucher struct radeon_ring *ring) 1064ea31bf69SAlex Deucher { 1065ea31bf69SAlex Deucher u32 rptr; 1066ea31bf69SAlex Deucher 1067ea31bf69SAlex Deucher if (rdev->wb.enabled) 1068ea31bf69SAlex Deucher rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 1069ea31bf69SAlex Deucher else 1070ea31bf69SAlex Deucher rptr = RREG32(RADEON_CP_RB_RPTR); 1071ea31bf69SAlex Deucher 1072ea31bf69SAlex Deucher return rptr; 1073ea31bf69SAlex Deucher } 1074ea31bf69SAlex Deucher 1075ea31bf69SAlex Deucher u32 r100_gfx_get_wptr(struct radeon_device *rdev, 1076ea31bf69SAlex Deucher struct radeon_ring *ring) 1077ea31bf69SAlex Deucher { 10780003b8d2SMasahiro Yamada return RREG32(RADEON_CP_RB_WPTR); 1079ea31bf69SAlex Deucher } 1080ea31bf69SAlex Deucher 1081ea31bf69SAlex Deucher void r100_gfx_set_wptr(struct radeon_device *rdev, 1082ea31bf69SAlex Deucher struct radeon_ring *ring) 1083ea31bf69SAlex Deucher { 1084ea31bf69SAlex Deucher WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1085ea31bf69SAlex Deucher (void)RREG32(RADEON_CP_RB_WPTR); 1086ea31bf69SAlex Deucher } 1087ea31bf69SAlex Deucher 108870967ab9SBen Hutchings static void r100_cp_load_microcode(struct radeon_device *rdev) 108970967ab9SBen Hutchings { 109070967ab9SBen Hutchings const __be32 *fw_data; 109170967ab9SBen Hutchings int i, size; 109270967ab9SBen Hutchings 109370967ab9SBen Hutchings if (r100_gui_wait_for_idle(rdev)) { 10947ca85295SJoe Perches pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 109570967ab9SBen Hutchings } 109670967ab9SBen Hutchings 10973ce0a23dSJerome Glisse if (rdev->me_fw) { 10983ce0a23dSJerome Glisse size = rdev->me_fw->size / 4; 10993ce0a23dSJerome Glisse fw_data = (const __be32 *)&rdev->me_fw->data[0]; 110070967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_ADDR, 0); 110170967ab9SBen Hutchings for (i = 0; i < size; i += 2) { 110270967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_DATAH, 110370967ab9SBen Hutchings be32_to_cpup(&fw_data[i])); 110470967ab9SBen Hutchings WREG32(RADEON_CP_ME_RAM_DATAL, 110570967ab9SBen Hutchings be32_to_cpup(&fw_data[i + 1])); 1106771fe6b9SJerome Glisse } 1107771fe6b9SJerome Glisse } 1108771fe6b9SJerome Glisse } 1109771fe6b9SJerome Glisse 1110771fe6b9SJerome Glisse int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1111771fe6b9SJerome Glisse { 1112e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1113771fe6b9SJerome Glisse unsigned rb_bufsz; 1114771fe6b9SJerome Glisse unsigned rb_blksz; 1115771fe6b9SJerome Glisse unsigned max_fetch; 1116771fe6b9SJerome Glisse unsigned pre_write_timer; 1117771fe6b9SJerome Glisse unsigned pre_write_limit; 1118771fe6b9SJerome Glisse unsigned indirect2_start; 1119771fe6b9SJerome Glisse unsigned indirect1_start; 1120771fe6b9SJerome Glisse uint32_t tmp; 1121771fe6b9SJerome Glisse int r; 1122771fe6b9SJerome Glisse 11235b54d679SNirmoy Das r100_debugfs_cp_init(rdev); 11243ce0a23dSJerome Glisse if (!rdev->me_fw) { 112570967ab9SBen Hutchings r = r100_cp_init_microcode(rdev); 112670967ab9SBen Hutchings if (r) { 112770967ab9SBen Hutchings DRM_ERROR("Failed to load firmware!\n"); 112870967ab9SBen Hutchings return r; 112970967ab9SBen Hutchings } 113070967ab9SBen Hutchings } 113170967ab9SBen Hutchings 1132771fe6b9SJerome Glisse /* Align ring size */ 1133b72a8925SDaniel Vetter rb_bufsz = order_base_2(ring_size / 8); 1134771fe6b9SJerome Glisse ring_size = (1 << (rb_bufsz + 1)) * 4; 1135771fe6b9SJerome Glisse r100_cp_load_microcode(rdev); 1136e32eb50dSChristian König r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 11372e1e6dadSChristian König RADEON_CP_PACKET2); 1138771fe6b9SJerome Glisse if (r) { 1139771fe6b9SJerome Glisse return r; 1140771fe6b9SJerome Glisse } 1141771fe6b9SJerome Glisse /* Each time the cp read 1024 bytes (16 dword/quadword) update 1142771fe6b9SJerome Glisse * the rptr copy in system ram */ 1143771fe6b9SJerome Glisse rb_blksz = 9; 1144771fe6b9SJerome Glisse /* cp will read 128bytes at a time (4 dwords) */ 1145771fe6b9SJerome Glisse max_fetch = 1; 1146e32eb50dSChristian König ring->align_mask = 16 - 1; 1147771fe6b9SJerome Glisse /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1148771fe6b9SJerome Glisse pre_write_timer = 64; 1149771fe6b9SJerome Glisse /* Force CP_RB_WPTR write if written more than one time before the 1150771fe6b9SJerome Glisse * delay expire 1151771fe6b9SJerome Glisse */ 1152771fe6b9SJerome Glisse pre_write_limit = 0; 1153771fe6b9SJerome Glisse /* Setup the cp cache like this (cache size is 96 dwords) : 1154771fe6b9SJerome Glisse * RING 0 to 15 1155771fe6b9SJerome Glisse * INDIRECT1 16 to 79 1156771fe6b9SJerome Glisse * INDIRECT2 80 to 95 1157771fe6b9SJerome Glisse * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1158771fe6b9SJerome Glisse * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1159771fe6b9SJerome Glisse * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1160771fe6b9SJerome Glisse * Idea being that most of the gpu cmd will be through indirect1 buffer 1161771fe6b9SJerome Glisse * so it gets the bigger cache. 1162771fe6b9SJerome Glisse */ 1163771fe6b9SJerome Glisse indirect2_start = 80; 1164771fe6b9SJerome Glisse indirect1_start = 16; 1165771fe6b9SJerome Glisse /* cp setup */ 1166771fe6b9SJerome Glisse WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1167d6f28938SAlex Deucher tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1168771fe6b9SJerome Glisse REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1169724c80e1SAlex Deucher REG_SET(RADEON_MAX_FETCH, max_fetch)); 1170d6f28938SAlex Deucher #ifdef __BIG_ENDIAN 1171d6f28938SAlex Deucher tmp |= RADEON_BUF_SWAP_32BIT; 1172d6f28938SAlex Deucher #endif 1173724c80e1SAlex Deucher WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1174d6f28938SAlex Deucher 1175771fe6b9SJerome Glisse /* Set ring address */ 1176e32eb50dSChristian König DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1177e32eb50dSChristian König WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1178771fe6b9SJerome Glisse /* Force read & write ptr to 0 */ 1179724c80e1SAlex Deucher WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1180771fe6b9SJerome Glisse WREG32(RADEON_CP_RB_RPTR_WR, 0); 1181e32eb50dSChristian König ring->wptr = 0; 1182e32eb50dSChristian König WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1183724c80e1SAlex Deucher 1184724c80e1SAlex Deucher /* set the wb address whether it's enabled or not */ 1185724c80e1SAlex Deucher WREG32(R_00070C_CP_RB_RPTR_ADDR, 1186724c80e1SAlex Deucher S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1187724c80e1SAlex Deucher WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1188724c80e1SAlex Deucher 1189724c80e1SAlex Deucher if (rdev->wb.enabled) 1190724c80e1SAlex Deucher WREG32(R_000770_SCRATCH_UMSK, 0xff); 1191724c80e1SAlex Deucher else { 1192724c80e1SAlex Deucher tmp |= RADEON_RB_NO_UPDATE; 1193724c80e1SAlex Deucher WREG32(R_000770_SCRATCH_UMSK, 0); 1194724c80e1SAlex Deucher } 1195724c80e1SAlex Deucher 1196771fe6b9SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp); 1197771fe6b9SJerome Glisse udelay(10); 1198771fe6b9SJerome Glisse /* Set cp mode to bus mastering & enable cp*/ 1199771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_MODE, 1200771fe6b9SJerome Glisse REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1201771fe6b9SJerome Glisse REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1202d75ee3beSAlex Deucher WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1203d75ee3beSAlex Deucher WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1204771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 12052099810fSDave Airlie 12062099810fSDave Airlie /* at this point everything should be setup correctly to enable master */ 12072099810fSDave Airlie pci_set_master(rdev->pdev); 12082099810fSDave Airlie 1209f712812eSAlex Deucher radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1210f712812eSAlex Deucher r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1211771fe6b9SJerome Glisse if (r) { 1212771fe6b9SJerome Glisse DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1213771fe6b9SJerome Glisse return r; 1214771fe6b9SJerome Glisse } 1215e32eb50dSChristian König ring->ready = true; 121653595338SDave Airlie radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1217c7eff978SAlex Deucher 121816c58081SSimon Kitching if (!ring->rptr_save_reg /* not resuming from suspend */ 121916c58081SSimon Kitching && radeon_ring_supports_scratch_reg(rdev, ring)) { 1220c7eff978SAlex Deucher r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1221c7eff978SAlex Deucher if (r) { 1222c7eff978SAlex Deucher DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 1223c7eff978SAlex Deucher ring->rptr_save_reg = 0; 1224c7eff978SAlex Deucher } 1225c7eff978SAlex Deucher } 1226771fe6b9SJerome Glisse return 0; 1227771fe6b9SJerome Glisse } 1228771fe6b9SJerome Glisse 1229771fe6b9SJerome Glisse void r100_cp_fini(struct radeon_device *rdev) 1230771fe6b9SJerome Glisse { 123145600232SJerome Glisse if (r100_cp_wait_for_idle(rdev)) { 123245600232SJerome Glisse DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 123345600232SJerome Glisse } 1234771fe6b9SJerome Glisse /* Disable ring */ 1235a18d7ea1SJerome Glisse r100_cp_disable(rdev); 1236c7eff978SAlex Deucher radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); 1237e32eb50dSChristian König radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1238771fe6b9SJerome Glisse DRM_INFO("radeon: cp finalized\n"); 1239771fe6b9SJerome Glisse } 1240771fe6b9SJerome Glisse 1241771fe6b9SJerome Glisse void r100_cp_disable(struct radeon_device *rdev) 1242771fe6b9SJerome Glisse { 1243771fe6b9SJerome Glisse /* Disable ring */ 124453595338SDave Airlie radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1245e32eb50dSChristian König rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1246771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_MODE, 0); 1247771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, 0); 1248724c80e1SAlex Deucher WREG32(R_000770_SCRATCH_UMSK, 0); 1249771fe6b9SJerome Glisse if (r100_gui_wait_for_idle(rdev)) { 12507ca85295SJoe Perches pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 1251771fe6b9SJerome Glisse } 1252771fe6b9SJerome Glisse } 1253771fe6b9SJerome Glisse 1254771fe6b9SJerome Glisse /* 1255771fe6b9SJerome Glisse * CS functions 1256771fe6b9SJerome Glisse */ 12570242f74dSAlex Deucher int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 12580242f74dSAlex Deucher struct radeon_cs_packet *pkt, 12590242f74dSAlex Deucher unsigned idx, 12600242f74dSAlex Deucher unsigned reg) 12610242f74dSAlex Deucher { 12620242f74dSAlex Deucher int r; 12630242f74dSAlex Deucher u32 tile_flags = 0; 12640242f74dSAlex Deucher u32 tmp; 12651d0c0942SChristian König struct radeon_bo_list *reloc; 12660242f74dSAlex Deucher u32 value; 12670242f74dSAlex Deucher 1268012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 12690242f74dSAlex Deucher if (r) { 12700242f74dSAlex Deucher DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 12710242f74dSAlex Deucher idx, reg); 1272c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 12730242f74dSAlex Deucher return r; 12740242f74dSAlex Deucher } 12750242f74dSAlex Deucher 12760242f74dSAlex Deucher value = radeon_get_ib_value(p, idx); 12770242f74dSAlex Deucher tmp = value & 0x003fffff; 1278df0af440SChristian König tmp += (((u32)reloc->gpu_offset) >> 10); 12790242f74dSAlex Deucher 12800242f74dSAlex Deucher if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1281df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MACRO) 12820242f74dSAlex Deucher tile_flags |= RADEON_DST_TILE_MACRO; 1283df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MICRO) { 12840242f74dSAlex Deucher if (reg == RADEON_SRC_PITCH_OFFSET) { 12850242f74dSAlex Deucher DRM_ERROR("Cannot src blit from microtiled surface\n"); 1286c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 12870242f74dSAlex Deucher return -EINVAL; 12880242f74dSAlex Deucher } 12890242f74dSAlex Deucher tile_flags |= RADEON_DST_TILE_MICRO; 12900242f74dSAlex Deucher } 12910242f74dSAlex Deucher 12920242f74dSAlex Deucher tmp |= tile_flags; 12930242f74dSAlex Deucher p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 12940242f74dSAlex Deucher } else 12950242f74dSAlex Deucher p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 12960242f74dSAlex Deucher return 0; 12970242f74dSAlex Deucher } 12980242f74dSAlex Deucher 12990242f74dSAlex Deucher int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 13000242f74dSAlex Deucher struct radeon_cs_packet *pkt, 13010242f74dSAlex Deucher int idx) 13020242f74dSAlex Deucher { 13030242f74dSAlex Deucher unsigned c, i; 13041d0c0942SChristian König struct radeon_bo_list *reloc; 13050242f74dSAlex Deucher struct r100_cs_track *track; 13060242f74dSAlex Deucher int r = 0; 13070242f74dSAlex Deucher volatile uint32_t *ib; 13080242f74dSAlex Deucher u32 idx_value; 13090242f74dSAlex Deucher 13100242f74dSAlex Deucher ib = p->ib.ptr; 13110242f74dSAlex Deucher track = (struct r100_cs_track *)p->track; 13120242f74dSAlex Deucher c = radeon_get_ib_value(p, idx++) & 0x1F; 13130242f74dSAlex Deucher if (c > 16) { 13140242f74dSAlex Deucher DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 13150242f74dSAlex Deucher pkt->opcode); 1316c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 13170242f74dSAlex Deucher return -EINVAL; 13180242f74dSAlex Deucher } 13190242f74dSAlex Deucher track->num_arrays = c; 13200242f74dSAlex Deucher for (i = 0; i < (c - 1); i+=2, idx+=3) { 1321012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 13220242f74dSAlex Deucher if (r) { 13230242f74dSAlex Deucher DRM_ERROR("No reloc for packet3 %d\n", 13240242f74dSAlex Deucher pkt->opcode); 1325c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 13260242f74dSAlex Deucher return r; 13270242f74dSAlex Deucher } 13280242f74dSAlex Deucher idx_value = radeon_get_ib_value(p, idx); 1329df0af440SChristian König ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 13300242f74dSAlex Deucher 13310242f74dSAlex Deucher track->arrays[i + 0].esize = idx_value >> 8; 13320242f74dSAlex Deucher track->arrays[i + 0].robj = reloc->robj; 13330242f74dSAlex Deucher track->arrays[i + 0].esize &= 0x7F; 1334012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 13350242f74dSAlex Deucher if (r) { 13360242f74dSAlex Deucher DRM_ERROR("No reloc for packet3 %d\n", 13370242f74dSAlex Deucher pkt->opcode); 1338c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 13390242f74dSAlex Deucher return r; 13400242f74dSAlex Deucher } 1341df0af440SChristian König ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); 13420242f74dSAlex Deucher track->arrays[i + 1].robj = reloc->robj; 13430242f74dSAlex Deucher track->arrays[i + 1].esize = idx_value >> 24; 13440242f74dSAlex Deucher track->arrays[i + 1].esize &= 0x7F; 13450242f74dSAlex Deucher } 13460242f74dSAlex Deucher if (c & 1) { 1347012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 13480242f74dSAlex Deucher if (r) { 13490242f74dSAlex Deucher DRM_ERROR("No reloc for packet3 %d\n", 13500242f74dSAlex Deucher pkt->opcode); 1351c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 13520242f74dSAlex Deucher return r; 13530242f74dSAlex Deucher } 13540242f74dSAlex Deucher idx_value = radeon_get_ib_value(p, idx); 1355df0af440SChristian König ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 13560242f74dSAlex Deucher track->arrays[i + 0].robj = reloc->robj; 13570242f74dSAlex Deucher track->arrays[i + 0].esize = idx_value >> 8; 13580242f74dSAlex Deucher track->arrays[i + 0].esize &= 0x7F; 13590242f74dSAlex Deucher } 13600242f74dSAlex Deucher return r; 13610242f74dSAlex Deucher } 13620242f74dSAlex Deucher 1363771fe6b9SJerome Glisse int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1364771fe6b9SJerome Glisse struct radeon_cs_packet *pkt, 1365068a117cSJerome Glisse const unsigned *auth, unsigned n, 1366771fe6b9SJerome Glisse radeon_packet0_check_t check) 1367771fe6b9SJerome Glisse { 1368771fe6b9SJerome Glisse unsigned reg; 1369771fe6b9SJerome Glisse unsigned i, j, m; 1370771fe6b9SJerome Glisse unsigned idx; 1371771fe6b9SJerome Glisse int r; 1372771fe6b9SJerome Glisse 1373771fe6b9SJerome Glisse idx = pkt->idx + 1; 1374771fe6b9SJerome Glisse reg = pkt->reg; 1375068a117cSJerome Glisse /* Check that register fall into register range 1376068a117cSJerome Glisse * determined by the number of entry (n) in the 1377068a117cSJerome Glisse * safe register bitmap. 1378068a117cSJerome Glisse */ 1379771fe6b9SJerome Glisse if (pkt->one_reg_wr) { 1380771fe6b9SJerome Glisse if ((reg >> 7) > n) { 1381771fe6b9SJerome Glisse return -EINVAL; 1382771fe6b9SJerome Glisse } 1383771fe6b9SJerome Glisse } else { 1384771fe6b9SJerome Glisse if (((reg + (pkt->count << 2)) >> 7) > n) { 1385771fe6b9SJerome Glisse return -EINVAL; 1386771fe6b9SJerome Glisse } 1387771fe6b9SJerome Glisse } 1388771fe6b9SJerome Glisse for (i = 0; i <= pkt->count; i++, idx++) { 1389771fe6b9SJerome Glisse j = (reg >> 7); 1390771fe6b9SJerome Glisse m = 1 << ((reg >> 2) & 31); 1391771fe6b9SJerome Glisse if (auth[j] & m) { 1392771fe6b9SJerome Glisse r = check(p, pkt, idx, reg); 1393771fe6b9SJerome Glisse if (r) { 1394771fe6b9SJerome Glisse return r; 1395771fe6b9SJerome Glisse } 1396771fe6b9SJerome Glisse } 1397771fe6b9SJerome Glisse if (pkt->one_reg_wr) { 1398771fe6b9SJerome Glisse if (!(auth[j] & m)) { 1399771fe6b9SJerome Glisse break; 1400771fe6b9SJerome Glisse } 1401771fe6b9SJerome Glisse } else { 1402771fe6b9SJerome Glisse reg += 4; 1403771fe6b9SJerome Glisse } 1404771fe6b9SJerome Glisse } 1405771fe6b9SJerome Glisse return 0; 1406771fe6b9SJerome Glisse } 1407771fe6b9SJerome Glisse 1408771fe6b9SJerome Glisse /** 1409463e2989SLee Jones * r100_cs_packet_parse_vline() - parse userspace VLINE packet 14100d8357c2SLee Jones * @p: parser structure holding parsing context. 1411531369e6SDave Airlie * 1412531369e6SDave Airlie * Userspace sends a special sequence for VLINE waits. 1413531369e6SDave Airlie * PACKET0 - VLINE_START_END + value 1414531369e6SDave Airlie * PACKET0 - WAIT_UNTIL +_value 1415531369e6SDave Airlie * RELOC (P3) - crtc_id in reloc. 1416531369e6SDave Airlie * 1417531369e6SDave Airlie * This function parses this and relocates the VLINE START END 1418531369e6SDave Airlie * and WAIT UNTIL packets to the correct crtc. 1419531369e6SDave Airlie * It also detects a switched off crtc and nulls out the 1420531369e6SDave Airlie * wait in that case. 1421531369e6SDave Airlie */ 1422531369e6SDave Airlie int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1423531369e6SDave Airlie { 1424531369e6SDave Airlie struct drm_crtc *crtc; 1425531369e6SDave Airlie struct radeon_crtc *radeon_crtc; 1426531369e6SDave Airlie struct radeon_cs_packet p3reloc, waitreloc; 1427531369e6SDave Airlie int crtc_id; 1428531369e6SDave Airlie int r; 1429531369e6SDave Airlie uint32_t header, h_idx, reg; 1430513bcb46SDave Airlie volatile uint32_t *ib; 1431531369e6SDave Airlie 1432f2e39221SJerome Glisse ib = p->ib.ptr; 1433531369e6SDave Airlie 1434531369e6SDave Airlie /* parse the wait until */ 1435c38f34b5SIlija Hadzic r = radeon_cs_packet_parse(p, &waitreloc, p->idx); 1436531369e6SDave Airlie if (r) 1437531369e6SDave Airlie return r; 1438531369e6SDave Airlie 1439531369e6SDave Airlie /* check its a wait until and only 1 count */ 1440531369e6SDave Airlie if (waitreloc.reg != RADEON_WAIT_UNTIL || 1441531369e6SDave Airlie waitreloc.count != 0) { 1442531369e6SDave Airlie DRM_ERROR("vline wait had illegal wait until segment\n"); 1443a3a88a66SPaul Bolle return -EINVAL; 1444531369e6SDave Airlie } 1445531369e6SDave Airlie 1446513bcb46SDave Airlie if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1447531369e6SDave Airlie DRM_ERROR("vline wait had illegal wait until\n"); 1448a3a88a66SPaul Bolle return -EINVAL; 1449531369e6SDave Airlie } 1450531369e6SDave Airlie 1451531369e6SDave Airlie /* jump over the NOP */ 1452c38f34b5SIlija Hadzic r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1453531369e6SDave Airlie if (r) 1454531369e6SDave Airlie return r; 1455531369e6SDave Airlie 1456531369e6SDave Airlie h_idx = p->idx - 2; 145790ebd065SAlex Deucher p->idx += waitreloc.count + 2; 145890ebd065SAlex Deucher p->idx += p3reloc.count + 2; 1459531369e6SDave Airlie 1460513bcb46SDave Airlie header = radeon_get_ib_value(p, h_idx); 1461513bcb46SDave Airlie crtc_id = radeon_get_ib_value(p, h_idx + 5); 14624e872ae2SIlija Hadzic reg = R100_CP_PACKET0_GET_REG(header); 1463418da172SKeith Packard crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id); 1464b957f457SRob Clark if (!crtc) { 1465531369e6SDave Airlie DRM_ERROR("cannot find crtc %d\n", crtc_id); 146610e10d34SVille Syrjälä return -ENOENT; 1467531369e6SDave Airlie } 1468531369e6SDave Airlie radeon_crtc = to_radeon_crtc(crtc); 1469531369e6SDave Airlie crtc_id = radeon_crtc->crtc_id; 1470531369e6SDave Airlie 1471531369e6SDave Airlie if (!crtc->enabled) { 1472531369e6SDave Airlie /* if the CRTC isn't enabled - we need to nop out the wait until */ 1473513bcb46SDave Airlie ib[h_idx + 2] = PACKET2(0); 1474513bcb46SDave Airlie ib[h_idx + 3] = PACKET2(0); 1475531369e6SDave Airlie } else if (crtc_id == 1) { 1476531369e6SDave Airlie switch (reg) { 1477531369e6SDave Airlie case AVIVO_D1MODE_VLINE_START_END: 147890ebd065SAlex Deucher header &= ~R300_CP_PACKET0_REG_MASK; 1479531369e6SDave Airlie header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1480531369e6SDave Airlie break; 1481531369e6SDave Airlie case RADEON_CRTC_GUI_TRIG_VLINE: 148290ebd065SAlex Deucher header &= ~R300_CP_PACKET0_REG_MASK; 1483531369e6SDave Airlie header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1484531369e6SDave Airlie break; 1485531369e6SDave Airlie default: 1486531369e6SDave Airlie DRM_ERROR("unknown crtc reloc\n"); 1487a3a88a66SPaul Bolle return -EINVAL; 1488531369e6SDave Airlie } 1489513bcb46SDave Airlie ib[h_idx] = header; 1490513bcb46SDave Airlie ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1491531369e6SDave Airlie } 1492a3a88a66SPaul Bolle 1493a3a88a66SPaul Bolle return 0; 1494531369e6SDave Airlie } 1495531369e6SDave Airlie 1496551ebd83SDave Airlie static int r100_get_vtx_size(uint32_t vtx_fmt) 1497551ebd83SDave Airlie { 1498551ebd83SDave Airlie int vtx_size; 1499551ebd83SDave Airlie vtx_size = 2; 1500551ebd83SDave Airlie /* ordered according to bits in spec */ 1501551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1502551ebd83SDave Airlie vtx_size++; 1503551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1504551ebd83SDave Airlie vtx_size += 3; 1505551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1506551ebd83SDave Airlie vtx_size++; 1507551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1508551ebd83SDave Airlie vtx_size++; 1509551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1510551ebd83SDave Airlie vtx_size += 3; 1511551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1512551ebd83SDave Airlie vtx_size++; 1513551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1514551ebd83SDave Airlie vtx_size++; 1515551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1516551ebd83SDave Airlie vtx_size += 2; 1517551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1518551ebd83SDave Airlie vtx_size += 2; 1519551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1520551ebd83SDave Airlie vtx_size++; 1521551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1522551ebd83SDave Airlie vtx_size += 2; 1523551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1524551ebd83SDave Airlie vtx_size++; 1525551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1526551ebd83SDave Airlie vtx_size += 2; 1527551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1528551ebd83SDave Airlie vtx_size++; 1529551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1530551ebd83SDave Airlie vtx_size++; 1531551ebd83SDave Airlie /* blend weight */ 1532551ebd83SDave Airlie if (vtx_fmt & (0x7 << 15)) 1533551ebd83SDave Airlie vtx_size += (vtx_fmt >> 15) & 0x7; 1534551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1535551ebd83SDave Airlie vtx_size += 3; 1536551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1537551ebd83SDave Airlie vtx_size += 2; 1538551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1539551ebd83SDave Airlie vtx_size++; 1540551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1541551ebd83SDave Airlie vtx_size++; 1542551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1543551ebd83SDave Airlie vtx_size++; 1544551ebd83SDave Airlie if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1545551ebd83SDave Airlie vtx_size++; 1546551ebd83SDave Airlie return vtx_size; 1547551ebd83SDave Airlie } 1548551ebd83SDave Airlie 1549771fe6b9SJerome Glisse static int r100_packet0_check(struct radeon_cs_parser *p, 1550551ebd83SDave Airlie struct radeon_cs_packet *pkt, 1551551ebd83SDave Airlie unsigned idx, unsigned reg) 1552771fe6b9SJerome Glisse { 15531d0c0942SChristian König struct radeon_bo_list *reloc; 1554551ebd83SDave Airlie struct r100_cs_track *track; 1555771fe6b9SJerome Glisse volatile uint32_t *ib; 1556771fe6b9SJerome Glisse uint32_t tmp; 1557771fe6b9SJerome Glisse int r; 1558551ebd83SDave Airlie int i, face; 1559e024e110SDave Airlie u32 tile_flags = 0; 1560513bcb46SDave Airlie u32 idx_value; 1561771fe6b9SJerome Glisse 1562f2e39221SJerome Glisse ib = p->ib.ptr; 1563551ebd83SDave Airlie track = (struct r100_cs_track *)p->track; 1564551ebd83SDave Airlie 1565513bcb46SDave Airlie idx_value = radeon_get_ib_value(p, idx); 1566513bcb46SDave Airlie 1567771fe6b9SJerome Glisse switch (reg) { 1568531369e6SDave Airlie case RADEON_CRTC_GUI_TRIG_VLINE: 1569531369e6SDave Airlie r = r100_cs_packet_parse_vline(p); 1570531369e6SDave Airlie if (r) { 1571531369e6SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1572531369e6SDave Airlie idx, reg); 1573c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1574531369e6SDave Airlie return r; 1575531369e6SDave Airlie } 1576531369e6SDave Airlie break; 1577771fe6b9SJerome Glisse /* FIXME: only allow PACKET3 blit? easier to check for out of 1578771fe6b9SJerome Glisse * range access */ 1579771fe6b9SJerome Glisse case RADEON_DST_PITCH_OFFSET: 1580771fe6b9SJerome Glisse case RADEON_SRC_PITCH_OFFSET: 1581551ebd83SDave Airlie r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1582551ebd83SDave Airlie if (r) 1583551ebd83SDave Airlie return r; 1584551ebd83SDave Airlie break; 1585551ebd83SDave Airlie case RADEON_RB3D_DEPTHOFFSET: 1586012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1587771fe6b9SJerome Glisse if (r) { 1588771fe6b9SJerome Glisse DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1589771fe6b9SJerome Glisse idx, reg); 1590c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1591771fe6b9SJerome Glisse return r; 1592771fe6b9SJerome Glisse } 1593551ebd83SDave Airlie track->zb.robj = reloc->robj; 1594513bcb46SDave Airlie track->zb.offset = idx_value; 159540b4a759SMarek Olšák track->zb_dirty = true; 1596df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1597771fe6b9SJerome Glisse break; 1598771fe6b9SJerome Glisse case RADEON_RB3D_COLOROFFSET: 1599012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1600551ebd83SDave Airlie if (r) { 1601551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1602551ebd83SDave Airlie idx, reg); 1603c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1604551ebd83SDave Airlie return r; 1605551ebd83SDave Airlie } 1606551ebd83SDave Airlie track->cb[0].robj = reloc->robj; 1607513bcb46SDave Airlie track->cb[0].offset = idx_value; 160840b4a759SMarek Olšák track->cb_dirty = true; 1609df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1610551ebd83SDave Airlie break; 1611771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_0: 1612771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_1: 1613771fe6b9SJerome Glisse case RADEON_PP_TXOFFSET_2: 1614551ebd83SDave Airlie i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1615012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1616771fe6b9SJerome Glisse if (r) { 1617771fe6b9SJerome Glisse DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1618771fe6b9SJerome Glisse idx, reg); 1619c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1620771fe6b9SJerome Glisse return r; 1621771fe6b9SJerome Glisse } 1622f2746f83SAlex Deucher if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1623df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MACRO) 1624f2746f83SAlex Deucher tile_flags |= RADEON_TXO_MACRO_TILE; 1625df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MICRO) 1626f2746f83SAlex Deucher tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1627f2746f83SAlex Deucher 1628f2746f83SAlex Deucher tmp = idx_value & ~(0x7 << 2); 1629f2746f83SAlex Deucher tmp |= tile_flags; 1630df0af440SChristian König ib[idx] = tmp + ((u32)reloc->gpu_offset); 1631f2746f83SAlex Deucher } else 1632df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1633551ebd83SDave Airlie track->textures[i].robj = reloc->robj; 163440b4a759SMarek Olšák track->tex_dirty = true; 1635771fe6b9SJerome Glisse break; 1636551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_0: 1637551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_1: 1638551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_2: 1639551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_3: 1640551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T0_4: 1641551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1642012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1643551ebd83SDave Airlie if (r) { 1644551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1645551ebd83SDave Airlie idx, reg); 1646c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1647551ebd83SDave Airlie return r; 1648551ebd83SDave Airlie } 1649513bcb46SDave Airlie track->textures[0].cube_info[i].offset = idx_value; 1650df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1651551ebd83SDave Airlie track->textures[0].cube_info[i].robj = reloc->robj; 165240b4a759SMarek Olšák track->tex_dirty = true; 1653551ebd83SDave Airlie break; 1654551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_0: 1655551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_1: 1656551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_2: 1657551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_3: 1658551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T1_4: 1659551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1660012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1661551ebd83SDave Airlie if (r) { 1662551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1663551ebd83SDave Airlie idx, reg); 1664c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1665551ebd83SDave Airlie return r; 1666551ebd83SDave Airlie } 1667513bcb46SDave Airlie track->textures[1].cube_info[i].offset = idx_value; 1668df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1669551ebd83SDave Airlie track->textures[1].cube_info[i].robj = reloc->robj; 167040b4a759SMarek Olšák track->tex_dirty = true; 1671551ebd83SDave Airlie break; 1672551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_0: 1673551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_1: 1674551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_2: 1675551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_3: 1676551ebd83SDave Airlie case RADEON_PP_CUBIC_OFFSET_T2_4: 1677551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1678012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1679551ebd83SDave Airlie if (r) { 1680551ebd83SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1681551ebd83SDave Airlie idx, reg); 1682c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1683551ebd83SDave Airlie return r; 1684551ebd83SDave Airlie } 1685513bcb46SDave Airlie track->textures[2].cube_info[i].offset = idx_value; 1686df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1687551ebd83SDave Airlie track->textures[2].cube_info[i].robj = reloc->robj; 168840b4a759SMarek Olšák track->tex_dirty = true; 1689551ebd83SDave Airlie break; 1690551ebd83SDave Airlie case RADEON_RE_WIDTH_HEIGHT: 1691513bcb46SDave Airlie track->maxy = ((idx_value >> 16) & 0x7FF); 169240b4a759SMarek Olšák track->cb_dirty = true; 169340b4a759SMarek Olšák track->zb_dirty = true; 1694551ebd83SDave Airlie break; 1695e024e110SDave Airlie case RADEON_RB3D_COLORPITCH: 1696012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1697e024e110SDave Airlie if (r) { 1698e024e110SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1699e024e110SDave Airlie idx, reg); 1700c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1701e024e110SDave Airlie return r; 1702e024e110SDave Airlie } 1703c9068eb2SAlex Deucher if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1704df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MACRO) 1705e024e110SDave Airlie tile_flags |= RADEON_COLOR_TILE_ENABLE; 1706df0af440SChristian König if (reloc->tiling_flags & RADEON_TILING_MICRO) 1707e024e110SDave Airlie tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1708e024e110SDave Airlie 1709513bcb46SDave Airlie tmp = idx_value & ~(0x7 << 16); 1710e024e110SDave Airlie tmp |= tile_flags; 1711e024e110SDave Airlie ib[idx] = tmp; 1712c9068eb2SAlex Deucher } else 1713c9068eb2SAlex Deucher ib[idx] = idx_value; 1714551ebd83SDave Airlie 1715513bcb46SDave Airlie track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 171640b4a759SMarek Olšák track->cb_dirty = true; 1717551ebd83SDave Airlie break; 1718551ebd83SDave Airlie case RADEON_RB3D_DEPTHPITCH: 1719513bcb46SDave Airlie track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 172040b4a759SMarek Olšák track->zb_dirty = true; 1721551ebd83SDave Airlie break; 1722551ebd83SDave Airlie case RADEON_RB3D_CNTL: 1723513bcb46SDave Airlie switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1724551ebd83SDave Airlie case 7: 1725551ebd83SDave Airlie case 8: 1726551ebd83SDave Airlie case 9: 1727551ebd83SDave Airlie case 11: 1728551ebd83SDave Airlie case 12: 1729551ebd83SDave Airlie track->cb[0].cpp = 1; 1730551ebd83SDave Airlie break; 1731551ebd83SDave Airlie case 3: 1732551ebd83SDave Airlie case 4: 1733551ebd83SDave Airlie case 15: 1734551ebd83SDave Airlie track->cb[0].cpp = 2; 1735551ebd83SDave Airlie break; 1736551ebd83SDave Airlie case 6: 1737551ebd83SDave Airlie track->cb[0].cpp = 4; 1738551ebd83SDave Airlie break; 1739551ebd83SDave Airlie default: 1740551ebd83SDave Airlie DRM_ERROR("Invalid color buffer format (%d) !\n", 1741513bcb46SDave Airlie ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1742551ebd83SDave Airlie return -EINVAL; 1743551ebd83SDave Airlie } 1744513bcb46SDave Airlie track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 174540b4a759SMarek Olšák track->cb_dirty = true; 174640b4a759SMarek Olšák track->zb_dirty = true; 1747551ebd83SDave Airlie break; 1748551ebd83SDave Airlie case RADEON_RB3D_ZSTENCILCNTL: 1749513bcb46SDave Airlie switch (idx_value & 0xf) { 1750551ebd83SDave Airlie case 0: 1751551ebd83SDave Airlie track->zb.cpp = 2; 1752551ebd83SDave Airlie break; 1753551ebd83SDave Airlie case 2: 1754551ebd83SDave Airlie case 3: 1755551ebd83SDave Airlie case 4: 1756551ebd83SDave Airlie case 5: 1757551ebd83SDave Airlie case 9: 1758551ebd83SDave Airlie case 11: 1759551ebd83SDave Airlie track->zb.cpp = 4; 1760551ebd83SDave Airlie break; 1761551ebd83SDave Airlie default: 1762551ebd83SDave Airlie break; 1763551ebd83SDave Airlie } 176440b4a759SMarek Olšák track->zb_dirty = true; 1765e024e110SDave Airlie break; 176617782d99SDave Airlie case RADEON_RB3D_ZPASS_ADDR: 1767012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 176817782d99SDave Airlie if (r) { 176917782d99SDave Airlie DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 177017782d99SDave Airlie idx, reg); 1771c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 177217782d99SDave Airlie return r; 177317782d99SDave Airlie } 1774df0af440SChristian König ib[idx] = idx_value + ((u32)reloc->gpu_offset); 177517782d99SDave Airlie break; 1776551ebd83SDave Airlie case RADEON_PP_CNTL: 1777551ebd83SDave Airlie { 1778513bcb46SDave Airlie uint32_t temp = idx_value >> 4; 1779551ebd83SDave Airlie for (i = 0; i < track->num_texture; i++) 1780551ebd83SDave Airlie track->textures[i].enabled = !!(temp & (1 << i)); 178140b4a759SMarek Olšák track->tex_dirty = true; 1782551ebd83SDave Airlie } 1783551ebd83SDave Airlie break; 1784551ebd83SDave Airlie case RADEON_SE_VF_CNTL: 1785513bcb46SDave Airlie track->vap_vf_cntl = idx_value; 1786551ebd83SDave Airlie break; 1787551ebd83SDave Airlie case RADEON_SE_VTX_FMT: 1788513bcb46SDave Airlie track->vtx_size = r100_get_vtx_size(idx_value); 1789551ebd83SDave Airlie break; 1790551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_0: 1791551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_1: 1792551ebd83SDave Airlie case RADEON_PP_TEX_SIZE_2: 1793551ebd83SDave Airlie i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1794513bcb46SDave Airlie track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1795513bcb46SDave Airlie track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 179640b4a759SMarek Olšák track->tex_dirty = true; 1797551ebd83SDave Airlie break; 1798551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_0: 1799551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_1: 1800551ebd83SDave Airlie case RADEON_PP_TEX_PITCH_2: 1801551ebd83SDave Airlie i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1802513bcb46SDave Airlie track->textures[i].pitch = idx_value + 32; 180340b4a759SMarek Olšák track->tex_dirty = true; 1804551ebd83SDave Airlie break; 1805551ebd83SDave Airlie case RADEON_PP_TXFILTER_0: 1806551ebd83SDave Airlie case RADEON_PP_TXFILTER_1: 1807551ebd83SDave Airlie case RADEON_PP_TXFILTER_2: 1808551ebd83SDave Airlie i = (reg - RADEON_PP_TXFILTER_0) / 24; 1809513bcb46SDave Airlie track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1810551ebd83SDave Airlie >> RADEON_MAX_MIP_LEVEL_SHIFT); 1811513bcb46SDave Airlie tmp = (idx_value >> 23) & 0x7; 1812551ebd83SDave Airlie if (tmp == 2 || tmp == 6) 1813551ebd83SDave Airlie track->textures[i].roundup_w = false; 1814513bcb46SDave Airlie tmp = (idx_value >> 27) & 0x7; 1815551ebd83SDave Airlie if (tmp == 2 || tmp == 6) 1816551ebd83SDave Airlie track->textures[i].roundup_h = false; 181740b4a759SMarek Olšák track->tex_dirty = true; 1818551ebd83SDave Airlie break; 1819551ebd83SDave Airlie case RADEON_PP_TXFORMAT_0: 1820551ebd83SDave Airlie case RADEON_PP_TXFORMAT_1: 1821551ebd83SDave Airlie case RADEON_PP_TXFORMAT_2: 1822551ebd83SDave Airlie i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1823513bcb46SDave Airlie if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 18247bf2f607Szhengbin track->textures[i].use_pitch = true; 1825551ebd83SDave Airlie } else { 18267bf2f607Szhengbin track->textures[i].use_pitch = false; 1827008037d4SAlex Deucher track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT); 1828008037d4SAlex Deucher track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT); 1829551ebd83SDave Airlie } 1830513bcb46SDave Airlie if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1831551ebd83SDave Airlie track->textures[i].tex_coord_type = 2; 1832513bcb46SDave Airlie switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1833551ebd83SDave Airlie case RADEON_TXFORMAT_I8: 1834551ebd83SDave Airlie case RADEON_TXFORMAT_RGB332: 1835551ebd83SDave Airlie case RADEON_TXFORMAT_Y8: 1836551ebd83SDave Airlie track->textures[i].cpp = 1; 1837f9da52d5SRoland Scheidegger track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1838551ebd83SDave Airlie break; 1839551ebd83SDave Airlie case RADEON_TXFORMAT_AI88: 1840551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB1555: 1841551ebd83SDave Airlie case RADEON_TXFORMAT_RGB565: 1842551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB4444: 1843551ebd83SDave Airlie case RADEON_TXFORMAT_VYUY422: 1844551ebd83SDave Airlie case RADEON_TXFORMAT_YVYU422: 1845551ebd83SDave Airlie case RADEON_TXFORMAT_SHADOW16: 1846551ebd83SDave Airlie case RADEON_TXFORMAT_LDUDV655: 1847551ebd83SDave Airlie case RADEON_TXFORMAT_DUDV88: 1848551ebd83SDave Airlie track->textures[i].cpp = 2; 1849f9da52d5SRoland Scheidegger track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1850551ebd83SDave Airlie break; 1851551ebd83SDave Airlie case RADEON_TXFORMAT_ARGB8888: 1852551ebd83SDave Airlie case RADEON_TXFORMAT_RGBA8888: 1853551ebd83SDave Airlie case RADEON_TXFORMAT_SHADOW32: 1854551ebd83SDave Airlie case RADEON_TXFORMAT_LDUDUV8888: 1855551ebd83SDave Airlie track->textures[i].cpp = 4; 1856f9da52d5SRoland Scheidegger track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1857551ebd83SDave Airlie break; 1858d785d78bSDave Airlie case RADEON_TXFORMAT_DXT1: 1859d785d78bSDave Airlie track->textures[i].cpp = 1; 1860d785d78bSDave Airlie track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1861d785d78bSDave Airlie break; 1862d785d78bSDave Airlie case RADEON_TXFORMAT_DXT23: 1863d785d78bSDave Airlie case RADEON_TXFORMAT_DXT45: 1864d785d78bSDave Airlie track->textures[i].cpp = 1; 1865d785d78bSDave Airlie track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1866d785d78bSDave Airlie break; 1867551ebd83SDave Airlie } 1868513bcb46SDave Airlie track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1869513bcb46SDave Airlie track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 187040b4a759SMarek Olšák track->tex_dirty = true; 1871551ebd83SDave Airlie break; 1872551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_0: 1873551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_1: 1874551ebd83SDave Airlie case RADEON_PP_CUBIC_FACES_2: 1875513bcb46SDave Airlie tmp = idx_value; 1876551ebd83SDave Airlie i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1877551ebd83SDave Airlie for (face = 0; face < 4; face++) { 1878551ebd83SDave Airlie track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1879551ebd83SDave Airlie track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1880551ebd83SDave Airlie } 188140b4a759SMarek Olšák track->tex_dirty = true; 1882551ebd83SDave Airlie break; 1883771fe6b9SJerome Glisse default: 18847ca85295SJoe Perches pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); 1885551ebd83SDave Airlie return -EINVAL; 1886771fe6b9SJerome Glisse } 1887771fe6b9SJerome Glisse return 0; 1888771fe6b9SJerome Glisse } 1889771fe6b9SJerome Glisse 1890068a117cSJerome Glisse int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1891068a117cSJerome Glisse struct radeon_cs_packet *pkt, 18924c788679SJerome Glisse struct radeon_bo *robj) 1893068a117cSJerome Glisse { 1894068a117cSJerome Glisse unsigned idx; 1895513bcb46SDave Airlie u32 value; 1896068a117cSJerome Glisse idx = pkt->idx + 1; 1897513bcb46SDave Airlie value = radeon_get_ib_value(p, idx + 2); 18984c788679SJerome Glisse if ((value + 1) > radeon_bo_size(robj)) { 1899068a117cSJerome Glisse DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1900068a117cSJerome Glisse "(need %u have %lu) !\n", 1901513bcb46SDave Airlie value + 1, 19024c788679SJerome Glisse radeon_bo_size(robj)); 1903068a117cSJerome Glisse return -EINVAL; 1904068a117cSJerome Glisse } 1905068a117cSJerome Glisse return 0; 1906068a117cSJerome Glisse } 1907068a117cSJerome Glisse 1908771fe6b9SJerome Glisse static int r100_packet3_check(struct radeon_cs_parser *p, 1909771fe6b9SJerome Glisse struct radeon_cs_packet *pkt) 1910771fe6b9SJerome Glisse { 19111d0c0942SChristian König struct radeon_bo_list *reloc; 1912551ebd83SDave Airlie struct r100_cs_track *track; 1913771fe6b9SJerome Glisse unsigned idx; 1914771fe6b9SJerome Glisse volatile uint32_t *ib; 1915771fe6b9SJerome Glisse int r; 1916771fe6b9SJerome Glisse 1917f2e39221SJerome Glisse ib = p->ib.ptr; 1918771fe6b9SJerome Glisse idx = pkt->idx + 1; 1919551ebd83SDave Airlie track = (struct r100_cs_track *)p->track; 1920771fe6b9SJerome Glisse switch (pkt->opcode) { 1921771fe6b9SJerome Glisse case PACKET3_3D_LOAD_VBPNTR: 1922513bcb46SDave Airlie r = r100_packet3_load_vbpntr(p, pkt, idx); 1923513bcb46SDave Airlie if (r) 1924771fe6b9SJerome Glisse return r; 1925771fe6b9SJerome Glisse break; 1926771fe6b9SJerome Glisse case PACKET3_INDX_BUFFER: 1927012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1928771fe6b9SJerome Glisse if (r) { 1929771fe6b9SJerome Glisse DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1930c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1931771fe6b9SJerome Glisse return r; 1932771fe6b9SJerome Glisse } 1933df0af440SChristian König ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); 1934068a117cSJerome Glisse r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1935068a117cSJerome Glisse if (r) { 1936068a117cSJerome Glisse return r; 1937068a117cSJerome Glisse } 1938771fe6b9SJerome Glisse break; 1939771fe6b9SJerome Glisse case 0x23: 1940771fe6b9SJerome Glisse /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1941012e976dSIlija Hadzic r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1942771fe6b9SJerome Glisse if (r) { 1943771fe6b9SJerome Glisse DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1944c3ad63afSIlija Hadzic radeon_cs_dump_packet(p, pkt); 1945771fe6b9SJerome Glisse return r; 1946771fe6b9SJerome Glisse } 1947df0af440SChristian König ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); 1948551ebd83SDave Airlie track->num_arrays = 1; 1949513bcb46SDave Airlie track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1950551ebd83SDave Airlie 1951551ebd83SDave Airlie track->arrays[0].robj = reloc->robj; 1952551ebd83SDave Airlie track->arrays[0].esize = track->vtx_size; 1953551ebd83SDave Airlie 1954513bcb46SDave Airlie track->max_indx = radeon_get_ib_value(p, idx+1); 1955551ebd83SDave Airlie 1956513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1957551ebd83SDave Airlie track->immd_dwords = pkt->count - 1; 1958551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1959551ebd83SDave Airlie if (r) 1960551ebd83SDave Airlie return r; 1961771fe6b9SJerome Glisse break; 1962771fe6b9SJerome Glisse case PACKET3_3D_DRAW_IMMD: 1963513bcb46SDave Airlie if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1964551ebd83SDave Airlie DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1965551ebd83SDave Airlie return -EINVAL; 1966551ebd83SDave Airlie } 1967cf57fc7aSAlex Deucher track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 1968513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1969551ebd83SDave Airlie track->immd_dwords = pkt->count - 1; 1970551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1971551ebd83SDave Airlie if (r) 1972551ebd83SDave Airlie return r; 1973551ebd83SDave Airlie break; 1974771fe6b9SJerome Glisse /* triggers drawing using in-packet vertex data */ 1975771fe6b9SJerome Glisse case PACKET3_3D_DRAW_IMMD_2: 1976513bcb46SDave Airlie if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1977551ebd83SDave Airlie DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1978551ebd83SDave Airlie return -EINVAL; 1979551ebd83SDave Airlie } 1980513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1981551ebd83SDave Airlie track->immd_dwords = pkt->count; 1982551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1983551ebd83SDave Airlie if (r) 1984551ebd83SDave Airlie return r; 1985551ebd83SDave Airlie break; 1986771fe6b9SJerome Glisse /* triggers drawing using in-packet vertex data */ 1987771fe6b9SJerome Glisse case PACKET3_3D_DRAW_VBUF_2: 1988513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1989551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1990551ebd83SDave Airlie if (r) 1991551ebd83SDave Airlie return r; 1992551ebd83SDave Airlie break; 1993771fe6b9SJerome Glisse /* triggers drawing of vertex buffers setup elsewhere */ 1994771fe6b9SJerome Glisse case PACKET3_3D_DRAW_INDX_2: 1995513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1996551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 1997551ebd83SDave Airlie if (r) 1998551ebd83SDave Airlie return r; 1999551ebd83SDave Airlie break; 2000771fe6b9SJerome Glisse /* triggers drawing using indices to vertex buffer */ 2001771fe6b9SJerome Glisse case PACKET3_3D_DRAW_VBUF: 2002513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2003551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 2004551ebd83SDave Airlie if (r) 2005551ebd83SDave Airlie return r; 2006551ebd83SDave Airlie break; 2007771fe6b9SJerome Glisse /* triggers drawing of vertex buffers setup elsewhere */ 2008771fe6b9SJerome Glisse case PACKET3_3D_DRAW_INDX: 2009513bcb46SDave Airlie track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2010551ebd83SDave Airlie r = r100_cs_track_check(p->rdev, track); 2011551ebd83SDave Airlie if (r) 2012551ebd83SDave Airlie return r; 2013551ebd83SDave Airlie break; 2014771fe6b9SJerome Glisse /* triggers drawing using indices to vertex buffer */ 2015ab9e1f59SDave Airlie case PACKET3_3D_CLEAR_HIZ: 2016ab9e1f59SDave Airlie case PACKET3_3D_CLEAR_ZMASK: 2017ab9e1f59SDave Airlie if (p->rdev->hyperz_filp != p->filp) 2018ab9e1f59SDave Airlie return -EINVAL; 2019ab9e1f59SDave Airlie break; 2020771fe6b9SJerome Glisse case PACKET3_NOP: 2021771fe6b9SJerome Glisse break; 2022771fe6b9SJerome Glisse default: 2023771fe6b9SJerome Glisse DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2024771fe6b9SJerome Glisse return -EINVAL; 2025771fe6b9SJerome Glisse } 2026771fe6b9SJerome Glisse return 0; 2027771fe6b9SJerome Glisse } 2028771fe6b9SJerome Glisse 2029771fe6b9SJerome Glisse int r100_cs_parse(struct radeon_cs_parser *p) 2030771fe6b9SJerome Glisse { 2031771fe6b9SJerome Glisse struct radeon_cs_packet pkt; 20329f022ddfSJerome Glisse struct r100_cs_track *track; 2033771fe6b9SJerome Glisse int r; 2034771fe6b9SJerome Glisse 20359f022ddfSJerome Glisse track = kzalloc(sizeof(*track), GFP_KERNEL); 2036ce067913SDan Carpenter if (!track) 2037ce067913SDan Carpenter return -ENOMEM; 20389f022ddfSJerome Glisse r100_cs_track_clear(p->rdev, track); 20399f022ddfSJerome Glisse p->track = track; 2040771fe6b9SJerome Glisse do { 2041c38f34b5SIlija Hadzic r = radeon_cs_packet_parse(p, &pkt, p->idx); 2042771fe6b9SJerome Glisse if (r) { 2043771fe6b9SJerome Glisse return r; 2044771fe6b9SJerome Glisse } 2045771fe6b9SJerome Glisse p->idx += pkt.count + 2; 2046771fe6b9SJerome Glisse switch (pkt.type) { 20474e872ae2SIlija Hadzic case RADEON_PACKET_TYPE0: 2048551ebd83SDave Airlie if (p->rdev->family >= CHIP_R200) 2049551ebd83SDave Airlie r = r100_cs_parse_packet0(p, &pkt, 2050551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm, 2051551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm_size, 2052551ebd83SDave Airlie &r200_packet0_check); 2053551ebd83SDave Airlie else 2054551ebd83SDave Airlie r = r100_cs_parse_packet0(p, &pkt, 2055551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm, 2056551ebd83SDave Airlie p->rdev->config.r100.reg_safe_bm_size, 2057551ebd83SDave Airlie &r100_packet0_check); 2058771fe6b9SJerome Glisse break; 20594e872ae2SIlija Hadzic case RADEON_PACKET_TYPE2: 2060771fe6b9SJerome Glisse break; 20614e872ae2SIlija Hadzic case RADEON_PACKET_TYPE3: 2062771fe6b9SJerome Glisse r = r100_packet3_check(p, &pkt); 2063771fe6b9SJerome Glisse break; 2064771fe6b9SJerome Glisse default: 2065771fe6b9SJerome Glisse DRM_ERROR("Unknown packet type %d !\n", 2066771fe6b9SJerome Glisse pkt.type); 2067771fe6b9SJerome Glisse return -EINVAL; 2068771fe6b9SJerome Glisse } 206966b3543eSIlija Hadzic if (r) 2070771fe6b9SJerome Glisse return r; 20716d2d13ddSChristian König } while (p->idx < p->chunk_ib->length_dw); 2072771fe6b9SJerome Glisse return 0; 2073771fe6b9SJerome Glisse } 2074771fe6b9SJerome Glisse 20750242f74dSAlex Deucher static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 20760242f74dSAlex Deucher { 20770242f74dSAlex Deucher DRM_ERROR("pitch %d\n", t->pitch); 20780242f74dSAlex Deucher DRM_ERROR("use_pitch %d\n", t->use_pitch); 20790242f74dSAlex Deucher DRM_ERROR("width %d\n", t->width); 20800242f74dSAlex Deucher DRM_ERROR("width_11 %d\n", t->width_11); 20810242f74dSAlex Deucher DRM_ERROR("height %d\n", t->height); 20820242f74dSAlex Deucher DRM_ERROR("height_11 %d\n", t->height_11); 20830242f74dSAlex Deucher DRM_ERROR("num levels %d\n", t->num_levels); 20840242f74dSAlex Deucher DRM_ERROR("depth %d\n", t->txdepth); 20850242f74dSAlex Deucher DRM_ERROR("bpp %d\n", t->cpp); 20860242f74dSAlex Deucher DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 20870242f74dSAlex Deucher DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 20880242f74dSAlex Deucher DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 20890242f74dSAlex Deucher DRM_ERROR("compress format %d\n", t->compress_format); 20900242f74dSAlex Deucher } 20910242f74dSAlex Deucher 20920242f74dSAlex Deucher static int r100_track_compress_size(int compress_format, int w, int h) 20930242f74dSAlex Deucher { 20940242f74dSAlex Deucher int block_width, block_height, block_bytes; 20950242f74dSAlex Deucher int wblocks, hblocks; 20960242f74dSAlex Deucher int min_wblocks; 20970242f74dSAlex Deucher int sz; 20980242f74dSAlex Deucher 20990242f74dSAlex Deucher block_width = 4; 21000242f74dSAlex Deucher block_height = 4; 21010242f74dSAlex Deucher 21020242f74dSAlex Deucher switch (compress_format) { 21030242f74dSAlex Deucher case R100_TRACK_COMP_DXT1: 21040242f74dSAlex Deucher block_bytes = 8; 21050242f74dSAlex Deucher min_wblocks = 4; 21060242f74dSAlex Deucher break; 21070242f74dSAlex Deucher default: 21080242f74dSAlex Deucher case R100_TRACK_COMP_DXT35: 21090242f74dSAlex Deucher block_bytes = 16; 21100242f74dSAlex Deucher min_wblocks = 2; 21110242f74dSAlex Deucher break; 21120242f74dSAlex Deucher } 21130242f74dSAlex Deucher 21140242f74dSAlex Deucher hblocks = (h + block_height - 1) / block_height; 21150242f74dSAlex Deucher wblocks = (w + block_width - 1) / block_width; 21160242f74dSAlex Deucher if (wblocks < min_wblocks) 21170242f74dSAlex Deucher wblocks = min_wblocks; 21180242f74dSAlex Deucher sz = wblocks * hblocks * block_bytes; 21190242f74dSAlex Deucher return sz; 21200242f74dSAlex Deucher } 21210242f74dSAlex Deucher 21220242f74dSAlex Deucher static int r100_cs_track_cube(struct radeon_device *rdev, 21230242f74dSAlex Deucher struct r100_cs_track *track, unsigned idx) 21240242f74dSAlex Deucher { 21250242f74dSAlex Deucher unsigned face, w, h; 21260242f74dSAlex Deucher struct radeon_bo *cube_robj; 21270242f74dSAlex Deucher unsigned long size; 21280242f74dSAlex Deucher unsigned compress_format = track->textures[idx].compress_format; 21290242f74dSAlex Deucher 21300242f74dSAlex Deucher for (face = 0; face < 5; face++) { 21310242f74dSAlex Deucher cube_robj = track->textures[idx].cube_info[face].robj; 21320242f74dSAlex Deucher w = track->textures[idx].cube_info[face].width; 21330242f74dSAlex Deucher h = track->textures[idx].cube_info[face].height; 21340242f74dSAlex Deucher 21350242f74dSAlex Deucher if (compress_format) { 21360242f74dSAlex Deucher size = r100_track_compress_size(compress_format, w, h); 21370242f74dSAlex Deucher } else 21380242f74dSAlex Deucher size = w * h; 21390242f74dSAlex Deucher size *= track->textures[idx].cpp; 21400242f74dSAlex Deucher 21410242f74dSAlex Deucher size += track->textures[idx].cube_info[face].offset; 21420242f74dSAlex Deucher 21430242f74dSAlex Deucher if (size > radeon_bo_size(cube_robj)) { 21440242f74dSAlex Deucher DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 21450242f74dSAlex Deucher size, radeon_bo_size(cube_robj)); 21460242f74dSAlex Deucher r100_cs_track_texture_print(&track->textures[idx]); 21470242f74dSAlex Deucher return -1; 21480242f74dSAlex Deucher } 21490242f74dSAlex Deucher } 21500242f74dSAlex Deucher return 0; 21510242f74dSAlex Deucher } 21520242f74dSAlex Deucher 21530242f74dSAlex Deucher static int r100_cs_track_texture_check(struct radeon_device *rdev, 21540242f74dSAlex Deucher struct r100_cs_track *track) 21550242f74dSAlex Deucher { 21560242f74dSAlex Deucher struct radeon_bo *robj; 21570242f74dSAlex Deucher unsigned long size; 21580242f74dSAlex Deucher unsigned u, i, w, h, d; 21590242f74dSAlex Deucher int ret; 21600242f74dSAlex Deucher 21610242f74dSAlex Deucher for (u = 0; u < track->num_texture; u++) { 21620242f74dSAlex Deucher if (!track->textures[u].enabled) 21630242f74dSAlex Deucher continue; 21640242f74dSAlex Deucher if (track->textures[u].lookup_disable) 21650242f74dSAlex Deucher continue; 21660242f74dSAlex Deucher robj = track->textures[u].robj; 21670242f74dSAlex Deucher if (robj == NULL) { 21680242f74dSAlex Deucher DRM_ERROR("No texture bound to unit %u\n", u); 21690242f74dSAlex Deucher return -EINVAL; 21700242f74dSAlex Deucher } 21710242f74dSAlex Deucher size = 0; 21720242f74dSAlex Deucher for (i = 0; i <= track->textures[u].num_levels; i++) { 21730242f74dSAlex Deucher if (track->textures[u].use_pitch) { 21740242f74dSAlex Deucher if (rdev->family < CHIP_R300) 21750242f74dSAlex Deucher w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 21760242f74dSAlex Deucher else 21770242f74dSAlex Deucher w = track->textures[u].pitch / (1 << i); 21780242f74dSAlex Deucher } else { 21790242f74dSAlex Deucher w = track->textures[u].width; 21800242f74dSAlex Deucher if (rdev->family >= CHIP_RV515) 21810242f74dSAlex Deucher w |= track->textures[u].width_11; 21820242f74dSAlex Deucher w = w / (1 << i); 21830242f74dSAlex Deucher if (track->textures[u].roundup_w) 21840242f74dSAlex Deucher w = roundup_pow_of_two(w); 21850242f74dSAlex Deucher } 21860242f74dSAlex Deucher h = track->textures[u].height; 21870242f74dSAlex Deucher if (rdev->family >= CHIP_RV515) 21880242f74dSAlex Deucher h |= track->textures[u].height_11; 21890242f74dSAlex Deucher h = h / (1 << i); 21900242f74dSAlex Deucher if (track->textures[u].roundup_h) 21910242f74dSAlex Deucher h = roundup_pow_of_two(h); 21920242f74dSAlex Deucher if (track->textures[u].tex_coord_type == 1) { 21930242f74dSAlex Deucher d = (1 << track->textures[u].txdepth) / (1 << i); 21940242f74dSAlex Deucher if (!d) 21950242f74dSAlex Deucher d = 1; 21960242f74dSAlex Deucher } else { 21970242f74dSAlex Deucher d = 1; 21980242f74dSAlex Deucher } 21990242f74dSAlex Deucher if (track->textures[u].compress_format) { 22000242f74dSAlex Deucher 22010242f74dSAlex Deucher size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 22020242f74dSAlex Deucher /* compressed textures are block based */ 22030242f74dSAlex Deucher } else 22040242f74dSAlex Deucher size += w * h * d; 22050242f74dSAlex Deucher } 22060242f74dSAlex Deucher size *= track->textures[u].cpp; 22070242f74dSAlex Deucher 22080242f74dSAlex Deucher switch (track->textures[u].tex_coord_type) { 22090242f74dSAlex Deucher case 0: 22100242f74dSAlex Deucher case 1: 22110242f74dSAlex Deucher break; 22120242f74dSAlex Deucher case 2: 22130242f74dSAlex Deucher if (track->separate_cube) { 22140242f74dSAlex Deucher ret = r100_cs_track_cube(rdev, track, u); 22150242f74dSAlex Deucher if (ret) 22160242f74dSAlex Deucher return ret; 22170242f74dSAlex Deucher } else 22180242f74dSAlex Deucher size *= 6; 22190242f74dSAlex Deucher break; 22200242f74dSAlex Deucher default: 22210242f74dSAlex Deucher DRM_ERROR("Invalid texture coordinate type %u for unit " 22220242f74dSAlex Deucher "%u\n", track->textures[u].tex_coord_type, u); 22230242f74dSAlex Deucher return -EINVAL; 22240242f74dSAlex Deucher } 22250242f74dSAlex Deucher if (size > radeon_bo_size(robj)) { 22260242f74dSAlex Deucher DRM_ERROR("Texture of unit %u needs %lu bytes but is " 22270242f74dSAlex Deucher "%lu\n", u, size, radeon_bo_size(robj)); 22280242f74dSAlex Deucher r100_cs_track_texture_print(&track->textures[u]); 22290242f74dSAlex Deucher return -EINVAL; 22300242f74dSAlex Deucher } 22310242f74dSAlex Deucher } 22320242f74dSAlex Deucher return 0; 22330242f74dSAlex Deucher } 22340242f74dSAlex Deucher 22350242f74dSAlex Deucher int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 22360242f74dSAlex Deucher { 22370242f74dSAlex Deucher unsigned i; 22380242f74dSAlex Deucher unsigned long size; 22390242f74dSAlex Deucher unsigned prim_walk; 22400242f74dSAlex Deucher unsigned nverts; 22410242f74dSAlex Deucher unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 22420242f74dSAlex Deucher 22430242f74dSAlex Deucher if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 22440242f74dSAlex Deucher !track->blend_read_enable) 22450242f74dSAlex Deucher num_cb = 0; 22460242f74dSAlex Deucher 22470242f74dSAlex Deucher for (i = 0; i < num_cb; i++) { 22480242f74dSAlex Deucher if (track->cb[i].robj == NULL) { 22490242f74dSAlex Deucher DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 22500242f74dSAlex Deucher return -EINVAL; 22510242f74dSAlex Deucher } 22520242f74dSAlex Deucher size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 22530242f74dSAlex Deucher size += track->cb[i].offset; 22540242f74dSAlex Deucher if (size > radeon_bo_size(track->cb[i].robj)) { 22550242f74dSAlex Deucher DRM_ERROR("[drm] Buffer too small for color buffer %d " 22560242f74dSAlex Deucher "(need %lu have %lu) !\n", i, size, 22570242f74dSAlex Deucher radeon_bo_size(track->cb[i].robj)); 22580242f74dSAlex Deucher DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 22590242f74dSAlex Deucher i, track->cb[i].pitch, track->cb[i].cpp, 22600242f74dSAlex Deucher track->cb[i].offset, track->maxy); 22610242f74dSAlex Deucher return -EINVAL; 22620242f74dSAlex Deucher } 22630242f74dSAlex Deucher } 22640242f74dSAlex Deucher track->cb_dirty = false; 22650242f74dSAlex Deucher 22660242f74dSAlex Deucher if (track->zb_dirty && track->z_enabled) { 22670242f74dSAlex Deucher if (track->zb.robj == NULL) { 22680242f74dSAlex Deucher DRM_ERROR("[drm] No buffer for z buffer !\n"); 22690242f74dSAlex Deucher return -EINVAL; 22700242f74dSAlex Deucher } 22710242f74dSAlex Deucher size = track->zb.pitch * track->zb.cpp * track->maxy; 22720242f74dSAlex Deucher size += track->zb.offset; 22730242f74dSAlex Deucher if (size > radeon_bo_size(track->zb.robj)) { 22740242f74dSAlex Deucher DRM_ERROR("[drm] Buffer too small for z buffer " 22750242f74dSAlex Deucher "(need %lu have %lu) !\n", size, 22760242f74dSAlex Deucher radeon_bo_size(track->zb.robj)); 22770242f74dSAlex Deucher DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 22780242f74dSAlex Deucher track->zb.pitch, track->zb.cpp, 22790242f74dSAlex Deucher track->zb.offset, track->maxy); 22800242f74dSAlex Deucher return -EINVAL; 22810242f74dSAlex Deucher } 22820242f74dSAlex Deucher } 22830242f74dSAlex Deucher track->zb_dirty = false; 22840242f74dSAlex Deucher 22850242f74dSAlex Deucher if (track->aa_dirty && track->aaresolve) { 22860242f74dSAlex Deucher if (track->aa.robj == NULL) { 22870242f74dSAlex Deucher DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 22880242f74dSAlex Deucher return -EINVAL; 22890242f74dSAlex Deucher } 22900242f74dSAlex Deucher /* I believe the format comes from colorbuffer0. */ 22910242f74dSAlex Deucher size = track->aa.pitch * track->cb[0].cpp * track->maxy; 22920242f74dSAlex Deucher size += track->aa.offset; 22930242f74dSAlex Deucher if (size > radeon_bo_size(track->aa.robj)) { 22940242f74dSAlex Deucher DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 22950242f74dSAlex Deucher "(need %lu have %lu) !\n", i, size, 22960242f74dSAlex Deucher radeon_bo_size(track->aa.robj)); 22970242f74dSAlex Deucher DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 22980242f74dSAlex Deucher i, track->aa.pitch, track->cb[0].cpp, 22990242f74dSAlex Deucher track->aa.offset, track->maxy); 23000242f74dSAlex Deucher return -EINVAL; 23010242f74dSAlex Deucher } 23020242f74dSAlex Deucher } 23030242f74dSAlex Deucher track->aa_dirty = false; 23040242f74dSAlex Deucher 23050242f74dSAlex Deucher prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 23060242f74dSAlex Deucher if (track->vap_vf_cntl & (1 << 14)) { 23070242f74dSAlex Deucher nverts = track->vap_alt_nverts; 23080242f74dSAlex Deucher } else { 23090242f74dSAlex Deucher nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 23100242f74dSAlex Deucher } 23110242f74dSAlex Deucher switch (prim_walk) { 23120242f74dSAlex Deucher case 1: 23130242f74dSAlex Deucher for (i = 0; i < track->num_arrays; i++) { 23140242f74dSAlex Deucher size = track->arrays[i].esize * track->max_indx * 4; 23150242f74dSAlex Deucher if (track->arrays[i].robj == NULL) { 23160242f74dSAlex Deucher DRM_ERROR("(PW %u) Vertex array %u no buffer " 23170242f74dSAlex Deucher "bound\n", prim_walk, i); 23180242f74dSAlex Deucher return -EINVAL; 23190242f74dSAlex Deucher } 23200242f74dSAlex Deucher if (size > radeon_bo_size(track->arrays[i].robj)) { 23210242f74dSAlex Deucher dev_err(rdev->dev, "(PW %u) Vertex array %u " 23220242f74dSAlex Deucher "need %lu dwords have %lu dwords\n", 23230242f74dSAlex Deucher prim_walk, i, size >> 2, 23240242f74dSAlex Deucher radeon_bo_size(track->arrays[i].robj) 23250242f74dSAlex Deucher >> 2); 23260242f74dSAlex Deucher DRM_ERROR("Max indices %u\n", track->max_indx); 23270242f74dSAlex Deucher return -EINVAL; 23280242f74dSAlex Deucher } 23290242f74dSAlex Deucher } 23300242f74dSAlex Deucher break; 23310242f74dSAlex Deucher case 2: 23320242f74dSAlex Deucher for (i = 0; i < track->num_arrays; i++) { 23330242f74dSAlex Deucher size = track->arrays[i].esize * (nverts - 1) * 4; 23340242f74dSAlex Deucher if (track->arrays[i].robj == NULL) { 23350242f74dSAlex Deucher DRM_ERROR("(PW %u) Vertex array %u no buffer " 23360242f74dSAlex Deucher "bound\n", prim_walk, i); 23370242f74dSAlex Deucher return -EINVAL; 23380242f74dSAlex Deucher } 23390242f74dSAlex Deucher if (size > radeon_bo_size(track->arrays[i].robj)) { 23400242f74dSAlex Deucher dev_err(rdev->dev, "(PW %u) Vertex array %u " 23410242f74dSAlex Deucher "need %lu dwords have %lu dwords\n", 23420242f74dSAlex Deucher prim_walk, i, size >> 2, 23430242f74dSAlex Deucher radeon_bo_size(track->arrays[i].robj) 23440242f74dSAlex Deucher >> 2); 23450242f74dSAlex Deucher return -EINVAL; 23460242f74dSAlex Deucher } 23470242f74dSAlex Deucher } 23480242f74dSAlex Deucher break; 23490242f74dSAlex Deucher case 3: 23500242f74dSAlex Deucher size = track->vtx_size * nverts; 23510242f74dSAlex Deucher if (size != track->immd_dwords) { 23520242f74dSAlex Deucher DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 23530242f74dSAlex Deucher track->immd_dwords, size); 23540242f74dSAlex Deucher DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 23550242f74dSAlex Deucher nverts, track->vtx_size); 23560242f74dSAlex Deucher return -EINVAL; 23570242f74dSAlex Deucher } 23580242f74dSAlex Deucher break; 23590242f74dSAlex Deucher default: 23600242f74dSAlex Deucher DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 23610242f74dSAlex Deucher prim_walk); 23620242f74dSAlex Deucher return -EINVAL; 23630242f74dSAlex Deucher } 23640242f74dSAlex Deucher 23650242f74dSAlex Deucher if (track->tex_dirty) { 23660242f74dSAlex Deucher track->tex_dirty = false; 23670242f74dSAlex Deucher return r100_cs_track_texture_check(rdev, track); 23680242f74dSAlex Deucher } 23690242f74dSAlex Deucher return 0; 23700242f74dSAlex Deucher } 23710242f74dSAlex Deucher 23720242f74dSAlex Deucher void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 23730242f74dSAlex Deucher { 23740242f74dSAlex Deucher unsigned i, face; 23750242f74dSAlex Deucher 23760242f74dSAlex Deucher track->cb_dirty = true; 23770242f74dSAlex Deucher track->zb_dirty = true; 23780242f74dSAlex Deucher track->tex_dirty = true; 23790242f74dSAlex Deucher track->aa_dirty = true; 23800242f74dSAlex Deucher 23810242f74dSAlex Deucher if (rdev->family < CHIP_R300) { 23820242f74dSAlex Deucher track->num_cb = 1; 23830242f74dSAlex Deucher if (rdev->family <= CHIP_RS200) 23840242f74dSAlex Deucher track->num_texture = 3; 23850242f74dSAlex Deucher else 23860242f74dSAlex Deucher track->num_texture = 6; 23870242f74dSAlex Deucher track->maxy = 2048; 23887bf2f607Szhengbin track->separate_cube = true; 23890242f74dSAlex Deucher } else { 23900242f74dSAlex Deucher track->num_cb = 4; 23910242f74dSAlex Deucher track->num_texture = 16; 23920242f74dSAlex Deucher track->maxy = 4096; 23937bf2f607Szhengbin track->separate_cube = false; 23940242f74dSAlex Deucher track->aaresolve = false; 23950242f74dSAlex Deucher track->aa.robj = NULL; 23960242f74dSAlex Deucher } 23970242f74dSAlex Deucher 23980242f74dSAlex Deucher for (i = 0; i < track->num_cb; i++) { 23990242f74dSAlex Deucher track->cb[i].robj = NULL; 24000242f74dSAlex Deucher track->cb[i].pitch = 8192; 24010242f74dSAlex Deucher track->cb[i].cpp = 16; 24020242f74dSAlex Deucher track->cb[i].offset = 0; 24030242f74dSAlex Deucher } 24040242f74dSAlex Deucher track->z_enabled = true; 24050242f74dSAlex Deucher track->zb.robj = NULL; 24060242f74dSAlex Deucher track->zb.pitch = 8192; 24070242f74dSAlex Deucher track->zb.cpp = 4; 24080242f74dSAlex Deucher track->zb.offset = 0; 24090242f74dSAlex Deucher track->vtx_size = 0x7F; 24100242f74dSAlex Deucher track->immd_dwords = 0xFFFFFFFFUL; 24110242f74dSAlex Deucher track->num_arrays = 11; 24120242f74dSAlex Deucher track->max_indx = 0x00FFFFFFUL; 24130242f74dSAlex Deucher for (i = 0; i < track->num_arrays; i++) { 24140242f74dSAlex Deucher track->arrays[i].robj = NULL; 24150242f74dSAlex Deucher track->arrays[i].esize = 0x7F; 24160242f74dSAlex Deucher } 24170242f74dSAlex Deucher for (i = 0; i < track->num_texture; i++) { 24180242f74dSAlex Deucher track->textures[i].compress_format = R100_TRACK_COMP_NONE; 24190242f74dSAlex Deucher track->textures[i].pitch = 16536; 24200242f74dSAlex Deucher track->textures[i].width = 16536; 24210242f74dSAlex Deucher track->textures[i].height = 16536; 24220242f74dSAlex Deucher track->textures[i].width_11 = 1 << 11; 24230242f74dSAlex Deucher track->textures[i].height_11 = 1 << 11; 24240242f74dSAlex Deucher track->textures[i].num_levels = 12; 24250242f74dSAlex Deucher if (rdev->family <= CHIP_RS200) { 24260242f74dSAlex Deucher track->textures[i].tex_coord_type = 0; 24270242f74dSAlex Deucher track->textures[i].txdepth = 0; 24280242f74dSAlex Deucher } else { 24290242f74dSAlex Deucher track->textures[i].txdepth = 16; 24300242f74dSAlex Deucher track->textures[i].tex_coord_type = 1; 24310242f74dSAlex Deucher } 24320242f74dSAlex Deucher track->textures[i].cpp = 64; 24330242f74dSAlex Deucher track->textures[i].robj = NULL; 24340242f74dSAlex Deucher /* CS IB emission code makes sure texture unit are disabled */ 24350242f74dSAlex Deucher track->textures[i].enabled = false; 24360242f74dSAlex Deucher track->textures[i].lookup_disable = false; 24370242f74dSAlex Deucher track->textures[i].roundup_w = true; 24380242f74dSAlex Deucher track->textures[i].roundup_h = true; 24390242f74dSAlex Deucher if (track->separate_cube) 24400242f74dSAlex Deucher for (face = 0; face < 5; face++) { 24410242f74dSAlex Deucher track->textures[i].cube_info[face].robj = NULL; 24420242f74dSAlex Deucher track->textures[i].cube_info[face].width = 16536; 24430242f74dSAlex Deucher track->textures[i].cube_info[face].height = 16536; 24440242f74dSAlex Deucher track->textures[i].cube_info[face].offset = 0; 24450242f74dSAlex Deucher } 24460242f74dSAlex Deucher } 24470242f74dSAlex Deucher } 2448771fe6b9SJerome Glisse 2449771fe6b9SJerome Glisse /* 2450771fe6b9SJerome Glisse * Global GPU functions 2451771fe6b9SJerome Glisse */ 24521109ca09SLauri Kasanen static void r100_errata(struct radeon_device *rdev) 2453771fe6b9SJerome Glisse { 2454771fe6b9SJerome Glisse rdev->pll_errata = 0; 2455771fe6b9SJerome Glisse 2456771fe6b9SJerome Glisse if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2457771fe6b9SJerome Glisse rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2458771fe6b9SJerome Glisse } 2459771fe6b9SJerome Glisse 2460771fe6b9SJerome Glisse if (rdev->family == CHIP_RV100 || 2461771fe6b9SJerome Glisse rdev->family == CHIP_RS100 || 2462771fe6b9SJerome Glisse rdev->family == CHIP_RS200) { 2463771fe6b9SJerome Glisse rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2464771fe6b9SJerome Glisse } 2465771fe6b9SJerome Glisse } 2466771fe6b9SJerome Glisse 24671109ca09SLauri Kasanen static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2468771fe6b9SJerome Glisse { 2469771fe6b9SJerome Glisse unsigned i; 2470771fe6b9SJerome Glisse uint32_t tmp; 2471771fe6b9SJerome Glisse 2472771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 2473771fe6b9SJerome Glisse tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2474771fe6b9SJerome Glisse if (tmp >= n) { 2475771fe6b9SJerome Glisse return 0; 2476771fe6b9SJerome Glisse } 24770e1a351dSSam Ravnborg udelay(1); 2478771fe6b9SJerome Glisse } 2479771fe6b9SJerome Glisse return -1; 2480771fe6b9SJerome Glisse } 2481771fe6b9SJerome Glisse 2482771fe6b9SJerome Glisse int r100_gui_wait_for_idle(struct radeon_device *rdev) 2483771fe6b9SJerome Glisse { 2484771fe6b9SJerome Glisse unsigned i; 2485771fe6b9SJerome Glisse uint32_t tmp; 2486771fe6b9SJerome Glisse 2487771fe6b9SJerome Glisse if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 24887ca85295SJoe Perches pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n"); 2489771fe6b9SJerome Glisse } 2490771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 2491771fe6b9SJerome Glisse tmp = RREG32(RADEON_RBBM_STATUS); 24924612dc97SAlex Deucher if (!(tmp & RADEON_RBBM_ACTIVE)) { 2493771fe6b9SJerome Glisse return 0; 2494771fe6b9SJerome Glisse } 24950e1a351dSSam Ravnborg udelay(1); 2496771fe6b9SJerome Glisse } 2497771fe6b9SJerome Glisse return -1; 2498771fe6b9SJerome Glisse } 2499771fe6b9SJerome Glisse 2500771fe6b9SJerome Glisse int r100_mc_wait_for_idle(struct radeon_device *rdev) 2501771fe6b9SJerome Glisse { 2502771fe6b9SJerome Glisse unsigned i; 2503771fe6b9SJerome Glisse uint32_t tmp; 2504771fe6b9SJerome Glisse 2505771fe6b9SJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 2506771fe6b9SJerome Glisse /* read MC_STATUS */ 25074612dc97SAlex Deucher tmp = RREG32(RADEON_MC_STATUS); 25084612dc97SAlex Deucher if (tmp & RADEON_MC_IDLE) { 2509771fe6b9SJerome Glisse return 0; 2510771fe6b9SJerome Glisse } 25110e1a351dSSam Ravnborg udelay(1); 2512771fe6b9SJerome Glisse } 2513771fe6b9SJerome Glisse return -1; 2514771fe6b9SJerome Glisse } 2515771fe6b9SJerome Glisse 2516e32eb50dSChristian König bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2517771fe6b9SJerome Glisse { 2518225758d8SJerome Glisse u32 rbbm_status; 2519771fe6b9SJerome Glisse 2520225758d8SJerome Glisse rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2521225758d8SJerome Glisse if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2522ff212f25SChristian König radeon_ring_lockup_update(rdev, ring); 2523225758d8SJerome Glisse return false; 2524225758d8SJerome Glisse } 2525069211e5SChristian König return radeon_ring_test_lockup(rdev, ring); 2526225758d8SJerome Glisse } 2527225758d8SJerome Glisse 252874da01dcSAlex Deucher /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 252974da01dcSAlex Deucher void r100_enable_bm(struct radeon_device *rdev) 253074da01dcSAlex Deucher { 253174da01dcSAlex Deucher uint32_t tmp; 253274da01dcSAlex Deucher /* Enable bus mastering */ 253374da01dcSAlex Deucher tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 253474da01dcSAlex Deucher WREG32(RADEON_BUS_CNTL, tmp); 253574da01dcSAlex Deucher } 253674da01dcSAlex Deucher 253790aca4d2SJerome Glisse void r100_bm_disable(struct radeon_device *rdev) 253890aca4d2SJerome Glisse { 253990aca4d2SJerome Glisse u32 tmp; 254090aca4d2SJerome Glisse 254190aca4d2SJerome Glisse /* disable bus mastering */ 254290aca4d2SJerome Glisse tmp = RREG32(R_000030_BUS_CNTL); 254390aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2544771fe6b9SJerome Glisse mdelay(1); 254590aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 254690aca4d2SJerome Glisse mdelay(1); 254790aca4d2SJerome Glisse WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 254890aca4d2SJerome Glisse tmp = RREG32(RADEON_BUS_CNTL); 254990aca4d2SJerome Glisse mdelay(1); 2550642ce525SMichel Dänzer pci_clear_master(rdev->pdev); 255190aca4d2SJerome Glisse mdelay(1); 255290aca4d2SJerome Glisse } 255390aca4d2SJerome Glisse 255471fe2899SJérome Glisse int r100_asic_reset(struct radeon_device *rdev, bool hard) 2555771fe6b9SJerome Glisse { 255690aca4d2SJerome Glisse struct r100_mc_save save; 255790aca4d2SJerome Glisse u32 status, tmp; 255825b2ec5bSAlex Deucher int ret = 0; 2559771fe6b9SJerome Glisse 256090aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 256190aca4d2SJerome Glisse if (!G_000E40_GUI_ACTIVE(status)) { 2562771fe6b9SJerome Glisse return 0; 2563771fe6b9SJerome Glisse } 256425b2ec5bSAlex Deucher r100_mc_stop(rdev, &save); 256590aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 256690aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 256790aca4d2SJerome Glisse /* stop CP */ 256890aca4d2SJerome Glisse WREG32(RADEON_CP_CSQ_CNTL, 0); 256990aca4d2SJerome Glisse tmp = RREG32(RADEON_CP_RB_CNTL); 257090aca4d2SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 257190aca4d2SJerome Glisse WREG32(RADEON_CP_RB_RPTR_WR, 0); 257290aca4d2SJerome Glisse WREG32(RADEON_CP_RB_WPTR, 0); 257390aca4d2SJerome Glisse WREG32(RADEON_CP_RB_CNTL, tmp); 257490aca4d2SJerome Glisse /* save PCI state */ 257590aca4d2SJerome Glisse pci_save_state(rdev->pdev); 257690aca4d2SJerome Glisse /* disable bus mastering */ 257790aca4d2SJerome Glisse r100_bm_disable(rdev); 257890aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 257990aca4d2SJerome Glisse S_0000F0_SOFT_RESET_RE(1) | 258090aca4d2SJerome Glisse S_0000F0_SOFT_RESET_PP(1) | 258190aca4d2SJerome Glisse S_0000F0_SOFT_RESET_RB(1)); 258290aca4d2SJerome Glisse RREG32(R_0000F0_RBBM_SOFT_RESET); 258390aca4d2SJerome Glisse mdelay(500); 258490aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 258590aca4d2SJerome Glisse mdelay(1); 258690aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 258790aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2588771fe6b9SJerome Glisse /* reset CP */ 258990aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 259090aca4d2SJerome Glisse RREG32(R_0000F0_RBBM_SOFT_RESET); 259190aca4d2SJerome Glisse mdelay(500); 259290aca4d2SJerome Glisse WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 259390aca4d2SJerome Glisse mdelay(1); 259490aca4d2SJerome Glisse status = RREG32(R_000E40_RBBM_STATUS); 259590aca4d2SJerome Glisse dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 259690aca4d2SJerome Glisse /* restore PCI & busmastering */ 259790aca4d2SJerome Glisse pci_restore_state(rdev->pdev); 259890aca4d2SJerome Glisse r100_enable_bm(rdev); 2599771fe6b9SJerome Glisse /* Check if GPU is idle */ 260090aca4d2SJerome Glisse if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 260190aca4d2SJerome Glisse G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 260290aca4d2SJerome Glisse dev_err(rdev->dev, "failed to reset GPU\n"); 260325b2ec5bSAlex Deucher ret = -1; 260425b2ec5bSAlex Deucher } else 260590aca4d2SJerome Glisse dev_info(rdev->dev, "GPU reset succeed\n"); 260625b2ec5bSAlex Deucher r100_mc_resume(rdev, &save); 260725b2ec5bSAlex Deucher return ret; 2608771fe6b9SJerome Glisse } 2609771fe6b9SJerome Glisse 261092cde00cSAlex Deucher void r100_set_common_regs(struct radeon_device *rdev) 261192cde00cSAlex Deucher { 26122739d49cSAlex Deucher bool force_dac2 = false; 2613d668046cSDave Airlie u32 tmp; 26142739d49cSAlex Deucher 261592cde00cSAlex Deucher /* set these so they don't interfere with anything */ 261692cde00cSAlex Deucher WREG32(RADEON_OV0_SCALE_CNTL, 0); 261792cde00cSAlex Deucher WREG32(RADEON_SUBPIC_CNTL, 0); 261892cde00cSAlex Deucher WREG32(RADEON_VIPH_CONTROL, 0); 261992cde00cSAlex Deucher WREG32(RADEON_I2C_CNTL_1, 0); 262092cde00cSAlex Deucher WREG32(RADEON_DVI_I2C_CNTL_1, 0); 262192cde00cSAlex Deucher WREG32(RADEON_CAP0_TRIG_CNTL, 0); 262292cde00cSAlex Deucher WREG32(RADEON_CAP1_TRIG_CNTL, 0); 26232739d49cSAlex Deucher 26242739d49cSAlex Deucher /* always set up dac2 on rn50 and some rv100 as lots 26252739d49cSAlex Deucher * of servers seem to wire it up to a VGA port but 26262739d49cSAlex Deucher * don't report it in the bios connector 26272739d49cSAlex Deucher * table. 26282739d49cSAlex Deucher */ 2629d86a4126SThomas Zimmermann switch (rdev->pdev->device) { 26302739d49cSAlex Deucher /* RN50 */ 26312739d49cSAlex Deucher case 0x515e: 26322739d49cSAlex Deucher case 0x5969: 26332739d49cSAlex Deucher force_dac2 = true; 26342739d49cSAlex Deucher break; 26352739d49cSAlex Deucher /* RV100*/ 26362739d49cSAlex Deucher case 0x5159: 26372739d49cSAlex Deucher case 0x515a: 26382739d49cSAlex Deucher /* DELL triple head servers */ 2639d86a4126SThomas Zimmermann if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2640d86a4126SThomas Zimmermann ((rdev->pdev->subsystem_device == 0x016c) || 2641d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x016d) || 2642d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x016e) || 2643d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x016f) || 2644d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x0170) || 2645d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x017d) || 2646d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x017e) || 2647d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x0183) || 2648d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x018a) || 2649d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x019a))) 26502739d49cSAlex Deucher force_dac2 = true; 26512739d49cSAlex Deucher break; 26522739d49cSAlex Deucher } 26532739d49cSAlex Deucher 26542739d49cSAlex Deucher if (force_dac2) { 26552739d49cSAlex Deucher u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 26562739d49cSAlex Deucher u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 26572739d49cSAlex Deucher u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 26582739d49cSAlex Deucher 26592739d49cSAlex Deucher /* For CRT on DAC2, don't turn it on if BIOS didn't 26602739d49cSAlex Deucher enable it, even it's detected. 26612739d49cSAlex Deucher */ 26622739d49cSAlex Deucher 26632739d49cSAlex Deucher /* force it to crtc0 */ 26642739d49cSAlex Deucher dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 26652739d49cSAlex Deucher dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 26662739d49cSAlex Deucher disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 26672739d49cSAlex Deucher 26682739d49cSAlex Deucher /* set up the TV DAC */ 26692739d49cSAlex Deucher tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 26702739d49cSAlex Deucher RADEON_TV_DAC_STD_MASK | 26712739d49cSAlex Deucher RADEON_TV_DAC_RDACPD | 26722739d49cSAlex Deucher RADEON_TV_DAC_GDACPD | 26732739d49cSAlex Deucher RADEON_TV_DAC_BDACPD | 26742739d49cSAlex Deucher RADEON_TV_DAC_BGADJ_MASK | 26752739d49cSAlex Deucher RADEON_TV_DAC_DACADJ_MASK); 26762739d49cSAlex Deucher tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 26772739d49cSAlex Deucher RADEON_TV_DAC_NHOLD | 26782739d49cSAlex Deucher RADEON_TV_DAC_STD_PS2 | 26792739d49cSAlex Deucher (0x58 << 16)); 26802739d49cSAlex Deucher 26812739d49cSAlex Deucher WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 26822739d49cSAlex Deucher WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 26832739d49cSAlex Deucher WREG32(RADEON_DAC_CNTL2, dac2_cntl); 26842739d49cSAlex Deucher } 2685d668046cSDave Airlie 2686d668046cSDave Airlie /* switch PM block to ACPI mode */ 2687d668046cSDave Airlie tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2688d668046cSDave Airlie tmp &= ~RADEON_PM_MODE_SEL; 2689d668046cSDave Airlie WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2690d668046cSDave Airlie 269192cde00cSAlex Deucher } 2692771fe6b9SJerome Glisse 2693771fe6b9SJerome Glisse /* 2694771fe6b9SJerome Glisse * VRAM info 2695771fe6b9SJerome Glisse */ 2696771fe6b9SJerome Glisse static void r100_vram_get_type(struct radeon_device *rdev) 2697771fe6b9SJerome Glisse { 2698771fe6b9SJerome Glisse uint32_t tmp; 2699771fe6b9SJerome Glisse 2700771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = false; 2701771fe6b9SJerome Glisse if (rdev->flags & RADEON_IS_IGP) 2702771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 2703771fe6b9SJerome Glisse else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2704771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 2705771fe6b9SJerome Glisse if ((rdev->family == CHIP_RV100) || 2706771fe6b9SJerome Glisse (rdev->family == CHIP_RS100) || 2707771fe6b9SJerome Glisse (rdev->family == CHIP_RS200)) { 2708771fe6b9SJerome Glisse tmp = RREG32(RADEON_MEM_CNTL); 2709771fe6b9SJerome Glisse if (tmp & RV100_HALF_MODE) { 2710771fe6b9SJerome Glisse rdev->mc.vram_width = 32; 2711771fe6b9SJerome Glisse } else { 2712771fe6b9SJerome Glisse rdev->mc.vram_width = 64; 2713771fe6b9SJerome Glisse } 2714771fe6b9SJerome Glisse if (rdev->flags & RADEON_SINGLE_CRTC) { 2715771fe6b9SJerome Glisse rdev->mc.vram_width /= 4; 2716771fe6b9SJerome Glisse rdev->mc.vram_is_ddr = true; 2717771fe6b9SJerome Glisse } 2718771fe6b9SJerome Glisse } else if (rdev->family <= CHIP_RV280) { 2719771fe6b9SJerome Glisse tmp = RREG32(RADEON_MEM_CNTL); 2720771fe6b9SJerome Glisse if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2721771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 2722771fe6b9SJerome Glisse } else { 2723771fe6b9SJerome Glisse rdev->mc.vram_width = 64; 2724771fe6b9SJerome Glisse } 2725771fe6b9SJerome Glisse } else { 2726771fe6b9SJerome Glisse /* newer IGPs */ 2727771fe6b9SJerome Glisse rdev->mc.vram_width = 128; 2728771fe6b9SJerome Glisse } 2729771fe6b9SJerome Glisse } 2730771fe6b9SJerome Glisse 27312a0f8918SDave Airlie static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2732771fe6b9SJerome Glisse { 27332a0f8918SDave Airlie u32 aper_size; 27342a0f8918SDave Airlie u8 byte; 27352a0f8918SDave Airlie 27362a0f8918SDave Airlie aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 27372a0f8918SDave Airlie 27382a0f8918SDave Airlie /* Set HDP_APER_CNTL only on cards that are known not to be broken, 27392a0f8918SDave Airlie * that is has the 2nd generation multifunction PCI interface 27402a0f8918SDave Airlie */ 27412a0f8918SDave Airlie if (rdev->family == CHIP_RV280 || 27422a0f8918SDave Airlie rdev->family >= CHIP_RV350) { 27432a0f8918SDave Airlie WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 27442a0f8918SDave Airlie ~RADEON_HDP_APER_CNTL); 27452a0f8918SDave Airlie DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 27462a0f8918SDave Airlie return aper_size * 2; 27472a0f8918SDave Airlie } 27482a0f8918SDave Airlie 27492a0f8918SDave Airlie /* Older cards have all sorts of funny issues to deal with. First 27502a0f8918SDave Airlie * check if it's a multifunction card by reading the PCI config 27512a0f8918SDave Airlie * header type... Limit those to one aperture size 27522a0f8918SDave Airlie */ 27532a0f8918SDave Airlie pci_read_config_byte(rdev->pdev, 0xe, &byte); 27542a0f8918SDave Airlie if (byte & 0x80) { 27552a0f8918SDave Airlie DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 27562a0f8918SDave Airlie DRM_INFO("Limiting VRAM to one aperture\n"); 27572a0f8918SDave Airlie return aper_size; 27582a0f8918SDave Airlie } 27592a0f8918SDave Airlie 27602a0f8918SDave Airlie /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 27612a0f8918SDave Airlie * have set it up. We don't write this as it's broken on some ASICs but 27622a0f8918SDave Airlie * we expect the BIOS to have done the right thing (might be too optimistic...) 27632a0f8918SDave Airlie */ 27642a0f8918SDave Airlie if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 27652a0f8918SDave Airlie return aper_size * 2; 27662a0f8918SDave Airlie return aper_size; 27672a0f8918SDave Airlie } 27682a0f8918SDave Airlie 27692a0f8918SDave Airlie void r100_vram_init_sizes(struct radeon_device *rdev) 27702a0f8918SDave Airlie { 27712a0f8918SDave Airlie u64 config_aper_size; 27722a0f8918SDave Airlie 2773d594e46aSJerome Glisse /* work out accessible VRAM */ 277401d73a69SJordan Crouse rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 277501d73a69SJordan Crouse rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 277651e5fcd3SJerome Glisse rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 277751e5fcd3SJerome Glisse /* FIXME we don't use the second aperture yet when we could use it */ 277851e5fcd3SJerome Glisse if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 277951e5fcd3SJerome Glisse rdev->mc.visible_vram_size = rdev->mc.aper_size; 27802a0f8918SDave Airlie config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2781771fe6b9SJerome Glisse if (rdev->flags & RADEON_IS_IGP) { 2782771fe6b9SJerome Glisse uint32_t tom; 2783771fe6b9SJerome Glisse /* read NB_TOM to get the amount of ram stolen for the GPU */ 2784771fe6b9SJerome Glisse tom = RREG32(RADEON_NB_TOM); 27857a50f01aSDave Airlie rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 27867a50f01aSDave Airlie WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 27877a50f01aSDave Airlie rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2788771fe6b9SJerome Glisse } else { 27897a50f01aSDave Airlie rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2790771fe6b9SJerome Glisse /* Some production boards of m6 will report 0 2791771fe6b9SJerome Glisse * if it's 8 MB 2792771fe6b9SJerome Glisse */ 27937a50f01aSDave Airlie if (rdev->mc.real_vram_size == 0) { 27947a50f01aSDave Airlie rdev->mc.real_vram_size = 8192 * 1024; 27957a50f01aSDave Airlie WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2796771fe6b9SJerome Glisse } 27972a0f8918SDave Airlie /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2798d594e46aSJerome Glisse * Novell bug 204882 + along with lots of ubuntu ones 2799d594e46aSJerome Glisse */ 2800b7d8cce5SAlex Deucher if (rdev->mc.aper_size > config_aper_size) 2801b7d8cce5SAlex Deucher config_aper_size = rdev->mc.aper_size; 2802b7d8cce5SAlex Deucher 28037a50f01aSDave Airlie if (config_aper_size > rdev->mc.real_vram_size) 28047a50f01aSDave Airlie rdev->mc.mc_vram_size = config_aper_size; 28057a50f01aSDave Airlie else 28067a50f01aSDave Airlie rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2807771fe6b9SJerome Glisse } 2808d594e46aSJerome Glisse } 28092a0f8918SDave Airlie 281028d52043SDave Airlie void r100_vga_set_state(struct radeon_device *rdev, bool state) 281128d52043SDave Airlie { 281228d52043SDave Airlie uint32_t temp; 281328d52043SDave Airlie 281428d52043SDave Airlie temp = RREG32(RADEON_CONFIG_CNTL); 2815fbd62354SWambui Karuga if (!state) { 2816d75ee3beSAlex Deucher temp &= ~RADEON_CFG_VGA_RAM_EN; 2817d75ee3beSAlex Deucher temp |= RADEON_CFG_VGA_IO_DIS; 281828d52043SDave Airlie } else { 2819d75ee3beSAlex Deucher temp &= ~RADEON_CFG_VGA_IO_DIS; 282028d52043SDave Airlie } 282128d52043SDave Airlie WREG32(RADEON_CONFIG_CNTL, temp); 282228d52043SDave Airlie } 282328d52043SDave Airlie 28241109ca09SLauri Kasanen static void r100_mc_init(struct radeon_device *rdev) 28252a0f8918SDave Airlie { 2826d594e46aSJerome Glisse u64 base; 28272a0f8918SDave Airlie 2828d594e46aSJerome Glisse r100_vram_get_type(rdev); 28292a0f8918SDave Airlie r100_vram_init_sizes(rdev); 2830d594e46aSJerome Glisse base = rdev->mc.aper_base; 2831d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_IGP) 2832d594e46aSJerome Glisse base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2833d594e46aSJerome Glisse radeon_vram_location(rdev, &rdev->mc, base); 28348d369bb1SAlex Deucher rdev->mc.gtt_base_align = 0; 2835d594e46aSJerome Glisse if (!(rdev->flags & RADEON_IS_AGP)) 2836d594e46aSJerome Glisse radeon_gtt_location(rdev, &rdev->mc); 2837f47299c5SAlex Deucher radeon_update_bandwidth_info(rdev); 2838771fe6b9SJerome Glisse } 2839771fe6b9SJerome Glisse 2840771fe6b9SJerome Glisse 2841771fe6b9SJerome Glisse /* 2842771fe6b9SJerome Glisse * Indirect registers accessor 2843771fe6b9SJerome Glisse */ 2844771fe6b9SJerome Glisse void r100_pll_errata_after_index(struct radeon_device *rdev) 2845771fe6b9SJerome Glisse { 28464ce9198eSAlex Deucher if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2847771fe6b9SJerome Glisse (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2848771fe6b9SJerome Glisse (void)RREG32(RADEON_CRTC_GEN_CNTL); 2849771fe6b9SJerome Glisse } 28504ce9198eSAlex Deucher } 2851771fe6b9SJerome Glisse 2852771fe6b9SJerome Glisse static void r100_pll_errata_after_data(struct radeon_device *rdev) 2853771fe6b9SJerome Glisse { 2854771fe6b9SJerome Glisse /* This workarounds is necessary on RV100, RS100 and RS200 chips 2855771fe6b9SJerome Glisse * or the chip could hang on a subsequent access 2856771fe6b9SJerome Glisse */ 2857771fe6b9SJerome Glisse if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 28584de833c3SArnd Bergmann mdelay(5); 2859771fe6b9SJerome Glisse } 2860771fe6b9SJerome Glisse 2861771fe6b9SJerome Glisse /* This function is required to workaround a hardware bug in some (all?) 2862771fe6b9SJerome Glisse * revisions of the R300. This workaround should be called after every 2863771fe6b9SJerome Glisse * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2864771fe6b9SJerome Glisse * may not be correct. 2865771fe6b9SJerome Glisse */ 2866771fe6b9SJerome Glisse if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2867771fe6b9SJerome Glisse uint32_t save, tmp; 2868771fe6b9SJerome Glisse 2869771fe6b9SJerome Glisse save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2870771fe6b9SJerome Glisse tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2871771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2872771fe6b9SJerome Glisse tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2873771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2874771fe6b9SJerome Glisse } 2875771fe6b9SJerome Glisse } 2876771fe6b9SJerome Glisse 2877771fe6b9SJerome Glisse uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2878771fe6b9SJerome Glisse { 28790a5b7b0bSAlex Deucher unsigned long flags; 2880771fe6b9SJerome Glisse uint32_t data; 2881771fe6b9SJerome Glisse 28820a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2883771fe6b9SJerome Glisse WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2884771fe6b9SJerome Glisse r100_pll_errata_after_index(rdev); 2885771fe6b9SJerome Glisse data = RREG32(RADEON_CLOCK_CNTL_DATA); 2886771fe6b9SJerome Glisse r100_pll_errata_after_data(rdev); 28870a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2888771fe6b9SJerome Glisse return data; 2889771fe6b9SJerome Glisse } 2890771fe6b9SJerome Glisse 2891771fe6b9SJerome Glisse void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2892771fe6b9SJerome Glisse { 28930a5b7b0bSAlex Deucher unsigned long flags; 28940a5b7b0bSAlex Deucher 28950a5b7b0bSAlex Deucher spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2896771fe6b9SJerome Glisse WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2897771fe6b9SJerome Glisse r100_pll_errata_after_index(rdev); 2898771fe6b9SJerome Glisse WREG32(RADEON_CLOCK_CNTL_DATA, v); 2899771fe6b9SJerome Glisse r100_pll_errata_after_data(rdev); 29000a5b7b0bSAlex Deucher spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2901771fe6b9SJerome Glisse } 2902771fe6b9SJerome Glisse 29031109ca09SLauri Kasanen static void r100_set_safe_registers(struct radeon_device *rdev) 2904068a117cSJerome Glisse { 2905551ebd83SDave Airlie if (ASIC_IS_RN50(rdev)) { 2906551ebd83SDave Airlie rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2907551ebd83SDave Airlie rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2908551ebd83SDave Airlie } else if (rdev->family < CHIP_R200) { 2909551ebd83SDave Airlie rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2910551ebd83SDave Airlie rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2911551ebd83SDave Airlie } else { 2912d4550907SJerome Glisse r200_set_safe_registers(rdev); 2913551ebd83SDave Airlie } 2914068a117cSJerome Glisse } 2915068a117cSJerome Glisse 2916771fe6b9SJerome Glisse /* 2917771fe6b9SJerome Glisse * Debugfs info 2918771fe6b9SJerome Glisse */ 2919771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 29205b54d679SNirmoy Das static int r100_debugfs_rbbm_info_show(struct seq_file *m, void *unused) 2921771fe6b9SJerome Glisse { 29225b54d679SNirmoy Das struct radeon_device *rdev = (struct radeon_device *)m->private; 2923771fe6b9SJerome Glisse uint32_t reg, value; 2924771fe6b9SJerome Glisse unsigned i; 2925771fe6b9SJerome Glisse 2926771fe6b9SJerome Glisse seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2927771fe6b9SJerome Glisse seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2928771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2929771fe6b9SJerome Glisse for (i = 0; i < 64; i++) { 2930771fe6b9SJerome Glisse WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2931771fe6b9SJerome Glisse reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2932771fe6b9SJerome Glisse WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2933771fe6b9SJerome Glisse value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2934771fe6b9SJerome Glisse seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2935771fe6b9SJerome Glisse } 2936771fe6b9SJerome Glisse return 0; 2937771fe6b9SJerome Glisse } 2938771fe6b9SJerome Glisse 29395b54d679SNirmoy Das static int r100_debugfs_cp_ring_info_show(struct seq_file *m, void *unused) 2940771fe6b9SJerome Glisse { 29415b54d679SNirmoy Das struct radeon_device *rdev = (struct radeon_device *)m->private; 2942e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2943771fe6b9SJerome Glisse uint32_t rdp, wdp; 2944771fe6b9SJerome Glisse unsigned count, i, j; 2945771fe6b9SJerome Glisse 2946e32eb50dSChristian König radeon_ring_free_size(rdev, ring); 2947771fe6b9SJerome Glisse rdp = RREG32(RADEON_CP_RB_RPTR); 2948771fe6b9SJerome Glisse wdp = RREG32(RADEON_CP_RB_WPTR); 2949e32eb50dSChristian König count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2950771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2951771fe6b9SJerome Glisse seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2952771fe6b9SJerome Glisse seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2953e32eb50dSChristian König seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2954771fe6b9SJerome Glisse seq_printf(m, "%u dwords in ring\n", count); 29550eb3448aSAlex Ivanov if (ring->ready) { 2956771fe6b9SJerome Glisse for (j = 0; j <= count; j++) { 2957e32eb50dSChristian König i = (rdp + j) & ring->ptr_mask; 2958e32eb50dSChristian König seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2959771fe6b9SJerome Glisse } 29600eb3448aSAlex Ivanov } 2961771fe6b9SJerome Glisse return 0; 2962771fe6b9SJerome Glisse } 2963771fe6b9SJerome Glisse 2964771fe6b9SJerome Glisse 29655b54d679SNirmoy Das static int r100_debugfs_cp_csq_fifo_show(struct seq_file *m, void *unused) 2966771fe6b9SJerome Glisse { 29675b54d679SNirmoy Das struct radeon_device *rdev = (struct radeon_device *)m->private; 2968771fe6b9SJerome Glisse uint32_t csq_stat, csq2_stat, tmp; 2969771fe6b9SJerome Glisse unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2970771fe6b9SJerome Glisse unsigned i; 2971771fe6b9SJerome Glisse 2972771fe6b9SJerome Glisse seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2973771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2974771fe6b9SJerome Glisse csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2975771fe6b9SJerome Glisse csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2976771fe6b9SJerome Glisse r_rptr = (csq_stat >> 0) & 0x3ff; 2977771fe6b9SJerome Glisse r_wptr = (csq_stat >> 10) & 0x3ff; 2978771fe6b9SJerome Glisse ib1_rptr = (csq_stat >> 20) & 0x3ff; 2979771fe6b9SJerome Glisse ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2980771fe6b9SJerome Glisse ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2981771fe6b9SJerome Glisse ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2982771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2983771fe6b9SJerome Glisse seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2984771fe6b9SJerome Glisse seq_printf(m, "Ring rptr %u\n", r_rptr); 2985771fe6b9SJerome Glisse seq_printf(m, "Ring wptr %u\n", r_wptr); 2986771fe6b9SJerome Glisse seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2987771fe6b9SJerome Glisse seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2988771fe6b9SJerome Glisse seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 2989771fe6b9SJerome Glisse seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 2990771fe6b9SJerome Glisse /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 2991771fe6b9SJerome Glisse * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 2992771fe6b9SJerome Glisse seq_printf(m, "Ring fifo:\n"); 2993771fe6b9SJerome Glisse for (i = 0; i < 256; i++) { 2994771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2995771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA); 2996771fe6b9SJerome Glisse seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 2997771fe6b9SJerome Glisse } 2998771fe6b9SJerome Glisse seq_printf(m, "Indirect1 fifo:\n"); 2999771fe6b9SJerome Glisse for (i = 256; i <= 512; i++) { 3000771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3001771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA); 3002771fe6b9SJerome Glisse seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 3003771fe6b9SJerome Glisse } 3004771fe6b9SJerome Glisse seq_printf(m, "Indirect2 fifo:\n"); 3005771fe6b9SJerome Glisse for (i = 640; i < ib1_wptr; i++) { 3006771fe6b9SJerome Glisse WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3007771fe6b9SJerome Glisse tmp = RREG32(RADEON_CP_CSQ_DATA); 3008771fe6b9SJerome Glisse seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 3009771fe6b9SJerome Glisse } 3010771fe6b9SJerome Glisse return 0; 3011771fe6b9SJerome Glisse } 3012771fe6b9SJerome Glisse 30135b54d679SNirmoy Das static int r100_debugfs_mc_info_show(struct seq_file *m, void *unused) 3014771fe6b9SJerome Glisse { 30155b54d679SNirmoy Das struct radeon_device *rdev = (struct radeon_device *)m->private; 3016771fe6b9SJerome Glisse uint32_t tmp; 3017771fe6b9SJerome Glisse 3018771fe6b9SJerome Glisse tmp = RREG32(RADEON_CONFIG_MEMSIZE); 3019771fe6b9SJerome Glisse seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 3020771fe6b9SJerome Glisse tmp = RREG32(RADEON_MC_FB_LOCATION); 3021771fe6b9SJerome Glisse seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 3022771fe6b9SJerome Glisse tmp = RREG32(RADEON_BUS_CNTL); 3023771fe6b9SJerome Glisse seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 3024771fe6b9SJerome Glisse tmp = RREG32(RADEON_MC_AGP_LOCATION); 3025771fe6b9SJerome Glisse seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 3026771fe6b9SJerome Glisse tmp = RREG32(RADEON_AGP_BASE); 3027771fe6b9SJerome Glisse seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 3028771fe6b9SJerome Glisse tmp = RREG32(RADEON_HOST_PATH_CNTL); 3029771fe6b9SJerome Glisse seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 3030771fe6b9SJerome Glisse tmp = RREG32(0x01D0); 3031771fe6b9SJerome Glisse seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 3032771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_LO_ADDR); 3033771fe6b9SJerome Glisse seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 3034771fe6b9SJerome Glisse tmp = RREG32(RADEON_AIC_HI_ADDR); 3035771fe6b9SJerome Glisse seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 3036771fe6b9SJerome Glisse tmp = RREG32(0x01E4); 3037771fe6b9SJerome Glisse seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 3038771fe6b9SJerome Glisse return 0; 3039771fe6b9SJerome Glisse } 3040771fe6b9SJerome Glisse 30415b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_rbbm_info); 30425b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_ring_info); 30435b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_csq_fifo); 30445b54d679SNirmoy Das DEFINE_SHOW_ATTRIBUTE(r100_debugfs_mc_info); 3045771fe6b9SJerome Glisse 3046771fe6b9SJerome Glisse #endif 3047771fe6b9SJerome Glisse 30485b54d679SNirmoy Das void r100_debugfs_rbbm_init(struct radeon_device *rdev) 3049771fe6b9SJerome Glisse { 3050771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 30515b54d679SNirmoy Das struct dentry *root = rdev->ddev->primary->debugfs_root; 30525b54d679SNirmoy Das 30535b54d679SNirmoy Das debugfs_create_file("r100_rbbm_info", 0444, root, rdev, 30545b54d679SNirmoy Das &r100_debugfs_rbbm_info_fops); 3055771fe6b9SJerome Glisse #endif 3056771fe6b9SJerome Glisse } 3057771fe6b9SJerome Glisse 30585b54d679SNirmoy Das void r100_debugfs_cp_init(struct radeon_device *rdev) 3059771fe6b9SJerome Glisse { 3060771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 30615b54d679SNirmoy Das struct dentry *root = rdev->ddev->primary->debugfs_root; 30625b54d679SNirmoy Das 30635b54d679SNirmoy Das debugfs_create_file("r100_cp_ring_info", 0444, root, rdev, 30645b54d679SNirmoy Das &r100_debugfs_cp_ring_info_fops); 30655b54d679SNirmoy Das debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev, 30665b54d679SNirmoy Das &r100_debugfs_cp_csq_fifo_fops); 3067771fe6b9SJerome Glisse #endif 3068771fe6b9SJerome Glisse } 3069771fe6b9SJerome Glisse 30705b54d679SNirmoy Das void r100_debugfs_mc_info_init(struct radeon_device *rdev) 3071771fe6b9SJerome Glisse { 3072771fe6b9SJerome Glisse #if defined(CONFIG_DEBUG_FS) 30735b54d679SNirmoy Das struct dentry *root = rdev->ddev->primary->debugfs_root; 30745b54d679SNirmoy Das 30755b54d679SNirmoy Das debugfs_create_file("r100_mc_info", 0444, root, rdev, 30765b54d679SNirmoy Das &r100_debugfs_mc_info_fops); 3077771fe6b9SJerome Glisse #endif 3078771fe6b9SJerome Glisse } 3079e024e110SDave Airlie 3080e024e110SDave Airlie int r100_set_surface_reg(struct radeon_device *rdev, int reg, 3081e024e110SDave Airlie uint32_t tiling_flags, uint32_t pitch, 3082e024e110SDave Airlie uint32_t offset, uint32_t obj_size) 3083e024e110SDave Airlie { 3084e024e110SDave Airlie int surf_index = reg * 16; 3085e024e110SDave Airlie int flags = 0; 3086e024e110SDave Airlie 3087e024e110SDave Airlie if (rdev->family <= CHIP_RS200) { 3088e024e110SDave Airlie if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3089e024e110SDave Airlie == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3090e024e110SDave Airlie flags |= RADEON_SURF_TILE_COLOR_BOTH; 3091e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MACRO) 3092e024e110SDave Airlie flags |= RADEON_SURF_TILE_COLOR_MACRO; 309367d5ced5SAlex Deucher /* setting pitch to 0 disables tiling */ 309467d5ced5SAlex Deucher if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 309567d5ced5SAlex Deucher == 0) 309667d5ced5SAlex Deucher pitch = 0; 3097e024e110SDave Airlie } else if (rdev->family <= CHIP_RV280) { 3098e024e110SDave Airlie if (tiling_flags & (RADEON_TILING_MACRO)) 3099e024e110SDave Airlie flags |= R200_SURF_TILE_COLOR_MACRO; 3100e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MICRO) 3101e024e110SDave Airlie flags |= R200_SURF_TILE_COLOR_MICRO; 3102e024e110SDave Airlie } else { 3103e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MACRO) 3104e024e110SDave Airlie flags |= R300_SURF_TILE_MACRO; 3105e024e110SDave Airlie if (tiling_flags & RADEON_TILING_MICRO) 3106e024e110SDave Airlie flags |= R300_SURF_TILE_MICRO; 3107e024e110SDave Airlie } 3108e024e110SDave Airlie 3109c88f9f0cSMichel Dänzer if (tiling_flags & RADEON_TILING_SWAP_16BIT) 3110c88f9f0cSMichel Dänzer flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3111c88f9f0cSMichel Dänzer if (tiling_flags & RADEON_TILING_SWAP_32BIT) 3112c88f9f0cSMichel Dänzer flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 3113c88f9f0cSMichel Dänzer 3114f5c5f040SDave Airlie /* r100/r200 divide by 16 */ 3115f5c5f040SDave Airlie if (rdev->family < CHIP_R300) 3116f5c5f040SDave Airlie flags |= pitch / 16; 3117f5c5f040SDave Airlie else 3118f5c5f040SDave Airlie flags |= pitch / 8; 3119f5c5f040SDave Airlie 3120f5c5f040SDave Airlie 3121d9fdaafbSDave Airlie DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 3122e024e110SDave Airlie WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 3123e024e110SDave Airlie WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 3124e024e110SDave Airlie WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 3125e024e110SDave Airlie return 0; 3126e024e110SDave Airlie } 3127e024e110SDave Airlie 3128e024e110SDave Airlie void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 3129e024e110SDave Airlie { 3130e024e110SDave Airlie int surf_index = reg * 16; 3131e024e110SDave Airlie WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 3132e024e110SDave Airlie } 3133c93bb85bSJerome Glisse 3134c93bb85bSJerome Glisse void r100_bandwidth_update(struct radeon_device *rdev) 3135c93bb85bSJerome Glisse { 3136c93bb85bSJerome Glisse fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 3137c93bb85bSJerome Glisse fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 31381ef897e4STim Gardner fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; 31391ef897e4STim Gardner fixed20_12 crit_point_ff = {0}; 3140c93bb85bSJerome Glisse uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 3141c93bb85bSJerome Glisse fixed20_12 memtcas_ff[8] = { 314268adac5eSBen Skeggs dfixed_init(1), 314368adac5eSBen Skeggs dfixed_init(2), 314468adac5eSBen Skeggs dfixed_init(3), 314568adac5eSBen Skeggs dfixed_init(0), 314668adac5eSBen Skeggs dfixed_init_half(1), 314768adac5eSBen Skeggs dfixed_init_half(2), 314868adac5eSBen Skeggs dfixed_init(0), 3149c93bb85bSJerome Glisse }; 3150c93bb85bSJerome Glisse fixed20_12 memtcas_rs480_ff[8] = { 315168adac5eSBen Skeggs dfixed_init(0), 315268adac5eSBen Skeggs dfixed_init(1), 315368adac5eSBen Skeggs dfixed_init(2), 315468adac5eSBen Skeggs dfixed_init(3), 315568adac5eSBen Skeggs dfixed_init(0), 315668adac5eSBen Skeggs dfixed_init_half(1), 315768adac5eSBen Skeggs dfixed_init_half(2), 315868adac5eSBen Skeggs dfixed_init_half(3), 3159c93bb85bSJerome Glisse }; 3160c93bb85bSJerome Glisse fixed20_12 memtcas2_ff[8] = { 316168adac5eSBen Skeggs dfixed_init(0), 316268adac5eSBen Skeggs dfixed_init(1), 316368adac5eSBen Skeggs dfixed_init(2), 316468adac5eSBen Skeggs dfixed_init(3), 316568adac5eSBen Skeggs dfixed_init(4), 316668adac5eSBen Skeggs dfixed_init(5), 316768adac5eSBen Skeggs dfixed_init(6), 316868adac5eSBen Skeggs dfixed_init(7), 3169c93bb85bSJerome Glisse }; 3170c93bb85bSJerome Glisse fixed20_12 memtrbs[8] = { 317168adac5eSBen Skeggs dfixed_init(1), 317268adac5eSBen Skeggs dfixed_init_half(1), 317368adac5eSBen Skeggs dfixed_init(2), 317468adac5eSBen Skeggs dfixed_init_half(2), 317568adac5eSBen Skeggs dfixed_init(3), 317668adac5eSBen Skeggs dfixed_init_half(3), 317768adac5eSBen Skeggs dfixed_init(4), 317868adac5eSBen Skeggs dfixed_init_half(4) 3179c93bb85bSJerome Glisse }; 3180c93bb85bSJerome Glisse fixed20_12 memtrbs_r4xx[8] = { 318168adac5eSBen Skeggs dfixed_init(4), 318268adac5eSBen Skeggs dfixed_init(5), 318368adac5eSBen Skeggs dfixed_init(6), 318468adac5eSBen Skeggs dfixed_init(7), 318568adac5eSBen Skeggs dfixed_init(8), 318668adac5eSBen Skeggs dfixed_init(9), 318768adac5eSBen Skeggs dfixed_init(10), 318868adac5eSBen Skeggs dfixed_init(11) 3189c93bb85bSJerome Glisse }; 3190c93bb85bSJerome Glisse fixed20_12 min_mem_eff; 3191c93bb85bSJerome Glisse fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 3192c93bb85bSJerome Glisse fixed20_12 cur_latency_mclk, cur_latency_sclk; 31931ef897e4STim Gardner fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0}, 3194c93bb85bSJerome Glisse disp_drain_rate2, read_return_rate; 3195c93bb85bSJerome Glisse fixed20_12 time_disp1_drop_priority; 3196c93bb85bSJerome Glisse int c; 3197c93bb85bSJerome Glisse int cur_size = 16; /* in octawords */ 3198c93bb85bSJerome Glisse int critical_point = 0, critical_point2; 3199c93bb85bSJerome Glisse /* uint32_t read_return_rate, time_disp1_drop_priority; */ 3200c93bb85bSJerome Glisse int stop_req, max_stop_req; 3201c93bb85bSJerome Glisse struct drm_display_mode *mode1 = NULL; 3202c93bb85bSJerome Glisse struct drm_display_mode *mode2 = NULL; 3203c93bb85bSJerome Glisse uint32_t pixel_bytes1 = 0; 3204c93bb85bSJerome Glisse uint32_t pixel_bytes2 = 0; 3205c93bb85bSJerome Glisse 32065b5561b3SMario Kleiner /* Guess line buffer size to be 8192 pixels */ 32075b5561b3SMario Kleiner u32 lb_size = 8192; 32085b5561b3SMario Kleiner 32098efe82caSAlex Deucher if (!rdev->mode_info.mode_config_initialized) 32108efe82caSAlex Deucher return; 32118efe82caSAlex Deucher 3212f46c0120SAlex Deucher radeon_update_display_priority(rdev); 3213f46c0120SAlex Deucher 3214c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[0]->base.enabled) { 3215489f3267SVille Syrjälä const struct drm_framebuffer *fb = 3216489f3267SVille Syrjälä rdev->mode_info.crtcs[0]->base.primary->fb; 3217489f3267SVille Syrjälä 3218c93bb85bSJerome Glisse mode1 = &rdev->mode_info.crtcs[0]->base.mode; 3219272725c7SVille Syrjälä pixel_bytes1 = fb->format->cpp[0]; 3220c93bb85bSJerome Glisse } 3221dfee5614SDave Airlie if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3222c93bb85bSJerome Glisse if (rdev->mode_info.crtcs[1]->base.enabled) { 3223489f3267SVille Syrjälä const struct drm_framebuffer *fb = 3224489f3267SVille Syrjälä rdev->mode_info.crtcs[1]->base.primary->fb; 3225489f3267SVille Syrjälä 3226c93bb85bSJerome Glisse mode2 = &rdev->mode_info.crtcs[1]->base.mode; 3227272725c7SVille Syrjälä pixel_bytes2 = fb->format->cpp[0]; 3228c93bb85bSJerome Glisse } 3229dfee5614SDave Airlie } 3230c93bb85bSJerome Glisse 323168adac5eSBen Skeggs min_mem_eff.full = dfixed_const_8(0); 3232c93bb85bSJerome Glisse /* get modes */ 3233c93bb85bSJerome Glisse if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 3234c93bb85bSJerome Glisse uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 3235c93bb85bSJerome Glisse mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 3236c93bb85bSJerome Glisse mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 3237c93bb85bSJerome Glisse /* check crtc enables */ 3238c93bb85bSJerome Glisse if (mode2) 3239c93bb85bSJerome Glisse mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 3240c93bb85bSJerome Glisse if (mode1) 3241c93bb85bSJerome Glisse mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 3242c93bb85bSJerome Glisse WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 3243c93bb85bSJerome Glisse } 3244c93bb85bSJerome Glisse 3245c93bb85bSJerome Glisse /* 3246c93bb85bSJerome Glisse * determine is there is enough bw for current mode 3247c93bb85bSJerome Glisse */ 3248f47299c5SAlex Deucher sclk_ff = rdev->pm.sclk; 3249f47299c5SAlex Deucher mclk_ff = rdev->pm.mclk; 3250c93bb85bSJerome Glisse 3251c93bb85bSJerome Glisse temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 325268adac5eSBen Skeggs temp_ff.full = dfixed_const(temp); 325368adac5eSBen Skeggs mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 3254c93bb85bSJerome Glisse 3255c93bb85bSJerome Glisse pix_clk.full = 0; 3256c93bb85bSJerome Glisse pix_clk2.full = 0; 3257c93bb85bSJerome Glisse peak_disp_bw.full = 0; 3258c93bb85bSJerome Glisse if (mode1) { 325968adac5eSBen Skeggs temp_ff.full = dfixed_const(1000); 326068adac5eSBen Skeggs pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 326168adac5eSBen Skeggs pix_clk.full = dfixed_div(pix_clk, temp_ff); 326268adac5eSBen Skeggs temp_ff.full = dfixed_const(pixel_bytes1); 326368adac5eSBen Skeggs peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 3264c93bb85bSJerome Glisse } 3265c93bb85bSJerome Glisse if (mode2) { 326668adac5eSBen Skeggs temp_ff.full = dfixed_const(1000); 326768adac5eSBen Skeggs pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 326868adac5eSBen Skeggs pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 326968adac5eSBen Skeggs temp_ff.full = dfixed_const(pixel_bytes2); 327068adac5eSBen Skeggs peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 3271c93bb85bSJerome Glisse } 3272c93bb85bSJerome Glisse 327368adac5eSBen Skeggs mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 3274c93bb85bSJerome Glisse if (peak_disp_bw.full >= mem_bw.full) { 3275c93bb85bSJerome Glisse DRM_ERROR("You may not have enough display bandwidth for current mode\n" 3276c93bb85bSJerome Glisse "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 3277c93bb85bSJerome Glisse } 3278c93bb85bSJerome Glisse 3279c93bb85bSJerome Glisse /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 3280c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_TIMING_CNTL); 3281c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 3282c93bb85bSJerome Glisse mem_trcd = ((temp >> 2) & 0x3) + 1; 3283c93bb85bSJerome Glisse mem_trp = ((temp & 0x3)) + 1; 3284c93bb85bSJerome Glisse mem_tras = ((temp & 0x70) >> 4) + 1; 3285c93bb85bSJerome Glisse } else if (rdev->family == CHIP_R300 || 3286c93bb85bSJerome Glisse rdev->family == CHIP_R350) { /* r300, r350 */ 3287c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 1; 3288c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 1; 3289c93bb85bSJerome Glisse mem_tras = ((temp >> 11) & 0xf) + 4; 3290c93bb85bSJerome Glisse } else if (rdev->family == CHIP_RV350 || 3291211eed65SAlex Deucher rdev->family == CHIP_RV380) { 3292c93bb85bSJerome Glisse /* rv3x0 */ 3293c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 3; 3294c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 3; 3295c93bb85bSJerome Glisse mem_tras = ((temp >> 11) & 0xf) + 6; 3296c93bb85bSJerome Glisse } else if (rdev->family == CHIP_R420 || 3297c93bb85bSJerome Glisse rdev->family == CHIP_R423 || 3298c93bb85bSJerome Glisse rdev->family == CHIP_RV410) { 3299c93bb85bSJerome Glisse /* r4xx */ 3300c93bb85bSJerome Glisse mem_trcd = (temp & 0xf) + 3; 3301c93bb85bSJerome Glisse if (mem_trcd > 15) 3302c93bb85bSJerome Glisse mem_trcd = 15; 3303c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0xf) + 3; 3304c93bb85bSJerome Glisse if (mem_trp > 15) 3305c93bb85bSJerome Glisse mem_trp = 15; 3306c93bb85bSJerome Glisse mem_tras = ((temp >> 12) & 0x1f) + 6; 3307c93bb85bSJerome Glisse if (mem_tras > 31) 3308c93bb85bSJerome Glisse mem_tras = 31; 3309c93bb85bSJerome Glisse } else { /* RV200, R200 */ 3310c93bb85bSJerome Glisse mem_trcd = (temp & 0x7) + 1; 3311c93bb85bSJerome Glisse mem_trp = ((temp >> 8) & 0x7) + 1; 3312c93bb85bSJerome Glisse mem_tras = ((temp >> 12) & 0xf) + 4; 3313c93bb85bSJerome Glisse } 3314c93bb85bSJerome Glisse /* convert to FF */ 331568adac5eSBen Skeggs trcd_ff.full = dfixed_const(mem_trcd); 331668adac5eSBen Skeggs trp_ff.full = dfixed_const(mem_trp); 331768adac5eSBen Skeggs tras_ff.full = dfixed_const(mem_tras); 3318c93bb85bSJerome Glisse 3319c93bb85bSJerome Glisse /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 3320c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3321c93bb85bSJerome Glisse data = (temp & (7 << 20)) >> 20; 3322c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 3323c93bb85bSJerome Glisse if (rdev->family == CHIP_RS480) /* don't think rs400 */ 3324c93bb85bSJerome Glisse tcas_ff = memtcas_rs480_ff[data]; 3325c93bb85bSJerome Glisse else 3326c93bb85bSJerome Glisse tcas_ff = memtcas_ff[data]; 3327c93bb85bSJerome Glisse } else 3328c93bb85bSJerome Glisse tcas_ff = memtcas2_ff[data]; 3329c93bb85bSJerome Glisse 3330c93bb85bSJerome Glisse if (rdev->family == CHIP_RS400 || 3331c93bb85bSJerome Glisse rdev->family == CHIP_RS480) { 3332c93bb85bSJerome Glisse /* extra cas latency stored in bits 23-25 0-4 clocks */ 3333c93bb85bSJerome Glisse data = (temp >> 23) & 0x7; 3334c93bb85bSJerome Glisse if (data < 5) 333568adac5eSBen Skeggs tcas_ff.full += dfixed_const(data); 3336c93bb85bSJerome Glisse } 3337c93bb85bSJerome Glisse 3338c93bb85bSJerome Glisse if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 3339c93bb85bSJerome Glisse /* on the R300, Tcas is included in Trbs. 3340c93bb85bSJerome Glisse */ 3341c93bb85bSJerome Glisse temp = RREG32(RADEON_MEM_CNTL); 3342c93bb85bSJerome Glisse data = (R300_MEM_NUM_CHANNELS_MASK & temp); 3343c93bb85bSJerome Glisse if (data == 1) { 3344c93bb85bSJerome Glisse if (R300_MEM_USE_CD_CH_ONLY & temp) { 3345c93bb85bSJerome Glisse temp = RREG32(R300_MC_IND_INDEX); 3346c93bb85bSJerome Glisse temp &= ~R300_MC_IND_ADDR_MASK; 3347c93bb85bSJerome Glisse temp |= R300_MC_READ_CNTL_CD_mcind; 3348c93bb85bSJerome Glisse WREG32(R300_MC_IND_INDEX, temp); 3349c93bb85bSJerome Glisse temp = RREG32(R300_MC_IND_DATA); 3350c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_C_MASK & temp); 3351c93bb85bSJerome Glisse } else { 3352c93bb85bSJerome Glisse temp = RREG32(R300_MC_READ_CNTL_AB); 3353c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3354c93bb85bSJerome Glisse } 3355c93bb85bSJerome Glisse } else { 3356c93bb85bSJerome Glisse temp = RREG32(R300_MC_READ_CNTL_AB); 3357c93bb85bSJerome Glisse data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3358c93bb85bSJerome Glisse } 3359c93bb85bSJerome Glisse if (rdev->family == CHIP_RV410 || 3360c93bb85bSJerome Glisse rdev->family == CHIP_R420 || 3361c93bb85bSJerome Glisse rdev->family == CHIP_R423) 3362c93bb85bSJerome Glisse trbs_ff = memtrbs_r4xx[data]; 3363c93bb85bSJerome Glisse else 3364c93bb85bSJerome Glisse trbs_ff = memtrbs[data]; 3365c93bb85bSJerome Glisse tcas_ff.full += trbs_ff.full; 3366c93bb85bSJerome Glisse } 3367c93bb85bSJerome Glisse 3368c93bb85bSJerome Glisse sclk_eff_ff.full = sclk_ff.full; 3369c93bb85bSJerome Glisse 3370c93bb85bSJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 3371c93bb85bSJerome Glisse fixed20_12 agpmode_ff; 337268adac5eSBen Skeggs agpmode_ff.full = dfixed_const(radeon_agpmode); 337368adac5eSBen Skeggs temp_ff.full = dfixed_const_666(16); 337468adac5eSBen Skeggs sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3375c93bb85bSJerome Glisse } 3376c93bb85bSJerome Glisse /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3377c93bb85bSJerome Glisse 3378c93bb85bSJerome Glisse if (ASIC_IS_R300(rdev)) { 337968adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(250); 3380c93bb85bSJerome Glisse } else { 3381c93bb85bSJerome Glisse if ((rdev->family == CHIP_RV100) || 3382c93bb85bSJerome Glisse rdev->flags & RADEON_IS_IGP) { 3383c93bb85bSJerome Glisse if (rdev->mc.vram_is_ddr) 338468adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(41); 3385c93bb85bSJerome Glisse else 338668adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(33); 3387c93bb85bSJerome Glisse } else { 3388c93bb85bSJerome Glisse if (rdev->mc.vram_width == 128) 338968adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(57); 3390c93bb85bSJerome Glisse else 339168adac5eSBen Skeggs sclk_delay_ff.full = dfixed_const(41); 3392c93bb85bSJerome Glisse } 3393c93bb85bSJerome Glisse } 3394c93bb85bSJerome Glisse 339568adac5eSBen Skeggs mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3396c93bb85bSJerome Glisse 3397c93bb85bSJerome Glisse if (rdev->mc.vram_is_ddr) { 3398c93bb85bSJerome Glisse if (rdev->mc.vram_width == 32) { 339968adac5eSBen Skeggs k1.full = dfixed_const(40); 3400c93bb85bSJerome Glisse c = 3; 3401c93bb85bSJerome Glisse } else { 340268adac5eSBen Skeggs k1.full = dfixed_const(20); 3403c93bb85bSJerome Glisse c = 1; 3404c93bb85bSJerome Glisse } 3405c93bb85bSJerome Glisse } else { 340668adac5eSBen Skeggs k1.full = dfixed_const(40); 3407c93bb85bSJerome Glisse c = 3; 3408c93bb85bSJerome Glisse } 3409c93bb85bSJerome Glisse 341068adac5eSBen Skeggs temp_ff.full = dfixed_const(2); 341168adac5eSBen Skeggs mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 341268adac5eSBen Skeggs temp_ff.full = dfixed_const(c); 341368adac5eSBen Skeggs mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 341468adac5eSBen Skeggs temp_ff.full = dfixed_const(4); 341568adac5eSBen Skeggs mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 341668adac5eSBen Skeggs mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3417c93bb85bSJerome Glisse mc_latency_mclk.full += k1.full; 3418c93bb85bSJerome Glisse 341968adac5eSBen Skeggs mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 342068adac5eSBen Skeggs mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3421c93bb85bSJerome Glisse 3422c93bb85bSJerome Glisse /* 3423c93bb85bSJerome Glisse HW cursor time assuming worst case of full size colour cursor. 3424c93bb85bSJerome Glisse */ 342568adac5eSBen Skeggs temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3426c93bb85bSJerome Glisse temp_ff.full += trcd_ff.full; 3427c93bb85bSJerome Glisse if (temp_ff.full < tras_ff.full) 3428c93bb85bSJerome Glisse temp_ff.full = tras_ff.full; 342968adac5eSBen Skeggs cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3430c93bb85bSJerome Glisse 343168adac5eSBen Skeggs temp_ff.full = dfixed_const(cur_size); 343268adac5eSBen Skeggs cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3433c93bb85bSJerome Glisse /* 3434c93bb85bSJerome Glisse Find the total latency for the display data. 3435c93bb85bSJerome Glisse */ 343668adac5eSBen Skeggs disp_latency_overhead.full = dfixed_const(8); 343768adac5eSBen Skeggs disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3438c93bb85bSJerome Glisse mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3439c93bb85bSJerome Glisse mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3440c93bb85bSJerome Glisse 3441c93bb85bSJerome Glisse if (mc_latency_mclk.full > mc_latency_sclk.full) 3442c93bb85bSJerome Glisse disp_latency.full = mc_latency_mclk.full; 3443c93bb85bSJerome Glisse else 3444c93bb85bSJerome Glisse disp_latency.full = mc_latency_sclk.full; 3445c93bb85bSJerome Glisse 3446c93bb85bSJerome Glisse /* setup Max GRPH_STOP_REQ default value */ 3447c93bb85bSJerome Glisse if (ASIC_IS_RV100(rdev)) 3448c93bb85bSJerome Glisse max_stop_req = 0x5c; 3449c93bb85bSJerome Glisse else 3450c93bb85bSJerome Glisse max_stop_req = 0x7c; 3451c93bb85bSJerome Glisse 3452c93bb85bSJerome Glisse if (mode1) { 3453c93bb85bSJerome Glisse /* CRTC1 3454c93bb85bSJerome Glisse Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3455c93bb85bSJerome Glisse GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3456c93bb85bSJerome Glisse */ 3457c93bb85bSJerome Glisse stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3458c93bb85bSJerome Glisse 3459c93bb85bSJerome Glisse if (stop_req > max_stop_req) 3460c93bb85bSJerome Glisse stop_req = max_stop_req; 3461c93bb85bSJerome Glisse 3462c93bb85bSJerome Glisse /* 3463c93bb85bSJerome Glisse Find the drain rate of the display buffer. 3464c93bb85bSJerome Glisse */ 346568adac5eSBen Skeggs temp_ff.full = dfixed_const((16/pixel_bytes1)); 346668adac5eSBen Skeggs disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3467c93bb85bSJerome Glisse 3468c93bb85bSJerome Glisse /* 3469c93bb85bSJerome Glisse Find the critical point of the display buffer. 3470c93bb85bSJerome Glisse */ 347168adac5eSBen Skeggs crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 347268adac5eSBen Skeggs crit_point_ff.full += dfixed_const_half(0); 3473c93bb85bSJerome Glisse 347468adac5eSBen Skeggs critical_point = dfixed_trunc(crit_point_ff); 3475c93bb85bSJerome Glisse 3476c93bb85bSJerome Glisse if (rdev->disp_priority == 2) { 3477c93bb85bSJerome Glisse critical_point = 0; 3478c93bb85bSJerome Glisse } 3479c93bb85bSJerome Glisse 3480c93bb85bSJerome Glisse /* 3481c93bb85bSJerome Glisse The critical point should never be above max_stop_req-4. Setting 3482c93bb85bSJerome Glisse GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3483c93bb85bSJerome Glisse */ 3484c93bb85bSJerome Glisse if (max_stop_req - critical_point < 4) 3485c93bb85bSJerome Glisse critical_point = 0; 3486c93bb85bSJerome Glisse 3487c93bb85bSJerome Glisse if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3488c93bb85bSJerome Glisse /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3489c93bb85bSJerome Glisse critical_point = 0x10; 3490c93bb85bSJerome Glisse } 3491c93bb85bSJerome Glisse 3492c93bb85bSJerome Glisse temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3493c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3494c93bb85bSJerome Glisse temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3495c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_START_REQ_MASK); 3496c93bb85bSJerome Glisse if ((rdev->family == CHIP_R350) && 3497c93bb85bSJerome Glisse (stop_req > 0x15)) { 3498c93bb85bSJerome Glisse stop_req -= 0x10; 3499c93bb85bSJerome Glisse } 3500c93bb85bSJerome Glisse temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3501c93bb85bSJerome Glisse temp |= RADEON_GRPH_BUFFER_SIZE; 3502c93bb85bSJerome Glisse temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3503c93bb85bSJerome Glisse RADEON_GRPH_CRITICAL_AT_SOF | 3504c93bb85bSJerome Glisse RADEON_GRPH_STOP_CNTL); 3505c93bb85bSJerome Glisse /* 3506c93bb85bSJerome Glisse Write the result into the register. 3507c93bb85bSJerome Glisse */ 3508c93bb85bSJerome Glisse WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3509c93bb85bSJerome Glisse (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3510c93bb85bSJerome Glisse 3511c93bb85bSJerome Glisse #if 0 3512c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS400) || 3513c93bb85bSJerome Glisse (rdev->family == CHIP_RS480)) { 3514c93bb85bSJerome Glisse /* attempt to program RS400 disp regs correctly ??? */ 3515c93bb85bSJerome Glisse temp = RREG32(RS400_DISP1_REG_CNTL); 3516c93bb85bSJerome Glisse temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3517c93bb85bSJerome Glisse RS400_DISP1_STOP_REQ_LEVEL_MASK); 3518c93bb85bSJerome Glisse WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3519c93bb85bSJerome Glisse (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3520c93bb85bSJerome Glisse (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3521c93bb85bSJerome Glisse temp = RREG32(RS400_DMIF_MEM_CNTL1); 3522c93bb85bSJerome Glisse temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3523c93bb85bSJerome Glisse RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3524c93bb85bSJerome Glisse WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3525c93bb85bSJerome Glisse (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3526c93bb85bSJerome Glisse (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3527c93bb85bSJerome Glisse } 3528c93bb85bSJerome Glisse #endif 3529c93bb85bSJerome Glisse 3530d9fdaafbSDave Airlie DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3531c93bb85bSJerome Glisse /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3532c93bb85bSJerome Glisse (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3533c93bb85bSJerome Glisse } 3534c93bb85bSJerome Glisse 3535c93bb85bSJerome Glisse if (mode2) { 3536c93bb85bSJerome Glisse u32 grph2_cntl; 3537c93bb85bSJerome Glisse stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3538c93bb85bSJerome Glisse 3539c93bb85bSJerome Glisse if (stop_req > max_stop_req) 3540c93bb85bSJerome Glisse stop_req = max_stop_req; 3541c93bb85bSJerome Glisse 3542c93bb85bSJerome Glisse /* 3543c93bb85bSJerome Glisse Find the drain rate of the display buffer. 3544c93bb85bSJerome Glisse */ 354568adac5eSBen Skeggs temp_ff.full = dfixed_const((16/pixel_bytes2)); 354668adac5eSBen Skeggs disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3547c93bb85bSJerome Glisse 3548c93bb85bSJerome Glisse grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3549c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3550c93bb85bSJerome Glisse grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3551c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3552c93bb85bSJerome Glisse if ((rdev->family == CHIP_R350) && 3553c93bb85bSJerome Glisse (stop_req > 0x15)) { 3554c93bb85bSJerome Glisse stop_req -= 0x10; 3555c93bb85bSJerome Glisse } 3556c93bb85bSJerome Glisse grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3557c93bb85bSJerome Glisse grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3558c93bb85bSJerome Glisse grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3559c93bb85bSJerome Glisse RADEON_GRPH_CRITICAL_AT_SOF | 3560c93bb85bSJerome Glisse RADEON_GRPH_STOP_CNTL); 3561c93bb85bSJerome Glisse 3562c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS100) || 3563c93bb85bSJerome Glisse (rdev->family == CHIP_RS200)) 3564c93bb85bSJerome Glisse critical_point2 = 0; 3565c93bb85bSJerome Glisse else { 3566c93bb85bSJerome Glisse temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 356768adac5eSBen Skeggs temp_ff.full = dfixed_const(temp); 356868adac5eSBen Skeggs temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3569c93bb85bSJerome Glisse if (sclk_ff.full < temp_ff.full) 3570c93bb85bSJerome Glisse temp_ff.full = sclk_ff.full; 3571c93bb85bSJerome Glisse 3572c93bb85bSJerome Glisse read_return_rate.full = temp_ff.full; 3573c93bb85bSJerome Glisse 3574c93bb85bSJerome Glisse if (mode1) { 3575c93bb85bSJerome Glisse temp_ff.full = read_return_rate.full - disp_drain_rate.full; 357668adac5eSBen Skeggs time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3577c93bb85bSJerome Glisse } else { 3578c93bb85bSJerome Glisse time_disp1_drop_priority.full = 0; 3579c93bb85bSJerome Glisse } 3580c93bb85bSJerome Glisse crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 358168adac5eSBen Skeggs crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 358268adac5eSBen Skeggs crit_point_ff.full += dfixed_const_half(0); 3583c93bb85bSJerome Glisse 358468adac5eSBen Skeggs critical_point2 = dfixed_trunc(crit_point_ff); 3585c93bb85bSJerome Glisse 3586c93bb85bSJerome Glisse if (rdev->disp_priority == 2) { 3587c93bb85bSJerome Glisse critical_point2 = 0; 3588c93bb85bSJerome Glisse } 3589c93bb85bSJerome Glisse 3590c93bb85bSJerome Glisse if (max_stop_req - critical_point2 < 4) 3591c93bb85bSJerome Glisse critical_point2 = 0; 3592c93bb85bSJerome Glisse 3593c93bb85bSJerome Glisse } 3594c93bb85bSJerome Glisse 3595c93bb85bSJerome Glisse if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3596c93bb85bSJerome Glisse /* some R300 cards have problem with this set to 0 */ 3597c93bb85bSJerome Glisse critical_point2 = 0x10; 3598c93bb85bSJerome Glisse } 3599c93bb85bSJerome Glisse 3600c93bb85bSJerome Glisse WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3601c93bb85bSJerome Glisse (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3602c93bb85bSJerome Glisse 3603c93bb85bSJerome Glisse if ((rdev->family == CHIP_RS400) || 3604c93bb85bSJerome Glisse (rdev->family == CHIP_RS480)) { 3605c93bb85bSJerome Glisse #if 0 3606c93bb85bSJerome Glisse /* attempt to program RS400 disp2 regs correctly ??? */ 3607c93bb85bSJerome Glisse temp = RREG32(RS400_DISP2_REQ_CNTL1); 3608c93bb85bSJerome Glisse temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3609c93bb85bSJerome Glisse RS400_DISP2_STOP_REQ_LEVEL_MASK); 3610c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3611c93bb85bSJerome Glisse (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3612c93bb85bSJerome Glisse (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3613c93bb85bSJerome Glisse temp = RREG32(RS400_DISP2_REQ_CNTL2); 3614c93bb85bSJerome Glisse temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3615c93bb85bSJerome Glisse RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3616c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3617c93bb85bSJerome Glisse (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3618c93bb85bSJerome Glisse (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3619c93bb85bSJerome Glisse #endif 3620c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3621c93bb85bSJerome Glisse WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3622c93bb85bSJerome Glisse WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3623c93bb85bSJerome Glisse WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3624c93bb85bSJerome Glisse } 3625c93bb85bSJerome Glisse 3626d9fdaafbSDave Airlie DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3627c93bb85bSJerome Glisse (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3628c93bb85bSJerome Glisse } 36295b5561b3SMario Kleiner 36305b5561b3SMario Kleiner /* Save number of lines the linebuffer leads before the scanout */ 36315b5561b3SMario Kleiner if (mode1) 36325b5561b3SMario Kleiner rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 36335b5561b3SMario Kleiner 36345b5561b3SMario Kleiner if (mode2) 36355b5561b3SMario Kleiner rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 3636c93bb85bSJerome Glisse } 3637551ebd83SDave Airlie 3638e32eb50dSChristian König int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 36393ce0a23dSJerome Glisse { 36403ce0a23dSJerome Glisse uint32_t scratch; 36413ce0a23dSJerome Glisse uint32_t tmp = 0; 36423ce0a23dSJerome Glisse unsigned i; 36433ce0a23dSJerome Glisse int r; 36443ce0a23dSJerome Glisse 36453ce0a23dSJerome Glisse r = radeon_scratch_get(rdev, &scratch); 36463ce0a23dSJerome Glisse if (r) { 36473ce0a23dSJerome Glisse DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 36483ce0a23dSJerome Glisse return r; 36493ce0a23dSJerome Glisse } 36503ce0a23dSJerome Glisse WREG32(scratch, 0xCAFEDEAD); 3651e32eb50dSChristian König r = radeon_ring_lock(rdev, ring, 2); 36523ce0a23dSJerome Glisse if (r) { 36533ce0a23dSJerome Glisse DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 36543ce0a23dSJerome Glisse radeon_scratch_free(rdev, scratch); 36553ce0a23dSJerome Glisse return r; 36563ce0a23dSJerome Glisse } 3657e32eb50dSChristian König radeon_ring_write(ring, PACKET0(scratch, 0)); 3658e32eb50dSChristian König radeon_ring_write(ring, 0xDEADBEEF); 36591538a9e0SMichel Dänzer radeon_ring_unlock_commit(rdev, ring, false); 36603ce0a23dSJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 36613ce0a23dSJerome Glisse tmp = RREG32(scratch); 36623ce0a23dSJerome Glisse if (tmp == 0xDEADBEEF) { 36633ce0a23dSJerome Glisse break; 36643ce0a23dSJerome Glisse } 36650e1a351dSSam Ravnborg udelay(1); 36663ce0a23dSJerome Glisse } 36673ce0a23dSJerome Glisse if (i < rdev->usec_timeout) { 36683ce0a23dSJerome Glisse DRM_INFO("ring test succeeded in %d usecs\n", i); 36693ce0a23dSJerome Glisse } else { 3670369d7ec1SAlex Deucher DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 36713ce0a23dSJerome Glisse scratch, tmp); 36723ce0a23dSJerome Glisse r = -EINVAL; 36733ce0a23dSJerome Glisse } 36743ce0a23dSJerome Glisse radeon_scratch_free(rdev, scratch); 36753ce0a23dSJerome Glisse return r; 36763ce0a23dSJerome Glisse } 36773ce0a23dSJerome Glisse 36783ce0a23dSJerome Glisse void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 36793ce0a23dSJerome Glisse { 3680e32eb50dSChristian König struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 36817b1f2485SChristian König 3682c7eff978SAlex Deucher if (ring->rptr_save_reg) { 3683c7eff978SAlex Deucher u32 next_rptr = ring->wptr + 2 + 3; 3684c7eff978SAlex Deucher radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); 3685c7eff978SAlex Deucher radeon_ring_write(ring, next_rptr); 3686c7eff978SAlex Deucher } 3687c7eff978SAlex Deucher 3688e32eb50dSChristian König radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3689e32eb50dSChristian König radeon_ring_write(ring, ib->gpu_addr); 3690e32eb50dSChristian König radeon_ring_write(ring, ib->length_dw); 36913ce0a23dSJerome Glisse } 36923ce0a23dSJerome Glisse 3693f712812eSAlex Deucher int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 36943ce0a23dSJerome Glisse { 3695f2e39221SJerome Glisse struct radeon_ib ib; 36963ce0a23dSJerome Glisse uint32_t scratch; 36973ce0a23dSJerome Glisse uint32_t tmp = 0; 36983ce0a23dSJerome Glisse unsigned i; 36993ce0a23dSJerome Glisse int r; 37003ce0a23dSJerome Glisse 37013ce0a23dSJerome Glisse r = radeon_scratch_get(rdev, &scratch); 37023ce0a23dSJerome Glisse if (r) { 37033ce0a23dSJerome Glisse DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 37043ce0a23dSJerome Glisse return r; 37053ce0a23dSJerome Glisse } 37063ce0a23dSJerome Glisse WREG32(scratch, 0xCAFEDEAD); 37074bf3dd92SChristian König r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); 37083ce0a23dSJerome Glisse if (r) { 3709af026c5bSMichel Dänzer DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3710af026c5bSMichel Dänzer goto free_scratch; 37113ce0a23dSJerome Glisse } 3712f2e39221SJerome Glisse ib.ptr[0] = PACKET0(scratch, 0); 3713f2e39221SJerome Glisse ib.ptr[1] = 0xDEADBEEF; 3714f2e39221SJerome Glisse ib.ptr[2] = PACKET2(0); 3715f2e39221SJerome Glisse ib.ptr[3] = PACKET2(0); 3716f2e39221SJerome Glisse ib.ptr[4] = PACKET2(0); 3717f2e39221SJerome Glisse ib.ptr[5] = PACKET2(0); 3718f2e39221SJerome Glisse ib.ptr[6] = PACKET2(0); 3719f2e39221SJerome Glisse ib.ptr[7] = PACKET2(0); 3720f2e39221SJerome Glisse ib.length_dw = 8; 37211538a9e0SMichel Dänzer r = radeon_ib_schedule(rdev, &ib, NULL, false); 37223ce0a23dSJerome Glisse if (r) { 3723af026c5bSMichel Dänzer DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3724af026c5bSMichel Dänzer goto free_ib; 37253ce0a23dSJerome Glisse } 372604db4cafSMatthew Dawson r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies( 372704db4cafSMatthew Dawson RADEON_USEC_IB_TEST_TIMEOUT)); 372804db4cafSMatthew Dawson if (r < 0) { 3729af026c5bSMichel Dänzer DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3730af026c5bSMichel Dänzer goto free_ib; 373104db4cafSMatthew Dawson } else if (r == 0) { 373204db4cafSMatthew Dawson DRM_ERROR("radeon: fence wait timed out.\n"); 373304db4cafSMatthew Dawson r = -ETIMEDOUT; 373404db4cafSMatthew Dawson goto free_ib; 37353ce0a23dSJerome Glisse } 373604db4cafSMatthew Dawson r = 0; 37373ce0a23dSJerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 37383ce0a23dSJerome Glisse tmp = RREG32(scratch); 37393ce0a23dSJerome Glisse if (tmp == 0xDEADBEEF) { 37403ce0a23dSJerome Glisse break; 37413ce0a23dSJerome Glisse } 37420e1a351dSSam Ravnborg udelay(1); 37433ce0a23dSJerome Glisse } 37443ce0a23dSJerome Glisse if (i < rdev->usec_timeout) { 37453ce0a23dSJerome Glisse DRM_INFO("ib test succeeded in %u usecs\n", i); 37463ce0a23dSJerome Glisse } else { 374762f288cfSPaul Bolle DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 37483ce0a23dSJerome Glisse scratch, tmp); 37493ce0a23dSJerome Glisse r = -EINVAL; 37503ce0a23dSJerome Glisse } 3751af026c5bSMichel Dänzer free_ib: 37523ce0a23dSJerome Glisse radeon_ib_free(rdev, &ib); 3753af026c5bSMichel Dänzer free_scratch: 3754af026c5bSMichel Dänzer radeon_scratch_free(rdev, scratch); 37553ce0a23dSJerome Glisse return r; 37563ce0a23dSJerome Glisse } 37579f022ddfSJerome Glisse 37589f022ddfSJerome Glisse void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 37599f022ddfSJerome Glisse { 37609f022ddfSJerome Glisse /* Shutdown CP we shouldn't need to do that but better be safe than 37619f022ddfSJerome Glisse * sorry 37629f022ddfSJerome Glisse */ 3763e32eb50dSChristian König rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 37649f022ddfSJerome Glisse WREG32(R_000740_CP_CSQ_CNTL, 0); 37659f022ddfSJerome Glisse 37669f022ddfSJerome Glisse /* Save few CRTC registers */ 3767ca6ffc64SJerome Glisse save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 37689f022ddfSJerome Glisse save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 37699f022ddfSJerome Glisse save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 37709f022ddfSJerome Glisse save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 37719f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 37729f022ddfSJerome Glisse save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 37739f022ddfSJerome Glisse save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 37749f022ddfSJerome Glisse } 37759f022ddfSJerome Glisse 37769f022ddfSJerome Glisse /* Disable VGA aperture access */ 3777ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 37789f022ddfSJerome Glisse /* Disable cursor, overlay, crtc */ 37799f022ddfSJerome Glisse WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 37809f022ddfSJerome Glisse WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 37819f022ddfSJerome Glisse S_000054_CRTC_DISPLAY_DIS(1)); 37829f022ddfSJerome Glisse WREG32(R_000050_CRTC_GEN_CNTL, 37839f022ddfSJerome Glisse (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 37849f022ddfSJerome Glisse S_000050_CRTC_DISP_REQ_EN_B(1)); 37859f022ddfSJerome Glisse WREG32(R_000420_OV0_SCALE_CNTL, 37869f022ddfSJerome Glisse C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 37879f022ddfSJerome Glisse WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 37889f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 37899f022ddfSJerome Glisse WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 37909f022ddfSJerome Glisse S_000360_CUR2_LOCK(1)); 37919f022ddfSJerome Glisse WREG32(R_0003F8_CRTC2_GEN_CNTL, 37929f022ddfSJerome Glisse (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 37939f022ddfSJerome Glisse S_0003F8_CRTC2_DISPLAY_DIS(1) | 37949f022ddfSJerome Glisse S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 37959f022ddfSJerome Glisse WREG32(R_000360_CUR2_OFFSET, 37969f022ddfSJerome Glisse C_000360_CUR2_LOCK & save->CUR2_OFFSET); 37979f022ddfSJerome Glisse } 37989f022ddfSJerome Glisse } 37999f022ddfSJerome Glisse 38009f022ddfSJerome Glisse void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 38019f022ddfSJerome Glisse { 38029f022ddfSJerome Glisse /* Update base address for crtc */ 3803d594e46aSJerome Glisse WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 38049f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3805d594e46aSJerome Glisse WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 38069f022ddfSJerome Glisse } 38079f022ddfSJerome Glisse /* Restore CRTC registers */ 3808ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 38099f022ddfSJerome Glisse WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 38109f022ddfSJerome Glisse WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 38119f022ddfSJerome Glisse if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 38129f022ddfSJerome Glisse WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 38139f022ddfSJerome Glisse } 38149f022ddfSJerome Glisse } 3815ca6ffc64SJerome Glisse 3816ca6ffc64SJerome Glisse void r100_vga_render_disable(struct radeon_device *rdev) 3817ca6ffc64SJerome Glisse { 3818ca6ffc64SJerome Glisse u32 tmp; 3819ca6ffc64SJerome Glisse 3820ca6ffc64SJerome Glisse tmp = RREG8(R_0003C2_GENMO_WT); 3821ca6ffc64SJerome Glisse WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3822ca6ffc64SJerome Glisse } 3823d4550907SJerome Glisse 3824d4550907SJerome Glisse static void r100_mc_program(struct radeon_device *rdev) 3825d4550907SJerome Glisse { 3826d4550907SJerome Glisse struct r100_mc_save save; 3827d4550907SJerome Glisse 3828d4550907SJerome Glisse /* Stops all mc clients */ 3829d4550907SJerome Glisse r100_mc_stop(rdev, &save); 3830d4550907SJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 3831d4550907SJerome Glisse WREG32(R_00014C_MC_AGP_LOCATION, 3832d4550907SJerome Glisse S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3833d4550907SJerome Glisse S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3834d4550907SJerome Glisse WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3835d4550907SJerome Glisse if (rdev->family > CHIP_RV200) 3836d4550907SJerome Glisse WREG32(R_00015C_AGP_BASE_2, 3837d4550907SJerome Glisse upper_32_bits(rdev->mc.agp_base) & 0xff); 3838d4550907SJerome Glisse } else { 3839d4550907SJerome Glisse WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3840d4550907SJerome Glisse WREG32(R_000170_AGP_BASE, 0); 3841d4550907SJerome Glisse if (rdev->family > CHIP_RV200) 3842d4550907SJerome Glisse WREG32(R_00015C_AGP_BASE_2, 0); 3843d4550907SJerome Glisse } 3844d4550907SJerome Glisse /* Wait for mc idle */ 3845d4550907SJerome Glisse if (r100_mc_wait_for_idle(rdev)) 3846d4550907SJerome Glisse dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3847d4550907SJerome Glisse /* Program MC, should be a 32bits limited address space */ 3848d4550907SJerome Glisse WREG32(R_000148_MC_FB_LOCATION, 3849d4550907SJerome Glisse S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3850d4550907SJerome Glisse S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3851d4550907SJerome Glisse r100_mc_resume(rdev, &save); 3852d4550907SJerome Glisse } 3853d4550907SJerome Glisse 38541109ca09SLauri Kasanen static void r100_clock_startup(struct radeon_device *rdev) 3855d4550907SJerome Glisse { 3856d4550907SJerome Glisse u32 tmp; 3857d4550907SJerome Glisse 3858d4550907SJerome Glisse if (radeon_dynclks != -1 && radeon_dynclks) 3859d4550907SJerome Glisse radeon_legacy_set_clock_gating(rdev, 1); 3860d4550907SJerome Glisse /* We need to force on some of the block */ 3861d4550907SJerome Glisse tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3862d4550907SJerome Glisse tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3863d4550907SJerome Glisse if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3864d4550907SJerome Glisse tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3865d4550907SJerome Glisse WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3866d4550907SJerome Glisse } 3867d4550907SJerome Glisse 3868d4550907SJerome Glisse static int r100_startup(struct radeon_device *rdev) 3869d4550907SJerome Glisse { 3870d4550907SJerome Glisse int r; 3871d4550907SJerome Glisse 387292cde00cSAlex Deucher /* set common regs */ 387392cde00cSAlex Deucher r100_set_common_regs(rdev); 387492cde00cSAlex Deucher /* program mc */ 3875d4550907SJerome Glisse r100_mc_program(rdev); 3876d4550907SJerome Glisse /* Resume clock */ 3877d4550907SJerome Glisse r100_clock_startup(rdev); 3878d4550907SJerome Glisse /* Initialize GART (initialize after TTM so we can allocate 3879d4550907SJerome Glisse * memory through TTM but finalize after TTM) */ 388017e15b0cSDave Airlie r100_enable_bm(rdev); 3881d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) { 3882d4550907SJerome Glisse r = r100_pci_gart_enable(rdev); 3883d4550907SJerome Glisse if (r) 3884d4550907SJerome Glisse return r; 3885d4550907SJerome Glisse } 3886724c80e1SAlex Deucher 3887724c80e1SAlex Deucher /* allocate wb buffer */ 3888724c80e1SAlex Deucher r = radeon_wb_init(rdev); 3889724c80e1SAlex Deucher if (r) 3890724c80e1SAlex Deucher return r; 3891724c80e1SAlex Deucher 389230eb77f4SJerome Glisse r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 389330eb77f4SJerome Glisse if (r) { 389430eb77f4SJerome Glisse dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 389530eb77f4SJerome Glisse return r; 389630eb77f4SJerome Glisse } 389730eb77f4SJerome Glisse 3898d4550907SJerome Glisse /* Enable IRQ */ 3899e49f3959SAdis Hamzić if (!rdev->irq.installed) { 3900e49f3959SAdis Hamzić r = radeon_irq_kms_init(rdev); 3901e49f3959SAdis Hamzić if (r) 3902e49f3959SAdis Hamzić return r; 3903e49f3959SAdis Hamzić } 3904e49f3959SAdis Hamzić 3905d4550907SJerome Glisse r100_irq_set(rdev); 3906cafe6609SJerome Glisse rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3907d4550907SJerome Glisse /* 1M ring buffer */ 3908d4550907SJerome Glisse r = r100_cp_init(rdev, 1024 * 1024); 3909d4550907SJerome Glisse if (r) { 3910ec4f2ac4SPaul Bolle dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3911d4550907SJerome Glisse return r; 3912d4550907SJerome Glisse } 3913b15ba512SJerome Glisse 39142898c348SChristian König r = radeon_ib_pool_init(rdev); 39152898c348SChristian König if (r) { 39162898c348SChristian König dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3917b15ba512SJerome Glisse return r; 39182898c348SChristian König } 3919b15ba512SJerome Glisse 3920d4550907SJerome Glisse return 0; 3921d4550907SJerome Glisse } 3922d4550907SJerome Glisse 3923d4550907SJerome Glisse int r100_resume(struct radeon_device *rdev) 3924d4550907SJerome Glisse { 39256b7746e8SJerome Glisse int r; 39266b7746e8SJerome Glisse 3927d4550907SJerome Glisse /* Make sur GART are not working */ 3928d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 3929d4550907SJerome Glisse r100_pci_gart_disable(rdev); 3930d4550907SJerome Glisse /* Resume clock before doing reset */ 3931d4550907SJerome Glisse r100_clock_startup(rdev); 3932d4550907SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3933a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 3934d4550907SJerome Glisse dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3935d4550907SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 3936d4550907SJerome Glisse RREG32(R_0007C0_CP_STAT)); 3937d4550907SJerome Glisse } 3938d4550907SJerome Glisse /* post */ 3939d4550907SJerome Glisse radeon_combios_asic_init(rdev->ddev); 3940d4550907SJerome Glisse /* Resume clock after posting */ 3941d4550907SJerome Glisse r100_clock_startup(rdev); 3942550e2d92SDave Airlie /* Initialize surface registers */ 3943550e2d92SDave Airlie radeon_surface_init(rdev); 3944b15ba512SJerome Glisse 3945b15ba512SJerome Glisse rdev->accel_working = true; 39466b7746e8SJerome Glisse r = r100_startup(rdev); 39476b7746e8SJerome Glisse if (r) { 39486b7746e8SJerome Glisse rdev->accel_working = false; 39496b7746e8SJerome Glisse } 39506b7746e8SJerome Glisse return r; 3951d4550907SJerome Glisse } 3952d4550907SJerome Glisse 3953d4550907SJerome Glisse int r100_suspend(struct radeon_device *rdev) 3954d4550907SJerome Glisse { 39556c7bcceaSAlex Deucher radeon_pm_suspend(rdev); 3956d4550907SJerome Glisse r100_cp_disable(rdev); 3957724c80e1SAlex Deucher radeon_wb_disable(rdev); 3958d4550907SJerome Glisse r100_irq_disable(rdev); 3959d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 3960d4550907SJerome Glisse r100_pci_gart_disable(rdev); 3961d4550907SJerome Glisse return 0; 3962d4550907SJerome Glisse } 3963d4550907SJerome Glisse 3964d4550907SJerome Glisse void r100_fini(struct radeon_device *rdev) 3965d4550907SJerome Glisse { 39666c7bcceaSAlex Deucher radeon_pm_fini(rdev); 3967d4550907SJerome Glisse r100_cp_fini(rdev); 3968724c80e1SAlex Deucher radeon_wb_fini(rdev); 39692898c348SChristian König radeon_ib_pool_fini(rdev); 3970d4550907SJerome Glisse radeon_gem_fini(rdev); 3971d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 3972d4550907SJerome Glisse r100_pci_gart_fini(rdev); 3973d0269ed8SJerome Glisse radeon_agp_fini(rdev); 3974d4550907SJerome Glisse radeon_irq_kms_fini(rdev); 3975d4550907SJerome Glisse radeon_fence_driver_fini(rdev); 39764c788679SJerome Glisse radeon_bo_fini(rdev); 3977d4550907SJerome Glisse radeon_atombios_fini(rdev); 3978d4550907SJerome Glisse kfree(rdev->bios); 3979d4550907SJerome Glisse rdev->bios = NULL; 3980d4550907SJerome Glisse } 3981d4550907SJerome Glisse 39824c712e6cSDave Airlie /* 39834c712e6cSDave Airlie * Due to how kexec works, it can leave the hw fully initialised when it 39844c712e6cSDave Airlie * boots the new kernel. However doing our init sequence with the CP and 39854c712e6cSDave Airlie * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 39864c712e6cSDave Airlie * do some quick sanity checks and restore sane values to avoid this 39874c712e6cSDave Airlie * problem. 39884c712e6cSDave Airlie */ 39894c712e6cSDave Airlie void r100_restore_sanity(struct radeon_device *rdev) 39904c712e6cSDave Airlie { 39914c712e6cSDave Airlie u32 tmp; 39924c712e6cSDave Airlie 39934c712e6cSDave Airlie tmp = RREG32(RADEON_CP_CSQ_CNTL); 39944c712e6cSDave Airlie if (tmp) { 39954c712e6cSDave Airlie WREG32(RADEON_CP_CSQ_CNTL, 0); 39964c712e6cSDave Airlie } 39974c712e6cSDave Airlie tmp = RREG32(RADEON_CP_RB_CNTL); 39984c712e6cSDave Airlie if (tmp) { 39994c712e6cSDave Airlie WREG32(RADEON_CP_RB_CNTL, 0); 40004c712e6cSDave Airlie } 40014c712e6cSDave Airlie tmp = RREG32(RADEON_SCRATCH_UMSK); 40024c712e6cSDave Airlie if (tmp) { 40034c712e6cSDave Airlie WREG32(RADEON_SCRATCH_UMSK, 0); 40044c712e6cSDave Airlie } 40054c712e6cSDave Airlie } 40064c712e6cSDave Airlie 4007d4550907SJerome Glisse int r100_init(struct radeon_device *rdev) 4008d4550907SJerome Glisse { 4009d4550907SJerome Glisse int r; 4010d4550907SJerome Glisse 4011d4550907SJerome Glisse /* Register debugfs file specific to this group of asics */ 40125b54d679SNirmoy Das r100_debugfs_mc_info_init(rdev); 4013d4550907SJerome Glisse /* Disable VGA */ 4014d4550907SJerome Glisse r100_vga_render_disable(rdev); 4015d4550907SJerome Glisse /* Initialize scratch registers */ 4016d4550907SJerome Glisse radeon_scratch_init(rdev); 4017d4550907SJerome Glisse /* Initialize surface registers */ 4018d4550907SJerome Glisse radeon_surface_init(rdev); 40194c712e6cSDave Airlie /* sanity check some register to avoid hangs like after kexec */ 40204c712e6cSDave Airlie r100_restore_sanity(rdev); 4021d4550907SJerome Glisse /* TODO: disable VGA need to use VGA request */ 4022d4550907SJerome Glisse /* BIOS*/ 4023d4550907SJerome Glisse if (!radeon_get_bios(rdev)) { 4024d4550907SJerome Glisse if (ASIC_IS_AVIVO(rdev)) 4025d4550907SJerome Glisse return -EINVAL; 4026d4550907SJerome Glisse } 4027d4550907SJerome Glisse if (rdev->is_atom_bios) { 4028d4550907SJerome Glisse dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4029d4550907SJerome Glisse return -EINVAL; 4030d4550907SJerome Glisse } else { 4031d4550907SJerome Glisse r = radeon_combios_init(rdev); 4032d4550907SJerome Glisse if (r) 4033d4550907SJerome Glisse return r; 4034d4550907SJerome Glisse } 4035d4550907SJerome Glisse /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4036a2d07b74SJerome Glisse if (radeon_asic_reset(rdev)) { 4037d4550907SJerome Glisse dev_warn(rdev->dev, 4038d4550907SJerome Glisse "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4039d4550907SJerome Glisse RREG32(R_000E40_RBBM_STATUS), 4040d4550907SJerome Glisse RREG32(R_0007C0_CP_STAT)); 4041d4550907SJerome Glisse } 4042d4550907SJerome Glisse /* check if cards are posted or not */ 404372542d77SDave Airlie if (radeon_boot_test_post_card(rdev) == false) 404472542d77SDave Airlie return -EINVAL; 4045d4550907SJerome Glisse /* Set asic errata */ 4046d4550907SJerome Glisse r100_errata(rdev); 4047d4550907SJerome Glisse /* Initialize clocks */ 4048d4550907SJerome Glisse radeon_get_clock_info(rdev->ddev); 4049d594e46aSJerome Glisse /* initialize AGP */ 4050d594e46aSJerome Glisse if (rdev->flags & RADEON_IS_AGP) { 4051d594e46aSJerome Glisse r = radeon_agp_init(rdev); 4052d594e46aSJerome Glisse if (r) { 4053d594e46aSJerome Glisse radeon_agp_disable(rdev); 4054d594e46aSJerome Glisse } 4055d594e46aSJerome Glisse } 4056d594e46aSJerome Glisse /* initialize VRAM */ 4057d594e46aSJerome Glisse r100_mc_init(rdev); 4058d4550907SJerome Glisse /* Fence driver */ 4059*519424d7SBernard Zhao radeon_fence_driver_init(rdev); 4060d4550907SJerome Glisse /* Memory manager */ 40614c788679SJerome Glisse r = radeon_bo_init(rdev); 4062d4550907SJerome Glisse if (r) 4063d4550907SJerome Glisse return r; 4064d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) { 4065d4550907SJerome Glisse r = r100_pci_gart_init(rdev); 4066d4550907SJerome Glisse if (r) 4067d4550907SJerome Glisse return r; 4068d4550907SJerome Glisse } 4069d4550907SJerome Glisse r100_set_safe_registers(rdev); 4070b15ba512SJerome Glisse 40716c7bcceaSAlex Deucher /* Initialize power management */ 40726c7bcceaSAlex Deucher radeon_pm_init(rdev); 40736c7bcceaSAlex Deucher 4074d4550907SJerome Glisse rdev->accel_working = true; 4075d4550907SJerome Glisse r = r100_startup(rdev); 4076d4550907SJerome Glisse if (r) { 4077d4550907SJerome Glisse /* Somethings want wront with the accel init stop accel */ 4078d4550907SJerome Glisse dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4079d4550907SJerome Glisse r100_cp_fini(rdev); 4080724c80e1SAlex Deucher radeon_wb_fini(rdev); 40812898c348SChristian König radeon_ib_pool_fini(rdev); 4082655efd3dSJerome Glisse radeon_irq_kms_fini(rdev); 4083d4550907SJerome Glisse if (rdev->flags & RADEON_IS_PCI) 4084d4550907SJerome Glisse r100_pci_gart_fini(rdev); 4085d4550907SJerome Glisse rdev->accel_working = false; 4086d4550907SJerome Glisse } 4087d4550907SJerome Glisse return 0; 4088d4550907SJerome Glisse } 40896fcbef7aSAndi Kleen 40909e5acbc2SDenys Vlasenko uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg) 40919e5acbc2SDenys Vlasenko { 40929e5acbc2SDenys Vlasenko unsigned long flags; 40939e5acbc2SDenys Vlasenko uint32_t ret; 40949e5acbc2SDenys Vlasenko 40959e5acbc2SDenys Vlasenko spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 40969e5acbc2SDenys Vlasenko writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 40979e5acbc2SDenys Vlasenko ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 40989e5acbc2SDenys Vlasenko spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 40999e5acbc2SDenys Vlasenko return ret; 41009e5acbc2SDenys Vlasenko } 41019e5acbc2SDenys Vlasenko 41029e5acbc2SDenys Vlasenko void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v) 41039e5acbc2SDenys Vlasenko { 41049e5acbc2SDenys Vlasenko unsigned long flags; 41059e5acbc2SDenys Vlasenko 41069e5acbc2SDenys Vlasenko spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 41079e5acbc2SDenys Vlasenko writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 41089e5acbc2SDenys Vlasenko writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 41099e5acbc2SDenys Vlasenko spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 41109e5acbc2SDenys Vlasenko } 41119e5acbc2SDenys Vlasenko 41126fcbef7aSAndi Kleen u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 41136fcbef7aSAndi Kleen { 41146fcbef7aSAndi Kleen if (reg < rdev->rio_mem_size) 41156fcbef7aSAndi Kleen return ioread32(rdev->rio_mem + reg); 41166fcbef7aSAndi Kleen else { 41176fcbef7aSAndi Kleen iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 41186fcbef7aSAndi Kleen return ioread32(rdev->rio_mem + RADEON_MM_DATA); 41196fcbef7aSAndi Kleen } 41206fcbef7aSAndi Kleen } 41216fcbef7aSAndi Kleen 41226fcbef7aSAndi Kleen void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 41236fcbef7aSAndi Kleen { 41246fcbef7aSAndi Kleen if (reg < rdev->rio_mem_size) 41256fcbef7aSAndi Kleen iowrite32(v, rdev->rio_mem + reg); 41266fcbef7aSAndi Kleen else { 41276fcbef7aSAndi Kleen iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 41286fcbef7aSAndi Kleen iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 41296fcbef7aSAndi Kleen } 41306fcbef7aSAndi Kleen } 4131