1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <linux/backlight.h> 28 #include <linux/dmi.h> 29 #include <linux/pci.h> 30 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/drm_file.h> 33 #include <drm/radeon_drm.h> 34 35 #include <acpi/video.h> 36 37 #include "atom.h" 38 #include "radeon_atombios.h" 39 #include "radeon.h" 40 #include "radeon_asic.h" 41 #include "radeon_audio.h" 42 43 extern int atom_debug; 44 45 static u8 46 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 47 { 48 u8 backlight_level; 49 u32 bios_2_scratch; 50 51 if (rdev->family >= CHIP_R600) 52 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 53 else 54 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 55 56 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 57 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 58 59 return backlight_level; 60 } 61 62 static void 63 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 64 u8 backlight_level) 65 { 66 u32 bios_2_scratch; 67 68 if (rdev->family >= CHIP_R600) 69 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 70 else 71 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 72 73 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 74 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 75 ATOM_S2_CURRENT_BL_LEVEL_MASK); 76 77 if (rdev->family >= CHIP_R600) 78 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 79 else 80 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 81 } 82 83 u8 84 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 85 { 86 struct drm_device *dev = radeon_encoder->base.dev; 87 struct radeon_device *rdev = dev->dev_private; 88 89 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 90 return 0; 91 92 return radeon_atom_get_backlight_level_from_reg(rdev); 93 } 94 95 void 96 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 97 { 98 struct drm_encoder *encoder = &radeon_encoder->base; 99 struct drm_device *dev = radeon_encoder->base.dev; 100 struct radeon_device *rdev = dev->dev_private; 101 struct radeon_encoder_atom_dig *dig; 102 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 103 int index; 104 105 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 106 return; 107 108 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 109 radeon_encoder->enc_priv) { 110 dig = radeon_encoder->enc_priv; 111 dig->backlight_level = level; 112 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 113 114 switch (radeon_encoder->encoder_id) { 115 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 116 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 117 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 118 if (dig->backlight_level == 0) { 119 args.ucAction = ATOM_LCD_BLOFF; 120 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 121 } else { 122 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 123 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 124 args.ucAction = ATOM_LCD_BLON; 125 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 126 } 127 break; 128 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 129 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 130 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 133 if (dig->backlight_level == 0) 134 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 135 else { 136 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 137 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 138 } 139 break; 140 default: 141 break; 142 } 143 } 144 } 145 146 static u8 radeon_atom_bl_level(struct backlight_device *bd) 147 { 148 u8 level; 149 150 /* Convert brightness to hardware level */ 151 if (bd->props.brightness < 0) 152 level = 0; 153 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 154 level = RADEON_MAX_BL_LEVEL; 155 else 156 level = bd->props.brightness; 157 158 return level; 159 } 160 161 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 162 { 163 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 164 struct radeon_encoder *radeon_encoder = pdata->encoder; 165 166 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 167 168 return 0; 169 } 170 171 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 172 { 173 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 174 struct radeon_encoder *radeon_encoder = pdata->encoder; 175 struct drm_device *dev = radeon_encoder->base.dev; 176 struct radeon_device *rdev = dev->dev_private; 177 178 return radeon_atom_get_backlight_level_from_reg(rdev); 179 } 180 181 static const struct backlight_ops radeon_atom_backlight_ops = { 182 .get_brightness = radeon_atom_backlight_get_brightness, 183 .update_status = radeon_atom_backlight_update_status, 184 }; 185 186 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 187 struct drm_connector *drm_connector) 188 { 189 struct drm_device *dev = radeon_encoder->base.dev; 190 struct radeon_device *rdev = dev->dev_private; 191 struct backlight_device *bd; 192 struct backlight_properties props; 193 struct radeon_backlight_privdata *pdata; 194 struct radeon_encoder_atom_dig *dig; 195 char bl_name[16]; 196 197 /* Mac laptops with multiple GPUs use the gmux driver for backlight 198 * so don't register a backlight device 199 */ 200 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 201 (rdev->pdev->device == 0x6741) && 202 !dmi_match(DMI_PRODUCT_NAME, "iMac12,1")) 203 return; 204 205 if (!radeon_encoder->enc_priv) 206 return; 207 208 if (!rdev->is_atom_bios) 209 return; 210 211 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 212 return; 213 214 if (!acpi_video_backlight_use_native()) { 215 drm_info(dev, "Skipping radeon atom DIG backlight registration\n"); 216 return; 217 } 218 219 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 220 if (!pdata) { 221 DRM_ERROR("Memory allocation failed\n"); 222 goto error; 223 } 224 225 memset(&props, 0, sizeof(props)); 226 props.max_brightness = RADEON_MAX_BL_LEVEL; 227 props.type = BACKLIGHT_RAW; 228 snprintf(bl_name, sizeof(bl_name), 229 "radeon_bl%d", dev->primary->index); 230 bd = backlight_device_register(bl_name, drm_connector->kdev, 231 pdata, &radeon_atom_backlight_ops, &props); 232 if (IS_ERR(bd)) { 233 DRM_ERROR("Backlight registration failed\n"); 234 goto error; 235 } 236 237 pdata->encoder = radeon_encoder; 238 239 dig = radeon_encoder->enc_priv; 240 dig->bl_dev = bd; 241 242 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 243 /* Set a reasonable default here if the level is 0 otherwise 244 * fbdev will attempt to turn the backlight on after console 245 * unblanking and it will try and restore 0 which turns the backlight 246 * off again. 247 */ 248 if (bd->props.brightness == 0) 249 bd->props.brightness = RADEON_MAX_BL_LEVEL; 250 bd->props.power = FB_BLANK_UNBLANK; 251 backlight_update_status(bd); 252 253 DRM_INFO("radeon atom DIG backlight initialized\n"); 254 rdev->mode_info.bl_encoder = radeon_encoder; 255 256 return; 257 258 error: 259 kfree(pdata); 260 return; 261 } 262 263 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 264 { 265 struct drm_device *dev = radeon_encoder->base.dev; 266 struct radeon_device *rdev = dev->dev_private; 267 struct backlight_device *bd = NULL; 268 struct radeon_encoder_atom_dig *dig; 269 270 if (!radeon_encoder->enc_priv) 271 return; 272 273 if (!rdev->is_atom_bios) 274 return; 275 276 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 277 return; 278 279 dig = radeon_encoder->enc_priv; 280 bd = dig->bl_dev; 281 dig->bl_dev = NULL; 282 283 if (bd) { 284 struct radeon_legacy_backlight_privdata *pdata; 285 286 pdata = bl_get_data(bd); 287 backlight_device_unregister(bd); 288 kfree(pdata); 289 290 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 291 } 292 } 293 294 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 295 const struct drm_display_mode *mode, 296 struct drm_display_mode *adjusted_mode) 297 { 298 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 299 struct drm_device *dev = encoder->dev; 300 struct radeon_device *rdev = dev->dev_private; 301 302 /* set the active encoder to connector routing */ 303 radeon_encoder_set_active_device(encoder); 304 drm_mode_set_crtcinfo(adjusted_mode, 0); 305 306 /* hw bug */ 307 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 308 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 309 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 310 311 /* vertical FP must be at least 1 */ 312 if (mode->crtc_vsync_start == mode->crtc_vdisplay) 313 adjusted_mode->crtc_vsync_start++; 314 315 /* get the native mode for scaling */ 316 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 317 radeon_panel_mode_fixup(encoder, adjusted_mode); 318 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 319 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 320 if (tv_dac) { 321 if (tv_dac->tv_std == TV_STD_NTSC || 322 tv_dac->tv_std == TV_STD_NTSC_J || 323 tv_dac->tv_std == TV_STD_PAL_M) 324 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 325 else 326 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 327 } 328 } else if (radeon_encoder->rmx_type != RMX_OFF) { 329 radeon_panel_mode_fixup(encoder, adjusted_mode); 330 } 331 332 if (ASIC_IS_DCE3(rdev) && 333 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 334 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 335 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 336 radeon_dp_set_link_config(connector, adjusted_mode); 337 } 338 339 return true; 340 } 341 342 static void 343 atombios_dac_setup(struct drm_encoder *encoder, int action) 344 { 345 struct drm_device *dev = encoder->dev; 346 struct radeon_device *rdev = dev->dev_private; 347 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 348 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 349 int index = 0; 350 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 351 352 memset(&args, 0, sizeof(args)); 353 354 switch (radeon_encoder->encoder_id) { 355 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 356 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 357 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 358 break; 359 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 360 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 361 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 362 break; 363 } 364 365 args.ucAction = action; 366 367 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 368 args.ucDacStandard = ATOM_DAC1_PS2; 369 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 370 args.ucDacStandard = ATOM_DAC1_CV; 371 else { 372 switch (dac_info->tv_std) { 373 case TV_STD_PAL: 374 case TV_STD_PAL_M: 375 case TV_STD_SCART_PAL: 376 case TV_STD_SECAM: 377 case TV_STD_PAL_CN: 378 args.ucDacStandard = ATOM_DAC1_PAL; 379 break; 380 case TV_STD_NTSC: 381 case TV_STD_NTSC_J: 382 case TV_STD_PAL_60: 383 default: 384 args.ucDacStandard = ATOM_DAC1_NTSC; 385 break; 386 } 387 } 388 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 389 390 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 391 392 } 393 394 static void 395 atombios_tv_setup(struct drm_encoder *encoder, int action) 396 { 397 struct drm_device *dev = encoder->dev; 398 struct radeon_device *rdev = dev->dev_private; 399 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 400 TV_ENCODER_CONTROL_PS_ALLOCATION args; 401 int index = 0; 402 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 403 404 memset(&args, 0, sizeof(args)); 405 406 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 407 408 args.sTVEncoder.ucAction = action; 409 410 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 411 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 412 else { 413 switch (dac_info->tv_std) { 414 case TV_STD_NTSC: 415 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 416 break; 417 case TV_STD_PAL: 418 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 419 break; 420 case TV_STD_PAL_M: 421 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 422 break; 423 case TV_STD_PAL_60: 424 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 425 break; 426 case TV_STD_NTSC_J: 427 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 428 break; 429 case TV_STD_SCART_PAL: 430 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 431 break; 432 case TV_STD_SECAM: 433 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 434 break; 435 case TV_STD_PAL_CN: 436 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 437 break; 438 default: 439 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 440 break; 441 } 442 } 443 444 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 445 446 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 447 448 } 449 450 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 451 { 452 int bpc = 8; 453 454 if (encoder->crtc) { 455 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 456 bpc = radeon_crtc->bpc; 457 } 458 459 switch (bpc) { 460 case 0: 461 return PANEL_BPC_UNDEFINE; 462 case 6: 463 return PANEL_6BIT_PER_COLOR; 464 case 8: 465 default: 466 return PANEL_8BIT_PER_COLOR; 467 case 10: 468 return PANEL_10BIT_PER_COLOR; 469 case 12: 470 return PANEL_12BIT_PER_COLOR; 471 case 16: 472 return PANEL_16BIT_PER_COLOR; 473 } 474 } 475 476 union dvo_encoder_control { 477 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 478 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 479 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 480 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 481 }; 482 483 void 484 atombios_dvo_setup(struct drm_encoder *encoder, int action) 485 { 486 struct drm_device *dev = encoder->dev; 487 struct radeon_device *rdev = dev->dev_private; 488 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 489 union dvo_encoder_control args; 490 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 491 uint8_t frev, crev; 492 493 memset(&args, 0, sizeof(args)); 494 495 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 496 return; 497 498 /* some R4xx chips have the wrong frev */ 499 if (rdev->family <= CHIP_RV410) 500 frev = 1; 501 502 switch (frev) { 503 case 1: 504 switch (crev) { 505 case 1: 506 /* R4xx, R5xx */ 507 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 508 509 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 510 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 511 512 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 513 break; 514 case 2: 515 /* RS600/690/740 */ 516 args.dvo.sDVOEncoder.ucAction = action; 517 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 518 /* DFP1, CRT1, TV1 depending on the type of port */ 519 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 520 521 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 522 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 523 break; 524 case 3: 525 /* R6xx */ 526 args.dvo_v3.ucAction = action; 527 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 528 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 529 break; 530 case 4: 531 /* DCE8 */ 532 args.dvo_v4.ucAction = action; 533 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 534 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 535 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 536 break; 537 default: 538 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 539 break; 540 } 541 break; 542 default: 543 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 544 break; 545 } 546 547 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 548 } 549 550 union lvds_encoder_control { 551 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 552 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 553 }; 554 555 void 556 atombios_digital_setup(struct drm_encoder *encoder, int action) 557 { 558 struct drm_device *dev = encoder->dev; 559 struct radeon_device *rdev = dev->dev_private; 560 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 561 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 562 union lvds_encoder_control args; 563 int index = 0; 564 int hdmi_detected = 0; 565 uint8_t frev, crev; 566 567 if (!dig) 568 return; 569 570 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 571 hdmi_detected = 1; 572 573 memset(&args, 0, sizeof(args)); 574 575 switch (radeon_encoder->encoder_id) { 576 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 577 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 578 break; 579 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 580 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 581 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 582 break; 583 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 584 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 585 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 586 else 587 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 588 break; 589 } 590 591 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 592 return; 593 594 switch (frev) { 595 case 1: 596 case 2: 597 switch (crev) { 598 case 1: 599 args.v1.ucMisc = 0; 600 args.v1.ucAction = action; 601 if (hdmi_detected) 602 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 603 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 604 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 605 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 606 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 607 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 608 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 609 } else { 610 if (dig->linkb) 611 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 612 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 613 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 614 /*if (pScrn->rgbBits == 8) */ 615 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 616 } 617 break; 618 case 2: 619 case 3: 620 args.v2.ucMisc = 0; 621 args.v2.ucAction = action; 622 if (crev == 3) { 623 if (dig->coherent_mode) 624 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 625 } 626 if (hdmi_detected) 627 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 628 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 629 args.v2.ucTruncate = 0; 630 args.v2.ucSpatial = 0; 631 args.v2.ucTemporal = 0; 632 args.v2.ucFRC = 0; 633 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 634 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 635 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 636 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 637 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 638 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 639 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 640 } 641 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 642 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 643 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 644 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 645 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 646 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 647 } 648 } else { 649 if (dig->linkb) 650 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 651 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 652 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 653 } 654 break; 655 default: 656 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 657 break; 658 } 659 break; 660 default: 661 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 662 break; 663 } 664 665 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 666 } 667 668 int 669 atombios_get_encoder_mode(struct drm_encoder *encoder) 670 { 671 struct drm_device *dev = encoder->dev; 672 struct radeon_device *rdev = dev->dev_private; 673 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 674 struct drm_connector *connector; 675 struct radeon_connector *radeon_connector; 676 struct radeon_connector_atom_dig *dig_connector; 677 struct radeon_encoder_atom_dig *dig_enc; 678 679 if (radeon_encoder_is_digital(encoder)) { 680 dig_enc = radeon_encoder->enc_priv; 681 if (dig_enc->active_mst_links) 682 return ATOM_ENCODER_MODE_DP_MST; 683 } 684 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset) 685 return ATOM_ENCODER_MODE_DP_MST; 686 /* dp bridges are always DP */ 687 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 688 return ATOM_ENCODER_MODE_DP; 689 690 /* DVO is always DVO */ 691 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 692 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 693 return ATOM_ENCODER_MODE_DVO; 694 695 connector = radeon_get_connector_for_encoder(encoder); 696 /* if we don't have an active device yet, just use one of 697 * the connectors tied to the encoder. 698 */ 699 if (!connector) 700 connector = radeon_get_connector_for_encoder_init(encoder); 701 radeon_connector = to_radeon_connector(connector); 702 703 switch (connector->connector_type) { 704 case DRM_MODE_CONNECTOR_DVII: 705 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 706 if (radeon_audio != 0) { 707 if (radeon_connector->use_digital && 708 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 709 return ATOM_ENCODER_MODE_HDMI; 710 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 711 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 712 return ATOM_ENCODER_MODE_HDMI; 713 else if (radeon_connector->use_digital) 714 return ATOM_ENCODER_MODE_DVI; 715 else 716 return ATOM_ENCODER_MODE_CRT; 717 } else if (radeon_connector->use_digital) { 718 return ATOM_ENCODER_MODE_DVI; 719 } else { 720 return ATOM_ENCODER_MODE_CRT; 721 } 722 break; 723 case DRM_MODE_CONNECTOR_DVID: 724 case DRM_MODE_CONNECTOR_HDMIA: 725 default: 726 if (radeon_audio != 0) { 727 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 728 return ATOM_ENCODER_MODE_HDMI; 729 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 730 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 731 return ATOM_ENCODER_MODE_HDMI; 732 else 733 return ATOM_ENCODER_MODE_DVI; 734 } else { 735 return ATOM_ENCODER_MODE_DVI; 736 } 737 break; 738 case DRM_MODE_CONNECTOR_LVDS: 739 return ATOM_ENCODER_MODE_LVDS; 740 break; 741 case DRM_MODE_CONNECTOR_DisplayPort: 742 dig_connector = radeon_connector->con_priv; 743 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 744 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 745 if (radeon_audio != 0 && 746 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 747 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 748 return ATOM_ENCODER_MODE_DP_AUDIO; 749 return ATOM_ENCODER_MODE_DP; 750 } else if (radeon_audio != 0) { 751 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 752 return ATOM_ENCODER_MODE_HDMI; 753 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 754 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 755 return ATOM_ENCODER_MODE_HDMI; 756 else 757 return ATOM_ENCODER_MODE_DVI; 758 } else { 759 return ATOM_ENCODER_MODE_DVI; 760 } 761 break; 762 case DRM_MODE_CONNECTOR_eDP: 763 if (radeon_audio != 0 && 764 drm_detect_monitor_audio(radeon_connector_edid(connector)) && 765 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 766 return ATOM_ENCODER_MODE_DP_AUDIO; 767 return ATOM_ENCODER_MODE_DP; 768 case DRM_MODE_CONNECTOR_DVIA: 769 case DRM_MODE_CONNECTOR_VGA: 770 return ATOM_ENCODER_MODE_CRT; 771 break; 772 case DRM_MODE_CONNECTOR_Composite: 773 case DRM_MODE_CONNECTOR_SVIDEO: 774 case DRM_MODE_CONNECTOR_9PinDIN: 775 /* fix me */ 776 return ATOM_ENCODER_MODE_TV; 777 /*return ATOM_ENCODER_MODE_CV;*/ 778 break; 779 } 780 } 781 782 /* 783 * DIG Encoder/Transmitter Setup 784 * 785 * DCE 3.0/3.1 786 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 787 * Supports up to 3 digital outputs 788 * - 2 DIG encoder blocks. 789 * DIG1 can drive UNIPHY link A or link B 790 * DIG2 can drive UNIPHY link B or LVTMA 791 * 792 * DCE 3.2 793 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 794 * Supports up to 5 digital outputs 795 * - 2 DIG encoder blocks. 796 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 797 * 798 * DCE 4.0/5.0/6.0 799 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 800 * Supports up to 6 digital outputs 801 * - 6 DIG encoder blocks. 802 * - DIG to PHY mapping is hardcoded 803 * DIG1 drives UNIPHY0 link A, A+B 804 * DIG2 drives UNIPHY0 link B 805 * DIG3 drives UNIPHY1 link A, A+B 806 * DIG4 drives UNIPHY1 link B 807 * DIG5 drives UNIPHY2 link A, A+B 808 * DIG6 drives UNIPHY2 link B 809 * 810 * DCE 4.1 811 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 812 * Supports up to 6 digital outputs 813 * - 2 DIG encoder blocks. 814 * llano 815 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 816 * ontario 817 * DIG1 drives UNIPHY0/1/2 link A 818 * DIG2 drives UNIPHY0/1/2 link B 819 * 820 * Routing 821 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 822 * Examples: 823 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 824 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 825 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 826 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 827 */ 828 829 union dig_encoder_control { 830 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 831 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 832 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 833 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 834 }; 835 836 void 837 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override) 838 { 839 struct drm_device *dev = encoder->dev; 840 struct radeon_device *rdev = dev->dev_private; 841 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 842 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 843 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 844 union dig_encoder_control args; 845 int index = 0; 846 uint8_t frev, crev; 847 int dp_clock = 0; 848 int dp_lane_count = 0; 849 int hpd_id = RADEON_HPD_NONE; 850 851 if (connector) { 852 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 853 struct radeon_connector_atom_dig *dig_connector = 854 radeon_connector->con_priv; 855 856 dp_clock = dig_connector->dp_clock; 857 dp_lane_count = dig_connector->dp_lane_count; 858 hpd_id = radeon_connector->hpd.hpd; 859 } 860 861 /* no dig encoder assigned */ 862 if (dig->dig_encoder == -1) 863 return; 864 865 memset(&args, 0, sizeof(args)); 866 867 if (ASIC_IS_DCE4(rdev)) 868 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 869 else { 870 if (dig->dig_encoder) 871 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 872 else 873 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 874 } 875 876 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 877 return; 878 879 switch (frev) { 880 case 1: 881 switch (crev) { 882 case 1: 883 args.v1.ucAction = action; 884 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 885 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 886 args.v3.ucPanelMode = panel_mode; 887 else 888 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 889 890 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 891 args.v1.ucLaneNum = dp_lane_count; 892 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 893 args.v1.ucLaneNum = 8; 894 else 895 args.v1.ucLaneNum = 4; 896 897 switch (radeon_encoder->encoder_id) { 898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 899 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 900 break; 901 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 902 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 903 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 904 break; 905 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 906 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 907 break; 908 } 909 if (dig->linkb) 910 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 911 else 912 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 913 914 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 915 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 916 917 break; 918 case 2: 919 case 3: 920 args.v3.ucAction = action; 921 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 922 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 923 args.v3.ucPanelMode = panel_mode; 924 else 925 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 926 927 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 928 args.v3.ucLaneNum = dp_lane_count; 929 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 930 args.v3.ucLaneNum = 8; 931 else 932 args.v3.ucLaneNum = 4; 933 934 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 935 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 936 if (enc_override != -1) 937 args.v3.acConfig.ucDigSel = enc_override; 938 else 939 args.v3.acConfig.ucDigSel = dig->dig_encoder; 940 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 941 break; 942 case 4: 943 args.v4.ucAction = action; 944 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 945 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 946 args.v4.ucPanelMode = panel_mode; 947 else 948 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 949 950 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 951 args.v4.ucLaneNum = dp_lane_count; 952 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 953 args.v4.ucLaneNum = 8; 954 else 955 args.v4.ucLaneNum = 4; 956 957 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 958 if (dp_clock == 540000) 959 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 960 else if (dp_clock == 324000) 961 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 962 else if (dp_clock == 270000) 963 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 964 else 965 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 966 } 967 968 if (enc_override != -1) 969 args.v4.acConfig.ucDigSel = enc_override; 970 else 971 args.v4.acConfig.ucDigSel = dig->dig_encoder; 972 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 973 if (hpd_id == RADEON_HPD_NONE) 974 args.v4.ucHPD_ID = 0; 975 else 976 args.v4.ucHPD_ID = hpd_id + 1; 977 break; 978 default: 979 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 980 break; 981 } 982 break; 983 default: 984 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 985 break; 986 } 987 988 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 989 990 } 991 992 void 993 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 994 { 995 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1); 996 } 997 998 union dig_transmitter_control { 999 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 1000 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 1001 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 1002 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 1003 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 1004 }; 1005 1006 void 1007 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe) 1008 { 1009 struct drm_device *dev = encoder->dev; 1010 struct radeon_device *rdev = dev->dev_private; 1011 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1012 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1013 struct drm_connector *connector; 1014 union dig_transmitter_control args; 1015 int index = 0; 1016 uint8_t frev, crev; 1017 bool is_dp = false; 1018 int pll_id = 0; 1019 int dp_clock = 0; 1020 int dp_lane_count = 0; 1021 int connector_object_id = 0; 1022 int igp_lane_info = 0; 1023 int dig_encoder = dig->dig_encoder; 1024 int hpd_id = RADEON_HPD_NONE; 1025 1026 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1027 connector = radeon_get_connector_for_encoder_init(encoder); 1028 /* just needed to avoid bailing in the encoder check. the encoder 1029 * isn't used for init 1030 */ 1031 dig_encoder = 0; 1032 } else 1033 connector = radeon_get_connector_for_encoder(encoder); 1034 1035 if (connector) { 1036 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1037 struct radeon_connector_atom_dig *dig_connector = 1038 radeon_connector->con_priv; 1039 1040 hpd_id = radeon_connector->hpd.hpd; 1041 dp_clock = dig_connector->dp_clock; 1042 dp_lane_count = dig_connector->dp_lane_count; 1043 connector_object_id = 1044 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1045 igp_lane_info = dig_connector->igp_lane_info; 1046 } 1047 1048 if (encoder->crtc) { 1049 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1050 pll_id = radeon_crtc->pll_id; 1051 } 1052 1053 /* no dig encoder assigned */ 1054 if (dig_encoder == -1) 1055 return; 1056 1057 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1058 is_dp = true; 1059 1060 memset(&args, 0, sizeof(args)); 1061 1062 switch (radeon_encoder->encoder_id) { 1063 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1064 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1065 break; 1066 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1067 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1068 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1069 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1070 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1071 break; 1072 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1073 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1074 break; 1075 } 1076 1077 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1078 return; 1079 1080 switch (frev) { 1081 case 1: 1082 switch (crev) { 1083 case 1: 1084 args.v1.ucAction = action; 1085 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1086 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1087 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1088 args.v1.asMode.ucLaneSel = lane_num; 1089 args.v1.asMode.ucLaneSet = lane_set; 1090 } else { 1091 if (is_dp) 1092 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1093 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1094 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1095 else 1096 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1097 } 1098 1099 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1100 1101 if (dig_encoder) 1102 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1103 else 1104 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1105 1106 if ((rdev->flags & RADEON_IS_IGP) && 1107 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1108 if (is_dp || 1109 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1110 if (igp_lane_info & 0x1) 1111 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1112 else if (igp_lane_info & 0x2) 1113 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1114 else if (igp_lane_info & 0x4) 1115 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1116 else if (igp_lane_info & 0x8) 1117 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1118 } else { 1119 if (igp_lane_info & 0x3) 1120 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1121 else if (igp_lane_info & 0xc) 1122 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1123 } 1124 } 1125 1126 if (dig->linkb) 1127 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1128 else 1129 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1130 1131 if (is_dp) 1132 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1133 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1134 if (dig->coherent_mode) 1135 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1136 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1137 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1138 } 1139 break; 1140 case 2: 1141 args.v2.ucAction = action; 1142 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1143 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1144 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1145 args.v2.asMode.ucLaneSel = lane_num; 1146 args.v2.asMode.ucLaneSet = lane_set; 1147 } else { 1148 if (is_dp) 1149 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1150 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1151 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1152 else 1153 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1154 } 1155 1156 args.v2.acConfig.ucEncoderSel = dig_encoder; 1157 if (dig->linkb) 1158 args.v2.acConfig.ucLinkSel = 1; 1159 1160 switch (radeon_encoder->encoder_id) { 1161 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1162 args.v2.acConfig.ucTransmitterSel = 0; 1163 break; 1164 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1165 args.v2.acConfig.ucTransmitterSel = 1; 1166 break; 1167 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1168 args.v2.acConfig.ucTransmitterSel = 2; 1169 break; 1170 } 1171 1172 if (is_dp) { 1173 args.v2.acConfig.fCoherentMode = 1; 1174 args.v2.acConfig.fDPConnector = 1; 1175 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1176 if (dig->coherent_mode) 1177 args.v2.acConfig.fCoherentMode = 1; 1178 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1179 args.v2.acConfig.fDualLinkConnector = 1; 1180 } 1181 break; 1182 case 3: 1183 args.v3.ucAction = action; 1184 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1185 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1186 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1187 args.v3.asMode.ucLaneSel = lane_num; 1188 args.v3.asMode.ucLaneSet = lane_set; 1189 } else { 1190 if (is_dp) 1191 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1192 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1193 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1194 else 1195 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1196 } 1197 1198 if (is_dp) 1199 args.v3.ucLaneNum = dp_lane_count; 1200 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1201 args.v3.ucLaneNum = 8; 1202 else 1203 args.v3.ucLaneNum = 4; 1204 1205 if (dig->linkb) 1206 args.v3.acConfig.ucLinkSel = 1; 1207 if (dig_encoder & 1) 1208 args.v3.acConfig.ucEncoderSel = 1; 1209 1210 /* Select the PLL for the PHY 1211 * DP PHY should be clocked from external src if there is 1212 * one. 1213 */ 1214 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1215 if (is_dp && rdev->clock.dp_extclk) 1216 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1217 else 1218 args.v3.acConfig.ucRefClkSource = pll_id; 1219 1220 switch (radeon_encoder->encoder_id) { 1221 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1222 args.v3.acConfig.ucTransmitterSel = 0; 1223 break; 1224 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1225 args.v3.acConfig.ucTransmitterSel = 1; 1226 break; 1227 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1228 args.v3.acConfig.ucTransmitterSel = 2; 1229 break; 1230 } 1231 1232 if (is_dp) 1233 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1234 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1235 if (dig->coherent_mode) 1236 args.v3.acConfig.fCoherentMode = 1; 1237 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1238 args.v3.acConfig.fDualLinkConnector = 1; 1239 } 1240 break; 1241 case 4: 1242 args.v4.ucAction = action; 1243 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1244 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1245 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1246 args.v4.asMode.ucLaneSel = lane_num; 1247 args.v4.asMode.ucLaneSet = lane_set; 1248 } else { 1249 if (is_dp) 1250 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1251 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1252 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1253 else 1254 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1255 } 1256 1257 if (is_dp) 1258 args.v4.ucLaneNum = dp_lane_count; 1259 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1260 args.v4.ucLaneNum = 8; 1261 else 1262 args.v4.ucLaneNum = 4; 1263 1264 if (dig->linkb) 1265 args.v4.acConfig.ucLinkSel = 1; 1266 if (dig_encoder & 1) 1267 args.v4.acConfig.ucEncoderSel = 1; 1268 1269 /* Select the PLL for the PHY 1270 * DP PHY should be clocked from external src if there is 1271 * one. 1272 */ 1273 /* On DCE5 DCPLL usually generates the DP ref clock */ 1274 if (is_dp) { 1275 if (rdev->clock.dp_extclk) 1276 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1277 else 1278 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1279 } else 1280 args.v4.acConfig.ucRefClkSource = pll_id; 1281 1282 switch (radeon_encoder->encoder_id) { 1283 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1284 args.v4.acConfig.ucTransmitterSel = 0; 1285 break; 1286 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1287 args.v4.acConfig.ucTransmitterSel = 1; 1288 break; 1289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1290 args.v4.acConfig.ucTransmitterSel = 2; 1291 break; 1292 } 1293 1294 if (is_dp) 1295 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1296 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1297 if (dig->coherent_mode) 1298 args.v4.acConfig.fCoherentMode = 1; 1299 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1300 args.v4.acConfig.fDualLinkConnector = 1; 1301 } 1302 break; 1303 case 5: 1304 args.v5.ucAction = action; 1305 if (is_dp) 1306 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1307 else 1308 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1309 1310 switch (radeon_encoder->encoder_id) { 1311 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1312 if (dig->linkb) 1313 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1314 else 1315 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1316 break; 1317 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1318 if (dig->linkb) 1319 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1320 else 1321 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1322 break; 1323 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1324 if (dig->linkb) 1325 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1326 else 1327 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1328 break; 1329 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1330 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1331 break; 1332 } 1333 if (is_dp) 1334 args.v5.ucLaneNum = dp_lane_count; 1335 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1336 args.v5.ucLaneNum = 8; 1337 else 1338 args.v5.ucLaneNum = 4; 1339 args.v5.ucConnObjId = connector_object_id; 1340 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1341 1342 if (is_dp && rdev->clock.dp_extclk) 1343 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1344 else 1345 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1346 1347 if (is_dp) 1348 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1349 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1350 if (dig->coherent_mode) 1351 args.v5.asConfig.ucCoherentMode = 1; 1352 } 1353 if (hpd_id == RADEON_HPD_NONE) 1354 args.v5.asConfig.ucHPDSel = 0; 1355 else 1356 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1357 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder); 1358 args.v5.ucDPLaneSet = lane_set; 1359 break; 1360 default: 1361 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1362 break; 1363 } 1364 break; 1365 default: 1366 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1367 break; 1368 } 1369 1370 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1371 } 1372 1373 void 1374 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 1375 { 1376 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1); 1377 } 1378 1379 bool 1380 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1381 { 1382 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1383 struct drm_device *dev = radeon_connector->base.dev; 1384 struct radeon_device *rdev = dev->dev_private; 1385 union dig_transmitter_control args; 1386 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1387 uint8_t frev, crev; 1388 1389 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1390 goto done; 1391 1392 if (!ASIC_IS_DCE4(rdev)) 1393 goto done; 1394 1395 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1396 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1397 goto done; 1398 1399 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1400 goto done; 1401 1402 memset(&args, 0, sizeof(args)); 1403 1404 args.v1.ucAction = action; 1405 1406 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1407 1408 /* wait for the panel to power up */ 1409 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1410 int i; 1411 1412 for (i = 0; i < 300; i++) { 1413 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1414 return true; 1415 mdelay(1); 1416 } 1417 return false; 1418 } 1419 done: 1420 return true; 1421 } 1422 1423 union external_encoder_control { 1424 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1425 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1426 }; 1427 1428 static void 1429 atombios_external_encoder_setup(struct drm_encoder *encoder, 1430 struct drm_encoder *ext_encoder, 1431 int action) 1432 { 1433 struct drm_device *dev = encoder->dev; 1434 struct radeon_device *rdev = dev->dev_private; 1435 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1436 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1437 union external_encoder_control args; 1438 struct drm_connector *connector; 1439 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1440 u8 frev, crev; 1441 int dp_clock = 0; 1442 int dp_lane_count = 0; 1443 int connector_object_id = 0; 1444 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1445 1446 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1447 connector = radeon_get_connector_for_encoder_init(encoder); 1448 else 1449 connector = radeon_get_connector_for_encoder(encoder); 1450 1451 if (connector) { 1452 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1453 struct radeon_connector_atom_dig *dig_connector = 1454 radeon_connector->con_priv; 1455 1456 dp_clock = dig_connector->dp_clock; 1457 dp_lane_count = dig_connector->dp_lane_count; 1458 connector_object_id = 1459 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1460 } 1461 1462 memset(&args, 0, sizeof(args)); 1463 1464 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1465 return; 1466 1467 switch (frev) { 1468 case 1: 1469 /* no params on frev 1 */ 1470 break; 1471 case 2: 1472 switch (crev) { 1473 case 1: 1474 case 2: 1475 args.v1.sDigEncoder.ucAction = action; 1476 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1477 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1478 1479 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1480 if (dp_clock == 270000) 1481 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1482 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1483 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1484 args.v1.sDigEncoder.ucLaneNum = 8; 1485 else 1486 args.v1.sDigEncoder.ucLaneNum = 4; 1487 break; 1488 case 3: 1489 args.v3.sExtEncoder.ucAction = action; 1490 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1491 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1492 else 1493 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1494 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1495 1496 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1497 if (dp_clock == 270000) 1498 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1499 else if (dp_clock == 540000) 1500 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1501 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1502 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1503 args.v3.sExtEncoder.ucLaneNum = 8; 1504 else 1505 args.v3.sExtEncoder.ucLaneNum = 4; 1506 switch (ext_enum) { 1507 case GRAPH_OBJECT_ENUM_ID1: 1508 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1509 break; 1510 case GRAPH_OBJECT_ENUM_ID2: 1511 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1512 break; 1513 case GRAPH_OBJECT_ENUM_ID3: 1514 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1515 break; 1516 } 1517 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1518 break; 1519 default: 1520 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1521 return; 1522 } 1523 break; 1524 default: 1525 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1526 return; 1527 } 1528 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1529 } 1530 1531 static void 1532 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1533 { 1534 struct drm_device *dev = encoder->dev; 1535 struct radeon_device *rdev = dev->dev_private; 1536 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1537 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1538 ENABLE_YUV_PS_ALLOCATION args; 1539 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1540 uint32_t temp, reg; 1541 1542 memset(&args, 0, sizeof(args)); 1543 1544 if (rdev->family >= CHIP_R600) 1545 reg = R600_BIOS_3_SCRATCH; 1546 else 1547 reg = RADEON_BIOS_3_SCRATCH; 1548 1549 /* XXX: fix up scratch reg handling */ 1550 temp = RREG32(reg); 1551 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1552 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1553 (radeon_crtc->crtc_id << 18))); 1554 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1555 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1556 else 1557 WREG32(reg, 0); 1558 1559 if (enable) 1560 args.ucEnable = ATOM_ENABLE; 1561 args.ucCRTC = radeon_crtc->crtc_id; 1562 1563 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1564 1565 WREG32(reg, temp); 1566 } 1567 1568 static void 1569 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1570 { 1571 struct drm_device *dev = encoder->dev; 1572 struct radeon_device *rdev = dev->dev_private; 1573 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1574 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1575 int index = 0; 1576 1577 memset(&args, 0, sizeof(args)); 1578 1579 switch (radeon_encoder->encoder_id) { 1580 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1581 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1582 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1583 break; 1584 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1585 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1586 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1587 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1588 break; 1589 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1590 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1591 break; 1592 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1593 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1594 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1595 else 1596 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1597 break; 1598 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1599 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1600 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1601 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1602 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1603 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1604 else 1605 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1606 break; 1607 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1608 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1609 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1610 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1611 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1612 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1613 else 1614 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1615 break; 1616 default: 1617 return; 1618 } 1619 1620 switch (mode) { 1621 case DRM_MODE_DPMS_ON: 1622 args.ucAction = ATOM_ENABLE; 1623 /* workaround for DVOOutputControl on some RS690 systems */ 1624 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1625 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1626 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1627 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1628 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1629 } else 1630 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1631 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1632 if (rdev->mode_info.bl_encoder) { 1633 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1634 1635 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1636 } else { 1637 args.ucAction = ATOM_LCD_BLON; 1638 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1639 } 1640 } 1641 break; 1642 case DRM_MODE_DPMS_STANDBY: 1643 case DRM_MODE_DPMS_SUSPEND: 1644 case DRM_MODE_DPMS_OFF: 1645 args.ucAction = ATOM_DISABLE; 1646 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1647 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1648 args.ucAction = ATOM_LCD_BLOFF; 1649 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1650 } 1651 break; 1652 } 1653 } 1654 1655 static void 1656 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1657 { 1658 struct drm_device *dev = encoder->dev; 1659 struct radeon_device *rdev = dev->dev_private; 1660 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1661 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1662 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1663 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1664 struct radeon_connector *radeon_connector = NULL; 1665 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1666 bool travis_quirk = false; 1667 1668 if (connector) { 1669 radeon_connector = to_radeon_connector(connector); 1670 radeon_dig_connector = radeon_connector->con_priv; 1671 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 1672 ENCODER_OBJECT_ID_TRAVIS) && 1673 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 1674 !ASIC_IS_DCE5(rdev)) 1675 travis_quirk = true; 1676 } 1677 1678 switch (mode) { 1679 case DRM_MODE_DPMS_ON: 1680 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1681 if (!connector) 1682 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1683 else 1684 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1685 1686 /* setup and enable the encoder */ 1687 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1688 atombios_dig_encoder_setup(encoder, 1689 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1690 dig->panel_mode); 1691 if (ext_encoder) { 1692 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1693 atombios_external_encoder_setup(encoder, ext_encoder, 1694 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1695 } 1696 } else if (ASIC_IS_DCE4(rdev)) { 1697 /* setup and enable the encoder */ 1698 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1699 } else { 1700 /* setup and enable the encoder and transmitter */ 1701 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1702 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1703 } 1704 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1705 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1706 atombios_set_edp_panel_power(connector, 1707 ATOM_TRANSMITTER_ACTION_POWER_ON); 1708 radeon_dig_connector->edp_on = true; 1709 } 1710 } 1711 /* enable the transmitter */ 1712 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1713 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1714 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ 1715 radeon_dp_link_train(encoder, connector); 1716 if (ASIC_IS_DCE4(rdev)) 1717 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1718 } 1719 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1720 if (rdev->mode_info.bl_encoder) 1721 atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1722 else 1723 atombios_dig_transmitter_setup(encoder, 1724 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1725 } 1726 if (ext_encoder) 1727 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1728 break; 1729 case DRM_MODE_DPMS_STANDBY: 1730 case DRM_MODE_DPMS_SUSPEND: 1731 case DRM_MODE_DPMS_OFF: 1732 1733 /* don't power off encoders with active MST links */ 1734 if (dig->active_mst_links) 1735 return; 1736 1737 if (ASIC_IS_DCE4(rdev)) { 1738 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) 1739 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1740 } 1741 if (ext_encoder) 1742 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1743 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1744 atombios_dig_transmitter_setup(encoder, 1745 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1746 1747 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && 1748 connector && !travis_quirk) 1749 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1750 if (ASIC_IS_DCE4(rdev)) { 1751 /* disable the transmitter */ 1752 atombios_dig_transmitter_setup(encoder, 1753 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1754 } else { 1755 /* disable the encoder and transmitter */ 1756 atombios_dig_transmitter_setup(encoder, 1757 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1758 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1759 } 1760 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1761 if (travis_quirk) 1762 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1763 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1764 atombios_set_edp_panel_power(connector, 1765 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1766 radeon_dig_connector->edp_on = false; 1767 } 1768 } 1769 break; 1770 } 1771 } 1772 1773 static void 1774 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1775 { 1776 struct drm_device *dev = encoder->dev; 1777 struct radeon_device *rdev = dev->dev_private; 1778 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1779 int encoder_mode = atombios_get_encoder_mode(encoder); 1780 1781 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1782 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1783 radeon_encoder->active_device); 1784 1785 if ((radeon_audio != 0) && 1786 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 1787 ENCODER_MODE_IS_DP(encoder_mode))) 1788 radeon_audio_dpms(encoder, mode); 1789 1790 switch (radeon_encoder->encoder_id) { 1791 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1792 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1793 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1794 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1795 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1796 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1797 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1798 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1799 radeon_atom_encoder_dpms_avivo(encoder, mode); 1800 break; 1801 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1802 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1803 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1804 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1805 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1806 radeon_atom_encoder_dpms_dig(encoder, mode); 1807 break; 1808 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1809 if (ASIC_IS_DCE5(rdev)) { 1810 switch (mode) { 1811 case DRM_MODE_DPMS_ON: 1812 atombios_dvo_setup(encoder, ATOM_ENABLE); 1813 break; 1814 case DRM_MODE_DPMS_STANDBY: 1815 case DRM_MODE_DPMS_SUSPEND: 1816 case DRM_MODE_DPMS_OFF: 1817 atombios_dvo_setup(encoder, ATOM_DISABLE); 1818 break; 1819 } 1820 } else if (ASIC_IS_DCE3(rdev)) 1821 radeon_atom_encoder_dpms_dig(encoder, mode); 1822 else 1823 radeon_atom_encoder_dpms_avivo(encoder, mode); 1824 break; 1825 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1826 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1827 if (ASIC_IS_DCE5(rdev)) { 1828 switch (mode) { 1829 case DRM_MODE_DPMS_ON: 1830 atombios_dac_setup(encoder, ATOM_ENABLE); 1831 break; 1832 case DRM_MODE_DPMS_STANDBY: 1833 case DRM_MODE_DPMS_SUSPEND: 1834 case DRM_MODE_DPMS_OFF: 1835 atombios_dac_setup(encoder, ATOM_DISABLE); 1836 break; 1837 } 1838 } else 1839 radeon_atom_encoder_dpms_avivo(encoder, mode); 1840 break; 1841 default: 1842 return; 1843 } 1844 1845 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1846 1847 } 1848 1849 union crtc_source_param { 1850 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1851 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1852 }; 1853 1854 static void 1855 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1856 { 1857 struct drm_device *dev = encoder->dev; 1858 struct radeon_device *rdev = dev->dev_private; 1859 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1860 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1861 union crtc_source_param args; 1862 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1863 uint8_t frev, crev; 1864 struct radeon_encoder_atom_dig *dig; 1865 1866 memset(&args, 0, sizeof(args)); 1867 1868 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1869 return; 1870 1871 switch (frev) { 1872 case 1: 1873 switch (crev) { 1874 case 1: 1875 default: 1876 if (ASIC_IS_AVIVO(rdev)) 1877 args.v1.ucCRTC = radeon_crtc->crtc_id; 1878 else { 1879 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) 1880 args.v1.ucCRTC = radeon_crtc->crtc_id; 1881 else 1882 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1883 } 1884 switch (radeon_encoder->encoder_id) { 1885 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1886 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1887 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1888 break; 1889 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1890 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1891 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1892 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1893 else 1894 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1895 break; 1896 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1897 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1898 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1899 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1900 break; 1901 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1902 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1903 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1904 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1905 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1906 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1907 else 1908 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1909 break; 1910 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1911 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1912 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1913 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1914 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1915 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1916 else 1917 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1918 break; 1919 } 1920 break; 1921 case 2: 1922 args.v2.ucCRTC = radeon_crtc->crtc_id; 1923 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1924 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1925 1926 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1927 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1928 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1929 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1930 else 1931 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1932 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1933 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1934 } else { 1935 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1936 } 1937 switch (radeon_encoder->encoder_id) { 1938 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1939 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1940 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1941 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1942 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1943 dig = radeon_encoder->enc_priv; 1944 switch (dig->dig_encoder) { 1945 case 0: 1946 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1947 break; 1948 case 1: 1949 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1950 break; 1951 case 2: 1952 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1953 break; 1954 case 3: 1955 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1956 break; 1957 case 4: 1958 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1959 break; 1960 case 5: 1961 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1962 break; 1963 case 6: 1964 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1965 break; 1966 } 1967 break; 1968 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1969 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1970 break; 1971 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1972 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1973 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1974 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1975 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1976 else 1977 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1978 break; 1979 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1980 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1981 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1982 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1983 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1984 else 1985 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1986 break; 1987 } 1988 break; 1989 } 1990 break; 1991 default: 1992 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1993 return; 1994 } 1995 1996 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1997 1998 /* update scratch regs with new routing */ 1999 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 2000 } 2001 2002 void 2003 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe) 2004 { 2005 struct drm_device *dev = encoder->dev; 2006 struct radeon_device *rdev = dev->dev_private; 2007 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2008 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 2009 uint8_t frev, crev; 2010 union crtc_source_param args; 2011 2012 memset(&args, 0, sizeof(args)); 2013 2014 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2015 return; 2016 2017 if (frev != 1 && crev != 2) 2018 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev); 2019 2020 args.v2.ucCRTC = radeon_crtc->crtc_id; 2021 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST; 2022 2023 switch (fe) { 2024 case 0: 2025 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 2026 break; 2027 case 1: 2028 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 2029 break; 2030 case 2: 2031 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 2032 break; 2033 case 3: 2034 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 2035 break; 2036 case 4: 2037 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 2038 break; 2039 case 5: 2040 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 2041 break; 2042 case 6: 2043 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 2044 break; 2045 } 2046 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2047 } 2048 2049 static void 2050 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 2051 struct drm_display_mode *mode) 2052 { 2053 struct drm_device *dev = encoder->dev; 2054 struct radeon_device *rdev = dev->dev_private; 2055 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2056 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2057 2058 /* Funky macbooks */ 2059 if ((rdev->pdev->device == 0x71C5) && 2060 (rdev->pdev->subsystem_vendor == 0x106b) && 2061 (rdev->pdev->subsystem_device == 0x0080)) { 2062 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 2063 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 2064 2065 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 2066 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 2067 2068 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 2069 } 2070 } 2071 2072 /* set scaler clears this on some chips */ 2073 if (ASIC_IS_AVIVO(rdev) && 2074 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 2075 if (ASIC_IS_DCE8(rdev)) { 2076 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2077 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 2078 CIK_INTERLEAVE_EN); 2079 else 2080 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2081 } else if (ASIC_IS_DCE4(rdev)) { 2082 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2083 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 2084 EVERGREEN_INTERLEAVE_EN); 2085 else 2086 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2087 } else { 2088 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2089 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2090 AVIVO_D1MODE_INTERLEAVE_EN); 2091 else 2092 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2093 } 2094 } 2095 } 2096 2097 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx) 2098 { 2099 if (enc_idx < 0) 2100 return; 2101 rdev->mode_info.active_encoders &= ~(1 << enc_idx); 2102 } 2103 2104 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx) 2105 { 2106 struct drm_device *dev = encoder->dev; 2107 struct radeon_device *rdev = dev->dev_private; 2108 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2109 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2110 struct drm_encoder *test_encoder; 2111 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2112 uint32_t dig_enc_in_use = 0; 2113 int enc_idx = -1; 2114 2115 if (fe_idx >= 0) { 2116 enc_idx = fe_idx; 2117 goto assigned; 2118 } 2119 if (ASIC_IS_DCE6(rdev)) { 2120 /* DCE6 */ 2121 switch (radeon_encoder->encoder_id) { 2122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2123 if (dig->linkb) 2124 enc_idx = 1; 2125 else 2126 enc_idx = 0; 2127 break; 2128 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2129 if (dig->linkb) 2130 enc_idx = 3; 2131 else 2132 enc_idx = 2; 2133 break; 2134 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2135 if (dig->linkb) 2136 enc_idx = 5; 2137 else 2138 enc_idx = 4; 2139 break; 2140 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2141 enc_idx = 6; 2142 break; 2143 } 2144 goto assigned; 2145 } else if (ASIC_IS_DCE4(rdev)) { 2146 /* DCE4/5 */ 2147 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2148 /* ontario follows DCE4 */ 2149 if (rdev->family == CHIP_PALM) { 2150 if (dig->linkb) 2151 enc_idx = 1; 2152 else 2153 enc_idx = 0; 2154 } else 2155 /* llano follows DCE3.2 */ 2156 enc_idx = radeon_crtc->crtc_id; 2157 } else { 2158 switch (radeon_encoder->encoder_id) { 2159 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2160 if (dig->linkb) 2161 enc_idx = 1; 2162 else 2163 enc_idx = 0; 2164 break; 2165 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2166 if (dig->linkb) 2167 enc_idx = 3; 2168 else 2169 enc_idx = 2; 2170 break; 2171 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2172 if (dig->linkb) 2173 enc_idx = 5; 2174 else 2175 enc_idx = 4; 2176 break; 2177 } 2178 } 2179 goto assigned; 2180 } 2181 2182 /* 2183 * On DCE32 any encoder can drive any block so usually just use crtc id, 2184 * but Apple thinks different at least on iMac10,1, so there use linkb, 2185 * otherwise the internal eDP panel will stay dark. 2186 */ 2187 if (ASIC_IS_DCE32(rdev)) { 2188 if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1")) 2189 enc_idx = (dig->linkb) ? 1 : 0; 2190 else 2191 enc_idx = radeon_crtc->crtc_id; 2192 2193 goto assigned; 2194 } 2195 2196 /* on DCE3 - LVTMA can only be driven by DIGB */ 2197 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2198 struct radeon_encoder *radeon_test_encoder; 2199 2200 if (encoder == test_encoder) 2201 continue; 2202 2203 if (!radeon_encoder_is_digital(test_encoder)) 2204 continue; 2205 2206 radeon_test_encoder = to_radeon_encoder(test_encoder); 2207 dig = radeon_test_encoder->enc_priv; 2208 2209 if (dig->dig_encoder >= 0) 2210 dig_enc_in_use |= (1 << dig->dig_encoder); 2211 } 2212 2213 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2214 if (dig_enc_in_use & 0x2) 2215 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2216 return 1; 2217 } 2218 if (!(dig_enc_in_use & 1)) 2219 return 0; 2220 return 1; 2221 2222 assigned: 2223 if (enc_idx == -1) { 2224 DRM_ERROR("Got encoder index incorrect - returning 0\n"); 2225 return 0; 2226 } 2227 if (rdev->mode_info.active_encoders & (1 << enc_idx)) 2228 DRM_ERROR("chosen encoder in use %d\n", enc_idx); 2229 2230 rdev->mode_info.active_encoders |= (1 << enc_idx); 2231 return enc_idx; 2232 } 2233 2234 /* This only needs to be called once at startup */ 2235 void 2236 radeon_atom_encoder_init(struct radeon_device *rdev) 2237 { 2238 struct drm_device *dev = rdev->ddev; 2239 struct drm_encoder *encoder; 2240 2241 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2242 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2243 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2244 2245 switch (radeon_encoder->encoder_id) { 2246 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2247 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2248 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2249 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2250 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2251 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2252 break; 2253 default: 2254 break; 2255 } 2256 2257 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2258 atombios_external_encoder_setup(encoder, ext_encoder, 2259 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2260 } 2261 } 2262 2263 static void 2264 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2265 struct drm_display_mode *mode, 2266 struct drm_display_mode *adjusted_mode) 2267 { 2268 struct drm_device *dev = encoder->dev; 2269 struct radeon_device *rdev = dev->dev_private; 2270 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2271 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2272 int encoder_mode; 2273 2274 radeon_encoder->pixel_clock = adjusted_mode->clock; 2275 2276 /* need to call this here rather than in prepare() since we need some crtc info */ 2277 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2278 2279 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2280 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2281 atombios_yuv_setup(encoder, true); 2282 else 2283 atombios_yuv_setup(encoder, false); 2284 } 2285 2286 switch (radeon_encoder->encoder_id) { 2287 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2288 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2289 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2290 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2291 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2292 break; 2293 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2294 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2295 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2296 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2297 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2298 /* handled in dpms */ 2299 break; 2300 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2301 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2302 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2303 atombios_dvo_setup(encoder, ATOM_ENABLE); 2304 break; 2305 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2306 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2307 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2308 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2309 atombios_dac_setup(encoder, ATOM_ENABLE); 2310 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2311 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2312 atombios_tv_setup(encoder, ATOM_ENABLE); 2313 else 2314 atombios_tv_setup(encoder, ATOM_DISABLE); 2315 } 2316 break; 2317 } 2318 2319 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2320 2321 encoder_mode = atombios_get_encoder_mode(encoder); 2322 if (connector && (radeon_audio != 0) && 2323 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 2324 ENCODER_MODE_IS_DP(encoder_mode))) 2325 radeon_audio_mode_set(encoder, adjusted_mode); 2326 } 2327 2328 static bool 2329 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2330 { 2331 struct drm_device *dev = encoder->dev; 2332 struct radeon_device *rdev = dev->dev_private; 2333 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2334 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2335 2336 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2337 ATOM_DEVICE_CV_SUPPORT | 2338 ATOM_DEVICE_CRT_SUPPORT)) { 2339 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2340 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2341 uint8_t frev, crev; 2342 2343 memset(&args, 0, sizeof(args)); 2344 2345 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2346 return false; 2347 2348 args.sDacload.ucMisc = 0; 2349 2350 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2351 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2352 args.sDacload.ucDacType = ATOM_DAC_A; 2353 else 2354 args.sDacload.ucDacType = ATOM_DAC_B; 2355 2356 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2357 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2358 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2359 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2360 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2361 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2362 if (crev >= 3) 2363 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2364 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2365 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2366 if (crev >= 3) 2367 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2368 } 2369 2370 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2371 2372 return true; 2373 } else 2374 return false; 2375 } 2376 2377 static enum drm_connector_status 2378 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2379 { 2380 struct drm_device *dev = encoder->dev; 2381 struct radeon_device *rdev = dev->dev_private; 2382 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2383 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2384 uint32_t bios_0_scratch; 2385 2386 if (!atombios_dac_load_detect(encoder, connector)) { 2387 DRM_DEBUG_KMS("detect returned false \n"); 2388 return connector_status_unknown; 2389 } 2390 2391 if (rdev->family >= CHIP_R600) 2392 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2393 else 2394 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2395 2396 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2397 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2398 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2399 return connector_status_connected; 2400 } 2401 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2402 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2403 return connector_status_connected; 2404 } 2405 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2406 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2407 return connector_status_connected; 2408 } 2409 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2410 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2411 return connector_status_connected; /* CTV */ 2412 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2413 return connector_status_connected; /* STV */ 2414 } 2415 return connector_status_disconnected; 2416 } 2417 2418 static enum drm_connector_status 2419 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2420 { 2421 struct drm_device *dev = encoder->dev; 2422 struct radeon_device *rdev = dev->dev_private; 2423 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2424 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2425 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2426 u32 bios_0_scratch; 2427 2428 if (!ASIC_IS_DCE4(rdev)) 2429 return connector_status_unknown; 2430 2431 if (!ext_encoder) 2432 return connector_status_unknown; 2433 2434 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2435 return connector_status_unknown; 2436 2437 /* load detect on the dp bridge */ 2438 atombios_external_encoder_setup(encoder, ext_encoder, 2439 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2440 2441 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2442 2443 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2444 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2445 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2446 return connector_status_connected; 2447 } 2448 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2449 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2450 return connector_status_connected; 2451 } 2452 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2453 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2454 return connector_status_connected; 2455 } 2456 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2457 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2458 return connector_status_connected; /* CTV */ 2459 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2460 return connector_status_connected; /* STV */ 2461 } 2462 return connector_status_disconnected; 2463 } 2464 2465 void 2466 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2467 { 2468 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2469 2470 if (ext_encoder) 2471 /* ddc_setup on the dp bridge */ 2472 atombios_external_encoder_setup(encoder, ext_encoder, 2473 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2474 2475 } 2476 2477 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2478 { 2479 struct radeon_device *rdev = encoder->dev->dev_private; 2480 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2481 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2482 2483 if ((radeon_encoder->active_device & 2484 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2485 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2486 ENCODER_OBJECT_ID_NONE)) { 2487 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2488 if (dig) { 2489 if (dig->dig_encoder >= 0) 2490 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2491 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1); 2492 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2493 if (rdev->family >= CHIP_R600) 2494 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2495 else 2496 /* RS600/690/740 have only 1 afmt block */ 2497 dig->afmt = rdev->mode_info.afmt[0]; 2498 } 2499 } 2500 } 2501 2502 radeon_atom_output_lock(encoder, true); 2503 2504 if (connector) { 2505 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2506 2507 /* select the clock/data port if it uses a router */ 2508 if (radeon_connector->router.cd_valid) 2509 radeon_router_select_cd_port(radeon_connector); 2510 2511 /* turn eDP panel on for mode set */ 2512 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2513 atombios_set_edp_panel_power(connector, 2514 ATOM_TRANSMITTER_ACTION_POWER_ON); 2515 } 2516 2517 /* this is needed for the pll/ss setup to work correctly in some cases */ 2518 atombios_set_encoder_crtc_source(encoder); 2519 /* set up the FMT blocks */ 2520 if (ASIC_IS_DCE8(rdev)) 2521 dce8_program_fmt(encoder); 2522 else if (ASIC_IS_DCE4(rdev)) 2523 dce4_program_fmt(encoder); 2524 else if (ASIC_IS_DCE3(rdev)) 2525 dce3_program_fmt(encoder); 2526 else if (ASIC_IS_AVIVO(rdev)) 2527 avivo_program_fmt(encoder); 2528 } 2529 2530 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2531 { 2532 /* need to call this here as we need the crtc set up */ 2533 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2534 radeon_atom_output_lock(encoder, false); 2535 } 2536 2537 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2538 { 2539 struct drm_device *dev = encoder->dev; 2540 struct radeon_device *rdev = dev->dev_private; 2541 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2542 struct radeon_encoder_atom_dig *dig; 2543 2544 /* check for pre-DCE3 cards with shared encoders; 2545 * can't really use the links individually, so don't disable 2546 * the encoder if it's in use by another connector 2547 */ 2548 if (!ASIC_IS_DCE3(rdev)) { 2549 struct drm_encoder *other_encoder; 2550 struct radeon_encoder *other_radeon_encoder; 2551 2552 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2553 other_radeon_encoder = to_radeon_encoder(other_encoder); 2554 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2555 drm_helper_encoder_in_use(other_encoder)) 2556 goto disable_done; 2557 } 2558 } 2559 2560 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2561 2562 switch (radeon_encoder->encoder_id) { 2563 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2564 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2565 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2566 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2567 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2568 break; 2569 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2570 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2571 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2572 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2573 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2574 /* handled in dpms */ 2575 break; 2576 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2577 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2578 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2579 atombios_dvo_setup(encoder, ATOM_DISABLE); 2580 break; 2581 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2582 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2583 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2584 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2585 atombios_dac_setup(encoder, ATOM_DISABLE); 2586 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2587 atombios_tv_setup(encoder, ATOM_DISABLE); 2588 break; 2589 } 2590 2591 disable_done: 2592 if (radeon_encoder_is_digital(encoder)) { 2593 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2594 if (rdev->asic->display.hdmi_enable) 2595 radeon_hdmi_enable(rdev, encoder, false); 2596 } 2597 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) { 2598 dig = radeon_encoder->enc_priv; 2599 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 2600 dig->dig_encoder = -1; 2601 radeon_encoder->active_device = 0; 2602 } 2603 } else 2604 radeon_encoder->active_device = 0; 2605 } 2606 2607 /* these are handled by the primary encoders */ 2608 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2609 { 2610 2611 } 2612 2613 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2614 { 2615 2616 } 2617 2618 static void 2619 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2620 struct drm_display_mode *mode, 2621 struct drm_display_mode *adjusted_mode) 2622 { 2623 2624 } 2625 2626 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2627 { 2628 2629 } 2630 2631 static void 2632 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2633 { 2634 2635 } 2636 2637 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2638 .dpms = radeon_atom_ext_dpms, 2639 .prepare = radeon_atom_ext_prepare, 2640 .mode_set = radeon_atom_ext_mode_set, 2641 .commit = radeon_atom_ext_commit, 2642 .disable = radeon_atom_ext_disable, 2643 /* no detect for TMDS/LVDS yet */ 2644 }; 2645 2646 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2647 .dpms = radeon_atom_encoder_dpms, 2648 .mode_fixup = radeon_atom_mode_fixup, 2649 .prepare = radeon_atom_encoder_prepare, 2650 .mode_set = radeon_atom_encoder_mode_set, 2651 .commit = radeon_atom_encoder_commit, 2652 .disable = radeon_atom_encoder_disable, 2653 .detect = radeon_atom_dig_detect, 2654 }; 2655 2656 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2657 .dpms = radeon_atom_encoder_dpms, 2658 .mode_fixup = radeon_atom_mode_fixup, 2659 .prepare = radeon_atom_encoder_prepare, 2660 .mode_set = radeon_atom_encoder_mode_set, 2661 .commit = radeon_atom_encoder_commit, 2662 .detect = radeon_atom_dac_detect, 2663 }; 2664 2665 void radeon_enc_destroy(struct drm_encoder *encoder) 2666 { 2667 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2668 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2669 radeon_atom_backlight_exit(radeon_encoder); 2670 kfree(radeon_encoder->enc_priv); 2671 drm_encoder_cleanup(encoder); 2672 kfree(radeon_encoder); 2673 } 2674 2675 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2676 .destroy = radeon_enc_destroy, 2677 }; 2678 2679 static struct radeon_encoder_atom_dac * 2680 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2681 { 2682 struct drm_device *dev = radeon_encoder->base.dev; 2683 struct radeon_device *rdev = dev->dev_private; 2684 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2685 2686 if (!dac) 2687 return NULL; 2688 2689 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2690 return dac; 2691 } 2692 2693 static struct radeon_encoder_atom_dig * 2694 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2695 { 2696 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2697 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2698 2699 if (!dig) 2700 return NULL; 2701 2702 /* coherent mode by default */ 2703 dig->coherent_mode = true; 2704 dig->dig_encoder = -1; 2705 2706 if (encoder_enum == 2) 2707 dig->linkb = true; 2708 else 2709 dig->linkb = false; 2710 2711 return dig; 2712 } 2713 2714 void 2715 radeon_add_atom_encoder(struct drm_device *dev, 2716 uint32_t encoder_enum, 2717 uint32_t supported_device, 2718 u16 caps) 2719 { 2720 struct radeon_device *rdev = dev->dev_private; 2721 struct drm_encoder *encoder; 2722 struct radeon_encoder *radeon_encoder; 2723 2724 /* see if we already added it */ 2725 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2726 radeon_encoder = to_radeon_encoder(encoder); 2727 if (radeon_encoder->encoder_enum == encoder_enum) { 2728 radeon_encoder->devices |= supported_device; 2729 return; 2730 } 2731 2732 } 2733 2734 /* add a new one */ 2735 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2736 if (!radeon_encoder) 2737 return; 2738 2739 encoder = &radeon_encoder->base; 2740 switch (rdev->num_crtc) { 2741 case 1: 2742 encoder->possible_crtcs = 0x1; 2743 break; 2744 case 2: 2745 default: 2746 encoder->possible_crtcs = 0x3; 2747 break; 2748 case 4: 2749 encoder->possible_crtcs = 0xf; 2750 break; 2751 case 6: 2752 encoder->possible_crtcs = 0x3f; 2753 break; 2754 } 2755 2756 radeon_encoder->enc_priv = NULL; 2757 2758 radeon_encoder->encoder_enum = encoder_enum; 2759 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2760 radeon_encoder->devices = supported_device; 2761 radeon_encoder->rmx_type = RMX_OFF; 2762 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2763 radeon_encoder->is_ext_encoder = false; 2764 radeon_encoder->caps = caps; 2765 2766 switch (radeon_encoder->encoder_id) { 2767 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2768 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2769 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2770 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2771 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2772 radeon_encoder->rmx_type = RMX_FULL; 2773 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2774 DRM_MODE_ENCODER_LVDS, NULL); 2775 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2776 } else { 2777 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2778 DRM_MODE_ENCODER_TMDS, NULL); 2779 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2780 } 2781 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2782 break; 2783 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2784 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2785 DRM_MODE_ENCODER_DAC, NULL); 2786 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2787 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2788 break; 2789 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2790 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2791 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2792 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2793 DRM_MODE_ENCODER_TVDAC, NULL); 2794 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2795 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2796 break; 2797 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2798 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2799 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2800 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2801 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2802 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2803 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2804 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2805 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2806 radeon_encoder->rmx_type = RMX_FULL; 2807 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2808 DRM_MODE_ENCODER_LVDS, NULL); 2809 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2810 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2811 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2812 DRM_MODE_ENCODER_DAC, NULL); 2813 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2814 } else { 2815 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2816 DRM_MODE_ENCODER_TMDS, NULL); 2817 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2818 } 2819 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2820 break; 2821 case ENCODER_OBJECT_ID_SI170B: 2822 case ENCODER_OBJECT_ID_CH7303: 2823 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2824 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2825 case ENCODER_OBJECT_ID_TITFP513: 2826 case ENCODER_OBJECT_ID_VT1623: 2827 case ENCODER_OBJECT_ID_HDMI_SI1930: 2828 case ENCODER_OBJECT_ID_TRAVIS: 2829 case ENCODER_OBJECT_ID_NUTMEG: 2830 /* these are handled by the primary encoders */ 2831 radeon_encoder->is_ext_encoder = true; 2832 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2833 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2834 DRM_MODE_ENCODER_LVDS, NULL); 2835 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2836 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2837 DRM_MODE_ENCODER_DAC, NULL); 2838 else 2839 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 2840 DRM_MODE_ENCODER_TMDS, NULL); 2841 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2842 break; 2843 } 2844 } 2845