1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "atom.h" 31 #include <linux/backlight.h> 32 33 extern int atom_debug; 34 35 static u8 36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 37 { 38 u8 backlight_level; 39 u32 bios_2_scratch; 40 41 if (rdev->family >= CHIP_R600) 42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 43 else 44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 45 46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 48 49 return backlight_level; 50 } 51 52 static void 53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 54 u8 backlight_level) 55 { 56 u32 bios_2_scratch; 57 58 if (rdev->family >= CHIP_R600) 59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 60 else 61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 62 63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 65 ATOM_S2_CURRENT_BL_LEVEL_MASK); 66 67 if (rdev->family >= CHIP_R600) 68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 69 else 70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 71 } 72 73 u8 74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 75 { 76 struct drm_device *dev = radeon_encoder->base.dev; 77 struct radeon_device *rdev = dev->dev_private; 78 79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 80 return 0; 81 82 return radeon_atom_get_backlight_level_from_reg(rdev); 83 } 84 85 void 86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 87 { 88 struct drm_encoder *encoder = &radeon_encoder->base; 89 struct drm_device *dev = radeon_encoder->base.dev; 90 struct radeon_device *rdev = dev->dev_private; 91 struct radeon_encoder_atom_dig *dig; 92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 93 int index; 94 95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 96 return; 97 98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 99 radeon_encoder->enc_priv) { 100 dig = radeon_encoder->enc_priv; 101 dig->backlight_level = level; 102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 103 104 switch (radeon_encoder->encoder_id) { 105 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 108 if (dig->backlight_level == 0) { 109 args.ucAction = ATOM_LCD_BLOFF; 110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 111 } else { 112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 114 args.ucAction = ATOM_LCD_BLON; 115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 116 } 117 break; 118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 122 if (dig->backlight_level == 0) 123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 124 else { 125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 127 } 128 break; 129 default: 130 break; 131 } 132 } 133 } 134 135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 136 137 static u8 radeon_atom_bl_level(struct backlight_device *bd) 138 { 139 u8 level; 140 141 /* Convert brightness to hardware level */ 142 if (bd->props.brightness < 0) 143 level = 0; 144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 145 level = RADEON_MAX_BL_LEVEL; 146 else 147 level = bd->props.brightness; 148 149 return level; 150 } 151 152 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 153 { 154 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 155 struct radeon_encoder *radeon_encoder = pdata->encoder; 156 157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 158 159 return 0; 160 } 161 162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 163 { 164 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 165 struct radeon_encoder *radeon_encoder = pdata->encoder; 166 struct drm_device *dev = radeon_encoder->base.dev; 167 struct radeon_device *rdev = dev->dev_private; 168 169 return radeon_atom_get_backlight_level_from_reg(rdev); 170 } 171 172 static const struct backlight_ops radeon_atom_backlight_ops = { 173 .get_brightness = radeon_atom_backlight_get_brightness, 174 .update_status = radeon_atom_backlight_update_status, 175 }; 176 177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 178 struct drm_connector *drm_connector) 179 { 180 struct drm_device *dev = radeon_encoder->base.dev; 181 struct radeon_device *rdev = dev->dev_private; 182 struct backlight_device *bd; 183 struct backlight_properties props; 184 struct radeon_backlight_privdata *pdata; 185 struct radeon_encoder_atom_dig *dig; 186 char bl_name[16]; 187 188 /* Mac laptops with multiple GPUs use the gmux driver for backlight 189 * so don't register a backlight device 190 */ 191 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 192 (rdev->pdev->device == 0x6741)) 193 return; 194 195 if (!radeon_encoder->enc_priv) 196 return; 197 198 if (!rdev->is_atom_bios) 199 return; 200 201 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 202 return; 203 204 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 205 if (!pdata) { 206 DRM_ERROR("Memory allocation failed\n"); 207 goto error; 208 } 209 210 memset(&props, 0, sizeof(props)); 211 props.max_brightness = RADEON_MAX_BL_LEVEL; 212 props.type = BACKLIGHT_RAW; 213 snprintf(bl_name, sizeof(bl_name), 214 "radeon_bl%d", dev->primary->index); 215 bd = backlight_device_register(bl_name, drm_connector->kdev, 216 pdata, &radeon_atom_backlight_ops, &props); 217 if (IS_ERR(bd)) { 218 DRM_ERROR("Backlight registration failed\n"); 219 goto error; 220 } 221 222 pdata->encoder = radeon_encoder; 223 224 dig = radeon_encoder->enc_priv; 225 dig->bl_dev = bd; 226 227 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 228 /* Set a reasonable default here if the level is 0 otherwise 229 * fbdev will attempt to turn the backlight on after console 230 * unblanking and it will try and restore 0 which turns the backlight 231 * off again. 232 */ 233 if (bd->props.brightness == 0) 234 bd->props.brightness = RADEON_MAX_BL_LEVEL; 235 bd->props.power = FB_BLANK_UNBLANK; 236 backlight_update_status(bd); 237 238 DRM_INFO("radeon atom DIG backlight initialized\n"); 239 240 return; 241 242 error: 243 kfree(pdata); 244 return; 245 } 246 247 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 248 { 249 struct drm_device *dev = radeon_encoder->base.dev; 250 struct radeon_device *rdev = dev->dev_private; 251 struct backlight_device *bd = NULL; 252 struct radeon_encoder_atom_dig *dig; 253 254 if (!radeon_encoder->enc_priv) 255 return; 256 257 if (!rdev->is_atom_bios) 258 return; 259 260 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 261 return; 262 263 dig = radeon_encoder->enc_priv; 264 bd = dig->bl_dev; 265 dig->bl_dev = NULL; 266 267 if (bd) { 268 struct radeon_legacy_backlight_privdata *pdata; 269 270 pdata = bl_get_data(bd); 271 backlight_device_unregister(bd); 272 kfree(pdata); 273 274 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 275 } 276 } 277 278 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 279 280 void radeon_atom_backlight_init(struct radeon_encoder *encoder) 281 { 282 } 283 284 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 285 { 286 } 287 288 #endif 289 290 /* evil but including atombios.h is much worse */ 291 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 292 struct drm_display_mode *mode); 293 294 295 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 296 { 297 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 298 switch (radeon_encoder->encoder_id) { 299 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 300 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 301 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 302 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 303 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 304 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 305 case ENCODER_OBJECT_ID_INTERNAL_DDI: 306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 307 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 308 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 309 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 310 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 311 return true; 312 default: 313 return false; 314 } 315 } 316 317 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 318 const struct drm_display_mode *mode, 319 struct drm_display_mode *adjusted_mode) 320 { 321 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 322 struct drm_device *dev = encoder->dev; 323 struct radeon_device *rdev = dev->dev_private; 324 325 /* set the active encoder to connector routing */ 326 radeon_encoder_set_active_device(encoder); 327 drm_mode_set_crtcinfo(adjusted_mode, 0); 328 329 /* hw bug */ 330 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 331 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 332 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 333 334 /* get the native mode for scaling */ 335 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 336 radeon_panel_mode_fixup(encoder, adjusted_mode); 337 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 338 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 339 if (tv_dac) { 340 if (tv_dac->tv_std == TV_STD_NTSC || 341 tv_dac->tv_std == TV_STD_NTSC_J || 342 tv_dac->tv_std == TV_STD_PAL_M) 343 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 344 else 345 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 346 } 347 } else if (radeon_encoder->rmx_type != RMX_OFF) { 348 radeon_panel_mode_fixup(encoder, adjusted_mode); 349 } 350 351 if (ASIC_IS_DCE3(rdev) && 352 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 353 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 354 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 355 radeon_dp_set_link_config(connector, adjusted_mode); 356 } 357 358 return true; 359 } 360 361 static void 362 atombios_dac_setup(struct drm_encoder *encoder, int action) 363 { 364 struct drm_device *dev = encoder->dev; 365 struct radeon_device *rdev = dev->dev_private; 366 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 367 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 368 int index = 0; 369 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 370 371 memset(&args, 0, sizeof(args)); 372 373 switch (radeon_encoder->encoder_id) { 374 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 376 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 377 break; 378 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 379 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 380 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 381 break; 382 } 383 384 args.ucAction = action; 385 386 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 387 args.ucDacStandard = ATOM_DAC1_PS2; 388 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 389 args.ucDacStandard = ATOM_DAC1_CV; 390 else { 391 switch (dac_info->tv_std) { 392 case TV_STD_PAL: 393 case TV_STD_PAL_M: 394 case TV_STD_SCART_PAL: 395 case TV_STD_SECAM: 396 case TV_STD_PAL_CN: 397 args.ucDacStandard = ATOM_DAC1_PAL; 398 break; 399 case TV_STD_NTSC: 400 case TV_STD_NTSC_J: 401 case TV_STD_PAL_60: 402 default: 403 args.ucDacStandard = ATOM_DAC1_NTSC; 404 break; 405 } 406 } 407 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 408 409 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 410 411 } 412 413 static void 414 atombios_tv_setup(struct drm_encoder *encoder, int action) 415 { 416 struct drm_device *dev = encoder->dev; 417 struct radeon_device *rdev = dev->dev_private; 418 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 419 TV_ENCODER_CONTROL_PS_ALLOCATION args; 420 int index = 0; 421 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 422 423 memset(&args, 0, sizeof(args)); 424 425 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 426 427 args.sTVEncoder.ucAction = action; 428 429 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 430 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 431 else { 432 switch (dac_info->tv_std) { 433 case TV_STD_NTSC: 434 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 435 break; 436 case TV_STD_PAL: 437 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 438 break; 439 case TV_STD_PAL_M: 440 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 441 break; 442 case TV_STD_PAL_60: 443 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 444 break; 445 case TV_STD_NTSC_J: 446 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 447 break; 448 case TV_STD_SCART_PAL: 449 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 450 break; 451 case TV_STD_SECAM: 452 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 453 break; 454 case TV_STD_PAL_CN: 455 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 456 break; 457 default: 458 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 459 break; 460 } 461 } 462 463 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 464 465 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 466 467 } 468 469 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 470 { 471 int bpc = 8; 472 473 if (encoder->crtc) { 474 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 475 bpc = radeon_crtc->bpc; 476 } 477 478 switch (bpc) { 479 case 0: 480 return PANEL_BPC_UNDEFINE; 481 case 6: 482 return PANEL_6BIT_PER_COLOR; 483 case 8: 484 default: 485 return PANEL_8BIT_PER_COLOR; 486 case 10: 487 return PANEL_10BIT_PER_COLOR; 488 case 12: 489 return PANEL_12BIT_PER_COLOR; 490 case 16: 491 return PANEL_16BIT_PER_COLOR; 492 } 493 } 494 495 union dvo_encoder_control { 496 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 497 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 498 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 499 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 500 }; 501 502 void 503 atombios_dvo_setup(struct drm_encoder *encoder, int action) 504 { 505 struct drm_device *dev = encoder->dev; 506 struct radeon_device *rdev = dev->dev_private; 507 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 508 union dvo_encoder_control args; 509 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 510 uint8_t frev, crev; 511 512 memset(&args, 0, sizeof(args)); 513 514 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 515 return; 516 517 /* some R4xx chips have the wrong frev */ 518 if (rdev->family <= CHIP_RV410) 519 frev = 1; 520 521 switch (frev) { 522 case 1: 523 switch (crev) { 524 case 1: 525 /* R4xx, R5xx */ 526 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 527 528 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 529 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 530 531 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 532 break; 533 case 2: 534 /* RS600/690/740 */ 535 args.dvo.sDVOEncoder.ucAction = action; 536 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 537 /* DFP1, CRT1, TV1 depending on the type of port */ 538 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 539 540 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 541 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 542 break; 543 case 3: 544 /* R6xx */ 545 args.dvo_v3.ucAction = action; 546 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 547 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 548 break; 549 case 4: 550 /* DCE8 */ 551 args.dvo_v4.ucAction = action; 552 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 553 args.dvo_v4.ucDVOConfig = 0; /* XXX */ 554 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 555 break; 556 default: 557 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 558 break; 559 } 560 break; 561 default: 562 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 563 break; 564 } 565 566 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 567 } 568 569 union lvds_encoder_control { 570 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 571 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 572 }; 573 574 void 575 atombios_digital_setup(struct drm_encoder *encoder, int action) 576 { 577 struct drm_device *dev = encoder->dev; 578 struct radeon_device *rdev = dev->dev_private; 579 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 580 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 581 union lvds_encoder_control args; 582 int index = 0; 583 int hdmi_detected = 0; 584 uint8_t frev, crev; 585 586 if (!dig) 587 return; 588 589 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 590 hdmi_detected = 1; 591 592 memset(&args, 0, sizeof(args)); 593 594 switch (radeon_encoder->encoder_id) { 595 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 596 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 597 break; 598 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 599 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 600 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 601 break; 602 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 603 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 604 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 605 else 606 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 607 break; 608 } 609 610 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 611 return; 612 613 switch (frev) { 614 case 1: 615 case 2: 616 switch (crev) { 617 case 1: 618 args.v1.ucMisc = 0; 619 args.v1.ucAction = action; 620 if (hdmi_detected) 621 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 622 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 623 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 624 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 625 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 626 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 627 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 628 } else { 629 if (dig->linkb) 630 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 631 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 632 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 633 /*if (pScrn->rgbBits == 8) */ 634 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 635 } 636 break; 637 case 2: 638 case 3: 639 args.v2.ucMisc = 0; 640 args.v2.ucAction = action; 641 if (crev == 3) { 642 if (dig->coherent_mode) 643 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 644 } 645 if (hdmi_detected) 646 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 647 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 648 args.v2.ucTruncate = 0; 649 args.v2.ucSpatial = 0; 650 args.v2.ucTemporal = 0; 651 args.v2.ucFRC = 0; 652 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 653 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 654 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 655 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 656 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 657 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 658 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 659 } 660 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 661 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 662 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 663 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 664 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 665 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 666 } 667 } else { 668 if (dig->linkb) 669 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 670 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 671 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 672 } 673 break; 674 default: 675 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 676 break; 677 } 678 break; 679 default: 680 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 681 break; 682 } 683 684 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 685 } 686 687 int 688 atombios_get_encoder_mode(struct drm_encoder *encoder) 689 { 690 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 691 struct drm_connector *connector; 692 struct radeon_connector *radeon_connector; 693 struct radeon_connector_atom_dig *dig_connector; 694 695 /* dp bridges are always DP */ 696 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 697 return ATOM_ENCODER_MODE_DP; 698 699 /* DVO is always DVO */ 700 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 701 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 702 return ATOM_ENCODER_MODE_DVO; 703 704 connector = radeon_get_connector_for_encoder(encoder); 705 /* if we don't have an active device yet, just use one of 706 * the connectors tied to the encoder. 707 */ 708 if (!connector) 709 connector = radeon_get_connector_for_encoder_init(encoder); 710 radeon_connector = to_radeon_connector(connector); 711 712 switch (connector->connector_type) { 713 case DRM_MODE_CONNECTOR_DVII: 714 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 715 if (radeon_audio != 0) { 716 if (radeon_connector->use_digital && 717 (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 718 return ATOM_ENCODER_MODE_HDMI; 719 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 720 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 721 return ATOM_ENCODER_MODE_HDMI; 722 else if (radeon_connector->use_digital) 723 return ATOM_ENCODER_MODE_DVI; 724 else 725 return ATOM_ENCODER_MODE_CRT; 726 } else if (radeon_connector->use_digital) { 727 return ATOM_ENCODER_MODE_DVI; 728 } else { 729 return ATOM_ENCODER_MODE_CRT; 730 } 731 break; 732 case DRM_MODE_CONNECTOR_DVID: 733 case DRM_MODE_CONNECTOR_HDMIA: 734 default: 735 if (radeon_audio != 0) { 736 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 737 return ATOM_ENCODER_MODE_HDMI; 738 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 739 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 740 return ATOM_ENCODER_MODE_HDMI; 741 else 742 return ATOM_ENCODER_MODE_DVI; 743 } else { 744 return ATOM_ENCODER_MODE_DVI; 745 } 746 break; 747 case DRM_MODE_CONNECTOR_LVDS: 748 return ATOM_ENCODER_MODE_LVDS; 749 break; 750 case DRM_MODE_CONNECTOR_DisplayPort: 751 dig_connector = radeon_connector->con_priv; 752 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 753 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 754 return ATOM_ENCODER_MODE_DP; 755 } else if (radeon_audio != 0) { 756 if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 757 return ATOM_ENCODER_MODE_HDMI; 758 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 759 (radeon_connector->audio == RADEON_AUDIO_AUTO)) 760 return ATOM_ENCODER_MODE_HDMI; 761 else 762 return ATOM_ENCODER_MODE_DVI; 763 } else { 764 return ATOM_ENCODER_MODE_DVI; 765 } 766 break; 767 case DRM_MODE_CONNECTOR_eDP: 768 return ATOM_ENCODER_MODE_DP; 769 case DRM_MODE_CONNECTOR_DVIA: 770 case DRM_MODE_CONNECTOR_VGA: 771 return ATOM_ENCODER_MODE_CRT; 772 break; 773 case DRM_MODE_CONNECTOR_Composite: 774 case DRM_MODE_CONNECTOR_SVIDEO: 775 case DRM_MODE_CONNECTOR_9PinDIN: 776 /* fix me */ 777 return ATOM_ENCODER_MODE_TV; 778 /*return ATOM_ENCODER_MODE_CV;*/ 779 break; 780 } 781 } 782 783 /* 784 * DIG Encoder/Transmitter Setup 785 * 786 * DCE 3.0/3.1 787 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 788 * Supports up to 3 digital outputs 789 * - 2 DIG encoder blocks. 790 * DIG1 can drive UNIPHY link A or link B 791 * DIG2 can drive UNIPHY link B or LVTMA 792 * 793 * DCE 3.2 794 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 795 * Supports up to 5 digital outputs 796 * - 2 DIG encoder blocks. 797 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 798 * 799 * DCE 4.0/5.0/6.0 800 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 801 * Supports up to 6 digital outputs 802 * - 6 DIG encoder blocks. 803 * - DIG to PHY mapping is hardcoded 804 * DIG1 drives UNIPHY0 link A, A+B 805 * DIG2 drives UNIPHY0 link B 806 * DIG3 drives UNIPHY1 link A, A+B 807 * DIG4 drives UNIPHY1 link B 808 * DIG5 drives UNIPHY2 link A, A+B 809 * DIG6 drives UNIPHY2 link B 810 * 811 * DCE 4.1 812 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 813 * Supports up to 6 digital outputs 814 * - 2 DIG encoder blocks. 815 * llano 816 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 817 * ontario 818 * DIG1 drives UNIPHY0/1/2 link A 819 * DIG2 drives UNIPHY0/1/2 link B 820 * 821 * Routing 822 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 823 * Examples: 824 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 825 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 826 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 827 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 828 */ 829 830 union dig_encoder_control { 831 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 832 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 833 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 834 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 835 }; 836 837 void 838 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 839 { 840 struct drm_device *dev = encoder->dev; 841 struct radeon_device *rdev = dev->dev_private; 842 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 843 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 844 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 845 union dig_encoder_control args; 846 int index = 0; 847 uint8_t frev, crev; 848 int dp_clock = 0; 849 int dp_lane_count = 0; 850 int hpd_id = RADEON_HPD_NONE; 851 852 if (connector) { 853 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 854 struct radeon_connector_atom_dig *dig_connector = 855 radeon_connector->con_priv; 856 857 dp_clock = dig_connector->dp_clock; 858 dp_lane_count = dig_connector->dp_lane_count; 859 hpd_id = radeon_connector->hpd.hpd; 860 } 861 862 /* no dig encoder assigned */ 863 if (dig->dig_encoder == -1) 864 return; 865 866 memset(&args, 0, sizeof(args)); 867 868 if (ASIC_IS_DCE4(rdev)) 869 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 870 else { 871 if (dig->dig_encoder) 872 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 873 else 874 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 875 } 876 877 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 878 return; 879 880 switch (frev) { 881 case 1: 882 switch (crev) { 883 case 1: 884 args.v1.ucAction = action; 885 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 886 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 887 args.v3.ucPanelMode = panel_mode; 888 else 889 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 890 891 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 892 args.v1.ucLaneNum = dp_lane_count; 893 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 894 args.v1.ucLaneNum = 8; 895 else 896 args.v1.ucLaneNum = 4; 897 898 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 899 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 900 switch (radeon_encoder->encoder_id) { 901 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 902 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 903 break; 904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 905 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 906 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 907 break; 908 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 909 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 910 break; 911 } 912 if (dig->linkb) 913 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 914 else 915 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 916 break; 917 case 2: 918 case 3: 919 args.v3.ucAction = action; 920 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 921 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 922 args.v3.ucPanelMode = panel_mode; 923 else 924 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 925 926 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 927 args.v3.ucLaneNum = dp_lane_count; 928 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 929 args.v3.ucLaneNum = 8; 930 else 931 args.v3.ucLaneNum = 4; 932 933 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 934 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 935 args.v3.acConfig.ucDigSel = dig->dig_encoder; 936 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 937 break; 938 case 4: 939 args.v4.ucAction = action; 940 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 941 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 942 args.v4.ucPanelMode = panel_mode; 943 else 944 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 945 946 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 947 args.v4.ucLaneNum = dp_lane_count; 948 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 949 args.v4.ucLaneNum = 8; 950 else 951 args.v4.ucLaneNum = 4; 952 953 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 954 if (dp_clock == 540000) 955 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 956 else if (dp_clock == 324000) 957 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 958 else if (dp_clock == 270000) 959 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 960 else 961 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 962 } 963 args.v4.acConfig.ucDigSel = dig->dig_encoder; 964 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 965 if (hpd_id == RADEON_HPD_NONE) 966 args.v4.ucHPD_ID = 0; 967 else 968 args.v4.ucHPD_ID = hpd_id + 1; 969 break; 970 default: 971 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 972 break; 973 } 974 break; 975 default: 976 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 977 break; 978 } 979 980 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 981 982 } 983 984 union dig_transmitter_control { 985 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 986 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 987 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 988 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 989 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 990 }; 991 992 void 993 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 994 { 995 struct drm_device *dev = encoder->dev; 996 struct radeon_device *rdev = dev->dev_private; 997 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 998 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 999 struct drm_connector *connector; 1000 union dig_transmitter_control args; 1001 int index = 0; 1002 uint8_t frev, crev; 1003 bool is_dp = false; 1004 int pll_id = 0; 1005 int dp_clock = 0; 1006 int dp_lane_count = 0; 1007 int connector_object_id = 0; 1008 int igp_lane_info = 0; 1009 int dig_encoder = dig->dig_encoder; 1010 int hpd_id = RADEON_HPD_NONE; 1011 1012 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1013 connector = radeon_get_connector_for_encoder_init(encoder); 1014 /* just needed to avoid bailing in the encoder check. the encoder 1015 * isn't used for init 1016 */ 1017 dig_encoder = 0; 1018 } else 1019 connector = radeon_get_connector_for_encoder(encoder); 1020 1021 if (connector) { 1022 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1023 struct radeon_connector_atom_dig *dig_connector = 1024 radeon_connector->con_priv; 1025 1026 hpd_id = radeon_connector->hpd.hpd; 1027 dp_clock = dig_connector->dp_clock; 1028 dp_lane_count = dig_connector->dp_lane_count; 1029 connector_object_id = 1030 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1031 igp_lane_info = dig_connector->igp_lane_info; 1032 } 1033 1034 if (encoder->crtc) { 1035 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1036 pll_id = radeon_crtc->pll_id; 1037 } 1038 1039 /* no dig encoder assigned */ 1040 if (dig_encoder == -1) 1041 return; 1042 1043 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1044 is_dp = true; 1045 1046 memset(&args, 0, sizeof(args)); 1047 1048 switch (radeon_encoder->encoder_id) { 1049 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1050 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1051 break; 1052 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1053 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1054 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1055 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1056 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1057 break; 1058 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1059 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1060 break; 1061 } 1062 1063 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1064 return; 1065 1066 switch (frev) { 1067 case 1: 1068 switch (crev) { 1069 case 1: 1070 args.v1.ucAction = action; 1071 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1072 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1073 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1074 args.v1.asMode.ucLaneSel = lane_num; 1075 args.v1.asMode.ucLaneSet = lane_set; 1076 } else { 1077 if (is_dp) 1078 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1079 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1080 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1081 else 1082 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1083 } 1084 1085 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1086 1087 if (dig_encoder) 1088 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1089 else 1090 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1091 1092 if ((rdev->flags & RADEON_IS_IGP) && 1093 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1094 if (is_dp || 1095 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1096 if (igp_lane_info & 0x1) 1097 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1098 else if (igp_lane_info & 0x2) 1099 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1100 else if (igp_lane_info & 0x4) 1101 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1102 else if (igp_lane_info & 0x8) 1103 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1104 } else { 1105 if (igp_lane_info & 0x3) 1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1107 else if (igp_lane_info & 0xc) 1108 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1109 } 1110 } 1111 1112 if (dig->linkb) 1113 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1114 else 1115 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1116 1117 if (is_dp) 1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1119 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1120 if (dig->coherent_mode) 1121 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1122 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1124 } 1125 break; 1126 case 2: 1127 args.v2.ucAction = action; 1128 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1129 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1130 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1131 args.v2.asMode.ucLaneSel = lane_num; 1132 args.v2.asMode.ucLaneSet = lane_set; 1133 } else { 1134 if (is_dp) 1135 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1136 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1137 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1138 else 1139 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1140 } 1141 1142 args.v2.acConfig.ucEncoderSel = dig_encoder; 1143 if (dig->linkb) 1144 args.v2.acConfig.ucLinkSel = 1; 1145 1146 switch (radeon_encoder->encoder_id) { 1147 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1148 args.v2.acConfig.ucTransmitterSel = 0; 1149 break; 1150 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1151 args.v2.acConfig.ucTransmitterSel = 1; 1152 break; 1153 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1154 args.v2.acConfig.ucTransmitterSel = 2; 1155 break; 1156 } 1157 1158 if (is_dp) { 1159 args.v2.acConfig.fCoherentMode = 1; 1160 args.v2.acConfig.fDPConnector = 1; 1161 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1162 if (dig->coherent_mode) 1163 args.v2.acConfig.fCoherentMode = 1; 1164 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1165 args.v2.acConfig.fDualLinkConnector = 1; 1166 } 1167 break; 1168 case 3: 1169 args.v3.ucAction = action; 1170 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1171 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1172 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1173 args.v3.asMode.ucLaneSel = lane_num; 1174 args.v3.asMode.ucLaneSet = lane_set; 1175 } else { 1176 if (is_dp) 1177 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1178 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1179 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1180 else 1181 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1182 } 1183 1184 if (is_dp) 1185 args.v3.ucLaneNum = dp_lane_count; 1186 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1187 args.v3.ucLaneNum = 8; 1188 else 1189 args.v3.ucLaneNum = 4; 1190 1191 if (dig->linkb) 1192 args.v3.acConfig.ucLinkSel = 1; 1193 if (dig_encoder & 1) 1194 args.v3.acConfig.ucEncoderSel = 1; 1195 1196 /* Select the PLL for the PHY 1197 * DP PHY should be clocked from external src if there is 1198 * one. 1199 */ 1200 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1201 if (is_dp && rdev->clock.dp_extclk) 1202 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1203 else 1204 args.v3.acConfig.ucRefClkSource = pll_id; 1205 1206 switch (radeon_encoder->encoder_id) { 1207 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1208 args.v3.acConfig.ucTransmitterSel = 0; 1209 break; 1210 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1211 args.v3.acConfig.ucTransmitterSel = 1; 1212 break; 1213 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1214 args.v3.acConfig.ucTransmitterSel = 2; 1215 break; 1216 } 1217 1218 if (is_dp) 1219 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1220 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1221 if (dig->coherent_mode) 1222 args.v3.acConfig.fCoherentMode = 1; 1223 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1224 args.v3.acConfig.fDualLinkConnector = 1; 1225 } 1226 break; 1227 case 4: 1228 args.v4.ucAction = action; 1229 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1230 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1231 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1232 args.v4.asMode.ucLaneSel = lane_num; 1233 args.v4.asMode.ucLaneSet = lane_set; 1234 } else { 1235 if (is_dp) 1236 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1237 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1238 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1239 else 1240 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1241 } 1242 1243 if (is_dp) 1244 args.v4.ucLaneNum = dp_lane_count; 1245 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1246 args.v4.ucLaneNum = 8; 1247 else 1248 args.v4.ucLaneNum = 4; 1249 1250 if (dig->linkb) 1251 args.v4.acConfig.ucLinkSel = 1; 1252 if (dig_encoder & 1) 1253 args.v4.acConfig.ucEncoderSel = 1; 1254 1255 /* Select the PLL for the PHY 1256 * DP PHY should be clocked from external src if there is 1257 * one. 1258 */ 1259 /* On DCE5 DCPLL usually generates the DP ref clock */ 1260 if (is_dp) { 1261 if (rdev->clock.dp_extclk) 1262 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1263 else 1264 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1265 } else 1266 args.v4.acConfig.ucRefClkSource = pll_id; 1267 1268 switch (radeon_encoder->encoder_id) { 1269 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1270 args.v4.acConfig.ucTransmitterSel = 0; 1271 break; 1272 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1273 args.v4.acConfig.ucTransmitterSel = 1; 1274 break; 1275 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1276 args.v4.acConfig.ucTransmitterSel = 2; 1277 break; 1278 } 1279 1280 if (is_dp) 1281 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1282 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1283 if (dig->coherent_mode) 1284 args.v4.acConfig.fCoherentMode = 1; 1285 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1286 args.v4.acConfig.fDualLinkConnector = 1; 1287 } 1288 break; 1289 case 5: 1290 args.v5.ucAction = action; 1291 if (is_dp) 1292 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1293 else 1294 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1295 1296 switch (radeon_encoder->encoder_id) { 1297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1298 if (dig->linkb) 1299 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1300 else 1301 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1302 break; 1303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1304 if (dig->linkb) 1305 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1306 else 1307 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1308 break; 1309 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1310 if (dig->linkb) 1311 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1312 else 1313 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1314 break; 1315 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1316 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1317 break; 1318 } 1319 if (is_dp) 1320 args.v5.ucLaneNum = dp_lane_count; 1321 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1322 args.v5.ucLaneNum = 8; 1323 else 1324 args.v5.ucLaneNum = 4; 1325 args.v5.ucConnObjId = connector_object_id; 1326 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1327 1328 if (is_dp && rdev->clock.dp_extclk) 1329 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1330 else 1331 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1332 1333 if (is_dp) 1334 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1335 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1336 if (dig->coherent_mode) 1337 args.v5.asConfig.ucCoherentMode = 1; 1338 } 1339 if (hpd_id == RADEON_HPD_NONE) 1340 args.v5.asConfig.ucHPDSel = 0; 1341 else 1342 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1343 args.v5.ucDigEncoderSel = 1 << dig_encoder; 1344 args.v5.ucDPLaneSet = lane_set; 1345 break; 1346 default: 1347 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1348 break; 1349 } 1350 break; 1351 default: 1352 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1353 break; 1354 } 1355 1356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1357 } 1358 1359 bool 1360 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1361 { 1362 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1363 struct drm_device *dev = radeon_connector->base.dev; 1364 struct radeon_device *rdev = dev->dev_private; 1365 union dig_transmitter_control args; 1366 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1367 uint8_t frev, crev; 1368 1369 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1370 goto done; 1371 1372 if (!ASIC_IS_DCE4(rdev)) 1373 goto done; 1374 1375 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1376 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1377 goto done; 1378 1379 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1380 goto done; 1381 1382 memset(&args, 0, sizeof(args)); 1383 1384 args.v1.ucAction = action; 1385 1386 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1387 1388 /* wait for the panel to power up */ 1389 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1390 int i; 1391 1392 for (i = 0; i < 300; i++) { 1393 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1394 return true; 1395 mdelay(1); 1396 } 1397 return false; 1398 } 1399 done: 1400 return true; 1401 } 1402 1403 union external_encoder_control { 1404 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1405 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1406 }; 1407 1408 static void 1409 atombios_external_encoder_setup(struct drm_encoder *encoder, 1410 struct drm_encoder *ext_encoder, 1411 int action) 1412 { 1413 struct drm_device *dev = encoder->dev; 1414 struct radeon_device *rdev = dev->dev_private; 1415 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1416 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1417 union external_encoder_control args; 1418 struct drm_connector *connector; 1419 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1420 u8 frev, crev; 1421 int dp_clock = 0; 1422 int dp_lane_count = 0; 1423 int connector_object_id = 0; 1424 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1425 1426 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1427 connector = radeon_get_connector_for_encoder_init(encoder); 1428 else 1429 connector = radeon_get_connector_for_encoder(encoder); 1430 1431 if (connector) { 1432 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1433 struct radeon_connector_atom_dig *dig_connector = 1434 radeon_connector->con_priv; 1435 1436 dp_clock = dig_connector->dp_clock; 1437 dp_lane_count = dig_connector->dp_lane_count; 1438 connector_object_id = 1439 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1440 } 1441 1442 memset(&args, 0, sizeof(args)); 1443 1444 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1445 return; 1446 1447 switch (frev) { 1448 case 1: 1449 /* no params on frev 1 */ 1450 break; 1451 case 2: 1452 switch (crev) { 1453 case 1: 1454 case 2: 1455 args.v1.sDigEncoder.ucAction = action; 1456 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1457 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1458 1459 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1460 if (dp_clock == 270000) 1461 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1462 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1463 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1464 args.v1.sDigEncoder.ucLaneNum = 8; 1465 else 1466 args.v1.sDigEncoder.ucLaneNum = 4; 1467 break; 1468 case 3: 1469 args.v3.sExtEncoder.ucAction = action; 1470 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1471 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1472 else 1473 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1474 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1475 1476 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1477 if (dp_clock == 270000) 1478 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1479 else if (dp_clock == 540000) 1480 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1481 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1482 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1483 args.v3.sExtEncoder.ucLaneNum = 8; 1484 else 1485 args.v3.sExtEncoder.ucLaneNum = 4; 1486 switch (ext_enum) { 1487 case GRAPH_OBJECT_ENUM_ID1: 1488 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1489 break; 1490 case GRAPH_OBJECT_ENUM_ID2: 1491 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1492 break; 1493 case GRAPH_OBJECT_ENUM_ID3: 1494 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1495 break; 1496 } 1497 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1498 break; 1499 default: 1500 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1501 return; 1502 } 1503 break; 1504 default: 1505 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1506 return; 1507 } 1508 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1509 } 1510 1511 static void 1512 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1513 { 1514 struct drm_device *dev = encoder->dev; 1515 struct radeon_device *rdev = dev->dev_private; 1516 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1517 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1518 ENABLE_YUV_PS_ALLOCATION args; 1519 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1520 uint32_t temp, reg; 1521 1522 memset(&args, 0, sizeof(args)); 1523 1524 if (rdev->family >= CHIP_R600) 1525 reg = R600_BIOS_3_SCRATCH; 1526 else 1527 reg = RADEON_BIOS_3_SCRATCH; 1528 1529 /* XXX: fix up scratch reg handling */ 1530 temp = RREG32(reg); 1531 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1532 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1533 (radeon_crtc->crtc_id << 18))); 1534 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1535 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1536 else 1537 WREG32(reg, 0); 1538 1539 if (enable) 1540 args.ucEnable = ATOM_ENABLE; 1541 args.ucCRTC = radeon_crtc->crtc_id; 1542 1543 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1544 1545 WREG32(reg, temp); 1546 } 1547 1548 static void 1549 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1550 { 1551 struct drm_device *dev = encoder->dev; 1552 struct radeon_device *rdev = dev->dev_private; 1553 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1554 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1555 int index = 0; 1556 1557 memset(&args, 0, sizeof(args)); 1558 1559 switch (radeon_encoder->encoder_id) { 1560 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1561 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1562 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1563 break; 1564 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1565 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1566 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1567 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1568 break; 1569 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1570 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1571 break; 1572 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1573 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1574 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1575 else 1576 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1577 break; 1578 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1580 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1581 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1582 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1583 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1584 else 1585 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1586 break; 1587 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1588 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1589 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1590 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1591 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1592 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1593 else 1594 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1595 break; 1596 default: 1597 return; 1598 } 1599 1600 switch (mode) { 1601 case DRM_MODE_DPMS_ON: 1602 args.ucAction = ATOM_ENABLE; 1603 /* workaround for DVOOutputControl on some RS690 systems */ 1604 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1605 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1606 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1607 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1608 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1609 } else 1610 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1611 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1612 args.ucAction = ATOM_LCD_BLON; 1613 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1614 } 1615 break; 1616 case DRM_MODE_DPMS_STANDBY: 1617 case DRM_MODE_DPMS_SUSPEND: 1618 case DRM_MODE_DPMS_OFF: 1619 args.ucAction = ATOM_DISABLE; 1620 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1621 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1622 args.ucAction = ATOM_LCD_BLOFF; 1623 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1624 } 1625 break; 1626 } 1627 } 1628 1629 static void 1630 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1631 { 1632 struct drm_device *dev = encoder->dev; 1633 struct radeon_device *rdev = dev->dev_private; 1634 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1635 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1636 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1637 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1638 struct radeon_connector *radeon_connector = NULL; 1639 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1640 bool travis_quirk = false; 1641 1642 if (connector) { 1643 radeon_connector = to_radeon_connector(connector); 1644 radeon_dig_connector = radeon_connector->con_priv; 1645 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 1646 ENCODER_OBJECT_ID_TRAVIS) && 1647 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 1648 !ASIC_IS_DCE5(rdev)) 1649 travis_quirk = true; 1650 } 1651 1652 switch (mode) { 1653 case DRM_MODE_DPMS_ON: 1654 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1655 if (!connector) 1656 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1657 else 1658 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1659 1660 /* setup and enable the encoder */ 1661 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1662 atombios_dig_encoder_setup(encoder, 1663 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1664 dig->panel_mode); 1665 if (ext_encoder) { 1666 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1667 atombios_external_encoder_setup(encoder, ext_encoder, 1668 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1669 } 1670 } else if (ASIC_IS_DCE4(rdev)) { 1671 /* setup and enable the encoder */ 1672 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1673 } else { 1674 /* setup and enable the encoder and transmitter */ 1675 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1676 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1677 } 1678 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1679 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1680 atombios_set_edp_panel_power(connector, 1681 ATOM_TRANSMITTER_ACTION_POWER_ON); 1682 radeon_dig_connector->edp_on = true; 1683 } 1684 } 1685 /* enable the transmitter */ 1686 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1687 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1688 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ 1689 radeon_dp_link_train(encoder, connector); 1690 if (ASIC_IS_DCE4(rdev)) 1691 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1692 } 1693 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1694 atombios_dig_transmitter_setup(encoder, 1695 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1696 if (ext_encoder) 1697 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1698 break; 1699 case DRM_MODE_DPMS_STANDBY: 1700 case DRM_MODE_DPMS_SUSPEND: 1701 case DRM_MODE_DPMS_OFF: 1702 if (ASIC_IS_DCE4(rdev)) { 1703 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) 1704 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1705 } 1706 if (ext_encoder) 1707 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1708 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1709 atombios_dig_transmitter_setup(encoder, 1710 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1711 1712 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && 1713 connector && !travis_quirk) 1714 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1715 if (ASIC_IS_DCE4(rdev)) { 1716 /* disable the transmitter */ 1717 atombios_dig_transmitter_setup(encoder, 1718 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1719 } else { 1720 /* disable the encoder and transmitter */ 1721 atombios_dig_transmitter_setup(encoder, 1722 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1723 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1724 } 1725 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1726 if (travis_quirk) 1727 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 1728 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1729 atombios_set_edp_panel_power(connector, 1730 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1731 radeon_dig_connector->edp_on = false; 1732 } 1733 } 1734 break; 1735 } 1736 } 1737 1738 static void 1739 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1740 { 1741 struct drm_device *dev = encoder->dev; 1742 struct radeon_device *rdev = dev->dev_private; 1743 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1744 1745 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1746 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1747 radeon_encoder->active_device); 1748 switch (radeon_encoder->encoder_id) { 1749 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1750 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1751 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1752 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1753 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1754 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1755 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1756 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1757 radeon_atom_encoder_dpms_avivo(encoder, mode); 1758 break; 1759 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1760 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1761 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1762 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1763 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1764 radeon_atom_encoder_dpms_dig(encoder, mode); 1765 break; 1766 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1767 if (ASIC_IS_DCE5(rdev)) { 1768 switch (mode) { 1769 case DRM_MODE_DPMS_ON: 1770 atombios_dvo_setup(encoder, ATOM_ENABLE); 1771 break; 1772 case DRM_MODE_DPMS_STANDBY: 1773 case DRM_MODE_DPMS_SUSPEND: 1774 case DRM_MODE_DPMS_OFF: 1775 atombios_dvo_setup(encoder, ATOM_DISABLE); 1776 break; 1777 } 1778 } else if (ASIC_IS_DCE3(rdev)) 1779 radeon_atom_encoder_dpms_dig(encoder, mode); 1780 else 1781 radeon_atom_encoder_dpms_avivo(encoder, mode); 1782 break; 1783 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1784 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1785 if (ASIC_IS_DCE5(rdev)) { 1786 switch (mode) { 1787 case DRM_MODE_DPMS_ON: 1788 atombios_dac_setup(encoder, ATOM_ENABLE); 1789 break; 1790 case DRM_MODE_DPMS_STANDBY: 1791 case DRM_MODE_DPMS_SUSPEND: 1792 case DRM_MODE_DPMS_OFF: 1793 atombios_dac_setup(encoder, ATOM_DISABLE); 1794 break; 1795 } 1796 } else 1797 radeon_atom_encoder_dpms_avivo(encoder, mode); 1798 break; 1799 default: 1800 return; 1801 } 1802 1803 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1804 1805 } 1806 1807 union crtc_source_param { 1808 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1809 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1810 }; 1811 1812 static void 1813 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1814 { 1815 struct drm_device *dev = encoder->dev; 1816 struct radeon_device *rdev = dev->dev_private; 1817 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1818 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1819 union crtc_source_param args; 1820 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1821 uint8_t frev, crev; 1822 struct radeon_encoder_atom_dig *dig; 1823 1824 memset(&args, 0, sizeof(args)); 1825 1826 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1827 return; 1828 1829 switch (frev) { 1830 case 1: 1831 switch (crev) { 1832 case 1: 1833 default: 1834 if (ASIC_IS_AVIVO(rdev)) 1835 args.v1.ucCRTC = radeon_crtc->crtc_id; 1836 else { 1837 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1838 args.v1.ucCRTC = radeon_crtc->crtc_id; 1839 } else { 1840 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1841 } 1842 } 1843 switch (radeon_encoder->encoder_id) { 1844 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1845 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1846 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1847 break; 1848 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1849 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1850 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1851 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1852 else 1853 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1854 break; 1855 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1856 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1857 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1858 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1859 break; 1860 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1861 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1862 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1863 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1864 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1865 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1866 else 1867 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1868 break; 1869 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1870 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1871 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1872 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1873 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1874 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1875 else 1876 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1877 break; 1878 } 1879 break; 1880 case 2: 1881 args.v2.ucCRTC = radeon_crtc->crtc_id; 1882 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1883 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1884 1885 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1886 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1887 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1888 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1889 else 1890 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1891 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1892 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1893 } else { 1894 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1895 } 1896 switch (radeon_encoder->encoder_id) { 1897 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1899 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1900 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1901 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1902 dig = radeon_encoder->enc_priv; 1903 switch (dig->dig_encoder) { 1904 case 0: 1905 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1906 break; 1907 case 1: 1908 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1909 break; 1910 case 2: 1911 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1912 break; 1913 case 3: 1914 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1915 break; 1916 case 4: 1917 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1918 break; 1919 case 5: 1920 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1921 break; 1922 case 6: 1923 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1924 break; 1925 } 1926 break; 1927 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1928 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1929 break; 1930 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1931 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1932 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1933 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1934 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1935 else 1936 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1937 break; 1938 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1939 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1940 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1941 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1942 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1943 else 1944 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1945 break; 1946 } 1947 break; 1948 } 1949 break; 1950 default: 1951 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1952 return; 1953 } 1954 1955 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1956 1957 /* update scratch regs with new routing */ 1958 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1959 } 1960 1961 static void 1962 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1963 struct drm_display_mode *mode) 1964 { 1965 struct drm_device *dev = encoder->dev; 1966 struct radeon_device *rdev = dev->dev_private; 1967 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1968 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1969 1970 /* Funky macbooks */ 1971 if ((dev->pdev->device == 0x71C5) && 1972 (dev->pdev->subsystem_vendor == 0x106b) && 1973 (dev->pdev->subsystem_device == 0x0080)) { 1974 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1975 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1976 1977 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1978 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1979 1980 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1981 } 1982 } 1983 1984 /* set scaler clears this on some chips */ 1985 if (ASIC_IS_AVIVO(rdev) && 1986 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 1987 if (ASIC_IS_DCE8(rdev)) { 1988 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1989 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 1990 CIK_INTERLEAVE_EN); 1991 else 1992 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1993 } else if (ASIC_IS_DCE4(rdev)) { 1994 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1995 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 1996 EVERGREEN_INTERLEAVE_EN); 1997 else 1998 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1999 } else { 2000 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2001 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 2002 AVIVO_D1MODE_INTERLEAVE_EN); 2003 else 2004 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2005 } 2006 } 2007 } 2008 2009 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 2010 { 2011 struct drm_device *dev = encoder->dev; 2012 struct radeon_device *rdev = dev->dev_private; 2013 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 2014 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2015 struct drm_encoder *test_encoder; 2016 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2017 uint32_t dig_enc_in_use = 0; 2018 2019 if (ASIC_IS_DCE6(rdev)) { 2020 /* DCE6 */ 2021 switch (radeon_encoder->encoder_id) { 2022 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2023 if (dig->linkb) 2024 return 1; 2025 else 2026 return 0; 2027 break; 2028 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2029 if (dig->linkb) 2030 return 3; 2031 else 2032 return 2; 2033 break; 2034 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2035 if (dig->linkb) 2036 return 5; 2037 else 2038 return 4; 2039 break; 2040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2041 return 6; 2042 break; 2043 } 2044 } else if (ASIC_IS_DCE4(rdev)) { 2045 /* DCE4/5 */ 2046 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2047 /* ontario follows DCE4 */ 2048 if (rdev->family == CHIP_PALM) { 2049 if (dig->linkb) 2050 return 1; 2051 else 2052 return 0; 2053 } else 2054 /* llano follows DCE3.2 */ 2055 return radeon_crtc->crtc_id; 2056 } else { 2057 switch (radeon_encoder->encoder_id) { 2058 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2059 if (dig->linkb) 2060 return 1; 2061 else 2062 return 0; 2063 break; 2064 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2065 if (dig->linkb) 2066 return 3; 2067 else 2068 return 2; 2069 break; 2070 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2071 if (dig->linkb) 2072 return 5; 2073 else 2074 return 4; 2075 break; 2076 } 2077 } 2078 } 2079 2080 /* on DCE32 and encoder can driver any block so just crtc id */ 2081 if (ASIC_IS_DCE32(rdev)) { 2082 return radeon_crtc->crtc_id; 2083 } 2084 2085 /* on DCE3 - LVTMA can only be driven by DIGB */ 2086 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2087 struct radeon_encoder *radeon_test_encoder; 2088 2089 if (encoder == test_encoder) 2090 continue; 2091 2092 if (!radeon_encoder_is_digital(test_encoder)) 2093 continue; 2094 2095 radeon_test_encoder = to_radeon_encoder(test_encoder); 2096 dig = radeon_test_encoder->enc_priv; 2097 2098 if (dig->dig_encoder >= 0) 2099 dig_enc_in_use |= (1 << dig->dig_encoder); 2100 } 2101 2102 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2103 if (dig_enc_in_use & 0x2) 2104 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2105 return 1; 2106 } 2107 if (!(dig_enc_in_use & 1)) 2108 return 0; 2109 return 1; 2110 } 2111 2112 /* This only needs to be called once at startup */ 2113 void 2114 radeon_atom_encoder_init(struct radeon_device *rdev) 2115 { 2116 struct drm_device *dev = rdev->ddev; 2117 struct drm_encoder *encoder; 2118 2119 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2120 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2121 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2122 2123 switch (radeon_encoder->encoder_id) { 2124 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2127 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2128 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2129 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2130 break; 2131 default: 2132 break; 2133 } 2134 2135 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2136 atombios_external_encoder_setup(encoder, ext_encoder, 2137 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2138 } 2139 } 2140 2141 static void 2142 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2143 struct drm_display_mode *mode, 2144 struct drm_display_mode *adjusted_mode) 2145 { 2146 struct drm_device *dev = encoder->dev; 2147 struct radeon_device *rdev = dev->dev_private; 2148 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2149 2150 radeon_encoder->pixel_clock = adjusted_mode->clock; 2151 2152 /* need to call this here rather than in prepare() since we need some crtc info */ 2153 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2154 2155 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2156 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2157 atombios_yuv_setup(encoder, true); 2158 else 2159 atombios_yuv_setup(encoder, false); 2160 } 2161 2162 switch (radeon_encoder->encoder_id) { 2163 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2164 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2165 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2167 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2168 break; 2169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2171 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2173 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2174 /* handled in dpms */ 2175 break; 2176 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2177 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2178 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2179 atombios_dvo_setup(encoder, ATOM_ENABLE); 2180 break; 2181 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2182 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2183 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2184 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2185 atombios_dac_setup(encoder, ATOM_ENABLE); 2186 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2187 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2188 atombios_tv_setup(encoder, ATOM_ENABLE); 2189 else 2190 atombios_tv_setup(encoder, ATOM_DISABLE); 2191 } 2192 break; 2193 } 2194 2195 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2196 2197 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2198 if (rdev->asic->display.hdmi_enable) 2199 radeon_hdmi_enable(rdev, encoder, true); 2200 if (rdev->asic->display.hdmi_setmode) 2201 radeon_hdmi_setmode(rdev, encoder, adjusted_mode); 2202 } 2203 } 2204 2205 static bool 2206 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2207 { 2208 struct drm_device *dev = encoder->dev; 2209 struct radeon_device *rdev = dev->dev_private; 2210 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2211 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2212 2213 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2214 ATOM_DEVICE_CV_SUPPORT | 2215 ATOM_DEVICE_CRT_SUPPORT)) { 2216 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2217 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2218 uint8_t frev, crev; 2219 2220 memset(&args, 0, sizeof(args)); 2221 2222 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2223 return false; 2224 2225 args.sDacload.ucMisc = 0; 2226 2227 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2228 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2229 args.sDacload.ucDacType = ATOM_DAC_A; 2230 else 2231 args.sDacload.ucDacType = ATOM_DAC_B; 2232 2233 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2234 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2235 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2236 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2237 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2238 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2239 if (crev >= 3) 2240 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2241 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2242 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2243 if (crev >= 3) 2244 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2245 } 2246 2247 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2248 2249 return true; 2250 } else 2251 return false; 2252 } 2253 2254 static enum drm_connector_status 2255 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2256 { 2257 struct drm_device *dev = encoder->dev; 2258 struct radeon_device *rdev = dev->dev_private; 2259 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2260 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2261 uint32_t bios_0_scratch; 2262 2263 if (!atombios_dac_load_detect(encoder, connector)) { 2264 DRM_DEBUG_KMS("detect returned false \n"); 2265 return connector_status_unknown; 2266 } 2267 2268 if (rdev->family >= CHIP_R600) 2269 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2270 else 2271 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2272 2273 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2274 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2275 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2276 return connector_status_connected; 2277 } 2278 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2279 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2280 return connector_status_connected; 2281 } 2282 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2283 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2284 return connector_status_connected; 2285 } 2286 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2287 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2288 return connector_status_connected; /* CTV */ 2289 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2290 return connector_status_connected; /* STV */ 2291 } 2292 return connector_status_disconnected; 2293 } 2294 2295 static enum drm_connector_status 2296 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2297 { 2298 struct drm_device *dev = encoder->dev; 2299 struct radeon_device *rdev = dev->dev_private; 2300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2301 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2302 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2303 u32 bios_0_scratch; 2304 2305 if (!ASIC_IS_DCE4(rdev)) 2306 return connector_status_unknown; 2307 2308 if (!ext_encoder) 2309 return connector_status_unknown; 2310 2311 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2312 return connector_status_unknown; 2313 2314 /* load detect on the dp bridge */ 2315 atombios_external_encoder_setup(encoder, ext_encoder, 2316 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2317 2318 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2319 2320 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2321 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2322 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2323 return connector_status_connected; 2324 } 2325 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2326 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2327 return connector_status_connected; 2328 } 2329 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2330 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2331 return connector_status_connected; 2332 } 2333 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2334 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2335 return connector_status_connected; /* CTV */ 2336 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2337 return connector_status_connected; /* STV */ 2338 } 2339 return connector_status_disconnected; 2340 } 2341 2342 void 2343 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2344 { 2345 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2346 2347 if (ext_encoder) 2348 /* ddc_setup on the dp bridge */ 2349 atombios_external_encoder_setup(encoder, ext_encoder, 2350 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2351 2352 } 2353 2354 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2355 { 2356 struct radeon_device *rdev = encoder->dev->dev_private; 2357 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2358 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2359 2360 if ((radeon_encoder->active_device & 2361 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2362 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2363 ENCODER_OBJECT_ID_NONE)) { 2364 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2365 if (dig) { 2366 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2367 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2368 if (rdev->family >= CHIP_R600) 2369 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2370 else 2371 /* RS600/690/740 have only 1 afmt block */ 2372 dig->afmt = rdev->mode_info.afmt[0]; 2373 } 2374 } 2375 } 2376 2377 radeon_atom_output_lock(encoder, true); 2378 2379 if (connector) { 2380 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2381 2382 /* select the clock/data port if it uses a router */ 2383 if (radeon_connector->router.cd_valid) 2384 radeon_router_select_cd_port(radeon_connector); 2385 2386 /* turn eDP panel on for mode set */ 2387 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2388 atombios_set_edp_panel_power(connector, 2389 ATOM_TRANSMITTER_ACTION_POWER_ON); 2390 } 2391 2392 /* this is needed for the pll/ss setup to work correctly in some cases */ 2393 atombios_set_encoder_crtc_source(encoder); 2394 /* set up the FMT blocks */ 2395 if (ASIC_IS_DCE8(rdev)) 2396 dce8_program_fmt(encoder); 2397 else if (ASIC_IS_DCE4(rdev)) 2398 dce4_program_fmt(encoder); 2399 else if (ASIC_IS_DCE3(rdev)) 2400 dce3_program_fmt(encoder); 2401 else if (ASIC_IS_AVIVO(rdev)) 2402 avivo_program_fmt(encoder); 2403 } 2404 2405 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2406 { 2407 /* need to call this here as we need the crtc set up */ 2408 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2409 radeon_atom_output_lock(encoder, false); 2410 } 2411 2412 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2413 { 2414 struct drm_device *dev = encoder->dev; 2415 struct radeon_device *rdev = dev->dev_private; 2416 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2417 struct radeon_encoder_atom_dig *dig; 2418 2419 /* check for pre-DCE3 cards with shared encoders; 2420 * can't really use the links individually, so don't disable 2421 * the encoder if it's in use by another connector 2422 */ 2423 if (!ASIC_IS_DCE3(rdev)) { 2424 struct drm_encoder *other_encoder; 2425 struct radeon_encoder *other_radeon_encoder; 2426 2427 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2428 other_radeon_encoder = to_radeon_encoder(other_encoder); 2429 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2430 drm_helper_encoder_in_use(other_encoder)) 2431 goto disable_done; 2432 } 2433 } 2434 2435 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2436 2437 switch (radeon_encoder->encoder_id) { 2438 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2439 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2440 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2441 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2442 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2443 break; 2444 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2445 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2446 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2447 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2448 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2449 /* handled in dpms */ 2450 break; 2451 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2452 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2453 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2454 atombios_dvo_setup(encoder, ATOM_DISABLE); 2455 break; 2456 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2457 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2458 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2459 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2460 atombios_dac_setup(encoder, ATOM_DISABLE); 2461 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2462 atombios_tv_setup(encoder, ATOM_DISABLE); 2463 break; 2464 } 2465 2466 disable_done: 2467 if (radeon_encoder_is_digital(encoder)) { 2468 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2469 if (rdev->asic->display.hdmi_enable) 2470 radeon_hdmi_enable(rdev, encoder, false); 2471 } 2472 dig = radeon_encoder->enc_priv; 2473 dig->dig_encoder = -1; 2474 } 2475 radeon_encoder->active_device = 0; 2476 } 2477 2478 /* these are handled by the primary encoders */ 2479 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2480 { 2481 2482 } 2483 2484 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2485 { 2486 2487 } 2488 2489 static void 2490 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2491 struct drm_display_mode *mode, 2492 struct drm_display_mode *adjusted_mode) 2493 { 2494 2495 } 2496 2497 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2498 { 2499 2500 } 2501 2502 static void 2503 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2504 { 2505 2506 } 2507 2508 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2509 const struct drm_display_mode *mode, 2510 struct drm_display_mode *adjusted_mode) 2511 { 2512 return true; 2513 } 2514 2515 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2516 .dpms = radeon_atom_ext_dpms, 2517 .mode_fixup = radeon_atom_ext_mode_fixup, 2518 .prepare = radeon_atom_ext_prepare, 2519 .mode_set = radeon_atom_ext_mode_set, 2520 .commit = radeon_atom_ext_commit, 2521 .disable = radeon_atom_ext_disable, 2522 /* no detect for TMDS/LVDS yet */ 2523 }; 2524 2525 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2526 .dpms = radeon_atom_encoder_dpms, 2527 .mode_fixup = radeon_atom_mode_fixup, 2528 .prepare = radeon_atom_encoder_prepare, 2529 .mode_set = radeon_atom_encoder_mode_set, 2530 .commit = radeon_atom_encoder_commit, 2531 .disable = radeon_atom_encoder_disable, 2532 .detect = radeon_atom_dig_detect, 2533 }; 2534 2535 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2536 .dpms = radeon_atom_encoder_dpms, 2537 .mode_fixup = radeon_atom_mode_fixup, 2538 .prepare = radeon_atom_encoder_prepare, 2539 .mode_set = radeon_atom_encoder_mode_set, 2540 .commit = radeon_atom_encoder_commit, 2541 .detect = radeon_atom_dac_detect, 2542 }; 2543 2544 void radeon_enc_destroy(struct drm_encoder *encoder) 2545 { 2546 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2547 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2548 radeon_atom_backlight_exit(radeon_encoder); 2549 kfree(radeon_encoder->enc_priv); 2550 drm_encoder_cleanup(encoder); 2551 kfree(radeon_encoder); 2552 } 2553 2554 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2555 .destroy = radeon_enc_destroy, 2556 }; 2557 2558 static struct radeon_encoder_atom_dac * 2559 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2560 { 2561 struct drm_device *dev = radeon_encoder->base.dev; 2562 struct radeon_device *rdev = dev->dev_private; 2563 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2564 2565 if (!dac) 2566 return NULL; 2567 2568 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2569 return dac; 2570 } 2571 2572 static struct radeon_encoder_atom_dig * 2573 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2574 { 2575 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2576 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2577 2578 if (!dig) 2579 return NULL; 2580 2581 /* coherent mode by default */ 2582 dig->coherent_mode = true; 2583 dig->dig_encoder = -1; 2584 2585 if (encoder_enum == 2) 2586 dig->linkb = true; 2587 else 2588 dig->linkb = false; 2589 2590 return dig; 2591 } 2592 2593 void 2594 radeon_add_atom_encoder(struct drm_device *dev, 2595 uint32_t encoder_enum, 2596 uint32_t supported_device, 2597 u16 caps) 2598 { 2599 struct radeon_device *rdev = dev->dev_private; 2600 struct drm_encoder *encoder; 2601 struct radeon_encoder *radeon_encoder; 2602 2603 /* see if we already added it */ 2604 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2605 radeon_encoder = to_radeon_encoder(encoder); 2606 if (radeon_encoder->encoder_enum == encoder_enum) { 2607 radeon_encoder->devices |= supported_device; 2608 return; 2609 } 2610 2611 } 2612 2613 /* add a new one */ 2614 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2615 if (!radeon_encoder) 2616 return; 2617 2618 encoder = &radeon_encoder->base; 2619 switch (rdev->num_crtc) { 2620 case 1: 2621 encoder->possible_crtcs = 0x1; 2622 break; 2623 case 2: 2624 default: 2625 encoder->possible_crtcs = 0x3; 2626 break; 2627 case 4: 2628 encoder->possible_crtcs = 0xf; 2629 break; 2630 case 6: 2631 encoder->possible_crtcs = 0x3f; 2632 break; 2633 } 2634 2635 radeon_encoder->enc_priv = NULL; 2636 2637 radeon_encoder->encoder_enum = encoder_enum; 2638 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2639 radeon_encoder->devices = supported_device; 2640 radeon_encoder->rmx_type = RMX_OFF; 2641 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2642 radeon_encoder->is_ext_encoder = false; 2643 radeon_encoder->caps = caps; 2644 2645 switch (radeon_encoder->encoder_id) { 2646 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2647 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2648 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2649 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2650 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2651 radeon_encoder->rmx_type = RMX_FULL; 2652 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2653 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2654 } else { 2655 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2656 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2657 } 2658 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2659 break; 2660 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2661 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2662 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2663 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2664 break; 2665 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2666 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2667 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2668 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2669 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2670 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2671 break; 2672 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2674 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2675 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2676 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2677 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2678 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2679 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2680 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2681 radeon_encoder->rmx_type = RMX_FULL; 2682 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2683 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2684 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2685 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2686 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2687 } else { 2688 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2689 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2690 } 2691 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2692 break; 2693 case ENCODER_OBJECT_ID_SI170B: 2694 case ENCODER_OBJECT_ID_CH7303: 2695 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2696 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2697 case ENCODER_OBJECT_ID_TITFP513: 2698 case ENCODER_OBJECT_ID_VT1623: 2699 case ENCODER_OBJECT_ID_HDMI_SI1930: 2700 case ENCODER_OBJECT_ID_TRAVIS: 2701 case ENCODER_OBJECT_ID_NUTMEG: 2702 /* these are handled by the primary encoders */ 2703 radeon_encoder->is_ext_encoder = true; 2704 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2705 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2706 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2707 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2708 else 2709 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2710 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2711 break; 2712 } 2713 } 2714