15a042273SDillon Min // SPDX-License-Identifier: GPL-2.0-only
25a042273SDillon Min /*
35a042273SDillon Min * Ilitek ILI9341 TFT LCD drm_panel driver.
45a042273SDillon Min *
55a042273SDillon Min * This panel can be configured to support:
65a042273SDillon Min * - 16-bit parallel RGB interface
75a042273SDillon Min * - 18-bit parallel RGB interface
85a042273SDillon Min * - 4-line serial spi interface
95a042273SDillon Min *
105a042273SDillon Min * Copyright (C) 2021 Dillon Min <dillon.minfei@gmail.com>
115a042273SDillon Min *
125a042273SDillon Min * For dbi+dpi part:
135a042273SDillon Min * Derived from drivers/drm/gpu/panel/panel-ilitek-ili9322.c
145a042273SDillon Min * the reuse of DBI abstraction part referred from Linus's patch
155a042273SDillon Min * "drm/panel: s6e63m0: Switch to DBI abstraction for SPI"
165a042273SDillon Min *
175a042273SDillon Min * For only-dbi part, copy from David's code (drm/tiny/ili9341.c)
185a042273SDillon Min * Copyright 2018 David Lechner <david@lechnology.com>
195a042273SDillon Min */
205a042273SDillon Min
21eff0553dSThomas Zimmermann #include <linux/backlight.h>
225a042273SDillon Min #include <linux/bitops.h>
235a042273SDillon Min #include <linux/delay.h>
245a042273SDillon Min #include <linux/gpio/consumer.h>
25c6be5383SAndy Shevchenko #include <linux/mod_devicetable.h>
265a042273SDillon Min #include <linux/module.h>
27c6be5383SAndy Shevchenko #include <linux/property.h>
285a042273SDillon Min #include <linux/regulator/consumer.h>
295a042273SDillon Min #include <linux/spi/spi.h>
305a042273SDillon Min
315a042273SDillon Min #include <video/mipi_display.h>
325a042273SDillon Min
335a042273SDillon Min #include <drm/drm_atomic_helper.h>
345a042273SDillon Min #include <drm/drm_drv.h>
358ab59da2SThomas Zimmermann #include <drm/drm_fbdev_generic.h>
365a042273SDillon Min #include <drm/drm_gem_atomic_helper.h>
374a83c26aSDanilo Krummrich #include <drm/drm_gem_dma_helper.h>
385a042273SDillon Min #include <drm/drm_gem_framebuffer_helper.h>
395a042273SDillon Min #include <drm/drm_mipi_dbi.h>
405a042273SDillon Min #include <drm/drm_modes.h>
415a042273SDillon Min #include <drm/drm_panel.h>
425a042273SDillon Min #include <drm/drm_print.h>
435a042273SDillon Min
445a042273SDillon Min #define ILI9341_RGB_INTERFACE 0xb0 /* RGB Interface Signal Control */
455a042273SDillon Min #define ILI9341_FRC 0xb1 /* Frame Rate Control register */
465a042273SDillon Min #define ILI9341_DFC 0xb6 /* Display Function Control register */
475a042273SDillon Min #define ILI9341_POWER1 0xc0 /* Power Control 1 register */
485a042273SDillon Min #define ILI9341_POWER2 0xc1 /* Power Control 2 register */
495a042273SDillon Min #define ILI9341_VCOM1 0xc5 /* VCOM Control 1 register */
505a042273SDillon Min #define ILI9341_VCOM2 0xc7 /* VCOM Control 2 register */
515a042273SDillon Min #define ILI9341_POWERA 0xcb /* Power control A register */
525a042273SDillon Min #define ILI9341_POWERB 0xcf /* Power control B register */
535a042273SDillon Min #define ILI9341_PGAMMA 0xe0 /* Positive Gamma Correction register */
545a042273SDillon Min #define ILI9341_NGAMMA 0xe1 /* Negative Gamma Correction register */
555a042273SDillon Min #define ILI9341_DTCA 0xe8 /* Driver timing control A */
565a042273SDillon Min #define ILI9341_DTCB 0xea /* Driver timing control B */
575a042273SDillon Min #define ILI9341_POWER_SEQ 0xed /* Power on sequence register */
585a042273SDillon Min #define ILI9341_3GAMMA_EN 0xf2 /* 3 Gamma enable register */
595a042273SDillon Min #define ILI9341_INTERFACE 0xf6 /* Interface control register */
605a042273SDillon Min #define ILI9341_PRC 0xf7 /* Pump ratio control register */
615a042273SDillon Min #define ILI9341_ETMOD 0xb7 /* Entry mode set */
625a042273SDillon Min
635a042273SDillon Min #define ILI9341_MADCTL_BGR BIT(3)
645a042273SDillon Min #define ILI9341_MADCTL_MV BIT(5)
655a042273SDillon Min #define ILI9341_MADCTL_MX BIT(6)
665a042273SDillon Min #define ILI9341_MADCTL_MY BIT(7)
675a042273SDillon Min
685a042273SDillon Min #define ILI9341_POWER_B_LEN 3
695a042273SDillon Min #define ILI9341_POWER_SEQ_LEN 4
705a042273SDillon Min #define ILI9341_DTCA_LEN 3
715a042273SDillon Min #define ILI9341_DTCB_LEN 2
725a042273SDillon Min #define ILI9341_POWER_A_LEN 5
735a042273SDillon Min #define ILI9341_DFC_1_LEN 2
745a042273SDillon Min #define ILI9341_FRC_LEN 2
755a042273SDillon Min #define ILI9341_VCOM_1_LEN 2
765a042273SDillon Min #define ILI9341_DFC_2_LEN 4
775a042273SDillon Min #define ILI9341_COLUMN_ADDR_LEN 4
785a042273SDillon Min #define ILI9341_PAGE_ADDR_LEN 4
795a042273SDillon Min #define ILI9341_INTERFACE_LEN 3
805a042273SDillon Min #define ILI9341_PGAMMA_LEN 15
815a042273SDillon Min #define ILI9341_NGAMMA_LEN 15
825a042273SDillon Min #define ILI9341_CA_LEN 3
835a042273SDillon Min
845a042273SDillon Min #define ILI9341_PIXEL_DPI_16_BITS (BIT(6) | BIT(4))
855a042273SDillon Min #define ILI9341_PIXEL_DPI_18_BITS (BIT(6) | BIT(5))
865a042273SDillon Min #define ILI9341_GAMMA_CURVE_1 BIT(0)
875a042273SDillon Min #define ILI9341_IF_WE_MODE BIT(0)
885a042273SDillon Min #define ILI9341_IF_BIG_ENDIAN 0x00
895a042273SDillon Min #define ILI9341_IF_DM_RGB BIT(2)
905a042273SDillon Min #define ILI9341_IF_DM_INTERNAL 0x00
915a042273SDillon Min #define ILI9341_IF_DM_VSYNC BIT(3)
925a042273SDillon Min #define ILI9341_IF_RM_RGB BIT(1)
935a042273SDillon Min #define ILI9341_IF_RIM_RGB 0x00
945a042273SDillon Min
955a042273SDillon Min #define ILI9341_COLUMN_ADDR 0x00ef
965a042273SDillon Min #define ILI9341_PAGE_ADDR 0x013f
975a042273SDillon Min
985a042273SDillon Min #define ILI9341_RGB_EPL BIT(0)
995a042273SDillon Min #define ILI9341_RGB_DPL BIT(1)
1005a042273SDillon Min #define ILI9341_RGB_HSPL BIT(2)
1015a042273SDillon Min #define ILI9341_RGB_VSPL BIT(3)
1025a042273SDillon Min #define ILI9341_RGB_DE_MODE BIT(6)
1035a042273SDillon Min #define ILI9341_RGB_DISP_PATH_MEM BIT(7)
1045a042273SDillon Min
1055a042273SDillon Min #define ILI9341_DBI_VCOMH_4P6V 0x23
1065a042273SDillon Min #define ILI9341_DBI_PWR_2_DEFAULT 0x10
1075a042273SDillon Min #define ILI9341_DBI_PRC_NORMAL 0x20
1085a042273SDillon Min #define ILI9341_DBI_VCOM_1_VMH_4P25V 0x3e
1095a042273SDillon Min #define ILI9341_DBI_VCOM_1_VML_1P5V 0x28
1105a042273SDillon Min #define ILI9341_DBI_VCOM_2_DEC_58 0x86
1115a042273SDillon Min #define ILI9341_DBI_FRC_DIVA 0x00
1125a042273SDillon Min #define ILI9341_DBI_FRC_RTNA 0x1b
1135a042273SDillon Min #define ILI9341_DBI_EMS_GAS BIT(0)
1145a042273SDillon Min #define ILI9341_DBI_EMS_DTS BIT(1)
1155a042273SDillon Min #define ILI9341_DBI_EMS_GON BIT(2)
1165a042273SDillon Min
1175a042273SDillon Min /* struct ili9341_config - the system specific ILI9341 configuration */
1185a042273SDillon Min struct ili9341_config {
1195a042273SDillon Min u32 max_spi_speed;
1205a042273SDillon Min /* mode: the drm display mode */
1215a042273SDillon Min const struct drm_display_mode mode;
1225a042273SDillon Min /* ca: TODO: need comments for this register */
1235a042273SDillon Min u8 ca[ILI9341_CA_LEN];
1245a042273SDillon Min /* power_b: TODO: need comments for this register */
1255a042273SDillon Min u8 power_b[ILI9341_POWER_B_LEN];
1265a042273SDillon Min /* power_seq: TODO: need comments for this register */
1275a042273SDillon Min u8 power_seq[ILI9341_POWER_SEQ_LEN];
1285a042273SDillon Min /* dtca: TODO: need comments for this register */
1295a042273SDillon Min u8 dtca[ILI9341_DTCA_LEN];
1305a042273SDillon Min /* dtcb: TODO: need comments for this register */
1315a042273SDillon Min u8 dtcb[ILI9341_DTCB_LEN];
1325a042273SDillon Min /* power_a: TODO: need comments for this register */
1335a042273SDillon Min u8 power_a[ILI9341_POWER_A_LEN];
1345a042273SDillon Min /* frc: Frame Rate Control (In Normal Mode/Full Colors) (B1h) */
1355a042273SDillon Min u8 frc[ILI9341_FRC_LEN];
1365a042273SDillon Min /* prc: TODO: need comments for this register */
1375a042273SDillon Min u8 prc;
1385a042273SDillon Min /* dfc_1: B6h DISCTRL (Display Function Control) */
1395a042273SDillon Min u8 dfc_1[ILI9341_DFC_1_LEN];
1405a042273SDillon Min /* power_1: Power Control 1 (C0h) */
1415a042273SDillon Min u8 power_1;
1425a042273SDillon Min /* power_2: Power Control 2 (C1h) */
1435a042273SDillon Min u8 power_2;
1445a042273SDillon Min /* vcom_1: VCOM Control 1(C5h) */
1455a042273SDillon Min u8 vcom_1[ILI9341_VCOM_1_LEN];
1465a042273SDillon Min /* vcom_2: VCOM Control 2(C7h) */
1475a042273SDillon Min u8 vcom_2;
1485a042273SDillon Min /* address_mode: Memory Access Control (36h) */
1495a042273SDillon Min u8 address_mode;
1505a042273SDillon Min /* g3amma_en: TODO: need comments for this register */
1515a042273SDillon Min u8 g3amma_en;
1525a042273SDillon Min /* rgb_interface: RGB Interface Signal Control (B0h) */
1535a042273SDillon Min u8 rgb_interface;
1545a042273SDillon Min /* dfc_2: refer to dfc_1 */
1555a042273SDillon Min u8 dfc_2[ILI9341_DFC_2_LEN];
1565a042273SDillon Min /* column_addr: Column Address Set (2Ah) */
1575a042273SDillon Min u8 column_addr[ILI9341_COLUMN_ADDR_LEN];
1585a042273SDillon Min /* page_addr: Page Address Set (2Bh) */
1595a042273SDillon Min u8 page_addr[ILI9341_PAGE_ADDR_LEN];
1605a042273SDillon Min /* interface: Interface Control (F6h) */
1615a042273SDillon Min u8 interface[ILI9341_INTERFACE_LEN];
1625a042273SDillon Min /*
1635a042273SDillon Min * pixel_format: This command sets the pixel format for the RGB
1645a042273SDillon Min * image data used by
1655a042273SDillon Min */
1665a042273SDillon Min u8 pixel_format;
1675a042273SDillon Min /*
1685a042273SDillon Min * gamma_curve: This command is used to select the desired Gamma
1695a042273SDillon Min * curve for the
1705a042273SDillon Min */
1715a042273SDillon Min u8 gamma_curve;
1725a042273SDillon Min /* pgamma: Positive Gamma Correction (E0h) */
1735a042273SDillon Min u8 pgamma[ILI9341_PGAMMA_LEN];
1745a042273SDillon Min /* ngamma: Negative Gamma Correction (E1h) */
1755a042273SDillon Min u8 ngamma[ILI9341_NGAMMA_LEN];
1765a042273SDillon Min };
1775a042273SDillon Min
1785a042273SDillon Min struct ili9341 {
1795a042273SDillon Min struct device *dev;
1805a042273SDillon Min const struct ili9341_config *conf;
1815a042273SDillon Min struct drm_panel panel;
1825a042273SDillon Min struct gpio_desc *reset_gpio;
1835a042273SDillon Min struct gpio_desc *dc_gpio;
1845a042273SDillon Min struct mipi_dbi *dbi;
1855a042273SDillon Min u32 max_spi_speed;
1865a042273SDillon Min struct regulator_bulk_data supplies[3];
1875a042273SDillon Min };
1885a042273SDillon Min
1895a042273SDillon Min /*
1905a042273SDillon Min * The Stm32f429-disco board has a panel ili9341 connected to ltdc controller
1915a042273SDillon Min */
1925a042273SDillon Min static const struct ili9341_config ili9341_stm32f429_disco_data = {
1935a042273SDillon Min .max_spi_speed = 10000000,
1945a042273SDillon Min .mode = {
1955a042273SDillon Min .clock = 6100,
1965a042273SDillon Min .hdisplay = 240,
1975a042273SDillon Min .hsync_start = 240 + 10,/* hfp 10 */
1985a042273SDillon Min .hsync_end = 240 + 10 + 10,/* hsync 10 */
1995a042273SDillon Min .htotal = 240 + 10 + 10 + 20,/* hbp 20 */
2005a042273SDillon Min .vdisplay = 320,
2015a042273SDillon Min .vsync_start = 320 + 4,/* vfp 4 */
2025a042273SDillon Min .vsync_end = 320 + 4 + 2,/* vsync 2 */
2035a042273SDillon Min .vtotal = 320 + 4 + 2 + 2,/* vbp 2 */
2045a042273SDillon Min .flags = 0,
2055a042273SDillon Min .width_mm = 65,
2065a042273SDillon Min .height_mm = 50,
2075a042273SDillon Min .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
2085a042273SDillon Min },
2095a042273SDillon Min .ca = {0xc3, 0x08, 0x50},
2105a042273SDillon Min .power_b = {0x00, 0xc1, 0x30},
2115a042273SDillon Min .power_seq = {0x64, 0x03, 0x12, 0x81},
2125a042273SDillon Min .dtca = {0x85, 0x00, 0x78},
2135a042273SDillon Min .power_a = {0x39, 0x2c, 0x00, 0x34, 0x02},
2145a042273SDillon Min .prc = 0x20,
2155a042273SDillon Min .dtcb = {0x00, 0x00},
2165a042273SDillon Min /* 0x00 fosc, 0x1b 70hz */
2175a042273SDillon Min .frc = {0x00, 0x1b},
2185a042273SDillon Min /*
2195a042273SDillon Min * 0x0a Interval scan, AGND AGND AGND AGND
2205a042273SDillon Min * 0xa2 Normally white, G1 -> G320, S720 -> S1,
2215a042273SDillon Min * Scan Cycle 5 frames,85ms
2225a042273SDillon Min */
2235a042273SDillon Min .dfc_1 = {0x0a, 0xa2},
2245a042273SDillon Min /* 0x10 3.65v */
2255a042273SDillon Min .power_1 = 0x10,
2265a042273SDillon Min /* 0x10 AVDD=vci*2, VGH=vci*7, VGL=-vci*4 */
2275a042273SDillon Min .power_2 = 0x10,
2285a042273SDillon Min /* 0x45 VCOMH 4.425v, 0x15 VCOML -1.975*/
2295a042273SDillon Min .vcom_1 = {0x45, 0x15},
2305a042273SDillon Min /* 0x90 offset voltage, VMH-48, VML-48 */
2315a042273SDillon Min .vcom_2 = 0x90,
2325a042273SDillon Min /*
2335a042273SDillon Min * 0xc8 Row Address Order, Column Address Order
2345a042273SDillon Min * BGR 1
2355a042273SDillon Min */
2365a042273SDillon Min .address_mode = 0xc8,
2375a042273SDillon Min .g3amma_en = 0x00,
2385a042273SDillon Min /*
2395a042273SDillon Min * 0xc2
2405a042273SDillon Min * Display Data Path: Memory
2415a042273SDillon Min * RGB: DE mode
2425a042273SDillon Min * DOTCLK polarity set (data fetched at the falling time)
2435a042273SDillon Min */
2445a042273SDillon Min .rgb_interface = ILI9341_RGB_DISP_PATH_MEM |
2455a042273SDillon Min ILI9341_RGB_DE_MODE |
2465a042273SDillon Min ILI9341_RGB_DPL,
2475a042273SDillon Min /*
2485a042273SDillon Min * 0x0a
2495a042273SDillon Min * Gate outputs in non-display area: Interval scan
2505a042273SDillon Min * Determine source/VCOM output in a non-display area in the partial
2515a042273SDillon Min * display mode: AGND AGND AGND AGND
2525a042273SDillon Min *
2535a042273SDillon Min * 0xa7
2545a042273SDillon Min * Scan Cycle: 15 frames
2555a042273SDillon Min * fFLM = 60Hz: 255ms
2565a042273SDillon Min * Liquid crystal type: Normally white
2575a042273SDillon Min * Gate Output Scan Direction: G1 -> G320
2585a042273SDillon Min * Source Output Scan Direction: S720 -> S1
2595a042273SDillon Min *
2605a042273SDillon Min * 0x27
2615a042273SDillon Min * LCD Driver Line: 320 lines
2625a042273SDillon Min *
2635a042273SDillon Min * 0x04
2645a042273SDillon Min * PCDIV: 4
2655a042273SDillon Min */
2665a042273SDillon Min .dfc_2 = {0x0a, 0xa7, 0x27, 0x04},
2675a042273SDillon Min /* column address: 240 */
2685a042273SDillon Min .column_addr = {0x00, 0x00, (ILI9341_COLUMN_ADDR >> 4) & 0xff,
2695a042273SDillon Min ILI9341_COLUMN_ADDR & 0xff},
2705a042273SDillon Min /* page address: 320 */
2715a042273SDillon Min .page_addr = {0x00, 0x00, (ILI9341_PAGE_ADDR >> 4) & 0xff,
2725a042273SDillon Min ILI9341_PAGE_ADDR & 0xff},
2735a042273SDillon Min /*
2745a042273SDillon Min * Memory write control: When the transfer number of data exceeds
2755a042273SDillon Min * (EC-SC+1)*(EP-SP+1), the column and page number will be
2765a042273SDillon Min * reset, and the exceeding data will be written into the following
2775a042273SDillon Min * column and page.
2785a042273SDillon Min * Display Operation Mode: RGB Interface Mode
2795a042273SDillon Min * Interface for RAM Access: RGB interface
2805a042273SDillon Min * 16- bit RGB interface (1 transfer/pixel)
2815a042273SDillon Min */
2825a042273SDillon Min .interface = {ILI9341_IF_WE_MODE, 0x00,
2835a042273SDillon Min ILI9341_IF_DM_RGB | ILI9341_IF_RM_RGB},
2845a042273SDillon Min /* DPI: 16 bits / pixel */
2855a042273SDillon Min .pixel_format = ILI9341_PIXEL_DPI_16_BITS,
2865a042273SDillon Min /* Curve Selected: Gamma curve 1 (G2.2) */
2875a042273SDillon Min .gamma_curve = ILI9341_GAMMA_CURVE_1,
2885a042273SDillon Min .pgamma = {0x0f, 0x29, 0x24, 0x0c, 0x0e,
2895a042273SDillon Min 0x09, 0x4e, 0x78, 0x3c, 0x09,
2905a042273SDillon Min 0x13, 0x05, 0x17, 0x11, 0x00},
2915a042273SDillon Min .ngamma = {0x00, 0x16, 0x1b, 0x04, 0x11,
2925a042273SDillon Min 0x07, 0x31, 0x33, 0x42, 0x05,
2935a042273SDillon Min 0x0c, 0x0a, 0x28, 0x2f, 0x0f},
2945a042273SDillon Min };
2955a042273SDillon Min
panel_to_ili9341(struct drm_panel * panel)2965a042273SDillon Min static inline struct ili9341 *panel_to_ili9341(struct drm_panel *panel)
2975a042273SDillon Min {
2985a042273SDillon Min return container_of(panel, struct ili9341, panel);
2995a042273SDillon Min }
3005a042273SDillon Min
ili9341_dpi_init(struct ili9341 * ili)3015a042273SDillon Min static void ili9341_dpi_init(struct ili9341 *ili)
3025a042273SDillon Min {
3035a042273SDillon Min struct device *dev = (&ili->panel)->dev;
3045a042273SDillon Min struct mipi_dbi *dbi = ili->dbi;
3055a042273SDillon Min struct ili9341_config *cfg = (struct ili9341_config *)ili->conf;
3065a042273SDillon Min
3075a042273SDillon Min /* Power Control */
3085a042273SDillon Min mipi_dbi_command_stackbuf(dbi, 0xca, cfg->ca, ILI9341_CA_LEN);
3095a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_POWERB, cfg->power_b,
3105a042273SDillon Min ILI9341_POWER_B_LEN);
3115a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_POWER_SEQ, cfg->power_seq,
3125a042273SDillon Min ILI9341_POWER_SEQ_LEN);
3135a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_DTCA, cfg->dtca,
3145a042273SDillon Min ILI9341_DTCA_LEN);
3155a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_POWERA, cfg->power_a,
3165a042273SDillon Min ILI9341_POWER_A_LEN);
3175a042273SDillon Min mipi_dbi_command(ili->dbi, ILI9341_PRC, cfg->prc);
3185a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_DTCB, cfg->dtcb,
3195a042273SDillon Min ILI9341_DTCB_LEN);
3205a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_FRC, cfg->frc, ILI9341_FRC_LEN);
3215a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_DFC, cfg->dfc_1,
3225a042273SDillon Min ILI9341_DFC_1_LEN);
3235a042273SDillon Min mipi_dbi_command(dbi, ILI9341_POWER1, cfg->power_1);
3245a042273SDillon Min mipi_dbi_command(dbi, ILI9341_POWER2, cfg->power_2);
3255a042273SDillon Min
3265a042273SDillon Min /* VCOM */
3275a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_VCOM1, cfg->vcom_1,
3285a042273SDillon Min ILI9341_VCOM_1_LEN);
3295a042273SDillon Min mipi_dbi_command(dbi, ILI9341_VCOM2, cfg->vcom_2);
3305a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, cfg->address_mode);
3315a042273SDillon Min
3325a042273SDillon Min /* Gamma */
3335a042273SDillon Min mipi_dbi_command(dbi, ILI9341_3GAMMA_EN, cfg->g3amma_en);
3345a042273SDillon Min mipi_dbi_command(dbi, ILI9341_RGB_INTERFACE, cfg->rgb_interface);
3355a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_DFC, cfg->dfc_2,
3365a042273SDillon Min ILI9341_DFC_2_LEN);
3375a042273SDillon Min
3385a042273SDillon Min /* Colomn address set */
3395a042273SDillon Min mipi_dbi_command_stackbuf(dbi, MIPI_DCS_SET_COLUMN_ADDRESS,
3405a042273SDillon Min cfg->column_addr, ILI9341_COLUMN_ADDR_LEN);
3415a042273SDillon Min
3425a042273SDillon Min /* Page address set */
3435a042273SDillon Min mipi_dbi_command_stackbuf(dbi, MIPI_DCS_SET_PAGE_ADDRESS,
3445a042273SDillon Min cfg->page_addr, ILI9341_PAGE_ADDR_LEN);
3455a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_INTERFACE, cfg->interface,
3465a042273SDillon Min ILI9341_INTERFACE_LEN);
3475a042273SDillon Min
3485a042273SDillon Min /* Format */
3495a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, cfg->pixel_format);
3505a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_WRITE_MEMORY_START);
3515a042273SDillon Min msleep(200);
3525a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, cfg->gamma_curve);
3535a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_PGAMMA, cfg->pgamma,
3545a042273SDillon Min ILI9341_PGAMMA_LEN);
3555a042273SDillon Min mipi_dbi_command_stackbuf(dbi, ILI9341_NGAMMA, cfg->ngamma,
3565a042273SDillon Min ILI9341_NGAMMA_LEN);
3575a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
3585a042273SDillon Min msleep(200);
3595a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
3605a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_WRITE_MEMORY_START);
3615a042273SDillon Min
3625a042273SDillon Min dev_info(dev, "Initialized display rgb interface\n");
3635a042273SDillon Min }
3645a042273SDillon Min
ili9341_dpi_power_on(struct ili9341 * ili)3655a042273SDillon Min static int ili9341_dpi_power_on(struct ili9341 *ili)
3665a042273SDillon Min {
3675a042273SDillon Min struct device *dev = (&ili->panel)->dev;
3685a042273SDillon Min int ret = 0;
3695a042273SDillon Min
3705a042273SDillon Min /* Assert RESET */
3715a042273SDillon Min gpiod_set_value(ili->reset_gpio, 1);
3725a042273SDillon Min
3735a042273SDillon Min /* Enable power */
3745a042273SDillon Min ret = regulator_bulk_enable(ARRAY_SIZE(ili->supplies),
3755a042273SDillon Min ili->supplies);
3765a042273SDillon Min if (ret < 0) {
3775a042273SDillon Min dev_err(dev, "unable to enable vcc\n");
3785a042273SDillon Min return ret;
3795a042273SDillon Min }
3805a042273SDillon Min msleep(20);
3815a042273SDillon Min
3825a042273SDillon Min /* De-assert RESET */
3835a042273SDillon Min gpiod_set_value(ili->reset_gpio, 0);
3845a042273SDillon Min msleep(20);
3855a042273SDillon Min
3865a042273SDillon Min return 0;
3875a042273SDillon Min }
3885a042273SDillon Min
ili9341_dpi_power_off(struct ili9341 * ili)3895a042273SDillon Min static int ili9341_dpi_power_off(struct ili9341 *ili)
3905a042273SDillon Min {
3915a042273SDillon Min /* Assert RESET */
3925a042273SDillon Min gpiod_set_value(ili->reset_gpio, 1);
3935a042273SDillon Min
3945a042273SDillon Min /* Disable power */
3955a042273SDillon Min return regulator_bulk_disable(ARRAY_SIZE(ili->supplies),
3965a042273SDillon Min ili->supplies);
3975a042273SDillon Min }
3985a042273SDillon Min
ili9341_dpi_disable(struct drm_panel * panel)3995a042273SDillon Min static int ili9341_dpi_disable(struct drm_panel *panel)
4005a042273SDillon Min {
4015a042273SDillon Min struct ili9341 *ili = panel_to_ili9341(panel);
4025a042273SDillon Min
4035a042273SDillon Min mipi_dbi_command(ili->dbi, MIPI_DCS_SET_DISPLAY_OFF);
4045a042273SDillon Min return 0;
4055a042273SDillon Min }
4065a042273SDillon Min
ili9341_dpi_unprepare(struct drm_panel * panel)4075a042273SDillon Min static int ili9341_dpi_unprepare(struct drm_panel *panel)
4085a042273SDillon Min {
4095a042273SDillon Min struct ili9341 *ili = panel_to_ili9341(panel);
4105a042273SDillon Min
4115a042273SDillon Min return ili9341_dpi_power_off(ili);
4125a042273SDillon Min }
4135a042273SDillon Min
ili9341_dpi_prepare(struct drm_panel * panel)4145a042273SDillon Min static int ili9341_dpi_prepare(struct drm_panel *panel)
4155a042273SDillon Min {
4165a042273SDillon Min struct ili9341 *ili = panel_to_ili9341(panel);
4175a042273SDillon Min int ret;
4185a042273SDillon Min
4195a042273SDillon Min ret = ili9341_dpi_power_on(ili);
4205a042273SDillon Min if (ret < 0)
4215a042273SDillon Min return ret;
4225a042273SDillon Min
4235a042273SDillon Min ili9341_dpi_init(ili);
4245a042273SDillon Min
425*fa695db3SAndy Shevchenko return 0;
4265a042273SDillon Min }
4275a042273SDillon Min
ili9341_dpi_enable(struct drm_panel * panel)4285a042273SDillon Min static int ili9341_dpi_enable(struct drm_panel *panel)
4295a042273SDillon Min {
4305a042273SDillon Min struct ili9341 *ili = panel_to_ili9341(panel);
4315a042273SDillon Min
4325a042273SDillon Min mipi_dbi_command(ili->dbi, MIPI_DCS_SET_DISPLAY_ON);
4335a042273SDillon Min return 0;
4345a042273SDillon Min }
4355a042273SDillon Min
ili9341_dpi_get_modes(struct drm_panel * panel,struct drm_connector * connector)4365a042273SDillon Min static int ili9341_dpi_get_modes(struct drm_panel *panel,
4375a042273SDillon Min struct drm_connector *connector)
4385a042273SDillon Min {
4395a042273SDillon Min struct ili9341 *ili = panel_to_ili9341(panel);
4405a042273SDillon Min struct drm_device *drm = connector->dev;
4415a042273SDillon Min struct drm_display_mode *mode;
4425a042273SDillon Min struct drm_display_info *info;
4435a042273SDillon Min
4445a042273SDillon Min info = &connector->display_info;
4455a042273SDillon Min info->width_mm = ili->conf->mode.width_mm;
4465a042273SDillon Min info->height_mm = ili->conf->mode.height_mm;
4475a042273SDillon Min
4485a042273SDillon Min if (ili->conf->rgb_interface & ILI9341_RGB_DPL)
4495a042273SDillon Min info->bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
4505a042273SDillon Min else
4515a042273SDillon Min info->bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
4525a042273SDillon Min
4535a042273SDillon Min if (ili->conf->rgb_interface & ILI9341_RGB_EPL)
4545a042273SDillon Min info->bus_flags |= DRM_BUS_FLAG_DE_LOW;
4555a042273SDillon Min else
4565a042273SDillon Min info->bus_flags |= DRM_BUS_FLAG_DE_HIGH;
4575a042273SDillon Min
4585a042273SDillon Min mode = drm_mode_duplicate(drm, &ili->conf->mode);
4595a042273SDillon Min if (!mode) {
4605a042273SDillon Min drm_err(drm, "bad mode or failed to add mode\n");
4615a042273SDillon Min return -EINVAL;
4625a042273SDillon Min }
4635a042273SDillon Min drm_mode_set_name(mode);
4645a042273SDillon Min
4655a042273SDillon Min /* Set up the polarity */
4665a042273SDillon Min if (ili->conf->rgb_interface & ILI9341_RGB_HSPL)
4675a042273SDillon Min mode->flags |= DRM_MODE_FLAG_PHSYNC;
4685a042273SDillon Min else
4695a042273SDillon Min mode->flags |= DRM_MODE_FLAG_NHSYNC;
4705a042273SDillon Min
4715a042273SDillon Min if (ili->conf->rgb_interface & ILI9341_RGB_VSPL)
4725a042273SDillon Min mode->flags |= DRM_MODE_FLAG_PVSYNC;
4735a042273SDillon Min else
4745a042273SDillon Min mode->flags |= DRM_MODE_FLAG_NVSYNC;
4755a042273SDillon Min
4765a042273SDillon Min drm_mode_probed_add(connector, mode);
4775a042273SDillon Min
4785a042273SDillon Min return 1; /* Number of modes */
4795a042273SDillon Min }
4805a042273SDillon Min
4815a042273SDillon Min static const struct drm_panel_funcs ili9341_dpi_funcs = {
4825a042273SDillon Min .disable = ili9341_dpi_disable,
4835a042273SDillon Min .unprepare = ili9341_dpi_unprepare,
4845a042273SDillon Min .prepare = ili9341_dpi_prepare,
4855a042273SDillon Min .enable = ili9341_dpi_enable,
4865a042273SDillon Min .get_modes = ili9341_dpi_get_modes,
4875a042273SDillon Min };
4885a042273SDillon Min
ili9341_dbi_enable(struct drm_simple_display_pipe * pipe,struct drm_crtc_state * crtc_state,struct drm_plane_state * plane_state)4895a042273SDillon Min static void ili9341_dbi_enable(struct drm_simple_display_pipe *pipe,
4905a042273SDillon Min struct drm_crtc_state *crtc_state,
4915a042273SDillon Min struct drm_plane_state *plane_state)
4925a042273SDillon Min {
4935a042273SDillon Min struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
4945a042273SDillon Min struct mipi_dbi *dbi = &dbidev->dbi;
4955a042273SDillon Min u8 addr_mode;
4965a042273SDillon Min int ret, idx;
4975a042273SDillon Min
4985a042273SDillon Min if (!drm_dev_enter(pipe->crtc.dev, &idx))
4995a042273SDillon Min return;
5005a042273SDillon Min
5015a042273SDillon Min ret = mipi_dbi_poweron_conditional_reset(dbidev);
5025a042273SDillon Min if (ret < 0)
5035a042273SDillon Min goto out_exit;
5045a042273SDillon Min if (ret == 1)
5055a042273SDillon Min goto out_enable;
5065a042273SDillon Min
5075a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
5085a042273SDillon Min
5095a042273SDillon Min mipi_dbi_command(dbi, ILI9341_POWERB, 0x00, 0xc1, 0x30);
5105a042273SDillon Min mipi_dbi_command(dbi, ILI9341_POWER_SEQ, 0x64, 0x03, 0x12, 0x81);
5115a042273SDillon Min mipi_dbi_command(dbi, ILI9341_DTCA, 0x85, 0x00, 0x78);
5125a042273SDillon Min mipi_dbi_command(dbi, ILI9341_POWERA, 0x39, 0x2c, 0x00, 0x34, 0x02);
5135a042273SDillon Min mipi_dbi_command(dbi, ILI9341_PRC, ILI9341_DBI_PRC_NORMAL);
5145a042273SDillon Min mipi_dbi_command(dbi, ILI9341_DTCB, 0x00, 0x00);
5155a042273SDillon Min
5165a042273SDillon Min /* Power Control */
5175a042273SDillon Min mipi_dbi_command(dbi, ILI9341_POWER1, ILI9341_DBI_VCOMH_4P6V);
5185a042273SDillon Min mipi_dbi_command(dbi, ILI9341_POWER2, ILI9341_DBI_PWR_2_DEFAULT);
5195a042273SDillon Min /* VCOM */
5205a042273SDillon Min mipi_dbi_command(dbi, ILI9341_VCOM1, ILI9341_DBI_VCOM_1_VMH_4P25V,
5215a042273SDillon Min ILI9341_DBI_VCOM_1_VML_1P5V);
5225a042273SDillon Min mipi_dbi_command(dbi, ILI9341_VCOM2, ILI9341_DBI_VCOM_2_DEC_58);
5235a042273SDillon Min
5245a042273SDillon Min /* Memory Access Control */
5255a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT,
5265a042273SDillon Min MIPI_DCS_PIXEL_FMT_16BIT);
5275a042273SDillon Min
5285a042273SDillon Min /* Frame Rate */
5295a042273SDillon Min mipi_dbi_command(dbi, ILI9341_FRC, ILI9341_DBI_FRC_DIVA & 0x03,
5305a042273SDillon Min ILI9341_DBI_FRC_RTNA & 0x1f);
5315a042273SDillon Min
5325a042273SDillon Min /* Gamma */
5335a042273SDillon Min mipi_dbi_command(dbi, ILI9341_3GAMMA_EN, 0x00);
5345a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, ILI9341_GAMMA_CURVE_1);
5355a042273SDillon Min mipi_dbi_command(dbi, ILI9341_PGAMMA,
5365a042273SDillon Min 0x0f, 0x31, 0x2b, 0x0c, 0x0e, 0x08, 0x4e, 0xf1,
5375a042273SDillon Min 0x37, 0x07, 0x10, 0x03, 0x0e, 0x09, 0x00);
5385a042273SDillon Min mipi_dbi_command(dbi, ILI9341_NGAMMA,
5395a042273SDillon Min 0x00, 0x0e, 0x14, 0x03, 0x11, 0x07, 0x31, 0xc1,
5405a042273SDillon Min 0x48, 0x08, 0x0f, 0x0c, 0x31, 0x36, 0x0f);
5415a042273SDillon Min
5425a042273SDillon Min /* DDRAM */
5435a042273SDillon Min mipi_dbi_command(dbi, ILI9341_ETMOD, ILI9341_DBI_EMS_GAS |
5445a042273SDillon Min ILI9341_DBI_EMS_DTS |
5455a042273SDillon Min ILI9341_DBI_EMS_GON);
5465a042273SDillon Min
5475a042273SDillon Min /* Display */
5485a042273SDillon Min mipi_dbi_command(dbi, ILI9341_DFC, 0x08, 0x82, 0x27, 0x00);
5495a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
5505a042273SDillon Min msleep(100);
5515a042273SDillon Min
5525a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
5535a042273SDillon Min msleep(100);
5545a042273SDillon Min
5555a042273SDillon Min out_enable:
5565a042273SDillon Min switch (dbidev->rotation) {
5575a042273SDillon Min default:
5585a042273SDillon Min addr_mode = ILI9341_MADCTL_MX;
5595a042273SDillon Min break;
5605a042273SDillon Min case 90:
5615a042273SDillon Min addr_mode = ILI9341_MADCTL_MV;
5625a042273SDillon Min break;
5635a042273SDillon Min case 180:
5645a042273SDillon Min addr_mode = ILI9341_MADCTL_MY;
5655a042273SDillon Min break;
5665a042273SDillon Min case 270:
5675a042273SDillon Min addr_mode = ILI9341_MADCTL_MV | ILI9341_MADCTL_MY |
5685a042273SDillon Min ILI9341_MADCTL_MX;
5695a042273SDillon Min break;
5705a042273SDillon Min }
5715a042273SDillon Min
5725a042273SDillon Min addr_mode |= ILI9341_MADCTL_BGR;
5735a042273SDillon Min mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
5745a042273SDillon Min mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
5755a042273SDillon Min drm_info(&dbidev->drm, "Initialized display serial interface\n");
5765a042273SDillon Min out_exit:
5775a042273SDillon Min drm_dev_exit(idx);
5785a042273SDillon Min }
5795a042273SDillon Min
5805a042273SDillon Min static const struct drm_simple_display_pipe_funcs ili9341_dbi_funcs = {
58163aa5ec6SThomas Zimmermann DRM_MIPI_DBI_SIMPLE_DISPLAY_PIPE_FUNCS(ili9341_dbi_enable),
5825a042273SDillon Min };
5835a042273SDillon Min
5845a042273SDillon Min static const struct drm_display_mode ili9341_dbi_mode = {
5855a042273SDillon Min DRM_SIMPLE_MODE(240, 320, 37, 49),
5865a042273SDillon Min };
5875a042273SDillon Min
5884a83c26aSDanilo Krummrich DEFINE_DRM_GEM_DMA_FOPS(ili9341_dbi_fops);
5895a042273SDillon Min
5905a042273SDillon Min static struct drm_driver ili9341_dbi_driver = {
5915a042273SDillon Min .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
5925a042273SDillon Min .fops = &ili9341_dbi_fops,
5934a83c26aSDanilo Krummrich DRM_GEM_DMA_DRIVER_OPS_VMAP,
5945a042273SDillon Min .debugfs_init = mipi_dbi_debugfs_init,
5955a042273SDillon Min .name = "ili9341",
5965a042273SDillon Min .desc = "Ilitek ILI9341",
5975a042273SDillon Min .date = "20210716",
5985a042273SDillon Min .major = 1,
5995a042273SDillon Min .minor = 0,
6005a042273SDillon Min };
6015a042273SDillon Min
ili9341_dbi_probe(struct spi_device * spi,struct gpio_desc * dc,struct gpio_desc * reset)6025a042273SDillon Min static int ili9341_dbi_probe(struct spi_device *spi, struct gpio_desc *dc,
6035a042273SDillon Min struct gpio_desc *reset)
6045a042273SDillon Min {
6055a042273SDillon Min struct device *dev = &spi->dev;
6065a042273SDillon Min struct mipi_dbi_dev *dbidev;
6075a042273SDillon Min struct mipi_dbi *dbi;
6085a042273SDillon Min struct drm_device *drm;
6095a042273SDillon Min struct regulator *vcc;
6105a042273SDillon Min u32 rotation = 0;
6115a042273SDillon Min int ret;
6125a042273SDillon Min
6135a042273SDillon Min vcc = devm_regulator_get_optional(dev, "vcc");
614d14eb80eSDaniel Mack if (IS_ERR(vcc)) {
6155a042273SDillon Min dev_err(dev, "get optional vcc failed\n");
616d14eb80eSDaniel Mack vcc = NULL;
617d14eb80eSDaniel Mack }
6185a042273SDillon Min
6195a042273SDillon Min dbidev = devm_drm_dev_alloc(dev, &ili9341_dbi_driver,
6205a042273SDillon Min struct mipi_dbi_dev, drm);
6215a042273SDillon Min if (IS_ERR(dbidev))
6225a042273SDillon Min return PTR_ERR(dbidev);
6235a042273SDillon Min
6245a042273SDillon Min dbi = &dbidev->dbi;
6255a042273SDillon Min drm = &dbidev->drm;
6265a042273SDillon Min dbi->reset = reset;
6275a042273SDillon Min dbidev->regulator = vcc;
6285a042273SDillon Min
6295a042273SDillon Min drm_mode_config_init(drm);
6305a042273SDillon Min
6315a042273SDillon Min dbidev->backlight = devm_of_find_backlight(dev);
6325a042273SDillon Min if (IS_ERR(dbidev->backlight))
6335a042273SDillon Min return PTR_ERR(dbidev->backlight);
6345a042273SDillon Min
6355a042273SDillon Min device_property_read_u32(dev, "rotation", &rotation);
6365a042273SDillon Min
6375a042273SDillon Min ret = mipi_dbi_spi_init(spi, dbi, dc);
6385a042273SDillon Min if (ret)
6395a042273SDillon Min return ret;
6405a042273SDillon Min
6415a042273SDillon Min ret = mipi_dbi_dev_init(dbidev, &ili9341_dbi_funcs,
6425a042273SDillon Min &ili9341_dbi_mode, rotation);
6435a042273SDillon Min if (ret)
6445a042273SDillon Min return ret;
6455a042273SDillon Min
6465a042273SDillon Min drm_mode_config_reset(drm);
6475a042273SDillon Min
6485a042273SDillon Min ret = drm_dev_register(drm, 0);
6495a042273SDillon Min if (ret)
6505a042273SDillon Min return ret;
6515a042273SDillon Min
6525a042273SDillon Min spi_set_drvdata(spi, drm);
6535a042273SDillon Min
6545a042273SDillon Min drm_fbdev_generic_setup(drm, 0);
6555a042273SDillon Min
6565a042273SDillon Min return 0;
6575a042273SDillon Min }
6585a042273SDillon Min
ili9341_dpi_probe(struct spi_device * spi,struct gpio_desc * dc,struct gpio_desc * reset)6595a042273SDillon Min static int ili9341_dpi_probe(struct spi_device *spi, struct gpio_desc *dc,
6605a042273SDillon Min struct gpio_desc *reset)
6615a042273SDillon Min {
6625a042273SDillon Min struct device *dev = &spi->dev;
6635a042273SDillon Min struct ili9341 *ili;
6645a042273SDillon Min int ret;
6655a042273SDillon Min
6665a042273SDillon Min ili = devm_kzalloc(dev, sizeof(struct ili9341), GFP_KERNEL);
6675a042273SDillon Min if (!ili)
6685a042273SDillon Min return -ENOMEM;
6695a042273SDillon Min
6705a042273SDillon Min ili->dbi = devm_kzalloc(dev, sizeof(struct mipi_dbi),
6715a042273SDillon Min GFP_KERNEL);
6725a042273SDillon Min if (!ili->dbi)
6735a042273SDillon Min return -ENOMEM;
6745a042273SDillon Min
6755a042273SDillon Min ili->supplies[0].supply = "vci";
6765a042273SDillon Min ili->supplies[1].supply = "vddi";
6775a042273SDillon Min ili->supplies[2].supply = "vddi-led";
6785a042273SDillon Min ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ili->supplies),
6795a042273SDillon Min ili->supplies);
6805a042273SDillon Min if (ret < 0) {
6815a042273SDillon Min dev_err(dev, "failed to get regulators: %d\n", ret);
6825a042273SDillon Min return ret;
6835a042273SDillon Min }
6845a042273SDillon Min
6855a042273SDillon Min ret = mipi_dbi_spi_init(spi, ili->dbi, dc);
6865a042273SDillon Min if (ret)
6875a042273SDillon Min return ret;
6885a042273SDillon Min
6895a042273SDillon Min spi_set_drvdata(spi, ili);
6905a042273SDillon Min ili->reset_gpio = reset;
6915a042273SDillon Min /*
6925a042273SDillon Min * Every new incarnation of this display must have a unique
6935a042273SDillon Min * data entry for the system in this driver.
6945a042273SDillon Min */
695c6be5383SAndy Shevchenko ili->conf = device_get_match_data(dev);
6965a042273SDillon Min if (!ili->conf) {
6975a042273SDillon Min dev_err(dev, "missing device configuration\n");
6985a042273SDillon Min return -ENODEV;
6995a042273SDillon Min }
7005a042273SDillon Min
7015a042273SDillon Min ili->max_spi_speed = ili->conf->max_spi_speed;
7025a042273SDillon Min drm_panel_init(&ili->panel, dev, &ili9341_dpi_funcs,
7035a042273SDillon Min DRM_MODE_CONNECTOR_DPI);
7045a042273SDillon Min drm_panel_add(&ili->panel);
7055a042273SDillon Min
7065a042273SDillon Min return 0;
7075a042273SDillon Min }
7085a042273SDillon Min
ili9341_probe(struct spi_device * spi)7095a042273SDillon Min static int ili9341_probe(struct spi_device *spi)
7105a042273SDillon Min {
7115a042273SDillon Min struct device *dev = &spi->dev;
7125a042273SDillon Min struct gpio_desc *dc;
7135a042273SDillon Min struct gpio_desc *reset;
7145a042273SDillon Min const struct spi_device_id *id = spi_get_device_id(spi);
7155a042273SDillon Min
7165a042273SDillon Min reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
7175a042273SDillon Min if (IS_ERR(reset))
7181055cdd5SAndy Shevchenko return dev_err_probe(dev, PTR_ERR(reset), "Failed to get gpio 'reset'\n");
7195a042273SDillon Min
7205a042273SDillon Min dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
7215a042273SDillon Min if (IS_ERR(dc))
7221055cdd5SAndy Shevchenko return dev_err_probe(dev, PTR_ERR(dc), "Failed to get gpio 'dc'\n");
7235a042273SDillon Min
7245a042273SDillon Min if (!strcmp(id->name, "sf-tc240t-9370-t"))
7255a042273SDillon Min return ili9341_dpi_probe(spi, dc, reset);
7265a042273SDillon Min else if (!strcmp(id->name, "yx240qv29"))
7275a042273SDillon Min return ili9341_dbi_probe(spi, dc, reset);
7285a042273SDillon Min
729*fa695db3SAndy Shevchenko return -ENODEV;
7305a042273SDillon Min }
7315a042273SDillon Min
ili9341_remove(struct spi_device * spi)732a0386bbaSUwe Kleine-König static void ili9341_remove(struct spi_device *spi)
7335a042273SDillon Min {
7345a042273SDillon Min const struct spi_device_id *id = spi_get_device_id(spi);
7355a042273SDillon Min struct ili9341 *ili = spi_get_drvdata(spi);
7365a042273SDillon Min struct drm_device *drm = spi_get_drvdata(spi);
7375a042273SDillon Min
7385a042273SDillon Min if (!strcmp(id->name, "sf-tc240t-9370-t")) {
7395a042273SDillon Min ili9341_dpi_power_off(ili);
7405a042273SDillon Min drm_panel_remove(&ili->panel);
7415a042273SDillon Min } else if (!strcmp(id->name, "yx240qv29")) {
7425a042273SDillon Min drm_dev_unplug(drm);
7435a042273SDillon Min drm_atomic_helper_shutdown(drm);
7445a042273SDillon Min }
7455a042273SDillon Min }
7465a042273SDillon Min
ili9341_shutdown(struct spi_device * spi)7475a042273SDillon Min static void ili9341_shutdown(struct spi_device *spi)
7485a042273SDillon Min {
7495a042273SDillon Min const struct spi_device_id *id = spi_get_device_id(spi);
7505a042273SDillon Min
7515a042273SDillon Min if (!strcmp(id->name, "yx240qv29"))
7525a042273SDillon Min drm_atomic_helper_shutdown(spi_get_drvdata(spi));
7535a042273SDillon Min }
7545a042273SDillon Min
7555a042273SDillon Min static const struct of_device_id ili9341_of_match[] = {
7565a042273SDillon Min {
7575a042273SDillon Min .compatible = "st,sf-tc240t-9370-t",
7585a042273SDillon Min .data = &ili9341_stm32f429_disco_data,
7595a042273SDillon Min },
7605a042273SDillon Min {
7615a042273SDillon Min /* porting from tiny/ili9341.c
7625a042273SDillon Min * for original mipi dbi compitable
7635a042273SDillon Min */
7645a042273SDillon Min .compatible = "adafruit,yx240qv29",
7655a042273SDillon Min .data = NULL,
7665a042273SDillon Min },
7675a042273SDillon Min { }
7685a042273SDillon Min };
7695a042273SDillon Min MODULE_DEVICE_TABLE(of, ili9341_of_match);
7705a042273SDillon Min
7715a042273SDillon Min static const struct spi_device_id ili9341_id[] = {
7725a042273SDillon Min { "yx240qv29", 0 },
7735a042273SDillon Min { "sf-tc240t-9370-t", 0 },
7745a042273SDillon Min { }
7755a042273SDillon Min };
7765a042273SDillon Min MODULE_DEVICE_TABLE(spi, ili9341_id);
7775a042273SDillon Min
7785a042273SDillon Min static struct spi_driver ili9341_driver = {
7795a042273SDillon Min .probe = ili9341_probe,
7805a042273SDillon Min .remove = ili9341_remove,
7815a042273SDillon Min .shutdown = ili9341_shutdown,
7825a042273SDillon Min .id_table = ili9341_id,
7835a042273SDillon Min .driver = {
7845a042273SDillon Min .name = "panel-ilitek-ili9341",
7855a042273SDillon Min .of_match_table = ili9341_of_match,
7865a042273SDillon Min },
7875a042273SDillon Min };
7885a042273SDillon Min module_spi_driver(ili9341_driver);
7895a042273SDillon Min
7905a042273SDillon Min MODULE_AUTHOR("Dillon Min <dillon.minfei@gmail.com>");
7915a042273SDillon Min MODULE_DESCRIPTION("ILI9341 LCD panel driver");
7925a042273SDillon Min MODULE_LICENSE("GPL v2");
793