1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __OMAP_DRM_DSS_H 19 #define __OMAP_DRM_DSS_H 20 21 #include <linux/list.h> 22 #include <linux/kobject.h> 23 #include <linux/device.h> 24 #include <linux/interrupt.h> 25 #include <video/videomode.h> 26 #include <linux/platform_data/omapdss.h> 27 #include <uapi/drm/drm_mode.h> 28 #include <drm/drm_crtc.h> 29 30 #define DISPC_IRQ_FRAMEDONE (1 << 0) 31 #define DISPC_IRQ_VSYNC (1 << 1) 32 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) 33 #define DISPC_IRQ_EVSYNC_ODD (1 << 3) 34 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) 35 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) 36 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) 37 #define DISPC_IRQ_GFX_END_WIN (1 << 7) 38 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) 39 #define DISPC_IRQ_OCP_ERR (1 << 9) 40 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) 41 #define DISPC_IRQ_VID1_END_WIN (1 << 11) 42 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) 43 #define DISPC_IRQ_VID2_END_WIN (1 << 13) 44 #define DISPC_IRQ_SYNC_LOST (1 << 14) 45 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) 46 #define DISPC_IRQ_WAKEUP (1 << 16) 47 #define DISPC_IRQ_SYNC_LOST2 (1 << 17) 48 #define DISPC_IRQ_VSYNC2 (1 << 18) 49 #define DISPC_IRQ_VID3_END_WIN (1 << 19) 50 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) 51 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) 52 #define DISPC_IRQ_FRAMEDONE2 (1 << 22) 53 #define DISPC_IRQ_FRAMEDONEWB (1 << 23) 54 #define DISPC_IRQ_FRAMEDONETV (1 << 24) 55 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) 56 #define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26) 57 #define DISPC_IRQ_SYNC_LOST3 (1 << 27) 58 #define DISPC_IRQ_VSYNC3 (1 << 28) 59 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) 60 #define DISPC_IRQ_FRAMEDONE3 (1 << 30) 61 62 struct dss_device; 63 struct omap_drm_private; 64 struct omap_dss_device; 65 struct dss_lcd_mgr_config; 66 struct snd_aes_iec958; 67 struct snd_cea_861_aud_if; 68 struct hdmi_avi_infoframe; 69 70 enum omap_display_type { 71 OMAP_DISPLAY_TYPE_NONE = 0, 72 OMAP_DISPLAY_TYPE_DPI = 1 << 0, 73 OMAP_DISPLAY_TYPE_DBI = 1 << 1, 74 OMAP_DISPLAY_TYPE_SDI = 1 << 2, 75 OMAP_DISPLAY_TYPE_DSI = 1 << 3, 76 OMAP_DISPLAY_TYPE_VENC = 1 << 4, 77 OMAP_DISPLAY_TYPE_HDMI = 1 << 5, 78 OMAP_DISPLAY_TYPE_DVI = 1 << 6, 79 }; 80 81 enum omap_plane_id { 82 OMAP_DSS_GFX = 0, 83 OMAP_DSS_VIDEO1 = 1, 84 OMAP_DSS_VIDEO2 = 2, 85 OMAP_DSS_VIDEO3 = 3, 86 OMAP_DSS_WB = 4, 87 }; 88 89 enum omap_channel { 90 OMAP_DSS_CHANNEL_LCD = 0, 91 OMAP_DSS_CHANNEL_DIGIT = 1, 92 OMAP_DSS_CHANNEL_LCD2 = 2, 93 OMAP_DSS_CHANNEL_LCD3 = 3, 94 OMAP_DSS_CHANNEL_WB = 4, 95 }; 96 97 enum omap_color_mode { 98 _UNUSED_, 99 }; 100 101 enum omap_dss_load_mode { 102 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, 103 OMAP_DSS_LOAD_CLUT_ONLY = 1, 104 OMAP_DSS_LOAD_FRAME_ONLY = 2, 105 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, 106 }; 107 108 enum omap_dss_trans_key_type { 109 OMAP_DSS_COLOR_KEY_GFX_DST = 0, 110 OMAP_DSS_COLOR_KEY_VID_SRC = 1, 111 }; 112 113 enum omap_dss_signal_level { 114 OMAPDSS_SIG_ACTIVE_LOW, 115 OMAPDSS_SIG_ACTIVE_HIGH, 116 }; 117 118 enum omap_dss_signal_edge { 119 OMAPDSS_DRIVE_SIG_FALLING_EDGE, 120 OMAPDSS_DRIVE_SIG_RISING_EDGE, 121 }; 122 123 enum omap_dss_venc_type { 124 OMAP_DSS_VENC_TYPE_COMPOSITE, 125 OMAP_DSS_VENC_TYPE_SVIDEO, 126 }; 127 128 enum omap_dss_dsi_pixel_format { 129 OMAP_DSS_DSI_FMT_RGB888, 130 OMAP_DSS_DSI_FMT_RGB666, 131 OMAP_DSS_DSI_FMT_RGB666_PACKED, 132 OMAP_DSS_DSI_FMT_RGB565, 133 }; 134 135 enum omap_dss_dsi_mode { 136 OMAP_DSS_DSI_CMD_MODE = 0, 137 OMAP_DSS_DSI_VIDEO_MODE, 138 }; 139 140 enum omap_display_caps { 141 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, 142 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, 143 }; 144 145 enum omap_dss_display_state { 146 OMAP_DSS_DISPLAY_DISABLED = 0, 147 OMAP_DSS_DISPLAY_ACTIVE, 148 }; 149 150 enum omap_dss_rotation_type { 151 OMAP_DSS_ROT_NONE = 0, 152 OMAP_DSS_ROT_TILER = 1 << 0, 153 }; 154 155 enum omap_overlay_caps { 156 OMAP_DSS_OVL_CAP_SCALE = 1 << 0, 157 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, 158 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, 159 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, 160 OMAP_DSS_OVL_CAP_POS = 1 << 4, 161 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, 162 }; 163 164 enum omap_dss_clk_source { 165 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK 166 * OMAP4: DSS_FCLK */ 167 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK 168 * OMAP4: PLL1_CLK1 */ 169 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK 170 * OMAP4: PLL1_CLK2 */ 171 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ 172 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ 173 }; 174 175 enum omap_hdmi_flags { 176 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0, 177 }; 178 179 enum omap_dss_output_id { 180 OMAP_DSS_OUTPUT_DPI = 1 << 0, 181 OMAP_DSS_OUTPUT_DBI = 1 << 1, 182 OMAP_DSS_OUTPUT_SDI = 1 << 2, 183 OMAP_DSS_OUTPUT_DSI1 = 1 << 3, 184 OMAP_DSS_OUTPUT_DSI2 = 1 << 4, 185 OMAP_DSS_OUTPUT_VENC = 1 << 5, 186 OMAP_DSS_OUTPUT_HDMI = 1 << 6, 187 }; 188 189 /* DSI */ 190 191 enum omap_dss_dsi_trans_mode { 192 /* Sync Pulses: both sync start and end packets sent */ 193 OMAP_DSS_DSI_PULSE_MODE, 194 /* Sync Events: only sync start packets sent */ 195 OMAP_DSS_DSI_EVENT_MODE, 196 /* Burst: only sync start packets sent, pixels are time compressed */ 197 OMAP_DSS_DSI_BURST_MODE, 198 }; 199 200 struct omap_dss_dsi_videomode_timings { 201 unsigned long hsclk; 202 203 unsigned int ndl; 204 unsigned int bitspp; 205 206 /* pixels */ 207 u16 hact; 208 /* lines */ 209 u16 vact; 210 211 /* DSI video mode blanking data */ 212 /* Unit: byte clock cycles */ 213 u16 hss; 214 u16 hsa; 215 u16 hse; 216 u16 hfp; 217 u16 hbp; 218 /* Unit: line clocks */ 219 u16 vsa; 220 u16 vfp; 221 u16 vbp; 222 223 /* DSI blanking modes */ 224 int blanking_mode; 225 int hsa_blanking_mode; 226 int hbp_blanking_mode; 227 int hfp_blanking_mode; 228 229 enum omap_dss_dsi_trans_mode trans_mode; 230 231 bool ddr_clk_always_on; 232 int window_sync; 233 }; 234 235 struct omap_dss_dsi_config { 236 enum omap_dss_dsi_mode mode; 237 enum omap_dss_dsi_pixel_format pixel_format; 238 const struct videomode *vm; 239 240 unsigned long hs_clk_min, hs_clk_max; 241 unsigned long lp_clk_min, lp_clk_max; 242 243 bool ddr_clk_always_on; 244 enum omap_dss_dsi_trans_mode trans_mode; 245 }; 246 247 struct omap_dss_cpr_coefs { 248 s16 rr, rg, rb; 249 s16 gr, gg, gb; 250 s16 br, bg, bb; 251 }; 252 253 struct omap_overlay_info { 254 dma_addr_t paddr; 255 dma_addr_t p_uv_addr; /* for NV12 format */ 256 u16 screen_width; 257 u16 width; 258 u16 height; 259 u32 fourcc; 260 u8 rotation; 261 enum omap_dss_rotation_type rotation_type; 262 263 u16 pos_x; 264 u16 pos_y; 265 u16 out_width; /* if 0, out_width == width */ 266 u16 out_height; /* if 0, out_height == height */ 267 u8 global_alpha; 268 u8 pre_mult_alpha; 269 u8 zorder; 270 }; 271 272 struct omap_overlay_manager_info { 273 u32 default_color; 274 275 enum omap_dss_trans_key_type trans_key_type; 276 u32 trans_key; 277 bool trans_enabled; 278 279 bool partial_alpha_enabled; 280 281 bool cpr_enable; 282 struct omap_dss_cpr_coefs cpr_coefs; 283 }; 284 285 /* 22 pins means 1 clk lane and 10 data lanes */ 286 #define OMAP_DSS_MAX_DSI_PINS 22 287 288 struct omap_dsi_pin_config { 289 int num_pins; 290 /* 291 * pin numbers in the following order: 292 * clk+, clk- 293 * data1+, data1- 294 * data2+, data2- 295 * ... 296 */ 297 int pins[OMAP_DSS_MAX_DSI_PINS]; 298 }; 299 300 struct omap_dss_writeback_info { 301 u32 paddr; 302 u32 p_uv_addr; 303 u16 buf_width; 304 u16 width; 305 u16 height; 306 u32 fourcc; 307 u8 rotation; 308 enum omap_dss_rotation_type rotation_type; 309 u8 pre_mult_alpha; 310 }; 311 312 struct omapdss_dpi_ops { 313 int (*connect)(struct omap_dss_device *dssdev, 314 struct omap_dss_device *dst); 315 void (*disconnect)(struct omap_dss_device *dssdev, 316 struct omap_dss_device *dst); 317 318 int (*enable)(struct omap_dss_device *dssdev); 319 void (*disable)(struct omap_dss_device *dssdev); 320 321 int (*check_timings)(struct omap_dss_device *dssdev, 322 struct videomode *vm); 323 void (*set_timings)(struct omap_dss_device *dssdev, 324 struct videomode *vm); 325 void (*get_timings)(struct omap_dss_device *dssdev, 326 struct videomode *vm); 327 }; 328 329 struct omapdss_sdi_ops { 330 int (*connect)(struct omap_dss_device *dssdev, 331 struct omap_dss_device *dst); 332 void (*disconnect)(struct omap_dss_device *dssdev, 333 struct omap_dss_device *dst); 334 335 int (*enable)(struct omap_dss_device *dssdev); 336 void (*disable)(struct omap_dss_device *dssdev); 337 338 int (*check_timings)(struct omap_dss_device *dssdev, 339 struct videomode *vm); 340 void (*set_timings)(struct omap_dss_device *dssdev, 341 struct videomode *vm); 342 void (*get_timings)(struct omap_dss_device *dssdev, 343 struct videomode *vm); 344 }; 345 346 struct omapdss_dvi_ops { 347 int (*connect)(struct omap_dss_device *dssdev, 348 struct omap_dss_device *dst); 349 void (*disconnect)(struct omap_dss_device *dssdev, 350 struct omap_dss_device *dst); 351 352 int (*enable)(struct omap_dss_device *dssdev); 353 void (*disable)(struct omap_dss_device *dssdev); 354 355 int (*check_timings)(struct omap_dss_device *dssdev, 356 struct videomode *vm); 357 void (*set_timings)(struct omap_dss_device *dssdev, 358 struct videomode *vm); 359 void (*get_timings)(struct omap_dss_device *dssdev, 360 struct videomode *vm); 361 }; 362 363 struct omapdss_atv_ops { 364 int (*connect)(struct omap_dss_device *dssdev, 365 struct omap_dss_device *dst); 366 void (*disconnect)(struct omap_dss_device *dssdev, 367 struct omap_dss_device *dst); 368 369 int (*enable)(struct omap_dss_device *dssdev); 370 void (*disable)(struct omap_dss_device *dssdev); 371 372 int (*check_timings)(struct omap_dss_device *dssdev, 373 struct videomode *vm); 374 void (*set_timings)(struct omap_dss_device *dssdev, 375 struct videomode *vm); 376 void (*get_timings)(struct omap_dss_device *dssdev, 377 struct videomode *vm); 378 379 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); 380 u32 (*get_wss)(struct omap_dss_device *dssdev); 381 }; 382 383 struct omapdss_hdmi_ops { 384 int (*connect)(struct omap_dss_device *dssdev, 385 struct omap_dss_device *dst); 386 void (*disconnect)(struct omap_dss_device *dssdev, 387 struct omap_dss_device *dst); 388 389 int (*enable)(struct omap_dss_device *dssdev); 390 void (*disable)(struct omap_dss_device *dssdev); 391 392 int (*check_timings)(struct omap_dss_device *dssdev, 393 struct videomode *vm); 394 void (*set_timings)(struct omap_dss_device *dssdev, 395 struct videomode *vm); 396 void (*get_timings)(struct omap_dss_device *dssdev, 397 struct videomode *vm); 398 399 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); 400 void (*lost_hotplug)(struct omap_dss_device *dssdev); 401 bool (*detect)(struct omap_dss_device *dssdev); 402 403 int (*register_hpd_cb)(struct omap_dss_device *dssdev, 404 void (*cb)(void *cb_data, 405 enum drm_connector_status status), 406 void *cb_data); 407 void (*unregister_hpd_cb)(struct omap_dss_device *dssdev); 408 void (*enable_hpd)(struct omap_dss_device *dssdev); 409 void (*disable_hpd)(struct omap_dss_device *dssdev); 410 411 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode); 412 int (*set_infoframe)(struct omap_dss_device *dssdev, 413 const struct hdmi_avi_infoframe *avi); 414 }; 415 416 struct omapdss_dsi_ops { 417 int (*connect)(struct omap_dss_device *dssdev, 418 struct omap_dss_device *dst); 419 void (*disconnect)(struct omap_dss_device *dssdev, 420 struct omap_dss_device *dst); 421 422 int (*enable)(struct omap_dss_device *dssdev); 423 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes, 424 bool enter_ulps); 425 426 /* bus configuration */ 427 int (*set_config)(struct omap_dss_device *dssdev, 428 const struct omap_dss_dsi_config *cfg); 429 int (*configure_pins)(struct omap_dss_device *dssdev, 430 const struct omap_dsi_pin_config *pin_cfg); 431 432 void (*enable_hs)(struct omap_dss_device *dssdev, int channel, 433 bool enable); 434 int (*enable_te)(struct omap_dss_device *dssdev, bool enable); 435 436 int (*update)(struct omap_dss_device *dssdev, int channel, 437 void (*callback)(int, void *), void *data); 438 439 void (*bus_lock)(struct omap_dss_device *dssdev); 440 void (*bus_unlock)(struct omap_dss_device *dssdev); 441 442 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel); 443 void (*disable_video_output)(struct omap_dss_device *dssdev, 444 int channel); 445 446 int (*request_vc)(struct omap_dss_device *dssdev, int *channel); 447 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel, 448 int vc_id); 449 void (*release_vc)(struct omap_dss_device *dssdev, int channel); 450 451 /* data transfer */ 452 int (*dcs_write)(struct omap_dss_device *dssdev, int channel, 453 u8 *data, int len); 454 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel, 455 u8 *data, int len); 456 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 457 u8 *data, int len); 458 459 int (*gen_write)(struct omap_dss_device *dssdev, int channel, 460 u8 *data, int len); 461 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel, 462 u8 *data, int len); 463 int (*gen_read)(struct omap_dss_device *dssdev, int channel, 464 u8 *reqdata, int reqlen, 465 u8 *data, int len); 466 467 int (*bta_sync)(struct omap_dss_device *dssdev, int channel); 468 469 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev, 470 int channel, u16 plen); 471 }; 472 473 struct omap_dss_device { 474 struct kobject kobj; 475 struct device *dev; 476 477 struct module *owner; 478 479 struct list_head panel_list; 480 481 /* alias in the form of "display%d" */ 482 char alias[16]; 483 484 enum omap_display_type type; 485 enum omap_display_type output_type; 486 487 struct { 488 struct videomode vm; 489 490 enum omap_dss_dsi_pixel_format dsi_pix_fmt; 491 enum omap_dss_dsi_mode dsi_mode; 492 } panel; 493 494 const char *name; 495 496 struct omap_dss_driver *driver; 497 498 union { 499 const struct omapdss_dpi_ops *dpi; 500 const struct omapdss_sdi_ops *sdi; 501 const struct omapdss_dvi_ops *dvi; 502 const struct omapdss_hdmi_ops *hdmi; 503 const struct omapdss_atv_ops *atv; 504 const struct omapdss_dsi_ops *dsi; 505 } ops; 506 507 /* helper variable for driver suspend/resume */ 508 bool activate_after_resume; 509 510 enum omap_display_caps caps; 511 512 struct omap_dss_device *src; 513 514 enum omap_dss_display_state state; 515 516 /* OMAP DSS output specific fields */ 517 518 struct list_head list; 519 520 /* DISPC channel for this output */ 521 enum omap_channel dispc_channel; 522 bool dispc_channel_connected; 523 524 /* output instance */ 525 enum omap_dss_output_id id; 526 527 /* the port number in the DT node */ 528 int port_num; 529 530 /* dynamic fields */ 531 struct omap_dss_device *dst; 532 }; 533 534 struct omap_dss_driver { 535 int (*probe)(struct omap_dss_device *); 536 void (*remove)(struct omap_dss_device *); 537 538 int (*connect)(struct omap_dss_device *dssdev); 539 void (*disconnect)(struct omap_dss_device *dssdev); 540 541 int (*enable)(struct omap_dss_device *display); 542 void (*disable)(struct omap_dss_device *display); 543 int (*run_test)(struct omap_dss_device *display, int test); 544 545 int (*update)(struct omap_dss_device *dssdev, 546 u16 x, u16 y, u16 w, u16 h); 547 int (*sync)(struct omap_dss_device *dssdev); 548 549 int (*enable_te)(struct omap_dss_device *dssdev, bool enable); 550 int (*get_te)(struct omap_dss_device *dssdev); 551 552 u8 (*get_rotate)(struct omap_dss_device *dssdev); 553 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); 554 555 bool (*get_mirror)(struct omap_dss_device *dssdev); 556 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); 557 558 int (*memory_read)(struct omap_dss_device *dssdev, 559 void *buf, size_t size, 560 u16 x, u16 y, u16 w, u16 h); 561 562 int (*check_timings)(struct omap_dss_device *dssdev, 563 struct videomode *vm); 564 void (*set_timings)(struct omap_dss_device *dssdev, 565 struct videomode *vm); 566 void (*get_timings)(struct omap_dss_device *dssdev, 567 struct videomode *vm); 568 void (*get_size)(struct omap_dss_device *dssdev, 569 unsigned int *width, unsigned int *height); 570 571 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); 572 u32 (*get_wss)(struct omap_dss_device *dssdev); 573 574 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); 575 bool (*detect)(struct omap_dss_device *dssdev); 576 577 int (*register_hpd_cb)(struct omap_dss_device *dssdev, 578 void (*cb)(void *cb_data, 579 enum drm_connector_status status), 580 void *cb_data); 581 void (*unregister_hpd_cb)(struct omap_dss_device *dssdev); 582 void (*enable_hpd)(struct omap_dss_device *dssdev); 583 void (*disable_hpd)(struct omap_dss_device *dssdev); 584 585 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode); 586 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev, 587 const struct hdmi_avi_infoframe *avi); 588 }; 589 590 struct dss_device *omapdss_get_dss(void); 591 void omapdss_set_dss(struct dss_device *dss); 592 static inline bool omapdss_is_initialized(void) 593 { 594 return !!omapdss_get_dss(); 595 } 596 597 int omapdss_register_display(struct omap_dss_device *dssdev); 598 void omapdss_unregister_display(struct omap_dss_device *dssdev); 599 600 struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev); 601 void omap_dss_put_device(struct omap_dss_device *dssdev); 602 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) 603 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); 604 605 int omap_dss_get_num_overlay_managers(void); 606 607 int omap_dss_get_num_overlays(void); 608 609 int omapdss_register_output(struct omap_dss_device *output); 610 void omapdss_unregister_output(struct omap_dss_device *output); 611 struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id); 612 struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port); 613 int omapdss_output_set_device(struct omap_dss_device *out, 614 struct omap_dss_device *dssdev); 615 int omapdss_output_unset_device(struct omap_dss_device *out); 616 617 struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev); 618 619 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); 620 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 621 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 622 623 int omapdss_compat_init(void); 624 void omapdss_compat_uninit(void); 625 626 static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev) 627 { 628 return dssdev->src; 629 } 630 631 static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev) 632 { 633 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE; 634 } 635 636 struct omap_dss_device * 637 omapdss_of_find_source_for_first_ep(struct device_node *node); 638 639 struct device_node *dss_of_port_get_parent_device(struct device_node *port); 640 u32 dss_of_port_get_port_number(struct device_node *port); 641 642 struct dss_mgr_ops { 643 int (*connect)(struct omap_drm_private *priv, 644 enum omap_channel channel, 645 struct omap_dss_device *dst); 646 void (*disconnect)(struct omap_drm_private *priv, 647 enum omap_channel channel, 648 struct omap_dss_device *dst); 649 650 void (*start_update)(struct omap_drm_private *priv, 651 enum omap_channel channel); 652 int (*enable)(struct omap_drm_private *priv, 653 enum omap_channel channel); 654 void (*disable)(struct omap_drm_private *priv, 655 enum omap_channel channel); 656 void (*set_timings)(struct omap_drm_private *priv, 657 enum omap_channel channel, 658 const struct videomode *vm); 659 void (*set_lcd_config)(struct omap_drm_private *priv, 660 enum omap_channel channel, 661 const struct dss_lcd_mgr_config *config); 662 int (*register_framedone_handler)(struct omap_drm_private *priv, 663 enum omap_channel channel, 664 void (*handler)(void *), void *data); 665 void (*unregister_framedone_handler)(struct omap_drm_private *priv, 666 enum omap_channel channel, 667 void (*handler)(void *), void *data); 668 }; 669 670 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops, 671 struct omap_drm_private *priv); 672 void dss_uninstall_mgr_ops(void); 673 674 int dss_mgr_connect(struct omap_dss_device *dssdev, 675 struct omap_dss_device *dst); 676 void dss_mgr_disconnect(struct omap_dss_device *dssdev, 677 struct omap_dss_device *dst); 678 void dss_mgr_set_timings(struct omap_dss_device *dssdev, 679 const struct videomode *vm); 680 void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev, 681 const struct dss_lcd_mgr_config *config); 682 int dss_mgr_enable(struct omap_dss_device *dssdev); 683 void dss_mgr_disable(struct omap_dss_device *dssdev); 684 void dss_mgr_start_update(struct omap_dss_device *dssdev); 685 int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev, 686 void (*handler)(void *), void *data); 687 void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev, 688 void (*handler)(void *), void *data); 689 690 /* dispc ops */ 691 692 struct dispc_ops { 693 u32 (*read_irqstatus)(void); 694 void (*clear_irqstatus)(u32 mask); 695 void (*write_irqenable)(u32 mask); 696 697 int (*request_irq)(irq_handler_t handler, void *dev_id); 698 void (*free_irq)(void *dev_id); 699 700 int (*runtime_get)(void); 701 void (*runtime_put)(void); 702 703 int (*get_num_ovls)(void); 704 int (*get_num_mgrs)(void); 705 706 u32 (*get_memory_bandwidth_limit)(void); 707 708 void (*mgr_enable)(enum omap_channel channel, bool enable); 709 bool (*mgr_is_enabled)(enum omap_channel channel); 710 u32 (*mgr_get_vsync_irq)(enum omap_channel channel); 711 u32 (*mgr_get_framedone_irq)(enum omap_channel channel); 712 u32 (*mgr_get_sync_lost_irq)(enum omap_channel channel); 713 bool (*mgr_go_busy)(enum omap_channel channel); 714 void (*mgr_go)(enum omap_channel channel); 715 void (*mgr_set_lcd_config)(enum omap_channel channel, 716 const struct dss_lcd_mgr_config *config); 717 void (*mgr_set_timings)(enum omap_channel channel, 718 const struct videomode *vm); 719 void (*mgr_setup)(enum omap_channel channel, 720 const struct omap_overlay_manager_info *info); 721 enum omap_dss_output_id (*mgr_get_supported_outputs)(enum omap_channel channel); 722 u32 (*mgr_gamma_size)(enum omap_channel channel); 723 void (*mgr_set_gamma)(enum omap_channel channel, 724 const struct drm_color_lut *lut, 725 unsigned int length); 726 727 int (*ovl_enable)(enum omap_plane_id plane, bool enable); 728 int (*ovl_setup)(enum omap_plane_id plane, 729 const struct omap_overlay_info *oi, 730 const struct videomode *vm, bool mem_to_mem, 731 enum omap_channel channel); 732 733 const u32 *(*ovl_get_color_modes)(enum omap_plane_id plane); 734 }; 735 736 const struct dispc_ops *dispc_get_ops(struct dss_device *dss); 737 738 bool omapdss_component_is_display(struct device_node *node); 739 bool omapdss_component_is_output(struct device_node *node); 740 741 bool omapdss_stack_is_ready(void); 742 void omapdss_gather_components(struct device *dev); 743 744 #endif /* __OMAP_DRM_DSS_H */ 745