1 /* 2 * Copyright (C) 2009 Nokia Corporation 3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 4 * 5 * Some code and ideas taken from drivers/video/omap/ driver 6 * by Imre Deak. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef __OMAP2_DSS_H 22 #define __OMAP2_DSS_H 23 24 #include <linux/interrupt.h> 25 26 #include "omapdss.h" 27 28 struct dss_debugfs_entry; 29 struct platform_device; 30 struct seq_file; 31 32 #define MAX_DSS_LCD_MANAGERS 3 33 #define MAX_NUM_DSI 2 34 35 #ifdef pr_fmt 36 #undef pr_fmt 37 #endif 38 39 #ifdef DSS_SUBSYS_NAME 40 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt 41 #else 42 #define pr_fmt(fmt) fmt 43 #endif 44 45 #define DSSDBG(format, ...) \ 46 pr_debug(format, ## __VA_ARGS__) 47 48 #ifdef DSS_SUBSYS_NAME 49 #define DSSERR(format, ...) \ 50 pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__) 51 #else 52 #define DSSERR(format, ...) \ 53 pr_err("omapdss error: " format, ##__VA_ARGS__) 54 #endif 55 56 #ifdef DSS_SUBSYS_NAME 57 #define DSSINFO(format, ...) \ 58 pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__) 59 #else 60 #define DSSINFO(format, ...) \ 61 pr_info("omapdss: " format, ## __VA_ARGS__) 62 #endif 63 64 #ifdef DSS_SUBSYS_NAME 65 #define DSSWARN(format, ...) \ 66 pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__) 67 #else 68 #define DSSWARN(format, ...) \ 69 pr_warn("omapdss: " format, ##__VA_ARGS__) 70 #endif 71 72 /* OMAP TRM gives bitfields as start:end, where start is the higher bit 73 number. For example 7:0 */ 74 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 75 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 76 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) 77 #define FLD_MOD(orig, val, start, end) \ 78 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) 79 80 enum dss_model { 81 DSS_MODEL_OMAP2, 82 DSS_MODEL_OMAP3, 83 DSS_MODEL_OMAP4, 84 DSS_MODEL_OMAP5, 85 DSS_MODEL_DRA7, 86 }; 87 88 enum dss_io_pad_mode { 89 DSS_IO_PAD_MODE_RESET, 90 DSS_IO_PAD_MODE_RFBI, 91 DSS_IO_PAD_MODE_BYPASS, 92 }; 93 94 enum dss_hdmi_venc_clk_source_select { 95 DSS_VENC_TV_CLK = 0, 96 DSS_HDMI_M_PCLK = 1, 97 }; 98 99 enum dss_dsi_content_type { 100 DSS_DSI_CONTENT_DCS, 101 DSS_DSI_CONTENT_GENERIC, 102 }; 103 104 enum dss_writeback_channel { 105 DSS_WB_LCD1_MGR = 0, 106 DSS_WB_LCD2_MGR = 1, 107 DSS_WB_TV_MGR = 2, 108 DSS_WB_OVL0 = 3, 109 DSS_WB_OVL1 = 4, 110 DSS_WB_OVL2 = 5, 111 DSS_WB_OVL3 = 6, 112 DSS_WB_LCD3_MGR = 7, 113 }; 114 115 enum dss_clk_source { 116 DSS_CLK_SRC_FCK = 0, 117 118 DSS_CLK_SRC_PLL1_1, 119 DSS_CLK_SRC_PLL1_2, 120 DSS_CLK_SRC_PLL1_3, 121 122 DSS_CLK_SRC_PLL2_1, 123 DSS_CLK_SRC_PLL2_2, 124 DSS_CLK_SRC_PLL2_3, 125 126 DSS_CLK_SRC_HDMI_PLL, 127 }; 128 129 enum dss_pll_id { 130 DSS_PLL_DSI1, 131 DSS_PLL_DSI2, 132 DSS_PLL_HDMI, 133 DSS_PLL_VIDEO1, 134 DSS_PLL_VIDEO2, 135 }; 136 137 struct dss_pll; 138 139 #define DSS_PLL_MAX_HSDIVS 4 140 141 enum dss_pll_type { 142 DSS_PLL_TYPE_A, 143 DSS_PLL_TYPE_B, 144 }; 145 146 /* 147 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7. 148 * Type-B PLLs: clkout[0] refers to m2. 149 */ 150 struct dss_pll_clock_info { 151 /* rates that we get with dividers below */ 152 unsigned long fint; 153 unsigned long clkdco; 154 unsigned long clkout[DSS_PLL_MAX_HSDIVS]; 155 156 /* dividers */ 157 u16 n; 158 u16 m; 159 u32 mf; 160 u16 mX[DSS_PLL_MAX_HSDIVS]; 161 u16 sd; 162 }; 163 164 struct dss_pll_ops { 165 int (*enable)(struct dss_pll *pll); 166 void (*disable)(struct dss_pll *pll); 167 int (*set_config)(struct dss_pll *pll, 168 const struct dss_pll_clock_info *cinfo); 169 }; 170 171 struct dss_pll_hw { 172 enum dss_pll_type type; 173 174 unsigned int n_max; 175 unsigned int m_min; 176 unsigned int m_max; 177 unsigned int mX_max; 178 179 unsigned long fint_min, fint_max; 180 unsigned long clkdco_min, clkdco_low, clkdco_max; 181 182 u8 n_msb, n_lsb; 183 u8 m_msb, m_lsb; 184 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS]; 185 186 bool has_stopmode; 187 bool has_freqsel; 188 bool has_selfreqdco; 189 bool has_refsel; 190 191 /* DRA7 errata i886: use high N & M to avoid jitter */ 192 bool errata_i886; 193 }; 194 195 struct dss_pll { 196 const char *name; 197 enum dss_pll_id id; 198 struct dss_device *dss; 199 200 struct clk *clkin; 201 struct regulator *regulator; 202 203 void __iomem *base; 204 205 const struct dss_pll_hw *hw; 206 207 const struct dss_pll_ops *ops; 208 209 struct dss_pll_clock_info cinfo; 210 }; 211 212 /* Defines a generic omap register field */ 213 struct dss_reg_field { 214 u8 start, end; 215 }; 216 217 struct dispc_clock_info { 218 /* rates that we get with dividers below */ 219 unsigned long lck; 220 unsigned long pck; 221 222 /* dividers */ 223 u16 lck_div; 224 u16 pck_div; 225 }; 226 227 struct dss_lcd_mgr_config { 228 enum dss_io_pad_mode io_pad_mode; 229 230 bool stallmode; 231 bool fifohandcheck; 232 233 struct dispc_clock_info clock_info; 234 235 int video_port_width; 236 237 int lcden_sig_polarity; 238 }; 239 240 #define DSS_SZ_REGS SZ_512 241 242 struct dss_device { 243 struct platform_device *pdev; 244 void __iomem *base; 245 struct regmap *syscon_pll_ctrl; 246 u32 syscon_pll_ctrl_offset; 247 248 struct clk *parent_clk; 249 struct clk *dss_clk; 250 unsigned long dss_clk_rate; 251 252 unsigned long cache_req_pck; 253 unsigned long cache_prate; 254 struct dispc_clock_info cache_dispc_cinfo; 255 256 enum dss_clk_source dsi_clk_source[MAX_NUM_DSI]; 257 enum dss_clk_source dispc_clk_source; 258 enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; 259 260 bool ctx_valid; 261 u32 ctx[DSS_SZ_REGS / sizeof(u32)]; 262 263 const struct dss_features *feat; 264 265 struct { 266 struct dentry *root; 267 struct dss_debugfs_entry *clk; 268 struct dss_debugfs_entry *dss; 269 } debugfs; 270 271 struct dss_pll *plls[4]; 272 struct dss_pll *video1_pll; 273 struct dss_pll *video2_pll; 274 275 const struct dispc_ops *dispc_ops; 276 }; 277 278 /* core */ 279 static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput) 280 { 281 /* To be implemented when the OMAP platform will provide this feature */ 282 return 0; 283 } 284 285 static inline bool dss_mgr_is_lcd(enum omap_channel id) 286 { 287 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 || 288 id == OMAP_DSS_CHANNEL_LCD3) 289 return true; 290 else 291 return false; 292 } 293 294 /* DSS */ 295 #if defined(CONFIG_OMAP2_DSS_DEBUGFS) 296 struct dss_debugfs_entry * 297 dss_debugfs_create_file(struct dss_device *dss, const char *name, 298 int (*show_fn)(struct seq_file *s, void *data), 299 void *data); 300 void dss_debugfs_remove_file(struct dss_debugfs_entry *entry); 301 #else 302 static inline struct dss_debugfs_entry * 303 dss_debugfs_create_file(struct dss_device *dss, const char *name, 304 int (*show_fn)(struct seq_file *s, void *data), 305 void *data) 306 { 307 return NULL; 308 } 309 310 static inline void dss_debugfs_remove_file(struct dss_debugfs_entry *entry) 311 { 312 } 313 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */ 314 315 struct dss_device *dss_get_device(struct device *dev); 316 317 int dss_runtime_get(struct dss_device *dss); 318 void dss_runtime_put(struct dss_device *dss); 319 320 unsigned long dss_get_dispc_clk_rate(struct dss_device *dss); 321 unsigned long dss_get_max_fck_rate(struct dss_device *dss); 322 enum omap_dss_output_id dss_get_supported_outputs(struct dss_device *dss, 323 enum omap_channel channel); 324 int dss_dpi_select_source(struct dss_device *dss, int port, 325 enum omap_channel channel); 326 void dss_select_hdmi_venc_clk_source(struct dss_device *dss, 327 enum dss_hdmi_venc_clk_source_select src); 328 const char *dss_get_clk_source_name(enum dss_clk_source clk_src); 329 330 /* DSS VIDEO PLL */ 331 struct dss_pll *dss_video_pll_init(struct dss_device *dss, 332 struct platform_device *pdev, int id, 333 struct regulator *regulator); 334 void dss_video_pll_uninit(struct dss_pll *pll); 335 336 void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable); 337 338 void dss_sdi_init(struct dss_device *dss, int datapairs); 339 int dss_sdi_enable(struct dss_device *dss); 340 void dss_sdi_disable(struct dss_device *dss); 341 342 void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module, 343 enum dss_clk_source clk_src); 344 void dss_select_lcd_clk_source(struct dss_device *dss, 345 enum omap_channel channel, 346 enum dss_clk_source clk_src); 347 enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss); 348 enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss, 349 int dsi_module); 350 enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss, 351 enum omap_channel channel); 352 353 void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type); 354 void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable); 355 356 int dss_set_fck_rate(struct dss_device *dss, unsigned long rate); 357 358 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data); 359 bool dss_div_calc(struct dss_device *dss, unsigned long pck, 360 unsigned long fck_min, dss_div_calc_func func, void *data); 361 362 /* SDI */ 363 #ifdef CONFIG_OMAP2_DSS_SDI 364 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev, 365 struct device_node *port); 366 void sdi_uninit_port(struct device_node *port); 367 #else 368 static inline int sdi_init_port(struct dss_device *dss, 369 struct platform_device *pdev, 370 struct device_node *port) 371 { 372 return 0; 373 } 374 static inline void sdi_uninit_port(struct device_node *port) 375 { 376 } 377 #endif 378 379 /* DSI */ 380 381 #ifdef CONFIG_OMAP2_DSS_DSI 382 383 void dsi_dump_clocks(struct seq_file *s); 384 385 void dsi_irq_handler(void); 386 387 #endif 388 389 /* DPI */ 390 #ifdef CONFIG_OMAP2_DSS_DPI 391 int dpi_init_port(struct dss_device *dss, struct platform_device *pdev, 392 struct device_node *port, enum dss_model dss_model); 393 void dpi_uninit_port(struct device_node *port); 394 #else 395 static inline int dpi_init_port(struct dss_device *port, 396 struct platform_device *pdev, 397 struct device_node *port, 398 enum dss_model dss_model) 399 { 400 return 0; 401 } 402 static inline void dpi_uninit_port(struct device_node *port) 403 { 404 } 405 #endif 406 407 /* DISPC */ 408 void dispc_dump_clocks(struct seq_file *s); 409 410 int dispc_runtime_get(void); 411 void dispc_runtime_put(void); 412 413 void dispc_enable_sidle(void); 414 void dispc_disable_sidle(void); 415 416 void dispc_lcd_enable_signal(bool enable); 417 void dispc_pck_free_enable(bool enable); 418 void dispc_enable_fifomerge(bool enable); 419 420 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck, 421 unsigned long pck, void *data); 422 bool dispc_div_calc(unsigned long dispc, 423 unsigned long pck_min, unsigned long pck_max, 424 dispc_div_calc_func func, void *data); 425 426 bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm); 427 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 428 struct dispc_clock_info *cinfo); 429 430 431 void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, 432 u32 high); 433 void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, 434 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 435 bool manual_update); 436 437 void dispc_mgr_set_clock_div(enum omap_channel channel, 438 const struct dispc_clock_info *cinfo); 439 int dispc_mgr_get_clock_div(enum omap_channel channel, 440 struct dispc_clock_info *cinfo); 441 void dispc_set_tv_pclk(unsigned long pclk); 442 443 u32 dispc_wb_get_framedone_irq(void); 444 bool dispc_wb_go_busy(void); 445 void dispc_wb_go(void); 446 void dispc_wb_set_channel_in(enum dss_writeback_channel channel); 447 int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 448 bool mem_to_mem, const struct videomode *vm); 449 450 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 451 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr) 452 { 453 int b; 454 for (b = 0; b < 32; ++b) { 455 if (irqstatus & (1 << b)) 456 irq_arr[b]++; 457 } 458 } 459 #endif 460 461 /* PLL */ 462 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint, 463 unsigned long clkdco, void *data); 464 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc, 465 void *data); 466 467 int dss_pll_register(struct dss_device *dss, struct dss_pll *pll); 468 void dss_pll_unregister(struct dss_pll *pll); 469 struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name); 470 struct dss_pll *dss_pll_find_by_src(struct dss_device *dss, 471 enum dss_clk_source src); 472 unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src); 473 int dss_pll_enable(struct dss_pll *pll); 474 void dss_pll_disable(struct dss_pll *pll); 475 int dss_pll_set_config(struct dss_pll *pll, 476 const struct dss_pll_clock_info *cinfo); 477 478 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco, 479 unsigned long out_min, unsigned long out_max, 480 dss_hsdiv_calc_func func, void *data); 481 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, 482 unsigned long pll_min, unsigned long pll_max, 483 dss_pll_calc_func func, void *data); 484 485 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin, 486 unsigned long target_clkout, struct dss_pll_clock_info *cinfo); 487 488 int dss_pll_write_config_type_a(struct dss_pll *pll, 489 const struct dss_pll_clock_info *cinfo); 490 int dss_pll_write_config_type_b(struct dss_pll *pll, 491 const struct dss_pll_clock_info *cinfo); 492 int dss_pll_wait_reset_done(struct dss_pll *pll); 493 494 extern struct platform_driver omap_dsshw_driver; 495 extern struct platform_driver omap_dispchw_driver; 496 #ifdef CONFIG_OMAP2_DSS_DSI 497 extern struct platform_driver omap_dsihw_driver; 498 #endif 499 #ifdef CONFIG_OMAP2_DSS_VENC 500 extern struct platform_driver omap_venchw_driver; 501 #endif 502 #ifdef CONFIG_OMAP4_DSS_HDMI 503 extern struct platform_driver omapdss_hdmi4hw_driver; 504 #endif 505 #ifdef CONFIG_OMAP5_DSS_HDMI 506 extern struct platform_driver omapdss_hdmi5hw_driver; 507 #endif 508 509 #endif 510