1b7019ac5SIlia Mirkin /* SPDX-License-Identifier: MIT */ 20a34fb31SBen Skeggs #ifndef __NVKM_PCI_PRIV_H__ 30a34fb31SBen Skeggs #define __NVKM_PCI_PRIV_H__ 40a34fb31SBen Skeggs #define nvkm_pci(p) container_of((p), struct nvkm_pci, subdev) 50a34fb31SBen Skeggs #include <subdev/pci.h> 60a34fb31SBen Skeggs 7*9b70cd54SBen Skeggs int nvkm_pci_new_(const struct nvkm_pci_func *, struct nvkm_device *, enum nvkm_subdev_type, int, 8*9b70cd54SBen Skeggs struct nvkm_pci **); 90a34fb31SBen Skeggs 100a34fb31SBen Skeggs struct nvkm_pci_func { 11779d16aaSBen Skeggs void (*init)(struct nvkm_pci *); 120a34fb31SBen Skeggs u32 (*rd32)(struct nvkm_pci *, u16 addr); 130a34fb31SBen Skeggs void (*wr08)(struct nvkm_pci *, u16 addr, u8 data); 140a34fb31SBen Skeggs void (*wr32)(struct nvkm_pci *, u16 addr, u32 data); 150a34fb31SBen Skeggs void (*msi_rearm)(struct nvkm_pci *); 16bcc19d9bSKarol Herbst 17bcc19d9bSKarol Herbst struct { 18bcc19d9bSKarol Herbst int (*init)(struct nvkm_pci *); 19bcc19d9bSKarol Herbst int (*set_link)(struct nvkm_pci *, enum nvkm_pcie_speed, u8); 20bcc19d9bSKarol Herbst 21bcc19d9bSKarol Herbst enum nvkm_pcie_speed (*max_speed)(struct nvkm_pci *); 22bcc19d9bSKarol Herbst enum nvkm_pcie_speed (*cur_speed)(struct nvkm_pci *); 23bcc19d9bSKarol Herbst 24bcc19d9bSKarol Herbst void (*set_version)(struct nvkm_pci *, u8); 25bcc19d9bSKarol Herbst int (*version)(struct nvkm_pci *); 26bcc19d9bSKarol Herbst int (*version_supported)(struct nvkm_pci *); 27bcc19d9bSKarol Herbst } pcie; 280a34fb31SBen Skeggs }; 290a34fb31SBen Skeggs 300a34fb31SBen Skeggs u32 nv40_pci_rd32(struct nvkm_pci *, u16); 310a34fb31SBen Skeggs void nv40_pci_wr08(struct nvkm_pci *, u16, u8); 320a34fb31SBen Skeggs void nv40_pci_wr32(struct nvkm_pci *, u16, u32); 33b31505c4SBen Skeggs void nv40_pci_msi_rearm(struct nvkm_pci *); 343e55b53bSBen Skeggs 35c4266a9cSBen Skeggs void nv46_pci_msi_rearm(struct nvkm_pci *); 365d5b43f5SPierre Moreau 375d5b43f5SPierre Moreau void g84_pci_init(struct nvkm_pci *pci); 38bcc19d9bSKarol Herbst 39bcc19d9bSKarol Herbst /* pcie functions */ 405cca4bdcSKarol Herbst void g84_pcie_set_version(struct nvkm_pci *, u8); 415cca4bdcSKarol Herbst int g84_pcie_version(struct nvkm_pci *); 425cca4bdcSKarol Herbst void g84_pcie_set_link_speed(struct nvkm_pci *, enum nvkm_pcie_speed); 435cca4bdcSKarol Herbst enum nvkm_pcie_speed g84_pcie_cur_speed(struct nvkm_pci *); 445cca4bdcSKarol Herbst enum nvkm_pcie_speed g84_pcie_max_speed(struct nvkm_pci *); 455cca4bdcSKarol Herbst int g84_pcie_init(struct nvkm_pci *); 465cca4bdcSKarol Herbst int g84_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8); 475cca4bdcSKarol Herbst 48725af748SKarol Herbst int g92_pcie_version_supported(struct nvkm_pci *); 495cca4bdcSKarol Herbst 507c923844SKarol Herbst void gf100_pcie_set_version(struct nvkm_pci *, u8); 517c923844SKarol Herbst int gf100_pcie_version(struct nvkm_pci *); 527c923844SKarol Herbst void gf100_pcie_set_cap_speed(struct nvkm_pci *, bool); 537c923844SKarol Herbst int gf100_pcie_cap_speed(struct nvkm_pci *); 547c923844SKarol Herbst int gf100_pcie_init(struct nvkm_pci *); 557c923844SKarol Herbst int gf100_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8); 567c923844SKarol Herbst 57bcc19d9bSKarol Herbst int nvkm_pcie_oneinit(struct nvkm_pci *); 58bcc19d9bSKarol Herbst int nvkm_pcie_init(struct nvkm_pci *); 590a34fb31SBen Skeggs #endif 60