xref: /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c (revision d0034a7a4ac7fae708146ac0059b9c47a1543f0d)
1c39f472eSBen Skeggs /*
2c39f472eSBen Skeggs  * Copyright (C) 2010 Francisco Jerez.
3c39f472eSBen Skeggs  * All Rights Reserved.
4c39f472eSBen Skeggs  *
5c39f472eSBen Skeggs  * Permission is hereby granted, free of charge, to any person obtaining
6c39f472eSBen Skeggs  * a copy of this software and associated documentation files (the
7c39f472eSBen Skeggs  * "Software"), to deal in the Software without restriction, including
8c39f472eSBen Skeggs  * without limitation the rights to use, copy, modify, merge, publish,
9c39f472eSBen Skeggs  * distribute, sublicense, and/or sell copies of the Software, and to
10c39f472eSBen Skeggs  * permit persons to whom the Software is furnished to do so, subject to
11c39f472eSBen Skeggs  * the following conditions:
12c39f472eSBen Skeggs  *
13c39f472eSBen Skeggs  * The above copyright notice and this permission notice (including the
14c39f472eSBen Skeggs  * next paragraph) shall be included in all copies or substantial
15c39f472eSBen Skeggs  * portions of the Software.
16c39f472eSBen Skeggs  *
17c39f472eSBen Skeggs  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18c39f472eSBen Skeggs  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19c39f472eSBen Skeggs  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20c39f472eSBen Skeggs  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21c39f472eSBen Skeggs  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22c39f472eSBen Skeggs  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23c39f472eSBen Skeggs  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24c39f472eSBen Skeggs  *
25c39f472eSBen Skeggs  */
26a8c4362bSBen Skeggs #include "nv04.h"
27a8c4362bSBen Skeggs #include "fbmem.h"
28c39f472eSBen Skeggs 
29c39f472eSBen Skeggs #include <subdev/bios.h>
30c39f472eSBen Skeggs #include <subdev/bios/bmp.h>
31a8c4362bSBen Skeggs #include <subdev/bios/init.h>
32c39f472eSBen Skeggs #include <subdev/vga.h>
33c39f472eSBen Skeggs 
34c39f472eSBen Skeggs static void
nv05_devinit_meminit(struct nvkm_devinit * init)358ac3f64fSBen Skeggs nv05_devinit_meminit(struct nvkm_devinit *init)
36c39f472eSBen Skeggs {
37c39f472eSBen Skeggs 	static const u8 default_config_tab[][2] = {
38c39f472eSBen Skeggs 		{ 0x24, 0x00 },
39c39f472eSBen Skeggs 		{ 0x28, 0x00 },
40c39f472eSBen Skeggs 		{ 0x24, 0x01 },
41c39f472eSBen Skeggs 		{ 0x1f, 0x00 },
42c39f472eSBen Skeggs 		{ 0x0f, 0x00 },
43c39f472eSBen Skeggs 		{ 0x17, 0x00 },
44c39f472eSBen Skeggs 		{ 0x06, 0x00 },
45c39f472eSBen Skeggs 		{ 0x00, 0x00 }
46c39f472eSBen Skeggs 	};
47aa860e4bSBen Skeggs 	struct nvkm_subdev *subdev = &init->subdev;
48aa860e4bSBen Skeggs 	struct nvkm_device *device = subdev->device;
498ac3f64fSBen Skeggs 	struct nvkm_bios *bios = device->bios;
50c39f472eSBen Skeggs 	struct io_mapping *fb;
51c39f472eSBen Skeggs 	u32 patt = 0xdeadbeef;
52c39f472eSBen Skeggs 	u16 data;
53c39f472eSBen Skeggs 	u8 strap, ramcfg[2];
54c39f472eSBen Skeggs 	int i, v;
55c39f472eSBen Skeggs 
56c39f472eSBen Skeggs 	/* Map the framebuffer aperture */
578ac3f64fSBen Skeggs 	fb = fbmem_init(device);
58c39f472eSBen Skeggs 	if (!fb) {
59aa860e4bSBen Skeggs 		nvkm_error(subdev, "failed to map fb\n");
60c39f472eSBen Skeggs 		return;
61c39f472eSBen Skeggs 	}
62c39f472eSBen Skeggs 
638ac3f64fSBen Skeggs 	strap = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2;
64c39f472eSBen Skeggs 	if ((data = bmp_mem_init_table(bios))) {
657f5f518fSBen Skeggs 		ramcfg[0] = nvbios_rd08(bios, data + 2 * strap + 0);
667f5f518fSBen Skeggs 		ramcfg[1] = nvbios_rd08(bios, data + 2 * strap + 1);
67c39f472eSBen Skeggs 	} else {
68c39f472eSBen Skeggs 		ramcfg[0] = default_config_tab[strap][0];
69c39f472eSBen Skeggs 		ramcfg[1] = default_config_tab[strap][1];
70c39f472eSBen Skeggs 	}
71c39f472eSBen Skeggs 
72c39f472eSBen Skeggs 	/* Sequencer off */
73a8dae9feSBen Skeggs 	nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) | 0x20);
74c39f472eSBen Skeggs 
758ac3f64fSBen Skeggs 	if (nvkm_rd32(device, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
76c39f472eSBen Skeggs 		goto out;
77c39f472eSBen Skeggs 
788ac3f64fSBen Skeggs 	nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
79c39f472eSBen Skeggs 
80c39f472eSBen Skeggs 	/* If present load the hardcoded scrambling table */
81c39f472eSBen Skeggs 	if (data) {
82c39f472eSBen Skeggs 		for (i = 0, data += 0x10; i < 8; i++, data += 4) {
837f5f518fSBen Skeggs 			u32 scramble = nvbios_rd32(bios, data);
848ac3f64fSBen Skeggs 			nvkm_wr32(device, NV04_PFB_SCRAMBLE(i), scramble);
85c39f472eSBen Skeggs 		}
86c39f472eSBen Skeggs 	}
87c39f472eSBen Skeggs 
88c39f472eSBen Skeggs 	/* Set memory type/width/length defaults depending on the straps */
898ac3f64fSBen Skeggs 	nvkm_mask(device, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
90c39f472eSBen Skeggs 
91c39f472eSBen Skeggs 	if (ramcfg[1] & 0x80)
928ac3f64fSBen Skeggs 		nvkm_mask(device, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
93c39f472eSBen Skeggs 
948ac3f64fSBen Skeggs 	nvkm_mask(device, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
958ac3f64fSBen Skeggs 	nvkm_mask(device, NV04_PFB_CFG1, 0, 1);
96c39f472eSBen Skeggs 
97c39f472eSBen Skeggs 	/* Probe memory bus width */
98c39f472eSBen Skeggs 	for (i = 0; i < 4; i++)
99c39f472eSBen Skeggs 		fbmem_poke(fb, 4 * i, patt);
100c39f472eSBen Skeggs 
101c39f472eSBen Skeggs 	if (fbmem_peek(fb, 0xc) != patt)
1028ac3f64fSBen Skeggs 		nvkm_mask(device, NV04_PFB_BOOT_0,
103c39f472eSBen Skeggs 			  NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
104c39f472eSBen Skeggs 
105c39f472eSBen Skeggs 	/* Probe memory length */
1068ac3f64fSBen Skeggs 	v = nvkm_rd32(device, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
107c39f472eSBen Skeggs 
108c39f472eSBen Skeggs 	if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
109c39f472eSBen Skeggs 	    (!fbmem_readback(fb, 0x1000000, ++patt) ||
110c39f472eSBen Skeggs 	     !fbmem_readback(fb, 0, ++patt)))
1118ac3f64fSBen Skeggs 		nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
112c39f472eSBen Skeggs 			  NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
113c39f472eSBen Skeggs 
114c39f472eSBen Skeggs 	if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
115c39f472eSBen Skeggs 	    !fbmem_readback(fb, 0x800000, ++patt))
1168ac3f64fSBen Skeggs 		nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
117c39f472eSBen Skeggs 			  NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
118c39f472eSBen Skeggs 
119c39f472eSBen Skeggs 	if (!fbmem_readback(fb, 0x400000, ++patt))
1208ac3f64fSBen Skeggs 		nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
121c39f472eSBen Skeggs 			  NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
122c39f472eSBen Skeggs 
123c39f472eSBen Skeggs out:
124c39f472eSBen Skeggs 	/* Sequencer on */
125a8dae9feSBen Skeggs 	nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) & ~0x20);
126c39f472eSBen Skeggs 	fbmem_fini(fb);
127c39f472eSBen Skeggs }
128c39f472eSBen Skeggs 
129151abd44SBen Skeggs static const struct nvkm_devinit_func
130151abd44SBen Skeggs nv05_devinit = {
131c39f472eSBen Skeggs 	.dtor = nv04_devinit_dtor,
132151abd44SBen Skeggs 	.preinit = nv04_devinit_preinit,
133151abd44SBen Skeggs 	.post = nv04_devinit_post,
134c39f472eSBen Skeggs 	.meminit = nv05_devinit_meminit,
135c39f472eSBen Skeggs 	.pll_set = nv04_devinit_pll_set,
136151abd44SBen Skeggs };
137151abd44SBen Skeggs 
138151abd44SBen Skeggs int
nv05_devinit_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_devinit ** pinit)139*4a34fd0eSBen Skeggs nv05_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
140151abd44SBen Skeggs 		 struct nvkm_devinit **pinit)
141151abd44SBen Skeggs {
142*4a34fd0eSBen Skeggs 	return nv04_devinit_new_(&nv05_devinit, device, type, inst, pinit);
143151abd44SBen Skeggs }
144