xref: /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.c (revision 3eb66e91a25497065c5322b1268cbc3953642227)
139b7e6e5SMartin Peres /*
239b7e6e5SMartin Peres  * Copyright 2015 Martin Peres
339b7e6e5SMartin Peres  *
439b7e6e5SMartin Peres  * Permission is hereby granted, free of charge, to any person obtaining a
539b7e6e5SMartin Peres  * copy of this software and associated documentation files (the "Software"),
639b7e6e5SMartin Peres  * to deal in the Software without restriction, including without limitation
739b7e6e5SMartin Peres  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
839b7e6e5SMartin Peres  * and/or sell copies of the Software, and to permit persons to whom the
939b7e6e5SMartin Peres  * Software is furnished to do so, subject to the following conditions:
1039b7e6e5SMartin Peres  *
1139b7e6e5SMartin Peres  * The above copyright notice and this permission notice shall be included in
1239b7e6e5SMartin Peres  * all copies or substantial portions of the Software.
1339b7e6e5SMartin Peres  *
1439b7e6e5SMartin Peres  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1539b7e6e5SMartin Peres  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1639b7e6e5SMartin Peres  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1739b7e6e5SMartin Peres  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1839b7e6e5SMartin Peres  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1939b7e6e5SMartin Peres  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2039b7e6e5SMartin Peres  * OTHER DEALINGS IN THE SOFTWARE.
2139b7e6e5SMartin Peres  *
2239b7e6e5SMartin Peres  * Authors: Martin Peres
2339b7e6e5SMartin Peres  */
2439b7e6e5SMartin Peres #include <subdev/bios.h>
2539b7e6e5SMartin Peres #include <subdev/bios/bit.h>
26a8c119a4SKarol Herbst #include <subdev/bios/extdev.h>
2739b7e6e5SMartin Peres #include <subdev/bios/iccsense.h>
2839b7e6e5SMartin Peres 
295764ff60SBen Skeggs static u32
nvbios_iccsense_table(struct nvkm_bios * bios,u8 * ver,u8 * hdr,u8 * cnt,u8 * len)3039b7e6e5SMartin Peres nvbios_iccsense_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt,
3139b7e6e5SMartin Peres 		      u8 *len)
3239b7e6e5SMartin Peres {
3339b7e6e5SMartin Peres 	struct bit_entry bit_P;
345764ff60SBen Skeggs 	u32 iccsense;
3539b7e6e5SMartin Peres 
3639b7e6e5SMartin Peres 	if (bit_entry(bios, 'P', &bit_P) || bit_P.version != 2 ||
3739b7e6e5SMartin Peres 	    bit_P.length < 0x2c)
3839b7e6e5SMartin Peres 		return 0;
3939b7e6e5SMartin Peres 
405764ff60SBen Skeggs 	iccsense = nvbios_rd32(bios, bit_P.offset + 0x28);
4139b7e6e5SMartin Peres 	if (!iccsense)
4239b7e6e5SMartin Peres 		return 0;
4339b7e6e5SMartin Peres 
4439b7e6e5SMartin Peres 	*ver = nvbios_rd08(bios, iccsense + 0);
4539b7e6e5SMartin Peres 	switch (*ver) {
4639b7e6e5SMartin Peres 	case 0x10:
4739b7e6e5SMartin Peres 	case 0x20:
4839b7e6e5SMartin Peres 		*hdr = nvbios_rd08(bios, iccsense + 1);
4939b7e6e5SMartin Peres 		*len = nvbios_rd08(bios, iccsense + 2);
5039b7e6e5SMartin Peres 		*cnt = nvbios_rd08(bios, iccsense + 3);
5139b7e6e5SMartin Peres 		return iccsense;
5239b7e6e5SMartin Peres 	default:
5339b7e6e5SMartin Peres 		break;
5439b7e6e5SMartin Peres 	}
5539b7e6e5SMartin Peres 
5639b7e6e5SMartin Peres 	return 0;
5739b7e6e5SMartin Peres }
5839b7e6e5SMartin Peres 
5939b7e6e5SMartin Peres int
nvbios_iccsense_parse(struct nvkm_bios * bios,struct nvbios_iccsense * iccsense)6039b7e6e5SMartin Peres nvbios_iccsense_parse(struct nvkm_bios *bios, struct nvbios_iccsense *iccsense)
6139b7e6e5SMartin Peres {
6239b7e6e5SMartin Peres 	struct nvkm_subdev *subdev = &bios->subdev;
6339b7e6e5SMartin Peres 	u8 ver, hdr, cnt, len, i;
645764ff60SBen Skeggs 	u32 table, entry;
6539b7e6e5SMartin Peres 
6639b7e6e5SMartin Peres 	table = nvbios_iccsense_table(bios, &ver, &hdr, &cnt, &len);
6739b7e6e5SMartin Peres 	if (!table || !cnt)
6839b7e6e5SMartin Peres 		return -EINVAL;
6939b7e6e5SMartin Peres 
7039b7e6e5SMartin Peres 	if (ver != 0x10 && ver != 0x20) {
7139b7e6e5SMartin Peres 		nvkm_error(subdev, "ICCSENSE version 0x%02x unknown\n", ver);
7239b7e6e5SMartin Peres 		return -EINVAL;
7339b7e6e5SMartin Peres 	}
7439b7e6e5SMartin Peres 
7539b7e6e5SMartin Peres 	iccsense->nr_entry = cnt;
76*6da2ec56SKees Cook 	iccsense->rail = kmalloc_array(cnt, sizeof(struct pwr_rail_t),
77*6da2ec56SKees Cook 				       GFP_KERNEL);
7839b7e6e5SMartin Peres 	if (!iccsense->rail)
7939b7e6e5SMartin Peres 		return -ENOMEM;
8039b7e6e5SMartin Peres 
8139b7e6e5SMartin Peres 	for (i = 0; i < cnt; ++i) {
82a8c119a4SKarol Herbst 		struct nvbios_extdev_func extdev;
8339b7e6e5SMartin Peres 		struct pwr_rail_t *rail = &iccsense->rail[i];
84a8c119a4SKarol Herbst 		u8 res_start = 0;
85a8c119a4SKarol Herbst 		int r;
86a8c119a4SKarol Herbst 
8739b7e6e5SMartin Peres 		entry = table + hdr + i * len;
8839b7e6e5SMartin Peres 
8939b7e6e5SMartin Peres 		switch(ver) {
9039b7e6e5SMartin Peres 		case 0x10:
914dc33b12SKarol Herbst 			if ((nvbios_rd08(bios, entry + 0x1) & 0xf8) == 0xf8)
924dc33b12SKarol Herbst 				rail->mode = 1;
934dc33b12SKarol Herbst 			else
944dc33b12SKarol Herbst 				rail->mode = 0;
9539b7e6e5SMartin Peres 			rail->extdev_id = nvbios_rd08(bios, entry + 0x2);
96a8c119a4SKarol Herbst 			res_start = 0x3;
9739b7e6e5SMartin Peres 			break;
9839b7e6e5SMartin Peres 		case 0x20:
9939b7e6e5SMartin Peres 			rail->mode = nvbios_rd08(bios, entry);
10039b7e6e5SMartin Peres 			rail->extdev_id = nvbios_rd08(bios, entry + 0x1);
101a8c119a4SKarol Herbst 			res_start = 0x5;
10239b7e6e5SMartin Peres 			break;
103f5a5b523SBen Skeggs 		}
104a8c119a4SKarol Herbst 
105a8c119a4SKarol Herbst 		if (nvbios_extdev_parse(bios, rail->extdev_id, &extdev))
106a8c119a4SKarol Herbst 			continue;
107a8c119a4SKarol Herbst 
108a8c119a4SKarol Herbst 		switch (extdev.type) {
109a8c119a4SKarol Herbst 		case NVBIOS_EXTDEV_INA209:
110a8c119a4SKarol Herbst 		case NVBIOS_EXTDEV_INA219:
111a8c119a4SKarol Herbst 			rail->resistor_count = 1;
112a8c119a4SKarol Herbst 			break;
113a8c119a4SKarol Herbst 		case NVBIOS_EXTDEV_INA3221:
114a8c119a4SKarol Herbst 			rail->resistor_count = 3;
115a8c119a4SKarol Herbst 			break;
116a8c119a4SKarol Herbst 		default:
117a8c119a4SKarol Herbst 			rail->resistor_count = 0;
118a8c119a4SKarol Herbst 			break;
119f5a5b523SBen Skeggs 		}
120a8c119a4SKarol Herbst 
121a8c119a4SKarol Herbst 		for (r = 0; r < rail->resistor_count; ++r) {
122a8c119a4SKarol Herbst 			rail->resistors[r].mohm = nvbios_rd08(bios, entry + res_start + r * 2);
123a8c119a4SKarol Herbst 			rail->resistors[r].enabled = !(nvbios_rd08(bios, entry + res_start + r * 2 + 1) & 0x40);
124a8c119a4SKarol Herbst 		}
125a8c119a4SKarol Herbst 		rail->config = nvbios_rd16(bios, entry + res_start + rail->resistor_count * 2);
12639b7e6e5SMartin Peres 	}
12739b7e6e5SMartin Peres 
12839b7e6e5SMartin Peres 	return 0;
12939b7e6e5SMartin Peres }
130