xref: /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c (revision 2541626cfb794e57ba0575a6920826f591f7ced0)
1 /*
2  * Copyright 2019 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include "priv.h"
23 
24 #include <core/falcon.h>
25 #include <core/firmware.h>
26 #include <core/memory.h>
27 #include <subdev/mc.h>
28 #include <subdev/mmu.h>
29 #include <subdev/pmu.h>
30 #include <subdev/timer.h>
31 
32 #include <nvfw/acr.h>
33 #include <nvfw/flcn.h>
34 
35 const struct nvkm_acr_func
36 gm200_acr = {
37 };
38 
39 int
40 gm200_acr_nofw(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
41 {
42 	nvkm_warn(&acr->subdev, "firmware unavailable\n");
43 	return 0;
44 }
45 
46 int
47 gm200_acr_init(struct nvkm_acr *acr)
48 {
49 	return nvkm_acr_hsfw_boot(acr, "load");
50 }
51 
52 void
53 gm200_acr_wpr_check(struct nvkm_acr *acr, u64 *start, u64 *limit)
54 {
55 	struct nvkm_device *device = acr->subdev.device;
56 
57 	nvkm_wr32(device, 0x100cd4, 2);
58 	*start = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8;
59 	nvkm_wr32(device, 0x100cd4, 3);
60 	*limit = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8;
61 	*limit = *limit + 0x20000;
62 }
63 
64 void
65 gm200_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust)
66 {
67 	struct nvkm_subdev *subdev = &acr->subdev;
68 	struct wpr_header hdr;
69 	struct lsb_header lsb;
70 	struct nvkm_acr_lsf *lsfw;
71 	u32 offset = 0;
72 
73 	do {
74 		nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr));
75 		wpr_header_dump(subdev, &hdr);
76 
77 		list_for_each_entry(lsfw, &acr->lsfw, head) {
78 			if (lsfw->id != hdr.falcon_id)
79 				continue;
80 
81 			nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb));
82 			lsb_header_dump(subdev, &lsb);
83 
84 			lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust);
85 			break;
86 		}
87 		offset += sizeof(hdr);
88 	} while (hdr.falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID);
89 }
90 
91 void
92 gm200_acr_wpr_build_lsb_tail(struct nvkm_acr_lsfw *lsfw,
93 			     struct lsb_header_tail *hdr)
94 {
95 	hdr->ucode_off = lsfw->offset.img;
96 	hdr->ucode_size = lsfw->ucode_size;
97 	hdr->data_size = lsfw->data_size;
98 	hdr->bl_code_size = lsfw->bootloader_size;
99 	hdr->bl_imem_off = lsfw->bootloader_imem_offset;
100 	hdr->bl_data_off = lsfw->offset.bld;
101 	hdr->bl_data_size = lsfw->bl_data_size;
102 	hdr->app_code_off = lsfw->app_start_offset +
103 			   lsfw->app_resident_code_offset;
104 	hdr->app_code_size = lsfw->app_resident_code_size;
105 	hdr->app_data_off = lsfw->app_start_offset +
106 			   lsfw->app_resident_data_offset;
107 	hdr->app_data_size = lsfw->app_resident_data_size;
108 	hdr->flags = lsfw->func->flags;
109 }
110 
111 static int
112 gm200_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw)
113 {
114 	struct lsb_header hdr;
115 
116 	if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature)))
117 		return -EINVAL;
118 
119 	memcpy(&hdr.signature, lsfw->sig->data, lsfw->sig->size);
120 	gm200_acr_wpr_build_lsb_tail(lsfw, &hdr.tail);
121 
122 	nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr));
123 	return 0;
124 }
125 
126 int
127 gm200_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
128 {
129 	struct nvkm_acr_lsfw *lsfw;
130 	u32 offset = 0;
131 	int ret;
132 
133 	/* Fill per-LSF structures. */
134 	list_for_each_entry(lsfw, &acr->lsfw, head) {
135 		struct wpr_header hdr = {
136 			.falcon_id = lsfw->id,
137 			.lsb_offset = lsfw->offset.lsb,
138 			.bootstrap_owner = NVKM_ACR_LSF_PMU,
139 			.lazy_bootstrap = rtos && lsfw->id != rtos->id,
140 			.status = WPR_HEADER_V0_STATUS_COPY,
141 		};
142 
143 		/* Write WPR header. */
144 		nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
145 		offset += sizeof(hdr);
146 
147 		/* Write LSB header. */
148 		ret = gm200_acr_wpr_build_lsb(acr, lsfw);
149 		if (ret)
150 			return ret;
151 
152 		/* Write ucode image. */
153 		nvkm_wobj(acr->wpr, lsfw->offset.img,
154 				    lsfw->img.data,
155 				    lsfw->img.size);
156 
157 		/* Write bootloader data. */
158 		lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw);
159 	}
160 
161 	/* Finalise WPR. */
162 	nvkm_wo32(acr->wpr, offset, WPR_HEADER_V0_FALCON_ID_INVALID);
163 	return 0;
164 }
165 
166 static int
167 gm200_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size)
168 {
169 	int ret = nvkm_memory_new(acr->subdev.device, NVKM_MEM_TARGET_INST,
170 				  ALIGN(wpr_size, 0x40000), 0x40000, true,
171 				  &acr->wpr);
172 	if (ret)
173 		return ret;
174 
175 	acr->wpr_start = nvkm_memory_addr(acr->wpr);
176 	acr->wpr_end = acr->wpr_start + nvkm_memory_size(acr->wpr);
177 	return 0;
178 }
179 
180 u32
181 gm200_acr_wpr_layout(struct nvkm_acr *acr)
182 {
183 	struct nvkm_acr_lsfw *lsfw;
184 	u32 wpr = 0;
185 
186 	wpr += 11 /* MAX_LSF */ * sizeof(struct wpr_header);
187 
188 	list_for_each_entry(lsfw, &acr->lsfw, head) {
189 		wpr  = ALIGN(wpr, 256);
190 		lsfw->offset.lsb = wpr;
191 		wpr += sizeof(struct lsb_header);
192 
193 		wpr  = ALIGN(wpr, 4096);
194 		lsfw->offset.img = wpr;
195 		wpr += lsfw->img.size;
196 
197 		wpr  = ALIGN(wpr, 256);
198 		lsfw->offset.bld = wpr;
199 		lsfw->bl_data_size = ALIGN(lsfw->func->bld_size, 256);
200 		wpr += lsfw->bl_data_size;
201 	}
202 
203 	return wpr;
204 }
205 
206 int
207 gm200_acr_wpr_parse(struct nvkm_acr *acr)
208 {
209 	const struct wpr_header *hdr = (void *)acr->wpr_fw->data;
210 	struct nvkm_acr_lsfw *lsfw;
211 
212 	while (hdr->falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID) {
213 		wpr_header_dump(&acr->subdev, hdr);
214 		lsfw = nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id);
215 		if (IS_ERR(lsfw))
216 			return PTR_ERR(lsfw);
217 	}
218 
219 	return 0;
220 }
221 
222 int
223 gm200_acr_hsfw_load_bld(struct nvkm_falcon_fw *fw)
224 {
225 	struct flcn_bl_dmem_desc_v1 hsdesc = {
226 		.ctx_dma = FALCON_DMAIDX_VIRT,
227 		.code_dma_base = fw->vma->addr,
228 		.non_sec_code_off = fw->nmem_base,
229 		.non_sec_code_size = fw->nmem_size,
230 		.sec_code_off = fw->imem_base,
231 		.sec_code_size = fw->imem_size,
232 		.code_entry_point = 0,
233 		.data_dma_base = fw->vma->addr + fw->dmem_base_img,
234 		.data_size = fw->dmem_size,
235 	};
236 
237 	flcn_bl_dmem_desc_v1_dump(fw->falcon->user, &hsdesc);
238 
239 	return nvkm_falcon_pio_wr(fw->falcon, (u8 *)&hsdesc, 0, 0, DMEM, 0, sizeof(hsdesc), 0, 0);
240 }
241 
242 int
243 gm200_acr_hsfw_ctor(struct nvkm_acr *acr, const char *bl, const char *fw, const char *name, int ver,
244 		    const struct nvkm_acr_hsf_fwif *fwif)
245 {
246 	struct nvkm_acr_hsfw *hsfw;
247 
248 	if (!(hsfw = kzalloc(sizeof(*hsfw), GFP_KERNEL)))
249 		return -ENOMEM;
250 
251 	hsfw->falcon_id = fwif->falcon_id;
252 	hsfw->boot_mbox0 = fwif->boot_mbox0;
253 	hsfw->intr_clear = fwif->intr_clear;
254 	list_add_tail(&hsfw->head, &acr->hsfw);
255 
256 	return nvkm_falcon_fw_ctor_hs(fwif->func, name, &acr->subdev, bl, fw, ver, NULL, &hsfw->fw);
257 }
258 
259 const struct nvkm_falcon_fw_func
260 gm200_acr_unload_0 = {
261 	.signature = gm200_flcn_fw_signature,
262 	.reset = gm200_flcn_fw_reset,
263 	.load = gm200_flcn_fw_load,
264 	.load_bld = gm200_acr_hsfw_load_bld,
265 	.boot = gm200_flcn_fw_boot,
266 };
267 
268 MODULE_FIRMWARE("nvidia/gm200/acr/ucode_unload.bin");
269 MODULE_FIRMWARE("nvidia/gm204/acr/ucode_unload.bin");
270 MODULE_FIRMWARE("nvidia/gm206/acr/ucode_unload.bin");
271 MODULE_FIRMWARE("nvidia/gp100/acr/ucode_unload.bin");
272 
273 static const struct nvkm_acr_hsf_fwif
274 gm200_acr_unload_fwif[] = {
275 	{ 0, gm200_acr_hsfw_ctor, &gm200_acr_unload_0, NVKM_ACR_HSF_PMU, 0, 0x00000010 },
276 	{}
277 };
278 
279 static int
280 gm200_acr_load_setup(struct nvkm_falcon_fw *fw)
281 {
282 	struct flcn_acr_desc *desc = (void *)&fw->fw.img[fw->dmem_base_img];
283 	struct nvkm_acr *acr = fw->falcon->owner->device->acr;
284 
285 	desc->wpr_region_id = 1;
286 	desc->regions.no_regions = 2;
287 	desc->regions.region_props[0].start_addr = acr->wpr_start >> 8;
288 	desc->regions.region_props[0].end_addr = acr->wpr_end >> 8;
289 	desc->regions.region_props[0].region_id = 1;
290 	desc->regions.region_props[0].read_mask = 0xf;
291 	desc->regions.region_props[0].write_mask = 0xc;
292 	desc->regions.region_props[0].client_mask = 0x2;
293 	flcn_acr_desc_dump(&acr->subdev, desc);
294 	return 0;
295 }
296 
297 static const struct nvkm_falcon_fw_func
298 gm200_acr_load_0 = {
299 	.signature = gm200_flcn_fw_signature,
300 	.reset = gm200_flcn_fw_reset,
301 	.setup = gm200_acr_load_setup,
302 	.load = gm200_flcn_fw_load,
303 	.load_bld = gm200_acr_hsfw_load_bld,
304 	.boot = gm200_flcn_fw_boot,
305 };
306 
307 MODULE_FIRMWARE("nvidia/gm200/acr/bl.bin");
308 MODULE_FIRMWARE("nvidia/gm200/acr/ucode_load.bin");
309 
310 MODULE_FIRMWARE("nvidia/gm204/acr/bl.bin");
311 MODULE_FIRMWARE("nvidia/gm204/acr/ucode_load.bin");
312 
313 MODULE_FIRMWARE("nvidia/gm206/acr/bl.bin");
314 MODULE_FIRMWARE("nvidia/gm206/acr/ucode_load.bin");
315 
316 MODULE_FIRMWARE("nvidia/gp100/acr/bl.bin");
317 MODULE_FIRMWARE("nvidia/gp100/acr/ucode_load.bin");
318 
319 static const struct nvkm_acr_hsf_fwif
320 gm200_acr_load_fwif[] = {
321 	{ 0, gm200_acr_hsfw_ctor, &gm200_acr_load_0, NVKM_ACR_HSF_PMU, 0, 0x00000010 },
322 	{}
323 };
324 
325 static const struct nvkm_acr_func
326 gm200_acr_0 = {
327 	.load = gm200_acr_load_fwif,
328 	.unload = gm200_acr_unload_fwif,
329 	.wpr_parse = gm200_acr_wpr_parse,
330 	.wpr_layout = gm200_acr_wpr_layout,
331 	.wpr_alloc = gm200_acr_wpr_alloc,
332 	.wpr_build = gm200_acr_wpr_build,
333 	.wpr_patch = gm200_acr_wpr_patch,
334 	.wpr_check = gm200_acr_wpr_check,
335 	.init = gm200_acr_init,
336 	.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
337 			     BIT_ULL(NVKM_ACR_LSF_GPCCS),
338 };
339 
340 static int
341 gm200_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
342 {
343 	struct nvkm_subdev *subdev = &acr->subdev;
344 	const struct nvkm_acr_hsf_fwif *hsfwif;
345 
346 	hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad",
347 				    acr, "acr/bl", "acr/ucode_load", "load");
348 	if (IS_ERR(hsfwif))
349 		return PTR_ERR(hsfwif);
350 
351 	hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload",
352 				    acr, "acr/bl", "acr/ucode_unload",
353 				    "unload");
354 	if (IS_ERR(hsfwif))
355 		return PTR_ERR(hsfwif);
356 
357 	return 0;
358 }
359 
360 static const struct nvkm_acr_fwif
361 gm200_acr_fwif[] = {
362 	{  0, gm200_acr_load, &gm200_acr_0 },
363 	{ -1, gm200_acr_nofw, &gm200_acr },
364 	{}
365 };
366 
367 int
368 gm200_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
369 	      struct nvkm_acr **pacr)
370 {
371 	return nvkm_acr_new_(gm200_acr_fwif, device, type, inst, pacr);
372 }
373