1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "cgrp.h" 25 #include "chan.h" 26 #include "chid.h" 27 #include "runl.h" 28 29 #include "nv04.h" 30 #include "channv04.h" 31 #include "regsnv04.h" 32 33 #include <core/ramht.h> 34 #include <subdev/instmem.h> 35 #include <subdev/mc.h> 36 #include <subdev/timer.h> 37 #include <engine/sw.h> 38 39 #include <nvif/class.h> 40 41 static const struct nv04_fifo_ramfc 42 nv04_fifo_ramfc[] = { 43 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 44 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 45 { 16, 0, 0x08, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, 46 { 16, 16, 0x08, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, 47 { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_STATE }, 48 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, 49 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_ENGINE }, 50 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_PULL1 }, 51 {} 52 }; 53 54 void 55 nv04_chan_stop(struct nvkm_chan *chan) 56 { 57 struct nv04_fifo *fifo = nv04_fifo(chan->cgrp->runl->fifo); 58 struct nvkm_device *device = fifo->base.engine.subdev.device; 59 struct nvkm_memory *fctx = device->imem->ramfc; 60 const struct nv04_fifo_ramfc *c; 61 unsigned long flags; 62 u32 data = nv04_fifo_chan(chan)->ramfc; 63 u32 chid; 64 65 /* prevent fifo context switches */ 66 spin_lock_irqsave(&fifo->base.lock, flags); 67 nvkm_wr32(device, NV03_PFIFO_CACHES, 0); 68 69 /* if this channel is active, replace it with a null context */ 70 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->base.chid->mask; 71 if (chid == chan->id) { 72 nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); 73 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0); 74 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); 75 76 c = fifo->ramfc; 77 nvkm_kmap(fctx); 78 do { 79 u32 rm = ((1ULL << c->bits) - 1) << c->regs; 80 u32 cm = ((1ULL << c->bits) - 1) << c->ctxs; 81 u32 rv = (nvkm_rd32(device, c->regp) & rm) >> c->regs; 82 u32 cv = (nvkm_ro32(fctx, c->ctxp + data) & ~cm); 83 nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); 84 } while ((++c)->bits); 85 nvkm_done(fctx); 86 87 c = fifo->ramfc; 88 do { 89 nvkm_wr32(device, c->regp, 0x00000000); 90 } while ((++c)->bits); 91 92 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0); 93 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0); 94 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.chid->mask); 95 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 96 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 97 } 98 99 /* restore normal operation, after disabling dma mode */ 100 nvkm_mask(device, NV04_PFIFO_MODE, BIT(chan->id), 0); 101 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 102 spin_unlock_irqrestore(&fifo->base.lock, flags); 103 } 104 105 void 106 nv04_chan_start(struct nvkm_chan *chan) 107 { 108 struct nvkm_fifo *fifo = chan->cgrp->runl->fifo; 109 unsigned long flags; 110 111 spin_lock_irqsave(&fifo->lock, flags); 112 nvkm_mask(fifo->engine.subdev.device, NV04_PFIFO_MODE, BIT(chan->id), BIT(chan->id)); 113 spin_unlock_irqrestore(&fifo->lock, flags); 114 } 115 116 const struct nvkm_chan_func_inst 117 nv04_chan_inst = { 118 .size = 0x1000, 119 }; 120 121 static const struct nvkm_chan_func 122 nv04_chan = { 123 .inst = &nv04_chan_inst, 124 .start = nv04_chan_start, 125 .stop = nv04_chan_stop, 126 }; 127 128 const struct nvkm_cgrp_func 129 nv04_cgrp = { 130 }; 131 132 const struct nvkm_engn_func 133 nv04_engn = { 134 }; 135 136 void 137 nv04_fifo_pause(struct nvkm_fifo *fifo, unsigned long *pflags) 138 __acquires(fifo->lock) 139 { 140 struct nvkm_device *device = fifo->engine.subdev.device; 141 unsigned long flags; 142 143 spin_lock_irqsave(&fifo->lock, flags); 144 *pflags = flags; 145 146 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000); 147 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); 148 149 /* in some cases the puller may be left in an inconsistent state 150 * if you try to stop it while it's busy translating handles. 151 * sometimes you get a CACHE_ERROR, sometimes it just fails 152 * silently; sending incorrect instance offsets to PGRAPH after 153 * it's started up again. 154 * 155 * to avoid this, we invalidate the most recently calculated 156 * instance. 157 */ 158 nvkm_msec(device, 2000, 159 u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0); 160 if (!(tmp & NV04_PFIFO_CACHE1_PULL0_HASH_BUSY)) 161 break; 162 ); 163 164 if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) & 165 NV04_PFIFO_CACHE1_PULL0_HASH_FAILED) 166 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); 167 168 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0x00000000); 169 } 170 171 void 172 nv04_fifo_start(struct nvkm_fifo *fifo, unsigned long *pflags) 173 __releases(fifo->lock) 174 { 175 struct nvkm_device *device = fifo->engine.subdev.device; 176 unsigned long flags = *pflags; 177 178 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); 179 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000001); 180 181 spin_unlock_irqrestore(&fifo->lock, flags); 182 } 183 184 const struct nvkm_runl_func 185 nv04_runl = { 186 }; 187 188 int 189 nv04_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) 190 { 191 switch (engine->subdev.type) { 192 case NVKM_ENGINE_SW : return NV04_FIFO_ENGN_SW; 193 case NVKM_ENGINE_GR : return NV04_FIFO_ENGN_GR; 194 case NVKM_ENGINE_MPEG : return NV04_FIFO_ENGN_MPEG; 195 case NVKM_ENGINE_DMAOBJ: return NV04_FIFO_ENGN_DMA; 196 default: 197 WARN_ON(1); 198 return 0; 199 } 200 } 201 202 static const char * 203 nv_dma_state_err(u32 state) 204 { 205 static const char * const desc[] = { 206 "NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE", 207 "INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK" 208 }; 209 return desc[(state >> 29) & 0x7]; 210 } 211 212 static bool 213 nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data) 214 { 215 struct nvkm_sw *sw = device->sw; 216 const int subc = (addr & 0x0000e000) >> 13; 217 const int mthd = (addr & 0x00001ffc); 218 const u32 mask = 0x0000000f << (subc * 4); 219 u32 engine = nvkm_rd32(device, 0x003280); 220 bool handled = false; 221 222 switch (mthd) { 223 case 0x0000 ... 0x0000: /* subchannel's engine -> software */ 224 nvkm_wr32(device, 0x003280, (engine &= ~mask)); 225 fallthrough; 226 case 0x0180 ... 0x01fc: /* handle -> instance */ 227 data = nvkm_rd32(device, 0x003258) & 0x0000ffff; 228 fallthrough; 229 case 0x0100 ... 0x017c: 230 case 0x0200 ... 0x1ffc: /* pass method down to sw */ 231 if (!(engine & mask) && sw) 232 handled = nvkm_sw_mthd(sw, chid, subc, mthd, data); 233 break; 234 default: 235 break; 236 } 237 238 return handled; 239 } 240 241 static void 242 nv04_fifo_intr_cache_error(struct nvkm_fifo *fifo, u32 chid, u32 get) 243 { 244 struct nvkm_subdev *subdev = &fifo->engine.subdev; 245 struct nvkm_device *device = subdev->device; 246 struct nvkm_chan *chan; 247 unsigned long flags; 248 u32 pull0 = nvkm_rd32(device, 0x003250); 249 u32 mthd, data; 250 int ptr; 251 252 /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before wrapping on my 253 * G80 chips, but CACHE1 isn't big enough for this much data.. Tests 254 * show that it wraps around to the start at GET=0x800.. No clue as to 255 * why.. 256 */ 257 ptr = (get & 0x7ff) >> 2; 258 259 if (device->card_type < NV_40) { 260 mthd = nvkm_rd32(device, NV04_PFIFO_CACHE1_METHOD(ptr)); 261 data = nvkm_rd32(device, NV04_PFIFO_CACHE1_DATA(ptr)); 262 } else { 263 mthd = nvkm_rd32(device, NV40_PFIFO_CACHE1_METHOD(ptr)); 264 data = nvkm_rd32(device, NV40_PFIFO_CACHE1_DATA(ptr)); 265 } 266 267 if (!(pull0 & 0x00000100) || 268 !nv04_fifo_swmthd(device, chid, mthd, data)) { 269 chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); 270 nvkm_error(subdev, "CACHE_ERROR - " 271 "ch %d [%s] subc %d mthd %04x data %08x\n", 272 chid, chan ? chan->name : "unknown", 273 (mthd >> 13) & 7, mthd & 0x1ffc, data); 274 nvkm_chan_put(&chan, flags); 275 } 276 277 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0); 278 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); 279 280 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 281 nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) & ~1); 282 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); 283 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 284 nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) | 1); 285 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0); 286 287 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 288 nvkm_rd32(device, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); 289 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 290 } 291 292 static void 293 nv04_fifo_intr_dma_pusher(struct nvkm_fifo *fifo, u32 chid) 294 { 295 struct nvkm_subdev *subdev = &fifo->engine.subdev; 296 struct nvkm_device *device = subdev->device; 297 u32 dma_get = nvkm_rd32(device, 0x003244); 298 u32 dma_put = nvkm_rd32(device, 0x003240); 299 u32 push = nvkm_rd32(device, 0x003220); 300 u32 state = nvkm_rd32(device, 0x003228); 301 struct nvkm_chan *chan; 302 unsigned long flags; 303 const char *name; 304 305 chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); 306 name = chan ? chan->name : "unknown"; 307 if (device->card_type == NV_50) { 308 u32 ho_get = nvkm_rd32(device, 0x003328); 309 u32 ho_put = nvkm_rd32(device, 0x003320); 310 u32 ib_get = nvkm_rd32(device, 0x003334); 311 u32 ib_put = nvkm_rd32(device, 0x003330); 312 313 nvkm_error(subdev, "DMA_PUSHER - " 314 "ch %d [%s] get %02x%08x put %02x%08x ib_get %08x " 315 "ib_put %08x state %08x (err: %s) push %08x\n", 316 chid, name, ho_get, dma_get, ho_put, dma_put, 317 ib_get, ib_put, state, nv_dma_state_err(state), 318 push); 319 320 /* METHOD_COUNT, in DMA_STATE on earlier chipsets */ 321 nvkm_wr32(device, 0x003364, 0x00000000); 322 if (dma_get != dma_put || ho_get != ho_put) { 323 nvkm_wr32(device, 0x003244, dma_put); 324 nvkm_wr32(device, 0x003328, ho_put); 325 } else 326 if (ib_get != ib_put) 327 nvkm_wr32(device, 0x003334, ib_put); 328 } else { 329 nvkm_error(subdev, "DMA_PUSHER - ch %d [%s] get %08x put %08x " 330 "state %08x (err: %s) push %08x\n", 331 chid, name, dma_get, dma_put, state, 332 nv_dma_state_err(state), push); 333 334 if (dma_get != dma_put) 335 nvkm_wr32(device, 0x003244, dma_put); 336 } 337 nvkm_chan_put(&chan, flags); 338 339 nvkm_wr32(device, 0x003228, 0x00000000); 340 nvkm_wr32(device, 0x003220, 0x00000001); 341 nvkm_wr32(device, 0x002100, NV_PFIFO_INTR_DMA_PUSHER); 342 } 343 344 irqreturn_t 345 nv04_fifo_intr(struct nvkm_inth *inth) 346 { 347 struct nvkm_fifo *fifo = container_of(inth, typeof(*fifo), engine.subdev.inth); 348 struct nvkm_subdev *subdev = &fifo->engine.subdev; 349 struct nvkm_device *device = subdev->device; 350 u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0); 351 u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask; 352 u32 reassign, chid, get, sem; 353 354 reassign = nvkm_rd32(device, NV03_PFIFO_CACHES) & 1; 355 nvkm_wr32(device, NV03_PFIFO_CACHES, 0); 356 357 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->chid->mask; 358 get = nvkm_rd32(device, NV03_PFIFO_CACHE1_GET); 359 360 if (stat & NV_PFIFO_INTR_CACHE_ERROR) { 361 nv04_fifo_intr_cache_error(fifo, chid, get); 362 stat &= ~NV_PFIFO_INTR_CACHE_ERROR; 363 } 364 365 if (stat & NV_PFIFO_INTR_DMA_PUSHER) { 366 nv04_fifo_intr_dma_pusher(fifo, chid); 367 stat &= ~NV_PFIFO_INTR_DMA_PUSHER; 368 } 369 370 if (stat & NV_PFIFO_INTR_SEMAPHORE) { 371 stat &= ~NV_PFIFO_INTR_SEMAPHORE; 372 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); 373 374 sem = nvkm_rd32(device, NV10_PFIFO_CACHE1_SEMAPHORE); 375 nvkm_wr32(device, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); 376 377 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); 378 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 379 } 380 381 if (device->card_type == NV_50) { 382 if (stat & 0x00000010) { 383 stat &= ~0x00000010; 384 nvkm_wr32(device, 0x002100, 0x00000010); 385 } 386 387 if (stat & 0x40000000) { 388 nvkm_wr32(device, 0x002100, 0x40000000); 389 nvkm_event_ntfy(&fifo->nonstall.event, 0, NVKM_FIFO_NONSTALL_EVENT); 390 stat &= ~0x40000000; 391 } 392 } 393 394 if (stat) { 395 nvkm_warn(subdev, "intr %08x\n", stat); 396 nvkm_mask(device, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); 397 nvkm_wr32(device, NV03_PFIFO_INTR_0, stat); 398 } 399 400 nvkm_wr32(device, NV03_PFIFO_CACHES, reassign); 401 return IRQ_HANDLED; 402 } 403 404 void 405 nv04_fifo_init(struct nvkm_fifo *fifo) 406 { 407 struct nvkm_device *device = fifo->engine.subdev.device; 408 struct nvkm_instmem *imem = device->imem; 409 struct nvkm_ramht *ramht = imem->ramht; 410 struct nvkm_memory *ramro = imem->ramro; 411 struct nvkm_memory *ramfc = imem->ramfc; 412 413 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); 414 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); 415 416 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | 417 ((ramht->bits - 9) << 16) | 418 (ramht->gpuobj->addr >> 8)); 419 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); 420 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8); 421 422 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask); 423 424 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); 425 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); 426 427 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 428 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 429 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 430 } 431 432 int 433 nv04_fifo_runl_ctor(struct nvkm_fifo *fifo) 434 { 435 struct nvkm_runl *runl; 436 437 runl = nvkm_runl_new(fifo, 0, 0, 0); 438 if (IS_ERR(runl)) 439 return PTR_ERR(runl); 440 441 nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_SW, 0); 442 nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_DMAOBJ, 0); 443 nvkm_runl_add(runl, 1, fifo->func->engn , NVKM_ENGINE_GR, 0); 444 nvkm_runl_add(runl, 2, fifo->func->engn , NVKM_ENGINE_MPEG, 0); /* NV31- */ 445 return 0; 446 } 447 448 int 449 nv04_fifo_chid_ctor(struct nvkm_fifo *fifo, int nr) 450 { 451 /* The last CHID is reserved by HW as a "channel invalid" marker. */ 452 return nvkm_chid_new(&nvkm_chan_event, &fifo->engine.subdev, nr, 0, nr - 1, &fifo->chid); 453 } 454 455 static int 456 nv04_fifo_chid_nr(struct nvkm_fifo *fifo) 457 { 458 return 16; 459 } 460 461 int 462 nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, 463 enum nvkm_subdev_type type, int inst, int nr, const struct nv04_fifo_ramfc *ramfc, 464 struct nvkm_fifo **pfifo) 465 { 466 struct nv04_fifo *fifo; 467 int ret; 468 469 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) 470 return -ENOMEM; 471 fifo->ramfc = ramfc; 472 *pfifo = &fifo->base; 473 474 ret = nvkm_fifo_ctor(func, device, type, inst, &fifo->base); 475 if (ret) 476 return ret; 477 478 return 0; 479 } 480 481 static const struct nvkm_fifo_func 482 nv04_fifo = { 483 .chid_nr = nv04_fifo_chid_nr, 484 .chid_ctor = nv04_fifo_chid_ctor, 485 .runl_ctor = nv04_fifo_runl_ctor, 486 .init = nv04_fifo_init, 487 .intr = nv04_fifo_intr, 488 .engine_id = nv04_fifo_engine_id, 489 .pause = nv04_fifo_pause, 490 .start = nv04_fifo_start, 491 .runl = &nv04_runl, 492 .engn = &nv04_engn, 493 .engn_sw = &nv04_engn, 494 .cgrp = {{ }, &nv04_cgrp }, 495 .chan = {{ 0, 0, NV03_CHANNEL_DMA }, &nv04_chan, .oclass = &nv04_fifo_dma_oclass }, 496 }; 497 498 int 499 nv04_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 500 struct nvkm_fifo **pfifo) 501 { 502 return nv04_fifo_new_(&nv04_fifo, device, type, inst, 16, nv04_fifo_ramfc, pfifo); 503 } 504