1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "cgrp.h" 25 #include "chan.h" 26 #include "chid.h" 27 #include "runl.h" 28 29 #include "nv04.h" 30 #include "channv04.h" 31 #include "regsnv04.h" 32 33 #include <core/client.h> 34 #include <core/ramht.h> 35 #include <subdev/instmem.h> 36 #include <subdev/timer.h> 37 #include <engine/sw.h> 38 39 #include <nvif/class.h> 40 41 static const struct nv04_fifo_ramfc 42 nv04_fifo_ramfc[] = { 43 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 44 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 45 { 16, 0, 0x08, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, 46 { 16, 16, 0x08, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, 47 { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_STATE }, 48 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, 49 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_ENGINE }, 50 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_PULL1 }, 51 {} 52 }; 53 54 void 55 nv04_fifo_dma_fini(struct nvkm_fifo_chan *base) 56 { 57 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 58 struct nv04_fifo *fifo = chan->fifo; 59 struct nvkm_device *device = fifo->base.engine.subdev.device; 60 struct nvkm_memory *fctx = device->imem->ramfc; 61 const struct nv04_fifo_ramfc *c; 62 unsigned long flags; 63 u32 data = chan->ramfc; 64 u32 chid; 65 66 /* prevent fifo context switches */ 67 spin_lock_irqsave(&fifo->base.lock, flags); 68 nvkm_wr32(device, NV03_PFIFO_CACHES, 0); 69 70 /* if this channel is active, replace it with a null context */ 71 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->base.chid->mask; 72 if (chid == chan->base.chid) { 73 nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); 74 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0); 75 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); 76 77 c = fifo->ramfc; 78 nvkm_kmap(fctx); 79 do { 80 u32 rm = ((1ULL << c->bits) - 1) << c->regs; 81 u32 cm = ((1ULL << c->bits) - 1) << c->ctxs; 82 u32 rv = (nvkm_rd32(device, c->regp) & rm) >> c->regs; 83 u32 cv = (nvkm_ro32(fctx, c->ctxp + data) & ~cm); 84 nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); 85 } while ((++c)->bits); 86 nvkm_done(fctx); 87 88 c = fifo->ramfc; 89 do { 90 nvkm_wr32(device, c->regp, 0x00000000); 91 } while ((++c)->bits); 92 93 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0); 94 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0); 95 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.chid->mask); 96 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 97 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 98 } 99 100 /* restore normal operation, after disabling dma mode */ 101 nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); 102 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 103 spin_unlock_irqrestore(&fifo->base.lock, flags); 104 } 105 106 void 107 nv04_fifo_dma_init(struct nvkm_fifo_chan *base) 108 { 109 struct nv04_fifo_chan *chan = nv04_fifo_chan(base); 110 struct nv04_fifo *fifo = chan->fifo; 111 struct nvkm_device *device = fifo->base.engine.subdev.device; 112 u32 mask = 1 << chan->base.chid; 113 unsigned long flags; 114 spin_lock_irqsave(&fifo->base.lock, flags); 115 nvkm_mask(device, NV04_PFIFO_MODE, mask, mask); 116 spin_unlock_irqrestore(&fifo->base.lock, flags); 117 } 118 119 static const struct nvkm_chan_func 120 nv04_chan = { 121 }; 122 123 const struct nvkm_cgrp_func 124 nv04_cgrp = { 125 }; 126 127 const struct nvkm_engn_func 128 nv04_engn = { 129 }; 130 131 void 132 nv04_fifo_pause(struct nvkm_fifo *base, unsigned long *pflags) 133 __acquires(fifo->base.lock) 134 { 135 struct nv04_fifo *fifo = nv04_fifo(base); 136 struct nvkm_device *device = fifo->base.engine.subdev.device; 137 unsigned long flags; 138 139 spin_lock_irqsave(&fifo->base.lock, flags); 140 *pflags = flags; 141 142 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000); 143 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); 144 145 /* in some cases the puller may be left in an inconsistent state 146 * if you try to stop it while it's busy translating handles. 147 * sometimes you get a CACHE_ERROR, sometimes it just fails 148 * silently; sending incorrect instance offsets to PGRAPH after 149 * it's started up again. 150 * 151 * to avoid this, we invalidate the most recently calculated 152 * instance. 153 */ 154 nvkm_msec(device, 2000, 155 u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0); 156 if (!(tmp & NV04_PFIFO_CACHE1_PULL0_HASH_BUSY)) 157 break; 158 ); 159 160 if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) & 161 NV04_PFIFO_CACHE1_PULL0_HASH_FAILED) 162 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); 163 164 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0x00000000); 165 } 166 167 void 168 nv04_fifo_start(struct nvkm_fifo *base, unsigned long *pflags) 169 __releases(fifo->base.lock) 170 { 171 struct nv04_fifo *fifo = nv04_fifo(base); 172 struct nvkm_device *device = fifo->base.engine.subdev.device; 173 unsigned long flags = *pflags; 174 175 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); 176 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000001); 177 178 spin_unlock_irqrestore(&fifo->base.lock, flags); 179 } 180 181 const struct nvkm_runl_func 182 nv04_runl = { 183 }; 184 185 int 186 nv04_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine) 187 { 188 switch (engine->subdev.type) { 189 case NVKM_ENGINE_SW : return NV04_FIFO_ENGN_SW; 190 case NVKM_ENGINE_GR : return NV04_FIFO_ENGN_GR; 191 case NVKM_ENGINE_MPEG : return NV04_FIFO_ENGN_MPEG; 192 case NVKM_ENGINE_DMAOBJ: return NV04_FIFO_ENGN_DMA; 193 default: 194 WARN_ON(1); 195 return 0; 196 } 197 } 198 199 static const char * 200 nv_dma_state_err(u32 state) 201 { 202 static const char * const desc[] = { 203 "NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE", 204 "INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK" 205 }; 206 return desc[(state >> 29) & 0x7]; 207 } 208 209 static bool 210 nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data) 211 { 212 struct nvkm_sw *sw = device->sw; 213 const int subc = (addr & 0x0000e000) >> 13; 214 const int mthd = (addr & 0x00001ffc); 215 const u32 mask = 0x0000000f << (subc * 4); 216 u32 engine = nvkm_rd32(device, 0x003280); 217 bool handled = false; 218 219 switch (mthd) { 220 case 0x0000 ... 0x0000: /* subchannel's engine -> software */ 221 nvkm_wr32(device, 0x003280, (engine &= ~mask)); 222 fallthrough; 223 case 0x0180 ... 0x01fc: /* handle -> instance */ 224 data = nvkm_rd32(device, 0x003258) & 0x0000ffff; 225 fallthrough; 226 case 0x0100 ... 0x017c: 227 case 0x0200 ... 0x1ffc: /* pass method down to sw */ 228 if (!(engine & mask) && sw) 229 handled = nvkm_sw_mthd(sw, chid, subc, mthd, data); 230 break; 231 default: 232 break; 233 } 234 235 return handled; 236 } 237 238 static void 239 nv04_fifo_cache_error(struct nv04_fifo *fifo, u32 chid, u32 get) 240 { 241 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 242 struct nvkm_device *device = subdev->device; 243 struct nvkm_fifo_chan *chan; 244 unsigned long flags; 245 u32 pull0 = nvkm_rd32(device, 0x003250); 246 u32 mthd, data; 247 int ptr; 248 249 /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before wrapping on my 250 * G80 chips, but CACHE1 isn't big enough for this much data.. Tests 251 * show that it wraps around to the start at GET=0x800.. No clue as to 252 * why.. 253 */ 254 ptr = (get & 0x7ff) >> 2; 255 256 if (device->card_type < NV_40) { 257 mthd = nvkm_rd32(device, NV04_PFIFO_CACHE1_METHOD(ptr)); 258 data = nvkm_rd32(device, NV04_PFIFO_CACHE1_DATA(ptr)); 259 } else { 260 mthd = nvkm_rd32(device, NV40_PFIFO_CACHE1_METHOD(ptr)); 261 data = nvkm_rd32(device, NV40_PFIFO_CACHE1_DATA(ptr)); 262 } 263 264 if (!(pull0 & 0x00000100) || 265 !nv04_fifo_swmthd(device, chid, mthd, data)) { 266 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); 267 nvkm_error(subdev, "CACHE_ERROR - " 268 "ch %d [%s] subc %d mthd %04x data %08x\n", 269 chid, chan ? chan->object.client->name : "unknown", 270 (mthd >> 13) & 7, mthd & 0x1ffc, data); 271 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 272 } 273 274 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0); 275 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); 276 277 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 278 nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) & ~1); 279 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); 280 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 281 nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) | 1); 282 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0); 283 284 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 285 nvkm_rd32(device, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); 286 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 287 } 288 289 static void 290 nv04_fifo_dma_pusher(struct nv04_fifo *fifo, u32 chid) 291 { 292 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 293 struct nvkm_device *device = subdev->device; 294 u32 dma_get = nvkm_rd32(device, 0x003244); 295 u32 dma_put = nvkm_rd32(device, 0x003240); 296 u32 push = nvkm_rd32(device, 0x003220); 297 u32 state = nvkm_rd32(device, 0x003228); 298 struct nvkm_fifo_chan *chan; 299 unsigned long flags; 300 const char *name; 301 302 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); 303 name = chan ? chan->object.client->name : "unknown"; 304 if (device->card_type == NV_50) { 305 u32 ho_get = nvkm_rd32(device, 0x003328); 306 u32 ho_put = nvkm_rd32(device, 0x003320); 307 u32 ib_get = nvkm_rd32(device, 0x003334); 308 u32 ib_put = nvkm_rd32(device, 0x003330); 309 310 nvkm_error(subdev, "DMA_PUSHER - " 311 "ch %d [%s] get %02x%08x put %02x%08x ib_get %08x " 312 "ib_put %08x state %08x (err: %s) push %08x\n", 313 chid, name, ho_get, dma_get, ho_put, dma_put, 314 ib_get, ib_put, state, nv_dma_state_err(state), 315 push); 316 317 /* METHOD_COUNT, in DMA_STATE on earlier chipsets */ 318 nvkm_wr32(device, 0x003364, 0x00000000); 319 if (dma_get != dma_put || ho_get != ho_put) { 320 nvkm_wr32(device, 0x003244, dma_put); 321 nvkm_wr32(device, 0x003328, ho_put); 322 } else 323 if (ib_get != ib_put) 324 nvkm_wr32(device, 0x003334, ib_put); 325 } else { 326 nvkm_error(subdev, "DMA_PUSHER - ch %d [%s] get %08x put %08x " 327 "state %08x (err: %s) push %08x\n", 328 chid, name, dma_get, dma_put, state, 329 nv_dma_state_err(state), push); 330 331 if (dma_get != dma_put) 332 nvkm_wr32(device, 0x003244, dma_put); 333 } 334 nvkm_fifo_chan_put(&fifo->base, flags, &chan); 335 336 nvkm_wr32(device, 0x003228, 0x00000000); 337 nvkm_wr32(device, 0x003220, 0x00000001); 338 nvkm_wr32(device, 0x002100, NV_PFIFO_INTR_DMA_PUSHER); 339 } 340 341 void 342 nv04_fifo_intr(struct nvkm_fifo *base) 343 { 344 struct nv04_fifo *fifo = nv04_fifo(base); 345 struct nvkm_subdev *subdev = &fifo->base.engine.subdev; 346 struct nvkm_device *device = subdev->device; 347 u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0); 348 u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask; 349 u32 reassign, chid, get, sem; 350 351 reassign = nvkm_rd32(device, NV03_PFIFO_CACHES) & 1; 352 nvkm_wr32(device, NV03_PFIFO_CACHES, 0); 353 354 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->base.chid->mask; 355 get = nvkm_rd32(device, NV03_PFIFO_CACHE1_GET); 356 357 if (stat & NV_PFIFO_INTR_CACHE_ERROR) { 358 nv04_fifo_cache_error(fifo, chid, get); 359 stat &= ~NV_PFIFO_INTR_CACHE_ERROR; 360 } 361 362 if (stat & NV_PFIFO_INTR_DMA_PUSHER) { 363 nv04_fifo_dma_pusher(fifo, chid); 364 stat &= ~NV_PFIFO_INTR_DMA_PUSHER; 365 } 366 367 if (stat & NV_PFIFO_INTR_SEMAPHORE) { 368 stat &= ~NV_PFIFO_INTR_SEMAPHORE; 369 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); 370 371 sem = nvkm_rd32(device, NV10_PFIFO_CACHE1_SEMAPHORE); 372 nvkm_wr32(device, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); 373 374 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); 375 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 376 } 377 378 if (device->card_type == NV_50) { 379 if (stat & 0x00000010) { 380 stat &= ~0x00000010; 381 nvkm_wr32(device, 0x002100, 0x00000010); 382 } 383 384 if (stat & 0x40000000) { 385 nvkm_wr32(device, 0x002100, 0x40000000); 386 nvkm_fifo_uevent(&fifo->base); 387 stat &= ~0x40000000; 388 } 389 } 390 391 if (stat) { 392 nvkm_warn(subdev, "intr %08x\n", stat); 393 nvkm_mask(device, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); 394 nvkm_wr32(device, NV03_PFIFO_INTR_0, stat); 395 } 396 397 nvkm_wr32(device, NV03_PFIFO_CACHES, reassign); 398 } 399 400 void 401 nv04_fifo_init(struct nvkm_fifo *fifo) 402 { 403 struct nvkm_device *device = fifo->engine.subdev.device; 404 struct nvkm_instmem *imem = device->imem; 405 struct nvkm_ramht *ramht = imem->ramht; 406 struct nvkm_memory *ramro = imem->ramro; 407 struct nvkm_memory *ramfc = imem->ramfc; 408 409 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); 410 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); 411 412 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | 413 ((ramht->bits - 9) << 16) | 414 (ramht->gpuobj->addr >> 8)); 415 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); 416 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8); 417 418 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask); 419 420 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); 421 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); 422 423 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 424 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 425 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 426 } 427 428 int 429 nv04_fifo_runl_ctor(struct nvkm_fifo *fifo) 430 { 431 struct nvkm_runl *runl; 432 433 runl = nvkm_runl_new(fifo, 0, 0, 0); 434 if (IS_ERR(runl)) 435 return PTR_ERR(runl); 436 437 nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_SW, 0); 438 nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_DMAOBJ, 0); 439 nvkm_runl_add(runl, 1, fifo->func->engn , NVKM_ENGINE_GR, 0); 440 nvkm_runl_add(runl, 2, fifo->func->engn , NVKM_ENGINE_MPEG, 0); /* NV31- */ 441 return 0; 442 } 443 444 int 445 nv04_fifo_chid_ctor(struct nvkm_fifo *fifo, int nr) 446 { 447 /* The last CHID is reserved by HW as a "channel invalid" marker. */ 448 return nvkm_chid_new(&nvkm_chan_event, &fifo->engine.subdev, nr, 0, nr - 1, &fifo->chid); 449 } 450 451 static int 452 nv04_fifo_chid_nr(struct nvkm_fifo *fifo) 453 { 454 return 16; 455 } 456 457 int 458 nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, 459 enum nvkm_subdev_type type, int inst, int nr, const struct nv04_fifo_ramfc *ramfc, 460 struct nvkm_fifo **pfifo) 461 { 462 struct nv04_fifo *fifo; 463 int ret; 464 465 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) 466 return -ENOMEM; 467 fifo->ramfc = ramfc; 468 *pfifo = &fifo->base; 469 470 ret = nvkm_fifo_ctor(func, device, type, inst, &fifo->base); 471 if (ret) 472 return ret; 473 474 return 0; 475 } 476 477 static const struct nvkm_fifo_func 478 nv04_fifo = { 479 .chid_nr = nv04_fifo_chid_nr, 480 .chid_ctor = nv04_fifo_chid_ctor, 481 .runl_ctor = nv04_fifo_runl_ctor, 482 .init = nv04_fifo_init, 483 .intr = nv04_fifo_intr, 484 .engine_id = nv04_fifo_engine_id, 485 .pause = nv04_fifo_pause, 486 .start = nv04_fifo_start, 487 .runl = &nv04_runl, 488 .engn = &nv04_engn, 489 .engn_sw = &nv04_engn, 490 .cgrp = {{ }, &nv04_cgrp }, 491 .chan = {{ 0, 0, NV03_CHANNEL_DMA }, &nv04_chan, .oclass = &nv04_fifo_dma_oclass }, 492 }; 493 494 int 495 nv04_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 496 struct nvkm_fifo **pfifo) 497 { 498 return nv04_fifo_new_(&nv04_fifo, device, type, inst, 16, nv04_fifo_ramfc, pfifo); 499 } 500