1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "chan.h" 23 #include "chid.h" 24 #include "cgrp.h" 25 #include "runl.h" 26 #include "runq.h" 27 28 #include "gk104.h" 29 #include "changk104.h" 30 31 #include <core/gpuobj.h> 32 33 #include <nvif/class.h> 34 35 static u32 36 gv100_chan_doorbell_handle(struct nvkm_chan *chan) 37 { 38 return chan->id; 39 } 40 41 const struct nvkm_chan_func_userd 42 gv100_chan_userd = { 43 .bar = 1, /*FIXME: hw doesn't have poller, flip to user-allocated in uapi commit. */ 44 .size = 0x200, 45 .clear = gf100_chan_userd_clear, 46 }; 47 48 static const struct nvkm_chan_func 49 gv100_chan = { 50 .inst = &gf100_chan_inst, 51 .userd = &gv100_chan_userd, 52 .bind = gk104_chan_bind_inst, 53 .unbind = gk104_chan_unbind, 54 .start = gk104_chan_start, 55 .stop = gk104_chan_stop, 56 .preempt = gk110_chan_preempt, 57 .doorbell_handle = gv100_chan_doorbell_handle, 58 }; 59 60 const struct nvkm_engn_func 61 gv100_engn = { 62 .chsw = gk104_engn_chsw, 63 .cxid = gk104_engn_cxid, 64 }; 65 66 const struct nvkm_engn_func 67 gv100_engn_ce = { 68 .chsw = gk104_engn_chsw, 69 .cxid = gk104_engn_cxid, 70 }; 71 72 static bool 73 gv100_runq_intr_1_ctxnotvalid(struct nvkm_runq *runq, int chid) 74 { 75 struct nvkm_fifo *fifo = runq->fifo; 76 struct nvkm_device *device = fifo->engine.subdev.device; 77 struct nvkm_chan *chan; 78 unsigned long flags; 79 80 RUNQ_ERROR(runq, "CTXNOTVALID chid:%d", chid); 81 82 chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); 83 if (WARN_ON_ONCE(!chan)) 84 return false; 85 86 nvkm_chan_error(chan, true); 87 nvkm_chan_put(&chan, flags); 88 89 nvkm_mask(device, 0x0400ac + (runq->id * 0x2000), 0x00030000, 0x00030000); 90 nvkm_wr32(device, 0x040148 + (runq->id * 0x2000), 0x80000000); 91 return true; 92 } 93 94 const struct nvkm_runq_func 95 gv100_runq = { 96 .init = gk208_runq_init, 97 .intr = gk104_runq_intr, 98 .intr_0_names = gk104_runq_intr_0_names, 99 .intr_1_ctxnotvalid = gv100_runq_intr_1_ctxnotvalid, 100 .idle = gk104_runq_idle, 101 }; 102 103 void 104 gv100_runl_preempt(struct nvkm_runl *runl) 105 { 106 nvkm_wr32(runl->fifo->engine.subdev.device, 0x002638, BIT(runl->id)); 107 } 108 109 void 110 gv100_runl_insert_chan(struct nvkm_chan *chan, struct nvkm_memory *memory, u64 offset) 111 { 112 const u64 user = nvkm_memory_addr(chan->userd.mem) + chan->userd.base; 113 const u64 inst = chan->inst->addr; 114 115 nvkm_wo32(memory, offset + 0x0, lower_32_bits(user) | chan->runq << 1); 116 nvkm_wo32(memory, offset + 0x4, upper_32_bits(user)); 117 nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->id); 118 nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst)); 119 } 120 121 void 122 gv100_runl_insert_cgrp(struct nvkm_cgrp *cgrp, struct nvkm_memory *memory, u64 offset) 123 { 124 nvkm_wo32(memory, offset + 0x0, (128 << 24) | (3 << 16) | 0x00000001); 125 nvkm_wo32(memory, offset + 0x4, cgrp->chan_nr); 126 nvkm_wo32(memory, offset + 0x8, cgrp->id); 127 nvkm_wo32(memory, offset + 0xc, 0x00000000); 128 } 129 130 static const struct nvkm_runl_func 131 gv100_runl = { 132 .runqs = 2, 133 .size = 16, 134 .update = nv50_runl_update, 135 .insert_cgrp = gv100_runl_insert_cgrp, 136 .insert_chan = gv100_runl_insert_chan, 137 .commit = gk104_runl_commit, 138 .wait = nv50_runl_wait, 139 .pending = gk104_runl_pending, 140 .block = gk104_runl_block, 141 .allow = gk104_runl_allow, 142 .preempt = gv100_runl_preempt, 143 .preempt_pending = gf100_runl_preempt_pending, 144 }; 145 146 const struct nvkm_enum 147 gv100_fifo_mmu_fault_gpcclient[] = { 148 { 0x00, "T1_0" }, 149 { 0x01, "T1_1" }, 150 { 0x02, "T1_2" }, 151 { 0x03, "T1_3" }, 152 { 0x04, "T1_4" }, 153 { 0x05, "T1_5" }, 154 { 0x06, "T1_6" }, 155 { 0x07, "T1_7" }, 156 { 0x08, "PE_0" }, 157 { 0x09, "PE_1" }, 158 { 0x0a, "PE_2" }, 159 { 0x0b, "PE_3" }, 160 { 0x0c, "PE_4" }, 161 { 0x0d, "PE_5" }, 162 { 0x0e, "PE_6" }, 163 { 0x0f, "PE_7" }, 164 { 0x10, "RAST" }, 165 { 0x11, "GCC" }, 166 { 0x12, "GPCCS" }, 167 { 0x13, "PROP_0" }, 168 { 0x14, "PROP_1" }, 169 { 0x15, "PROP_2" }, 170 { 0x16, "PROP_3" }, 171 { 0x17, "GPM" }, 172 { 0x18, "LTP_UTLB_0" }, 173 { 0x19, "LTP_UTLB_1" }, 174 { 0x1a, "LTP_UTLB_2" }, 175 { 0x1b, "LTP_UTLB_3" }, 176 { 0x1c, "LTP_UTLB_4" }, 177 { 0x1d, "LTP_UTLB_5" }, 178 { 0x1e, "LTP_UTLB_6" }, 179 { 0x1f, "LTP_UTLB_7" }, 180 { 0x20, "RGG_UTLB" }, 181 { 0x21, "T1_8" }, 182 { 0x22, "T1_9" }, 183 { 0x23, "T1_10" }, 184 { 0x24, "T1_11" }, 185 { 0x25, "T1_12" }, 186 { 0x26, "T1_13" }, 187 { 0x27, "T1_14" }, 188 { 0x28, "T1_15" }, 189 { 0x29, "TPCCS_0" }, 190 { 0x2a, "TPCCS_1" }, 191 { 0x2b, "TPCCS_2" }, 192 { 0x2c, "TPCCS_3" }, 193 { 0x2d, "TPCCS_4" }, 194 { 0x2e, "TPCCS_5" }, 195 { 0x2f, "TPCCS_6" }, 196 { 0x30, "TPCCS_7" }, 197 { 0x31, "PE_8" }, 198 { 0x32, "PE_9" }, 199 { 0x33, "TPCCS_8" }, 200 { 0x34, "TPCCS_9" }, 201 { 0x35, "T1_16" }, 202 { 0x36, "T1_17" }, 203 { 0x37, "T1_18" }, 204 { 0x38, "T1_19" }, 205 { 0x39, "PE_10" }, 206 { 0x3a, "PE_11" }, 207 { 0x3b, "TPCCS_10" }, 208 { 0x3c, "TPCCS_11" }, 209 { 0x3d, "T1_20" }, 210 { 0x3e, "T1_21" }, 211 { 0x3f, "T1_22" }, 212 { 0x40, "T1_23" }, 213 { 0x41, "PE_12" }, 214 { 0x42, "PE_13" }, 215 { 0x43, "TPCCS_12" }, 216 { 0x44, "TPCCS_13" }, 217 { 0x45, "T1_24" }, 218 { 0x46, "T1_25" }, 219 { 0x47, "T1_26" }, 220 { 0x48, "T1_27" }, 221 { 0x49, "PE_14" }, 222 { 0x4a, "PE_15" }, 223 { 0x4b, "TPCCS_14" }, 224 { 0x4c, "TPCCS_15" }, 225 { 0x4d, "T1_28" }, 226 { 0x4e, "T1_29" }, 227 { 0x4f, "T1_30" }, 228 { 0x50, "T1_31" }, 229 { 0x51, "PE_16" }, 230 { 0x52, "PE_17" }, 231 { 0x53, "TPCCS_16" }, 232 { 0x54, "TPCCS_17" }, 233 { 0x55, "T1_32" }, 234 { 0x56, "T1_33" }, 235 { 0x57, "T1_34" }, 236 { 0x58, "T1_35" }, 237 { 0x59, "PE_18" }, 238 { 0x5a, "PE_19" }, 239 { 0x5b, "TPCCS_18" }, 240 { 0x5c, "TPCCS_19" }, 241 { 0x5d, "T1_36" }, 242 { 0x5e, "T1_37" }, 243 { 0x5f, "T1_38" }, 244 { 0x60, "T1_39" }, 245 {} 246 }; 247 248 const struct nvkm_enum 249 gv100_fifo_mmu_fault_hubclient[] = { 250 { 0x00, "VIP" }, 251 { 0x01, "CE0" }, 252 { 0x02, "CE1" }, 253 { 0x03, "DNISO" }, 254 { 0x04, "FE" }, 255 { 0x05, "FECS" }, 256 { 0x06, "HOST" }, 257 { 0x07, "HOST_CPU" }, 258 { 0x08, "HOST_CPU_NB" }, 259 { 0x09, "ISO" }, 260 { 0x0a, "MMU" }, 261 { 0x0b, "NVDEC" }, 262 { 0x0d, "NVENC1" }, 263 { 0x0e, "NISO" }, 264 { 0x0f, "P2P" }, 265 { 0x10, "PD" }, 266 { 0x11, "PERF" }, 267 { 0x12, "PMU" }, 268 { 0x13, "RASTERTWOD" }, 269 { 0x14, "SCC" }, 270 { 0x15, "SCC_NB" }, 271 { 0x16, "SEC" }, 272 { 0x17, "SSYNC" }, 273 { 0x18, "CE2" }, 274 { 0x19, "XV" }, 275 { 0x1a, "MMU_NB" }, 276 { 0x1b, "NVENC0" }, 277 { 0x1c, "DFALCON" }, 278 { 0x1d, "SKED" }, 279 { 0x1e, "AFALCON" }, 280 { 0x1f, "DONT_CARE" }, 281 { 0x20, "HSCE0" }, 282 { 0x21, "HSCE1" }, 283 { 0x22, "HSCE2" }, 284 { 0x23, "HSCE3" }, 285 { 0x24, "HSCE4" }, 286 { 0x25, "HSCE5" }, 287 { 0x26, "HSCE6" }, 288 { 0x27, "HSCE7" }, 289 { 0x28, "HSCE8" }, 290 { 0x29, "HSCE9" }, 291 { 0x2a, "HSHUB" }, 292 { 0x2b, "PTP_X0" }, 293 { 0x2c, "PTP_X1" }, 294 { 0x2d, "PTP_X2" }, 295 { 0x2e, "PTP_X3" }, 296 { 0x2f, "PTP_X4" }, 297 { 0x30, "PTP_X5" }, 298 { 0x31, "PTP_X6" }, 299 { 0x32, "PTP_X7" }, 300 { 0x33, "NVENC2" }, 301 { 0x34, "VPR_SCRUBBER0" }, 302 { 0x35, "VPR_SCRUBBER1" }, 303 { 0x36, "DWBIF" }, 304 { 0x37, "FBFALCON" }, 305 { 0x38, "CE_SHIM" }, 306 { 0x39, "GSP" }, 307 {} 308 }; 309 310 const struct nvkm_enum 311 gv100_fifo_mmu_fault_reason[] = { 312 { 0x00, "PDE" }, 313 { 0x01, "PDE_SIZE" }, 314 { 0x02, "PTE" }, 315 { 0x03, "VA_LIMIT_VIOLATION" }, 316 { 0x04, "UNBOUND_INST_BLOCK" }, 317 { 0x05, "PRIV_VIOLATION" }, 318 { 0x06, "RO_VIOLATION" }, 319 { 0x07, "WO_VIOLATION" }, 320 { 0x08, "PITCH_MASK_VIOLATION" }, 321 { 0x09, "WORK_CREATION" }, 322 { 0x0a, "UNSUPPORTED_APERTURE" }, 323 { 0x0b, "COMPRESSION_FAILURE" }, 324 { 0x0c, "UNSUPPORTED_KIND" }, 325 { 0x0d, "REGION_VIOLATION" }, 326 { 0x0e, "POISONED" }, 327 { 0x0f, "ATOMIC_VIOLATION" }, 328 {} 329 }; 330 331 static const struct nvkm_enum 332 gv100_fifo_mmu_fault_engine[] = { 333 { 0x01, "DISPLAY" }, 334 { 0x03, "PTP" }, 335 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, 336 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, 337 { 0x06, "PWR_PMU" }, 338 { 0x08, "IFB", NULL, NVKM_ENGINE_IFB }, 339 { 0x09, "PERF" }, 340 { 0x1f, "PHYSICAL" }, 341 { 0x20, "HOST0" }, 342 { 0x21, "HOST1" }, 343 { 0x22, "HOST2" }, 344 { 0x23, "HOST3" }, 345 { 0x24, "HOST4" }, 346 { 0x25, "HOST5" }, 347 { 0x26, "HOST6" }, 348 { 0x27, "HOST7" }, 349 { 0x28, "HOST8" }, 350 { 0x29, "HOST9" }, 351 { 0x2a, "HOST10" }, 352 { 0x2b, "HOST11" }, 353 { 0x2c, "HOST12" }, 354 { 0x2d, "HOST13" }, 355 {} 356 }; 357 358 const struct nvkm_enum 359 gv100_fifo_mmu_fault_access[] = { 360 { 0x0, "VIRT_READ" }, 361 { 0x1, "VIRT_WRITE" }, 362 { 0x2, "VIRT_ATOMIC" }, 363 { 0x3, "VIRT_PREFETCH" }, 364 { 0x4, "VIRT_ATOMIC_WEAK" }, 365 { 0x8, "PHYS_READ" }, 366 { 0x9, "PHYS_WRITE" }, 367 { 0xa, "PHYS_ATOMIC" }, 368 { 0xb, "PHYS_PREFETCH" }, 369 {} 370 }; 371 372 static const struct nvkm_fifo_func_mmu_fault 373 gv100_fifo_mmu_fault = { 374 .recover = gf100_fifo_mmu_fault_recover, 375 .access = gv100_fifo_mmu_fault_access, 376 .engine = gv100_fifo_mmu_fault_engine, 377 .reason = gv100_fifo_mmu_fault_reason, 378 .hubclient = gv100_fifo_mmu_fault_hubclient, 379 .gpcclient = gv100_fifo_mmu_fault_gpcclient, 380 }; 381 382 static void 383 gv100_fifo_intr_ctxsw_timeout(struct nvkm_fifo *fifo, u32 engm) 384 { 385 struct nvkm_runl *runl; 386 struct nvkm_engn *engn; 387 388 nvkm_runl_foreach(runl, fifo) { 389 nvkm_runl_foreach_engn_cond(engn, runl, engm & BIT(engn->id)) 390 nvkm_runl_rc_engn(runl, engn); 391 } 392 } 393 394 static const struct nvkm_fifo_func 395 gv100_fifo = { 396 .dtor = gk104_fifo_dtor, 397 .oneinit = gk104_fifo_oneinit, 398 .chid_nr = gm200_fifo_chid_nr, 399 .chid_ctor = gk110_fifo_chid_ctor, 400 .runq_nr = gm200_fifo_runq_nr, 401 .runl_ctor = gk104_fifo_runl_ctor, 402 .init = gk104_fifo_init, 403 .init_pbdmas = gk104_fifo_init_pbdmas, 404 .intr = gk104_fifo_intr, 405 .intr_ctxsw_timeout = gv100_fifo_intr_ctxsw_timeout, 406 .mmu_fault = &gv100_fifo_mmu_fault, 407 .engine_id = gk104_fifo_engine_id, 408 .nonstall = &gf100_fifo_nonstall, 409 .runl = &gv100_runl, 410 .runq = &gv100_runq, 411 .engn = &gv100_engn, 412 .engn_ce = &gv100_engn_ce, 413 .cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp, .force = true }, 414 .chan = {{ 0, 0, VOLTA_CHANNEL_GPFIFO_A }, &gv100_chan, .ctor = gv100_fifo_gpfifo_new }, 415 }; 416 417 int 418 gv100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 419 struct nvkm_fifo **pfifo) 420 { 421 return gk104_fifo_new_(&gv100_fifo, device, type, inst, 0, pfifo); 422 } 423