1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "chan.h" 23 #include "chid.h" 24 #include "cgrp.h" 25 #include "runl.h" 26 #include "runq.h" 27 28 #include "gk104.h" 29 #include "changk104.h" 30 31 #include <core/gpuobj.h> 32 33 #include <nvif/class.h> 34 35 static u32 36 gv100_chan_doorbell_handle(struct nvkm_chan *chan) 37 { 38 return chan->id; 39 } 40 41 static const struct nvkm_chan_func 42 gv100_chan = { 43 .inst = &gf100_chan_inst, 44 .bind = gk104_chan_bind_inst, 45 .unbind = gk104_chan_unbind, 46 .start = gk104_chan_start, 47 .stop = gk104_chan_stop, 48 .preempt = gk110_chan_preempt, 49 .doorbell_handle = gv100_chan_doorbell_handle, 50 }; 51 52 const struct nvkm_engn_func 53 gv100_engn = { 54 .chsw = gk104_engn_chsw, 55 .cxid = gk104_engn_cxid, 56 }; 57 58 const struct nvkm_engn_func 59 gv100_engn_ce = { 60 .chsw = gk104_engn_chsw, 61 .cxid = gk104_engn_cxid, 62 }; 63 64 static bool 65 gv100_runq_intr_1_ctxnotvalid(struct nvkm_runq *runq, int chid) 66 { 67 struct nvkm_fifo *fifo = runq->fifo; 68 struct nvkm_device *device = fifo->engine.subdev.device; 69 struct nvkm_chan *chan; 70 unsigned long flags; 71 72 RUNQ_ERROR(runq, "CTXNOTVALID chid:%d", chid); 73 74 chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); 75 if (WARN_ON_ONCE(!chan)) 76 return false; 77 78 nvkm_chan_error(chan, true); 79 nvkm_chan_put(&chan, flags); 80 81 nvkm_mask(device, 0x0400ac + (runq->id * 0x2000), 0x00030000, 0x00030000); 82 nvkm_wr32(device, 0x040148 + (runq->id * 0x2000), 0x80000000); 83 return true; 84 } 85 86 const struct nvkm_runq_func 87 gv100_runq = { 88 .init = gk208_runq_init, 89 .intr = gk104_runq_intr, 90 .intr_0_names = gk104_runq_intr_0_names, 91 .intr_1_ctxnotvalid = gv100_runq_intr_1_ctxnotvalid, 92 .idle = gk104_runq_idle, 93 }; 94 95 void 96 gv100_runl_preempt(struct nvkm_runl *runl) 97 { 98 nvkm_wr32(runl->fifo->engine.subdev.device, 0x002638, BIT(runl->id)); 99 } 100 101 void 102 gv100_runl_insert_chan(struct nvkm_chan *chan, struct nvkm_memory *memory, u64 offset) 103 { 104 struct nvkm_memory *usermem = gk104_fifo(chan->cgrp->runl->fifo)->user.mem; 105 const u64 user = nvkm_memory_addr(usermem) + (chan->id * 0x200); 106 const u64 inst = chan->inst->addr; 107 108 nvkm_wo32(memory, offset + 0x0, lower_32_bits(user) | chan->runq << 1); 109 nvkm_wo32(memory, offset + 0x4, upper_32_bits(user)); 110 nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->id); 111 nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst)); 112 } 113 114 void 115 gv100_runl_insert_cgrp(struct nvkm_cgrp *cgrp, struct nvkm_memory *memory, u64 offset) 116 { 117 nvkm_wo32(memory, offset + 0x0, (128 << 24) | (3 << 16) | 0x00000001); 118 nvkm_wo32(memory, offset + 0x4, cgrp->chan_nr); 119 nvkm_wo32(memory, offset + 0x8, cgrp->id); 120 nvkm_wo32(memory, offset + 0xc, 0x00000000); 121 } 122 123 static const struct nvkm_runl_func 124 gv100_runl = { 125 .runqs = 2, 126 .size = 16, 127 .update = nv50_runl_update, 128 .insert_cgrp = gv100_runl_insert_cgrp, 129 .insert_chan = gv100_runl_insert_chan, 130 .commit = gk104_runl_commit, 131 .wait = nv50_runl_wait, 132 .pending = gk104_runl_pending, 133 .block = gk104_runl_block, 134 .allow = gk104_runl_allow, 135 .preempt = gv100_runl_preempt, 136 .preempt_pending = gf100_runl_preempt_pending, 137 }; 138 139 const struct nvkm_enum 140 gv100_fifo_mmu_fault_gpcclient[] = { 141 { 0x00, "T1_0" }, 142 { 0x01, "T1_1" }, 143 { 0x02, "T1_2" }, 144 { 0x03, "T1_3" }, 145 { 0x04, "T1_4" }, 146 { 0x05, "T1_5" }, 147 { 0x06, "T1_6" }, 148 { 0x07, "T1_7" }, 149 { 0x08, "PE_0" }, 150 { 0x09, "PE_1" }, 151 { 0x0a, "PE_2" }, 152 { 0x0b, "PE_3" }, 153 { 0x0c, "PE_4" }, 154 { 0x0d, "PE_5" }, 155 { 0x0e, "PE_6" }, 156 { 0x0f, "PE_7" }, 157 { 0x10, "RAST" }, 158 { 0x11, "GCC" }, 159 { 0x12, "GPCCS" }, 160 { 0x13, "PROP_0" }, 161 { 0x14, "PROP_1" }, 162 { 0x15, "PROP_2" }, 163 { 0x16, "PROP_3" }, 164 { 0x17, "GPM" }, 165 { 0x18, "LTP_UTLB_0" }, 166 { 0x19, "LTP_UTLB_1" }, 167 { 0x1a, "LTP_UTLB_2" }, 168 { 0x1b, "LTP_UTLB_3" }, 169 { 0x1c, "LTP_UTLB_4" }, 170 { 0x1d, "LTP_UTLB_5" }, 171 { 0x1e, "LTP_UTLB_6" }, 172 { 0x1f, "LTP_UTLB_7" }, 173 { 0x20, "RGG_UTLB" }, 174 { 0x21, "T1_8" }, 175 { 0x22, "T1_9" }, 176 { 0x23, "T1_10" }, 177 { 0x24, "T1_11" }, 178 { 0x25, "T1_12" }, 179 { 0x26, "T1_13" }, 180 { 0x27, "T1_14" }, 181 { 0x28, "T1_15" }, 182 { 0x29, "TPCCS_0" }, 183 { 0x2a, "TPCCS_1" }, 184 { 0x2b, "TPCCS_2" }, 185 { 0x2c, "TPCCS_3" }, 186 { 0x2d, "TPCCS_4" }, 187 { 0x2e, "TPCCS_5" }, 188 { 0x2f, "TPCCS_6" }, 189 { 0x30, "TPCCS_7" }, 190 { 0x31, "PE_8" }, 191 { 0x32, "PE_9" }, 192 { 0x33, "TPCCS_8" }, 193 { 0x34, "TPCCS_9" }, 194 { 0x35, "T1_16" }, 195 { 0x36, "T1_17" }, 196 { 0x37, "T1_18" }, 197 { 0x38, "T1_19" }, 198 { 0x39, "PE_10" }, 199 { 0x3a, "PE_11" }, 200 { 0x3b, "TPCCS_10" }, 201 { 0x3c, "TPCCS_11" }, 202 { 0x3d, "T1_20" }, 203 { 0x3e, "T1_21" }, 204 { 0x3f, "T1_22" }, 205 { 0x40, "T1_23" }, 206 { 0x41, "PE_12" }, 207 { 0x42, "PE_13" }, 208 { 0x43, "TPCCS_12" }, 209 { 0x44, "TPCCS_13" }, 210 { 0x45, "T1_24" }, 211 { 0x46, "T1_25" }, 212 { 0x47, "T1_26" }, 213 { 0x48, "T1_27" }, 214 { 0x49, "PE_14" }, 215 { 0x4a, "PE_15" }, 216 { 0x4b, "TPCCS_14" }, 217 { 0x4c, "TPCCS_15" }, 218 { 0x4d, "T1_28" }, 219 { 0x4e, "T1_29" }, 220 { 0x4f, "T1_30" }, 221 { 0x50, "T1_31" }, 222 { 0x51, "PE_16" }, 223 { 0x52, "PE_17" }, 224 { 0x53, "TPCCS_16" }, 225 { 0x54, "TPCCS_17" }, 226 { 0x55, "T1_32" }, 227 { 0x56, "T1_33" }, 228 { 0x57, "T1_34" }, 229 { 0x58, "T1_35" }, 230 { 0x59, "PE_18" }, 231 { 0x5a, "PE_19" }, 232 { 0x5b, "TPCCS_18" }, 233 { 0x5c, "TPCCS_19" }, 234 { 0x5d, "T1_36" }, 235 { 0x5e, "T1_37" }, 236 { 0x5f, "T1_38" }, 237 { 0x60, "T1_39" }, 238 {} 239 }; 240 241 const struct nvkm_enum 242 gv100_fifo_mmu_fault_hubclient[] = { 243 { 0x00, "VIP" }, 244 { 0x01, "CE0" }, 245 { 0x02, "CE1" }, 246 { 0x03, "DNISO" }, 247 { 0x04, "FE" }, 248 { 0x05, "FECS" }, 249 { 0x06, "HOST" }, 250 { 0x07, "HOST_CPU" }, 251 { 0x08, "HOST_CPU_NB" }, 252 { 0x09, "ISO" }, 253 { 0x0a, "MMU" }, 254 { 0x0b, "NVDEC" }, 255 { 0x0d, "NVENC1" }, 256 { 0x0e, "NISO" }, 257 { 0x0f, "P2P" }, 258 { 0x10, "PD" }, 259 { 0x11, "PERF" }, 260 { 0x12, "PMU" }, 261 { 0x13, "RASTERTWOD" }, 262 { 0x14, "SCC" }, 263 { 0x15, "SCC_NB" }, 264 { 0x16, "SEC" }, 265 { 0x17, "SSYNC" }, 266 { 0x18, "CE2" }, 267 { 0x19, "XV" }, 268 { 0x1a, "MMU_NB" }, 269 { 0x1b, "NVENC0" }, 270 { 0x1c, "DFALCON" }, 271 { 0x1d, "SKED" }, 272 { 0x1e, "AFALCON" }, 273 { 0x1f, "DONT_CARE" }, 274 { 0x20, "HSCE0" }, 275 { 0x21, "HSCE1" }, 276 { 0x22, "HSCE2" }, 277 { 0x23, "HSCE3" }, 278 { 0x24, "HSCE4" }, 279 { 0x25, "HSCE5" }, 280 { 0x26, "HSCE6" }, 281 { 0x27, "HSCE7" }, 282 { 0x28, "HSCE8" }, 283 { 0x29, "HSCE9" }, 284 { 0x2a, "HSHUB" }, 285 { 0x2b, "PTP_X0" }, 286 { 0x2c, "PTP_X1" }, 287 { 0x2d, "PTP_X2" }, 288 { 0x2e, "PTP_X3" }, 289 { 0x2f, "PTP_X4" }, 290 { 0x30, "PTP_X5" }, 291 { 0x31, "PTP_X6" }, 292 { 0x32, "PTP_X7" }, 293 { 0x33, "NVENC2" }, 294 { 0x34, "VPR_SCRUBBER0" }, 295 { 0x35, "VPR_SCRUBBER1" }, 296 { 0x36, "DWBIF" }, 297 { 0x37, "FBFALCON" }, 298 { 0x38, "CE_SHIM" }, 299 { 0x39, "GSP" }, 300 {} 301 }; 302 303 const struct nvkm_enum 304 gv100_fifo_mmu_fault_reason[] = { 305 { 0x00, "PDE" }, 306 { 0x01, "PDE_SIZE" }, 307 { 0x02, "PTE" }, 308 { 0x03, "VA_LIMIT_VIOLATION" }, 309 { 0x04, "UNBOUND_INST_BLOCK" }, 310 { 0x05, "PRIV_VIOLATION" }, 311 { 0x06, "RO_VIOLATION" }, 312 { 0x07, "WO_VIOLATION" }, 313 { 0x08, "PITCH_MASK_VIOLATION" }, 314 { 0x09, "WORK_CREATION" }, 315 { 0x0a, "UNSUPPORTED_APERTURE" }, 316 { 0x0b, "COMPRESSION_FAILURE" }, 317 { 0x0c, "UNSUPPORTED_KIND" }, 318 { 0x0d, "REGION_VIOLATION" }, 319 { 0x0e, "POISONED" }, 320 { 0x0f, "ATOMIC_VIOLATION" }, 321 {} 322 }; 323 324 static const struct nvkm_enum 325 gv100_fifo_mmu_fault_engine[] = { 326 { 0x01, "DISPLAY" }, 327 { 0x03, "PTP" }, 328 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, 329 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, 330 { 0x06, "PWR_PMU" }, 331 { 0x08, "IFB", NULL, NVKM_ENGINE_IFB }, 332 { 0x09, "PERF" }, 333 { 0x1f, "PHYSICAL" }, 334 { 0x20, "HOST0" }, 335 { 0x21, "HOST1" }, 336 { 0x22, "HOST2" }, 337 { 0x23, "HOST3" }, 338 { 0x24, "HOST4" }, 339 { 0x25, "HOST5" }, 340 { 0x26, "HOST6" }, 341 { 0x27, "HOST7" }, 342 { 0x28, "HOST8" }, 343 { 0x29, "HOST9" }, 344 { 0x2a, "HOST10" }, 345 { 0x2b, "HOST11" }, 346 { 0x2c, "HOST12" }, 347 { 0x2d, "HOST13" }, 348 {} 349 }; 350 351 const struct nvkm_enum 352 gv100_fifo_mmu_fault_access[] = { 353 { 0x0, "VIRT_READ" }, 354 { 0x1, "VIRT_WRITE" }, 355 { 0x2, "VIRT_ATOMIC" }, 356 { 0x3, "VIRT_PREFETCH" }, 357 { 0x4, "VIRT_ATOMIC_WEAK" }, 358 { 0x8, "PHYS_READ" }, 359 { 0x9, "PHYS_WRITE" }, 360 { 0xa, "PHYS_ATOMIC" }, 361 { 0xb, "PHYS_PREFETCH" }, 362 {} 363 }; 364 365 static const struct nvkm_fifo_func_mmu_fault 366 gv100_fifo_mmu_fault = { 367 .recover = gf100_fifo_mmu_fault_recover, 368 .access = gv100_fifo_mmu_fault_access, 369 .engine = gv100_fifo_mmu_fault_engine, 370 .reason = gv100_fifo_mmu_fault_reason, 371 .hubclient = gv100_fifo_mmu_fault_hubclient, 372 .gpcclient = gv100_fifo_mmu_fault_gpcclient, 373 }; 374 375 static void 376 gv100_fifo_intr_ctxsw_timeout(struct nvkm_fifo *fifo, u32 engm) 377 { 378 struct nvkm_runl *runl; 379 struct nvkm_engn *engn; 380 381 nvkm_runl_foreach(runl, fifo) { 382 nvkm_runl_foreach_engn_cond(engn, runl, engm & BIT(engn->id)) 383 nvkm_runl_rc_engn(runl, engn); 384 } 385 } 386 387 static const struct nvkm_fifo_func 388 gv100_fifo = { 389 .dtor = gk104_fifo_dtor, 390 .oneinit = gk104_fifo_oneinit, 391 .chid_nr = gm200_fifo_chid_nr, 392 .chid_ctor = gk110_fifo_chid_ctor, 393 .runq_nr = gm200_fifo_runq_nr, 394 .runl_ctor = gk104_fifo_runl_ctor, 395 .init = gk104_fifo_init, 396 .init_pbdmas = gk104_fifo_init_pbdmas, 397 .intr = gk104_fifo_intr, 398 .intr_ctxsw_timeout = gv100_fifo_intr_ctxsw_timeout, 399 .mmu_fault = &gv100_fifo_mmu_fault, 400 .engine_id = gk104_fifo_engine_id, 401 .nonstall = &gf100_fifo_nonstall, 402 .runl = &gv100_runl, 403 .runq = &gv100_runq, 404 .engn = &gv100_engn, 405 .engn_ce = &gv100_engn_ce, 406 .cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp, .force = true }, 407 .chan = {{ 0, 0, VOLTA_CHANNEL_GPFIFO_A }, &gv100_chan, .ctor = gv100_fifo_gpfifo_new }, 408 }; 409 410 int 411 gv100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 412 struct nvkm_fifo **pfifo) 413 { 414 return gk104_fifo_new_(&gv100_fifo, device, type, inst, 0, pfifo); 415 } 416