1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "chan.h" 23 #include "cgrp.h" 24 #include "runl.h" 25 #include "runq.h" 26 27 #include "gk104.h" 28 #include "changk104.h" 29 30 #include <core/gpuobj.h> 31 32 #include <nvif/class.h> 33 34 static const struct nvkm_chan_func 35 gv100_chan = { 36 }; 37 38 const struct nvkm_engn_func 39 gv100_engn = { 40 }; 41 42 const struct nvkm_engn_func 43 gv100_engn_ce = { 44 }; 45 46 const struct nvkm_runq_func 47 gv100_runq = { 48 .init = gk208_runq_init, 49 .intr = gk104_runq_intr, 50 .intr_0_names = gk104_runq_intr_0_names, 51 }; 52 53 void 54 gv100_fifo_runlist_chan(struct gk104_fifo_chan *chan, 55 struct nvkm_memory *memory, u32 offset) 56 { 57 struct nvkm_memory *usermem = chan->fifo->user.mem; 58 const u64 user = nvkm_memory_addr(usermem) + (chan->base.chid * 0x200); 59 const u64 inst = chan->base.inst->addr; 60 61 nvkm_wo32(memory, offset + 0x0, lower_32_bits(user)); 62 nvkm_wo32(memory, offset + 0x4, upper_32_bits(user)); 63 nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->base.chid); 64 nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst)); 65 } 66 67 void 68 gv100_fifo_runlist_cgrp(struct nvkm_fifo_cgrp *cgrp, 69 struct nvkm_memory *memory, u32 offset) 70 { 71 nvkm_wo32(memory, offset + 0x0, (128 << 24) | (3 << 16) | 0x00000001); 72 nvkm_wo32(memory, offset + 0x4, cgrp->chan_nr); 73 nvkm_wo32(memory, offset + 0x8, cgrp->id); 74 nvkm_wo32(memory, offset + 0xc, 0x00000000); 75 } 76 77 static const struct gk104_fifo_runlist_func 78 gv100_fifo_runlist = { 79 .size = 16, 80 .cgrp = gv100_fifo_runlist_cgrp, 81 .chan = gv100_fifo_runlist_chan, 82 .commit = gk104_fifo_runlist_commit, 83 }; 84 85 static const struct nvkm_runl_func 86 gv100_runl = { 87 .wait = nv50_runl_wait, 88 .pending = gk104_runl_pending, 89 .block = gk104_runl_block, 90 .allow = gk104_runl_allow, 91 }; 92 93 const struct nvkm_enum 94 gv100_fifo_mmu_fault_gpcclient[] = { 95 { 0x00, "T1_0" }, 96 { 0x01, "T1_1" }, 97 { 0x02, "T1_2" }, 98 { 0x03, "T1_3" }, 99 { 0x04, "T1_4" }, 100 { 0x05, "T1_5" }, 101 { 0x06, "T1_6" }, 102 { 0x07, "T1_7" }, 103 { 0x08, "PE_0" }, 104 { 0x09, "PE_1" }, 105 { 0x0a, "PE_2" }, 106 { 0x0b, "PE_3" }, 107 { 0x0c, "PE_4" }, 108 { 0x0d, "PE_5" }, 109 { 0x0e, "PE_6" }, 110 { 0x0f, "PE_7" }, 111 { 0x10, "RAST" }, 112 { 0x11, "GCC" }, 113 { 0x12, "GPCCS" }, 114 { 0x13, "PROP_0" }, 115 { 0x14, "PROP_1" }, 116 { 0x15, "PROP_2" }, 117 { 0x16, "PROP_3" }, 118 { 0x17, "GPM" }, 119 { 0x18, "LTP_UTLB_0" }, 120 { 0x19, "LTP_UTLB_1" }, 121 { 0x1a, "LTP_UTLB_2" }, 122 { 0x1b, "LTP_UTLB_3" }, 123 { 0x1c, "LTP_UTLB_4" }, 124 { 0x1d, "LTP_UTLB_5" }, 125 { 0x1e, "LTP_UTLB_6" }, 126 { 0x1f, "LTP_UTLB_7" }, 127 { 0x20, "RGG_UTLB" }, 128 { 0x21, "T1_8" }, 129 { 0x22, "T1_9" }, 130 { 0x23, "T1_10" }, 131 { 0x24, "T1_11" }, 132 { 0x25, "T1_12" }, 133 { 0x26, "T1_13" }, 134 { 0x27, "T1_14" }, 135 { 0x28, "T1_15" }, 136 { 0x29, "TPCCS_0" }, 137 { 0x2a, "TPCCS_1" }, 138 { 0x2b, "TPCCS_2" }, 139 { 0x2c, "TPCCS_3" }, 140 { 0x2d, "TPCCS_4" }, 141 { 0x2e, "TPCCS_5" }, 142 { 0x2f, "TPCCS_6" }, 143 { 0x30, "TPCCS_7" }, 144 { 0x31, "PE_8" }, 145 { 0x32, "PE_9" }, 146 { 0x33, "TPCCS_8" }, 147 { 0x34, "TPCCS_9" }, 148 { 0x35, "T1_16" }, 149 { 0x36, "T1_17" }, 150 { 0x37, "T1_18" }, 151 { 0x38, "T1_19" }, 152 { 0x39, "PE_10" }, 153 { 0x3a, "PE_11" }, 154 { 0x3b, "TPCCS_10" }, 155 { 0x3c, "TPCCS_11" }, 156 { 0x3d, "T1_20" }, 157 { 0x3e, "T1_21" }, 158 { 0x3f, "T1_22" }, 159 { 0x40, "T1_23" }, 160 { 0x41, "PE_12" }, 161 { 0x42, "PE_13" }, 162 { 0x43, "TPCCS_12" }, 163 { 0x44, "TPCCS_13" }, 164 { 0x45, "T1_24" }, 165 { 0x46, "T1_25" }, 166 { 0x47, "T1_26" }, 167 { 0x48, "T1_27" }, 168 { 0x49, "PE_14" }, 169 { 0x4a, "PE_15" }, 170 { 0x4b, "TPCCS_14" }, 171 { 0x4c, "TPCCS_15" }, 172 { 0x4d, "T1_28" }, 173 { 0x4e, "T1_29" }, 174 { 0x4f, "T1_30" }, 175 { 0x50, "T1_31" }, 176 { 0x51, "PE_16" }, 177 { 0x52, "PE_17" }, 178 { 0x53, "TPCCS_16" }, 179 { 0x54, "TPCCS_17" }, 180 { 0x55, "T1_32" }, 181 { 0x56, "T1_33" }, 182 { 0x57, "T1_34" }, 183 { 0x58, "T1_35" }, 184 { 0x59, "PE_18" }, 185 { 0x5a, "PE_19" }, 186 { 0x5b, "TPCCS_18" }, 187 { 0x5c, "TPCCS_19" }, 188 { 0x5d, "T1_36" }, 189 { 0x5e, "T1_37" }, 190 { 0x5f, "T1_38" }, 191 { 0x60, "T1_39" }, 192 {} 193 }; 194 195 const struct nvkm_enum 196 gv100_fifo_mmu_fault_hubclient[] = { 197 { 0x00, "VIP" }, 198 { 0x01, "CE0" }, 199 { 0x02, "CE1" }, 200 { 0x03, "DNISO" }, 201 { 0x04, "FE" }, 202 { 0x05, "FECS" }, 203 { 0x06, "HOST" }, 204 { 0x07, "HOST_CPU" }, 205 { 0x08, "HOST_CPU_NB" }, 206 { 0x09, "ISO" }, 207 { 0x0a, "MMU" }, 208 { 0x0b, "NVDEC" }, 209 { 0x0d, "NVENC1" }, 210 { 0x0e, "NISO" }, 211 { 0x0f, "P2P" }, 212 { 0x10, "PD" }, 213 { 0x11, "PERF" }, 214 { 0x12, "PMU" }, 215 { 0x13, "RASTERTWOD" }, 216 { 0x14, "SCC" }, 217 { 0x15, "SCC_NB" }, 218 { 0x16, "SEC" }, 219 { 0x17, "SSYNC" }, 220 { 0x18, "CE2" }, 221 { 0x19, "XV" }, 222 { 0x1a, "MMU_NB" }, 223 { 0x1b, "NVENC0" }, 224 { 0x1c, "DFALCON" }, 225 { 0x1d, "SKED" }, 226 { 0x1e, "AFALCON" }, 227 { 0x1f, "DONT_CARE" }, 228 { 0x20, "HSCE0" }, 229 { 0x21, "HSCE1" }, 230 { 0x22, "HSCE2" }, 231 { 0x23, "HSCE3" }, 232 { 0x24, "HSCE4" }, 233 { 0x25, "HSCE5" }, 234 { 0x26, "HSCE6" }, 235 { 0x27, "HSCE7" }, 236 { 0x28, "HSCE8" }, 237 { 0x29, "HSCE9" }, 238 { 0x2a, "HSHUB" }, 239 { 0x2b, "PTP_X0" }, 240 { 0x2c, "PTP_X1" }, 241 { 0x2d, "PTP_X2" }, 242 { 0x2e, "PTP_X3" }, 243 { 0x2f, "PTP_X4" }, 244 { 0x30, "PTP_X5" }, 245 { 0x31, "PTP_X6" }, 246 { 0x32, "PTP_X7" }, 247 { 0x33, "NVENC2" }, 248 { 0x34, "VPR_SCRUBBER0" }, 249 { 0x35, "VPR_SCRUBBER1" }, 250 { 0x36, "DWBIF" }, 251 { 0x37, "FBFALCON" }, 252 { 0x38, "CE_SHIM" }, 253 { 0x39, "GSP" }, 254 {} 255 }; 256 257 const struct nvkm_enum 258 gv100_fifo_mmu_fault_reason[] = { 259 { 0x00, "PDE" }, 260 { 0x01, "PDE_SIZE" }, 261 { 0x02, "PTE" }, 262 { 0x03, "VA_LIMIT_VIOLATION" }, 263 { 0x04, "UNBOUND_INST_BLOCK" }, 264 { 0x05, "PRIV_VIOLATION" }, 265 { 0x06, "RO_VIOLATION" }, 266 { 0x07, "WO_VIOLATION" }, 267 { 0x08, "PITCH_MASK_VIOLATION" }, 268 { 0x09, "WORK_CREATION" }, 269 { 0x0a, "UNSUPPORTED_APERTURE" }, 270 { 0x0b, "COMPRESSION_FAILURE" }, 271 { 0x0c, "UNSUPPORTED_KIND" }, 272 { 0x0d, "REGION_VIOLATION" }, 273 { 0x0e, "POISONED" }, 274 { 0x0f, "ATOMIC_VIOLATION" }, 275 {} 276 }; 277 278 static const struct nvkm_enum 279 gv100_fifo_mmu_fault_engine[] = { 280 { 0x01, "DISPLAY" }, 281 { 0x03, "PTP" }, 282 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, 283 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, 284 { 0x06, "PWR_PMU" }, 285 { 0x08, "IFB", NULL, NVKM_ENGINE_IFB }, 286 { 0x09, "PERF" }, 287 { 0x1f, "PHYSICAL" }, 288 { 0x20, "HOST0" }, 289 { 0x21, "HOST1" }, 290 { 0x22, "HOST2" }, 291 { 0x23, "HOST3" }, 292 { 0x24, "HOST4" }, 293 { 0x25, "HOST5" }, 294 { 0x26, "HOST6" }, 295 { 0x27, "HOST7" }, 296 { 0x28, "HOST8" }, 297 { 0x29, "HOST9" }, 298 { 0x2a, "HOST10" }, 299 { 0x2b, "HOST11" }, 300 { 0x2c, "HOST12" }, 301 { 0x2d, "HOST13" }, 302 {} 303 }; 304 305 const struct nvkm_enum 306 gv100_fifo_mmu_fault_access[] = { 307 { 0x0, "VIRT_READ" }, 308 { 0x1, "VIRT_WRITE" }, 309 { 0x2, "VIRT_ATOMIC" }, 310 { 0x3, "VIRT_PREFETCH" }, 311 { 0x4, "VIRT_ATOMIC_WEAK" }, 312 { 0x8, "PHYS_READ" }, 313 { 0x9, "PHYS_WRITE" }, 314 { 0xa, "PHYS_ATOMIC" }, 315 { 0xb, "PHYS_PREFETCH" }, 316 {} 317 }; 318 319 static const struct nvkm_fifo_func_mmu_fault 320 gv100_fifo_mmu_fault = { 321 .recover = gf100_fifo_mmu_fault_recover, 322 .access = gv100_fifo_mmu_fault_access, 323 .engine = gv100_fifo_mmu_fault_engine, 324 .reason = gv100_fifo_mmu_fault_reason, 325 .hubclient = gv100_fifo_mmu_fault_hubclient, 326 .gpcclient = gv100_fifo_mmu_fault_gpcclient, 327 }; 328 329 static const struct nvkm_fifo_func 330 gv100_fifo = { 331 .dtor = gk104_fifo_dtor, 332 .oneinit = gk104_fifo_oneinit, 333 .chid_nr = gm200_fifo_chid_nr, 334 .chid_ctor = gk110_fifo_chid_ctor, 335 .runq_nr = gm200_fifo_runq_nr, 336 .runl_ctor = gk104_fifo_runl_ctor, 337 .init = gk104_fifo_init, 338 .init_pbdmas = gk104_fifo_init_pbdmas, 339 .fini = gk104_fifo_fini, 340 .intr = gk104_fifo_intr, 341 .mmu_fault = &gv100_fifo_mmu_fault, 342 .engine_id = gk104_fifo_engine_id, 343 .recover_chan = gk104_fifo_recover_chan, 344 .runlist = &gv100_fifo_runlist, 345 .nonstall = &gf100_fifo_nonstall, 346 .runl = &gv100_runl, 347 .runq = &gv100_runq, 348 .engn = &gv100_engn, 349 .engn_ce = &gv100_engn_ce, 350 .cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp, .force = true }, 351 .chan = {{ 0, 0, VOLTA_CHANNEL_GPFIFO_A }, &gv100_chan, .ctor = gv100_fifo_gpfifo_new }, 352 }; 353 354 int 355 gv100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 356 struct nvkm_fifo **pfifo) 357 { 358 return gk104_fifo_new_(&gv100_fifo, device, type, inst, 0, pfifo); 359 } 360