xref: /openbmc/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1b7019ac5SIlia Mirkin /* SPDX-License-Identifier: MIT */
2eaebfcc3SBen Skeggs #ifndef __NVKM_TOP_H__
3eaebfcc3SBen Skeggs #define __NVKM_TOP_H__
4eaebfcc3SBen Skeggs #include <core/subdev.h>
5eaebfcc3SBen Skeggs 
6eaebfcc3SBen Skeggs struct nvkm_top {
75f76f294SBen Skeggs 	const struct nvkm_top_func *func;
8eaebfcc3SBen Skeggs 	struct nvkm_subdev subdev;
95f76f294SBen Skeggs 	struct list_head device;
10eaebfcc3SBen Skeggs };
115f76f294SBen Skeggs 
123b9e93f7SBen Skeggs struct nvkm_top_device {
133b9e93f7SBen Skeggs 	enum nvkm_subdev_type type;
143b9e93f7SBen Skeggs 	int inst;
153b9e93f7SBen Skeggs 	u32 addr;
163b9e93f7SBen Skeggs 	int fault;
173b9e93f7SBen Skeggs 	int engine;
183b9e93f7SBen Skeggs 	int runlist;
193b9e93f7SBen Skeggs 	int reset;
203b9e93f7SBen Skeggs 	int intr;
213b9e93f7SBen Skeggs 	struct list_head head;
223b9e93f7SBen Skeggs };
233b9e93f7SBen Skeggs 
24*eec3f6dfSBen Skeggs int nvkm_top_parse(struct nvkm_device *);
25b7da823aSBen Skeggs u32 nvkm_top_addr(struct nvkm_device *, enum nvkm_subdev_type, int);
266997ea13SBen Skeggs u32 nvkm_top_reset(struct nvkm_device *, enum nvkm_subdev_type, int);
27a35047baSBen Skeggs u32 nvkm_top_intr_mask(struct nvkm_device *, enum nvkm_subdev_type, int);
28088bfe43SBen Skeggs int nvkm_top_fault_id(struct nvkm_device *, enum nvkm_subdev_type, int);
29ba083ec7SBen Skeggs struct nvkm_subdev *nvkm_top_fault(struct nvkm_device *, int fault);
30fb3e9c61SBen Skeggs 
31601c2a06SBen Skeggs int gk104_top_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_top **);
32f6df392dSBen Skeggs int ga100_top_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_top **);
33eaebfcc3SBen Skeggs #endif
34