1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "head.h" 23 #include "atom.h" 24 #include "core.h" 25 26 #include <nvif/pushc37b.h> 27 28 #include <nvhw/class/clc37d.h> 29 30 static int 31 headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh) 32 { 33 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; 34 const int i = head->base.index; 35 u8 depth; 36 int ret; 37 38 /*XXX: This is a dirty hack until OR depth handling is 39 * improved later for deep colour etc. 40 */ 41 switch (asyh->or.depth) { 42 case 6: depth = 5; break; 43 case 5: depth = 4; break; 44 case 2: depth = 1; break; 45 case 0: depth = 4; break; 46 default: 47 depth = asyh->or.depth; 48 WARN_ON(1); 49 break; 50 } 51 52 if ((ret = PUSH_WAIT(push, 2))) 53 return ret; 54 55 PUSH_NVSQ(push, NVC37D, 0x2004 + (i * 0x400), depth << 4 | 56 asyh->or.nvsync << 3 | 57 asyh->or.nhsync << 2 | 58 asyh->or.crc_raster); 59 return 0; 60 } 61 62 static int 63 headc37d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) 64 { 65 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; 66 const int i = head->base.index; 67 int ret; 68 69 if ((ret = PUSH_WAIT(push, 2))) 70 return ret; 71 72 PUSH_NVSQ(push, NVC37D, 0x2000 + (i * 0x400), 0x80000000 | 73 asyh->procamp.sat.sin << 16 | 74 asyh->procamp.sat.cos << 4); 75 return 0; 76 } 77 78 int 79 headc37d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) 80 { 81 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; 82 const int i = head->base.index; 83 int ret; 84 85 if ((ret = PUSH_WAIT(push, 2))) 86 return ret; 87 88 PUSH_NVSQ(push, NV907D, 0x2018 + (i * 0x400), asyh->dither.mode << 8 | 89 asyh->dither.bits << 4 | 90 asyh->dither.enable); 91 return 0; 92 } 93 94 int 95 headc37d_curs_clr(struct nv50_head *head) 96 { 97 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; 98 const int i = head->base.index; 99 int ret; 100 101 if ((ret = PUSH_WAIT(push, 4))) 102 return ret; 103 104 PUSH_NVSQ(push, NVC37D, 0x209c + (i * 0x400), 0x000000cf); 105 PUSH_NVSQ(push, NVC37D, 0x2088 + (i * 0x400), 0x00000000); 106 return 0; 107 } 108 109 int 110 headc37d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) 111 { 112 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; 113 const int i = head->base.index; 114 int ret; 115 116 if ((ret = PUSH_WAIT(push, 7))) 117 return ret; 118 119 PUSH_NVSQ(push, NVC37D, 0x209c + (i * 0x400), 0x80000000 | 120 asyh->curs.layout << 8 | 121 asyh->curs.format << 0, 122 0x20a0 + (i * 0x400), 0x000072ff); 123 PUSH_NVSQ(push, NVC37D, 0x2088 + (i * 0x400), asyh->curs.handle); 124 PUSH_NVSQ(push, NVC37D, 0x2090 + (i * 0x400), asyh->curs.offset >> 8); 125 return 0; 126 } 127 128 int 129 headc37d_curs_format(struct nv50_head *head, struct nv50_wndw_atom *asyw, 130 struct nv50_head_atom *asyh) 131 { 132 asyh->curs.format = asyw->image.format; 133 return 0; 134 } 135 136 static int 137 headc37d_olut_clr(struct nv50_head *head) 138 { 139 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; 140 const int i = head->base.index; 141 int ret; 142 143 if ((ret = PUSH_WAIT(push, 2))) 144 return ret; 145 146 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), 0x00000000); 147 return 0; 148 } 149 150 static int 151 headc37d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) 152 { 153 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; 154 const int i = head->base.index; 155 int ret; 156 157 if ((ret = PUSH_WAIT(push, 4))) 158 return ret; 159 160 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT(i), 161 NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, SIZE, asyh->olut.size) | 162 NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, RANGE, asyh->olut.range) | 163 NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, OUTPUT_MODE, asyh->olut.output_mode), 164 165 HEAD_SET_OFFSET_OUTPUT_LUT(i), asyh->olut.offset >> 8, 166 HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), asyh->olut.handle); 167 return 0; 168 } 169 170 static bool 171 headc37d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size) 172 { 173 if (size != 256 && size != 1024) 174 return false; 175 176 asyh->olut.size = size == 1024 ? NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025 : 177 NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257; 178 asyh->olut.range = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY; 179 asyh->olut.output_mode = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE; 180 asyh->olut.load = head907d_olut_load; 181 return true; 182 } 183 184 static int 185 headc37d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) 186 { 187 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; 188 struct nv50_head_mode *m = &asyh->mode; 189 const int i = head->base.index; 190 int ret; 191 192 if ((ret = PUSH_WAIT(push, 15))) 193 return ret; 194 195 PUSH_MTHD(push, NVC37D, HEAD_SET_RASTER_SIZE(i), 196 NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) | 197 NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active), 198 199 HEAD_SET_RASTER_SYNC_END(i), 200 NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) | 201 NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce), 202 203 HEAD_SET_RASTER_BLANK_END(i), 204 NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) | 205 NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke), 206 207 HEAD_SET_RASTER_BLANK_START(i), 208 NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) | 209 NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks)); 210 211 //XXX: 212 PUSH_NVSQ(push, NVC37D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s); 213 PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace); 214 215 PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i), 216 NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000)); 217 218 PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i), 219 NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000)); 220 221 /*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */ 222 PUSH_MTHD(push, NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS(i), 223 NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, CURSOR, USAGE_W256_H256) | 224 NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, OUTPUT_LUT, USAGE_1025) | 225 NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, UPSCALING_ALLOWED, TRUE)); 226 return 0; 227 } 228 229 int 230 headc37d_view(struct nv50_head *head, struct nv50_head_atom *asyh) 231 { 232 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; 233 const int i = head->base.index; 234 int ret; 235 236 if ((ret = PUSH_WAIT(push, 4))) 237 return ret; 238 239 PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_IN(i), 240 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) | 241 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH)); 242 243 PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT(i), 244 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) | 245 NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH)); 246 return 0; 247 } 248 249 void 250 headc37d_static_wndw_map(struct nv50_head *head, struct nv50_head_atom *asyh) 251 { 252 int i, end; 253 254 for (i = head->base.index * 2, end = i + 2; i < end; i++) 255 asyh->wndw.owned |= BIT(i); 256 } 257 258 const struct nv50_head_func 259 headc37d = { 260 .view = headc37d_view, 261 .mode = headc37d_mode, 262 .olut = headc37d_olut, 263 .olut_size = 1024, 264 .olut_set = headc37d_olut_set, 265 .olut_clr = headc37d_olut_clr, 266 .curs_layout = head917d_curs_layout, 267 .curs_format = headc37d_curs_format, 268 .curs_set = headc37d_curs_set, 269 .curs_clr = headc37d_curs_clr, 270 .dither = headc37d_dither, 271 .procamp = headc37d_procamp, 272 .or = headc37d_or, 273 .static_wndw_map = headc37d_static_wndw_map, 274 }; 275