1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 #include "handles.h" 30 31 #include <linux/dma-mapping.h> 32 #include <linux/hdmi.h> 33 #include <linux/component.h> 34 #include <linux/iopoll.h> 35 36 #include <drm/display/drm_dp_helper.h> 37 #include <drm/display/drm_scdc_helper.h> 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_fb_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_vblank.h> 44 45 #include <nvif/push507c.h> 46 47 #include <nvif/class.h> 48 #include <nvif/cl0002.h> 49 #include <nvif/cl5070.h> 50 #include <nvif/event.h> 51 #include <nvif/if0014.h> 52 #include <nvif/timer.h> 53 54 #include <nvhw/class/cl507c.h> 55 #include <nvhw/class/cl507d.h> 56 #include <nvhw/class/cl837d.h> 57 #include <nvhw/class/cl887d.h> 58 #include <nvhw/class/cl907d.h> 59 #include <nvhw/class/cl917d.h> 60 61 #include "nouveau_drv.h" 62 #include "nouveau_dma.h" 63 #include "nouveau_gem.h" 64 #include "nouveau_connector.h" 65 #include "nouveau_encoder.h" 66 #include "nouveau_fence.h" 67 #include "nouveau_fbcon.h" 68 69 #include <subdev/bios/dp.h> 70 71 /****************************************************************************** 72 * EVO channel 73 *****************************************************************************/ 74 75 static int 76 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 77 const s32 *oclass, u8 head, void *data, u32 size, 78 struct nv50_chan *chan) 79 { 80 struct nvif_sclass *sclass; 81 int ret, i, n; 82 83 chan->device = device; 84 85 ret = n = nvif_object_sclass_get(disp, &sclass); 86 if (ret < 0) 87 return ret; 88 89 while (oclass[0]) { 90 for (i = 0; i < n; i++) { 91 if (sclass[i].oclass == oclass[0]) { 92 ret = nvif_object_ctor(disp, "kmsChan", 0, 93 oclass[0], data, size, 94 &chan->user); 95 if (ret == 0) 96 nvif_object_map(&chan->user, NULL, 0); 97 nvif_object_sclass_put(&sclass); 98 return ret; 99 } 100 } 101 oclass++; 102 } 103 104 nvif_object_sclass_put(&sclass); 105 return -ENOSYS; 106 } 107 108 static void 109 nv50_chan_destroy(struct nv50_chan *chan) 110 { 111 nvif_object_dtor(&chan->user); 112 } 113 114 /****************************************************************************** 115 * DMA EVO channel 116 *****************************************************************************/ 117 118 void 119 nv50_dmac_destroy(struct nv50_dmac *dmac) 120 { 121 nvif_object_dtor(&dmac->vram); 122 nvif_object_dtor(&dmac->sync); 123 124 nv50_chan_destroy(&dmac->base); 125 126 nvif_mem_dtor(&dmac->_push.mem); 127 } 128 129 static void 130 nv50_dmac_kick(struct nvif_push *push) 131 { 132 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 133 134 dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr; 135 if (dmac->put != dmac->cur) { 136 /* Push buffer fetches are not coherent with BAR1, we need to ensure 137 * writes have been flushed right through to VRAM before writing PUT. 138 */ 139 if (dmac->push->mem.type & NVIF_MEM_VRAM) { 140 struct nvif_device *device = dmac->base.device; 141 nvif_wr32(&device->object, 0x070000, 0x00000001); 142 nvif_msec(device, 2000, 143 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 144 break; 145 ); 146 } 147 148 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur); 149 dmac->put = dmac->cur; 150 } 151 152 push->bgn = push->cur; 153 } 154 155 static int 156 nv50_dmac_free(struct nv50_dmac *dmac) 157 { 158 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 159 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */ 160 return get - dmac->cur - 5; 161 return dmac->max - dmac->cur; 162 } 163 164 static int 165 nv50_dmac_wind(struct nv50_dmac *dmac) 166 { 167 /* Wait for GET to depart from the beginning of the push buffer to 168 * prevent writing PUT == GET, which would be ignored by HW. 169 */ 170 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 171 if (get == 0) { 172 /* Corner-case, HW idle, but non-committed work pending. */ 173 if (dmac->put == 0) 174 nv50_dmac_kick(dmac->push); 175 176 if (nvif_msec(dmac->base.device, 2000, 177 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) 178 break; 179 ) < 0) 180 return -ETIMEDOUT; 181 } 182 183 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0)); 184 dmac->cur = 0; 185 return 0; 186 } 187 188 static int 189 nv50_dmac_wait(struct nvif_push *push, u32 size) 190 { 191 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 192 int free; 193 194 if (WARN_ON(size > dmac->max)) 195 return -EINVAL; 196 197 dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr; 198 if (dmac->cur + size >= dmac->max) { 199 int ret = nv50_dmac_wind(dmac); 200 if (ret) 201 return ret; 202 203 push->cur = dmac->_push.mem.object.map.ptr; 204 push->cur = push->cur + dmac->cur; 205 nv50_dmac_kick(push); 206 } 207 208 if (nvif_msec(dmac->base.device, 2000, 209 if ((free = nv50_dmac_free(dmac)) >= size) 210 break; 211 ) < 0) { 212 WARN_ON(1); 213 return -ETIMEDOUT; 214 } 215 216 push->bgn = dmac->_push.mem.object.map.ptr; 217 push->bgn = push->bgn + dmac->cur; 218 push->cur = push->bgn; 219 push->end = push->cur + free; 220 return 0; 221 } 222 223 MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)"); 224 static int nv50_dmac_vram_pushbuf = -1; 225 module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400); 226 227 int 228 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 229 const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf, 230 struct nv50_dmac *dmac) 231 { 232 struct nouveau_cli *cli = (void *)device->object.client; 233 struct nvif_disp_chan_v0 *args = data; 234 u8 type = NVIF_MEM_COHERENT; 235 int ret; 236 237 mutex_init(&dmac->lock); 238 239 /* Pascal added support for 47-bit physical addresses, but some 240 * parts of EVO still only accept 40-bit PAs. 241 * 242 * To avoid issues on systems with large amounts of RAM, and on 243 * systems where an IOMMU maps pages at a high address, we need 244 * to allocate push buffers in VRAM instead. 245 * 246 * This appears to match NVIDIA's behaviour on Pascal. 247 */ 248 if ((nv50_dmac_vram_pushbuf > 0) || 249 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL)) 250 type |= NVIF_MEM_VRAM; 251 252 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000, 253 &dmac->_push.mem); 254 if (ret) 255 return ret; 256 257 dmac->ptr = dmac->_push.mem.object.map.ptr; 258 dmac->_push.wait = nv50_dmac_wait; 259 dmac->_push.kick = nv50_dmac_kick; 260 dmac->push = &dmac->_push; 261 dmac->push->bgn = dmac->_push.mem.object.map.ptr; 262 dmac->push->cur = dmac->push->bgn; 263 dmac->push->end = dmac->push->bgn; 264 dmac->max = 0x1000/4 - 1; 265 266 /* EVO channels are affected by a HW bug where the last 12 DWORDs 267 * of the push buffer aren't able to be used safely. 268 */ 269 if (disp->oclass < GV100_DISP) 270 dmac->max -= 12; 271 272 args->pushbuf = nvif_handle(&dmac->_push.mem.object); 273 274 ret = nv50_chan_create(device, disp, oclass, head, data, size, 275 &dmac->base); 276 if (ret) 277 return ret; 278 279 if (syncbuf < 0) 280 return 0; 281 282 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, 283 NV_DMA_IN_MEMORY, 284 &(struct nv_dma_v0) { 285 .target = NV_DMA_V0_TARGET_VRAM, 286 .access = NV_DMA_V0_ACCESS_RDWR, 287 .start = syncbuf + 0x0000, 288 .limit = syncbuf + 0x0fff, 289 }, sizeof(struct nv_dma_v0), 290 &dmac->sync); 291 if (ret) 292 return ret; 293 294 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM, 295 NV_DMA_IN_MEMORY, 296 &(struct nv_dma_v0) { 297 .target = NV_DMA_V0_TARGET_VRAM, 298 .access = NV_DMA_V0_ACCESS_RDWR, 299 .start = 0, 300 .limit = device->info.ram_user - 1, 301 }, sizeof(struct nv_dma_v0), 302 &dmac->vram); 303 if (ret) 304 return ret; 305 306 return ret; 307 } 308 309 /****************************************************************************** 310 * Output path helpers 311 *****************************************************************************/ 312 static void 313 nv50_outp_dump_caps(struct nouveau_drm *drm, 314 struct nouveau_encoder *outp) 315 { 316 NV_DEBUG(drm, "%s caps: dp_interlace=%d\n", 317 outp->base.base.name, outp->caps.dp_interlace); 318 } 319 320 static int 321 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 322 struct drm_crtc_state *crtc_state, 323 struct drm_connector_state *conn_state, 324 struct drm_display_mode *native_mode) 325 { 326 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 327 struct drm_display_mode *mode = &crtc_state->mode; 328 struct drm_connector *connector = conn_state->connector; 329 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 330 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 331 332 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 333 asyc->scaler.full = false; 334 if (!native_mode) 335 return 0; 336 337 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 338 switch (connector->connector_type) { 339 case DRM_MODE_CONNECTOR_LVDS: 340 case DRM_MODE_CONNECTOR_eDP: 341 /* Don't force scaler for EDID modes with 342 * same size as the native one (e.g. different 343 * refresh rate) 344 */ 345 if (mode->hdisplay == native_mode->hdisplay && 346 mode->vdisplay == native_mode->vdisplay && 347 mode->type & DRM_MODE_TYPE_DRIVER) 348 break; 349 mode = native_mode; 350 asyc->scaler.full = true; 351 break; 352 default: 353 break; 354 } 355 } else { 356 mode = native_mode; 357 } 358 359 if (!drm_mode_equal(adjusted_mode, mode)) { 360 drm_mode_copy(adjusted_mode, mode); 361 crtc_state->mode_changed = true; 362 } 363 364 return 0; 365 } 366 367 static int 368 nv50_outp_atomic_check(struct drm_encoder *encoder, 369 struct drm_crtc_state *crtc_state, 370 struct drm_connector_state *conn_state) 371 { 372 struct drm_connector *connector = conn_state->connector; 373 struct nouveau_connector *nv_connector = nouveau_connector(connector); 374 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 375 int ret; 376 377 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 378 nv_connector->native_mode); 379 if (ret) 380 return ret; 381 382 if (crtc_state->mode_changed || crtc_state->connectors_changed) 383 asyh->or.bpc = connector->display_info.bpc; 384 385 return 0; 386 } 387 388 struct nouveau_connector * 389 nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) 390 { 391 struct drm_connector *connector; 392 struct drm_connector_state *connector_state; 393 struct drm_encoder *encoder = to_drm_encoder(outp); 394 int i; 395 396 for_each_new_connector_in_state(state, connector, connector_state, i) { 397 if (connector_state->best_encoder == encoder) 398 return nouveau_connector(connector); 399 } 400 401 return NULL; 402 } 403 404 struct nouveau_connector * 405 nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) 406 { 407 struct drm_connector *connector; 408 struct drm_connector_state *connector_state; 409 struct drm_encoder *encoder = to_drm_encoder(outp); 410 int i; 411 412 for_each_old_connector_in_state(state, connector, connector_state, i) { 413 if (connector_state->best_encoder == encoder) 414 return nouveau_connector(connector); 415 } 416 417 return NULL; 418 } 419 420 static struct nouveau_crtc * 421 nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp) 422 { 423 struct drm_crtc *crtc; 424 struct drm_crtc_state *crtc_state; 425 const u32 mask = drm_encoder_mask(&outp->base.base); 426 int i; 427 428 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 429 if (crtc_state->encoder_mask & mask) 430 return nouveau_crtc(crtc); 431 } 432 433 return NULL; 434 } 435 436 /****************************************************************************** 437 * DAC 438 *****************************************************************************/ 439 static void 440 nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 441 { 442 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 443 struct nv50_core *core = nv50_disp(encoder->dev)->core; 444 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE); 445 446 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL); 447 nv_encoder->crtc = NULL; 448 nvif_outp_release(&nv_encoder->outp); 449 } 450 451 static void 452 nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 453 { 454 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 455 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 456 struct nv50_head_atom *asyh = 457 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 458 struct nv50_core *core = nv50_disp(encoder->dev)->core; 459 u32 ctrl = 0; 460 461 switch (nv_crtc->index) { 462 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; 463 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break; 464 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break; 465 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break; 466 default: 467 WARN_ON(1); 468 break; 469 } 470 471 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT); 472 473 nvif_outp_acquire_rgb_crt(&nv_encoder->outp); 474 475 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh); 476 asyh->or.depth = 0; 477 478 nv_encoder->crtc = &nv_crtc->base; 479 } 480 481 static enum drm_connector_status 482 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 483 { 484 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 485 u32 loadval; 486 int ret; 487 488 loadval = nouveau_drm(encoder->dev)->vbios.dactestval; 489 if (loadval == 0) 490 loadval = 340; 491 492 ret = nvif_outp_load_detect(&nv_encoder->outp, loadval); 493 if (ret <= 0) 494 return connector_status_disconnected; 495 496 return connector_status_connected; 497 } 498 499 static const struct drm_encoder_helper_funcs 500 nv50_dac_help = { 501 .atomic_check = nv50_outp_atomic_check, 502 .atomic_enable = nv50_dac_atomic_enable, 503 .atomic_disable = nv50_dac_atomic_disable, 504 .detect = nv50_dac_detect 505 }; 506 507 static void 508 nv50_dac_destroy(struct drm_encoder *encoder) 509 { 510 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 511 512 nvif_outp_dtor(&nv_encoder->outp); 513 514 drm_encoder_cleanup(encoder); 515 kfree(encoder); 516 } 517 518 static const struct drm_encoder_funcs 519 nv50_dac_func = { 520 .destroy = nv50_dac_destroy, 521 }; 522 523 static int 524 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 525 { 526 struct nouveau_drm *drm = nouveau_drm(connector->dev); 527 struct nv50_disp *disp = nv50_disp(connector->dev); 528 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 529 struct nvkm_i2c_bus *bus; 530 struct nouveau_encoder *nv_encoder; 531 struct drm_encoder *encoder; 532 int type = DRM_MODE_ENCODER_DAC; 533 534 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 535 if (!nv_encoder) 536 return -ENOMEM; 537 nv_encoder->dcb = dcbe; 538 539 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 540 if (bus) 541 nv_encoder->i2c = &bus->i2c; 542 543 encoder = to_drm_encoder(nv_encoder); 544 encoder->possible_crtcs = dcbe->heads; 545 encoder->possible_clones = 0; 546 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 547 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 548 drm_encoder_helper_add(encoder, &nv50_dac_help); 549 550 drm_connector_attach_encoder(connector, encoder); 551 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp); 552 } 553 554 /* 555 * audio component binding for ELD notification 556 */ 557 static void 558 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port, 559 int dev_id) 560 { 561 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 562 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 563 port, dev_id); 564 } 565 566 static int 567 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id, 568 bool *enabled, unsigned char *buf, int max_bytes) 569 { 570 struct drm_device *drm_dev = dev_get_drvdata(kdev); 571 struct nouveau_drm *drm = nouveau_drm(drm_dev); 572 struct drm_encoder *encoder; 573 struct nouveau_encoder *nv_encoder; 574 struct nouveau_crtc *nv_crtc; 575 int ret = 0; 576 577 *enabled = false; 578 579 mutex_lock(&drm->audio.lock); 580 581 drm_for_each_encoder(encoder, drm->dev) { 582 struct nouveau_connector *nv_connector = NULL; 583 584 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) 585 continue; /* TODO */ 586 587 nv_encoder = nouveau_encoder(encoder); 588 nv_connector = nouveau_connector(nv_encoder->audio.connector); 589 nv_crtc = nouveau_crtc(nv_encoder->crtc); 590 591 if (!nv_crtc || nv_encoder->outp.or.id != port || nv_crtc->index != dev_id) 592 continue; 593 594 *enabled = nv_encoder->audio.enabled; 595 if (*enabled) { 596 ret = drm_eld_size(nv_connector->base.eld); 597 memcpy(buf, nv_connector->base.eld, 598 min(max_bytes, ret)); 599 } 600 break; 601 } 602 603 mutex_unlock(&drm->audio.lock); 604 605 return ret; 606 } 607 608 static const struct drm_audio_component_ops nv50_audio_component_ops = { 609 .get_eld = nv50_audio_component_get_eld, 610 }; 611 612 static int 613 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev, 614 void *data) 615 { 616 struct drm_device *drm_dev = dev_get_drvdata(kdev); 617 struct nouveau_drm *drm = nouveau_drm(drm_dev); 618 struct drm_audio_component *acomp = data; 619 620 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS))) 621 return -ENOMEM; 622 623 drm_modeset_lock_all(drm_dev); 624 acomp->ops = &nv50_audio_component_ops; 625 acomp->dev = kdev; 626 drm->audio.component = acomp; 627 drm_modeset_unlock_all(drm_dev); 628 return 0; 629 } 630 631 static void 632 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev, 633 void *data) 634 { 635 struct drm_device *drm_dev = dev_get_drvdata(kdev); 636 struct nouveau_drm *drm = nouveau_drm(drm_dev); 637 struct drm_audio_component *acomp = data; 638 639 drm_modeset_lock_all(drm_dev); 640 drm->audio.component = NULL; 641 acomp->ops = NULL; 642 acomp->dev = NULL; 643 drm_modeset_unlock_all(drm_dev); 644 } 645 646 static const struct component_ops nv50_audio_component_bind_ops = { 647 .bind = nv50_audio_component_bind, 648 .unbind = nv50_audio_component_unbind, 649 }; 650 651 static void 652 nv50_audio_component_init(struct nouveau_drm *drm) 653 { 654 if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops)) 655 return; 656 657 drm->audio.component_registered = true; 658 mutex_init(&drm->audio.lock); 659 } 660 661 static void 662 nv50_audio_component_fini(struct nouveau_drm *drm) 663 { 664 if (!drm->audio.component_registered) 665 return; 666 667 component_del(drm->dev->dev, &nv50_audio_component_bind_ops); 668 drm->audio.component_registered = false; 669 mutex_destroy(&drm->audio.lock); 670 } 671 672 /****************************************************************************** 673 * Audio 674 *****************************************************************************/ 675 static void 676 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 677 { 678 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 679 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 680 struct nv50_disp *disp = nv50_disp(encoder->dev); 681 struct nvif_outp *outp = &nv_encoder->outp; 682 struct { 683 struct nv50_disp_mthd_v1 base; 684 struct nv50_disp_sor_hda_eld_v0 eld; 685 } args = { 686 .base.version = 1, 687 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 688 .base.hasht = nv_encoder->dcb->hasht, 689 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 690 (0x0100 << nv_crtc->index), 691 }; 692 693 mutex_lock(&drm->audio.lock); 694 if (nv_encoder->audio.enabled) { 695 nv_encoder->audio.enabled = false; 696 nv_encoder->audio.connector = NULL; 697 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 698 } 699 mutex_unlock(&drm->audio.lock); 700 701 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index); 702 } 703 704 static void 705 nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, 706 struct nouveau_connector *nv_connector, struct drm_atomic_state *state, 707 struct drm_display_mode *mode) 708 { 709 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 710 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 711 struct nv50_disp *disp = nv50_disp(encoder->dev); 712 struct nvif_outp *outp = &nv_encoder->outp; 713 struct __packed { 714 struct { 715 struct nv50_disp_mthd_v1 mthd; 716 struct nv50_disp_sor_hda_eld_v0 eld; 717 } base; 718 u8 data[sizeof(nv_connector->base.eld)]; 719 } args = { 720 .base.mthd.version = 1, 721 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 722 .base.mthd.hasht = nv_encoder->dcb->hasht, 723 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 724 (0x0100 << nv_crtc->index), 725 }; 726 727 if (!drm_detect_monitor_audio(nv_connector->edid)) 728 return; 729 730 mutex_lock(&drm->audio.lock); 731 732 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 733 734 nvif_mthd(&disp->disp->object, 0, &args, 735 sizeof(args.base) + drm_eld_size(args.data)); 736 nv_encoder->audio.enabled = true; 737 nv_encoder->audio.connector = &nv_connector->base; 738 739 mutex_unlock(&drm->audio.lock); 740 741 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index); 742 } 743 744 /****************************************************************************** 745 * HDMI 746 *****************************************************************************/ 747 static void 748 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 749 { 750 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 751 struct nv50_disp *disp = nv50_disp(encoder->dev); 752 struct { 753 struct nv50_disp_mthd_v1 base; 754 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 755 } args = { 756 .base.version = 1, 757 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 758 .base.hasht = nv_encoder->dcb->hasht, 759 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 760 (0x0100 << nv_crtc->index), 761 }; 762 763 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 764 } 765 766 static void 767 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, 768 struct nouveau_connector *nv_connector, struct drm_atomic_state *state, 769 struct drm_display_mode *mode) 770 { 771 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 772 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 773 struct nv50_disp *disp = nv50_disp(encoder->dev); 774 struct { 775 struct nv50_disp_mthd_v1 base; 776 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 777 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 778 } args = { 779 .base.version = 1, 780 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 781 .base.hasht = nv_encoder->dcb->hasht, 782 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 783 (0x0100 << nv_crtc->index), 784 .pwr.state = 1, 785 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 786 }; 787 struct drm_hdmi_info *hdmi; 788 u32 max_ac_packet; 789 union hdmi_infoframe avi_frame; 790 union hdmi_infoframe vendor_frame; 791 bool high_tmds_clock_ratio = false, scrambling = false; 792 u8 config; 793 int ret; 794 int size; 795 796 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 797 return; 798 799 hdmi = &nv_connector->base.display_info.hdmi; 800 801 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, 802 &nv_connector->base, mode); 803 if (!ret) { 804 drm_hdmi_avi_infoframe_quant_range(&avi_frame.avi, 805 &nv_connector->base, mode, 806 HDMI_QUANTIZATION_RANGE_FULL); 807 /* We have an AVI InfoFrame, populate it to the display */ 808 args.pwr.avi_infoframe_length 809 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 810 } 811 812 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 813 &nv_connector->base, mode); 814 if (!ret) { 815 /* We have a Vendor InfoFrame, populate it to the display */ 816 args.pwr.vendor_infoframe_length 817 = hdmi_infoframe_pack(&vendor_frame, 818 args.infoframes 819 + args.pwr.avi_infoframe_length, 820 17); 821 } 822 823 max_ac_packet = mode->htotal - mode->hdisplay; 824 max_ac_packet -= args.pwr.rekey; 825 max_ac_packet -= 18; /* constant from tegra */ 826 args.pwr.max_ac_packet = max_ac_packet / 32; 827 828 if (hdmi->scdc.scrambling.supported) { 829 high_tmds_clock_ratio = mode->clock > 340000; 830 scrambling = high_tmds_clock_ratio || 831 hdmi->scdc.scrambling.low_rates; 832 } 833 834 args.pwr.scdc = 835 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 836 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 837 838 size = sizeof(args.base) 839 + sizeof(args.pwr) 840 + args.pwr.avi_infoframe_length 841 + args.pwr.vendor_infoframe_length; 842 nvif_mthd(&disp->disp->object, 0, &args, size); 843 844 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); 845 846 /* If SCDC is supported by the downstream monitor, update 847 * divider / scrambling settings to what we programmed above. 848 */ 849 if (!hdmi->scdc.scrambling.supported) 850 return; 851 852 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 853 if (ret < 0) { 854 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 855 return; 856 } 857 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 858 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 859 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 860 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 861 if (ret < 0) 862 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 863 config, ret); 864 } 865 866 /****************************************************************************** 867 * MST 868 *****************************************************************************/ 869 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 870 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 871 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 872 873 struct nv50_mstc { 874 struct nv50_mstm *mstm; 875 struct drm_dp_mst_port *port; 876 struct drm_connector connector; 877 878 struct drm_display_mode *native; 879 struct edid *edid; 880 }; 881 882 struct nv50_msto { 883 struct drm_encoder encoder; 884 885 /* head is statically assigned on msto creation */ 886 struct nv50_head *head; 887 struct nv50_mstc *mstc; 888 bool disabled; 889 bool enabled; 890 }; 891 892 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder) 893 { 894 struct nv50_msto *msto; 895 896 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 897 return nouveau_encoder(encoder); 898 899 msto = nv50_msto(encoder); 900 if (!msto->mstc) 901 return NULL; 902 return msto->mstc->mstm->outp; 903 } 904 905 static void 906 nv50_msto_cleanup(struct drm_atomic_state *state, 907 struct drm_dp_mst_topology_state *mst_state, 908 struct drm_dp_mst_topology_mgr *mgr, 909 struct nv50_msto *msto) 910 { 911 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 912 struct drm_dp_mst_atomic_payload *payload = 913 drm_atomic_get_mst_payload_state(mst_state, msto->mstc->port); 914 915 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 916 917 if (msto->disabled) { 918 msto->mstc = NULL; 919 msto->disabled = false; 920 } else if (msto->enabled) { 921 drm_dp_add_payload_part2(mgr, state, payload); 922 msto->enabled = false; 923 } 924 } 925 926 static void 927 nv50_msto_prepare(struct drm_atomic_state *state, 928 struct drm_dp_mst_topology_state *mst_state, 929 struct drm_dp_mst_topology_mgr *mgr, 930 struct nv50_msto *msto) 931 { 932 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 933 struct nv50_mstc *mstc = msto->mstc; 934 struct nv50_mstm *mstm = mstc->mstm; 935 struct drm_dp_mst_atomic_payload *payload; 936 struct { 937 struct nv50_disp_mthd_v1 base; 938 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 939 } args = { 940 .base.version = 1, 941 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 942 .base.hasht = mstm->outp->dcb->hasht, 943 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 944 (0x0100 << msto->head->base.index), 945 }; 946 947 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 948 949 payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port); 950 951 // TODO: Figure out if we want to do a better job of handling VCPI allocation failures here? 952 if (msto->disabled) { 953 drm_dp_remove_payload(mgr, mst_state, payload); 954 } else { 955 if (msto->enabled) 956 drm_dp_add_payload_part1(mgr, mst_state, payload); 957 958 args.vcpi.start_slot = payload->vc_start_slot; 959 args.vcpi.num_slots = payload->time_slots; 960 args.vcpi.pbn = payload->pbn; 961 args.vcpi.aligned_pbn = payload->time_slots * mst_state->pbn_div; 962 } 963 964 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 965 msto->encoder.name, msto->head->base.base.name, 966 args.vcpi.start_slot, args.vcpi.num_slots, 967 args.vcpi.pbn, args.vcpi.aligned_pbn); 968 969 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 970 } 971 972 static int 973 nv50_msto_atomic_check(struct drm_encoder *encoder, 974 struct drm_crtc_state *crtc_state, 975 struct drm_connector_state *conn_state) 976 { 977 struct drm_atomic_state *state = crtc_state->state; 978 struct drm_connector *connector = conn_state->connector; 979 struct drm_dp_mst_topology_state *mst_state; 980 struct nv50_mstc *mstc = nv50_mstc(connector); 981 struct nv50_mstm *mstm = mstc->mstm; 982 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 983 int slots; 984 int ret; 985 986 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 987 mstc->native); 988 if (ret) 989 return ret; 990 991 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 992 return 0; 993 994 /* 995 * When restoring duplicated states, we need to make sure that the bw 996 * remains the same and avoid recalculating it, as the connector's bpc 997 * may have changed after the state was duplicated 998 */ 999 if (!state->duplicated) { 1000 const int clock = crtc_state->adjusted_mode.clock; 1001 1002 asyh->or.bpc = connector->display_info.bpc; 1003 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, 1004 false); 1005 } 1006 1007 mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr); 1008 if (IS_ERR(mst_state)) 1009 return PTR_ERR(mst_state); 1010 1011 if (!mst_state->pbn_div) { 1012 struct nouveau_encoder *outp = mstc->mstm->outp; 1013 1014 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr, 1015 outp->dp.link_bw, outp->dp.link_nr); 1016 } 1017 1018 slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn); 1019 if (slots < 0) 1020 return slots; 1021 1022 asyh->dp.tu = slots; 1023 1024 return 0; 1025 } 1026 1027 static u8 1028 nv50_dp_bpc_to_depth(unsigned int bpc) 1029 { 1030 switch (bpc) { 1031 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; 1032 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; 1033 case 10: 1034 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; 1035 } 1036 } 1037 1038 static void 1039 nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1040 { 1041 struct nv50_msto *msto = nv50_msto(encoder); 1042 struct nv50_head *head = msto->head; 1043 struct nv50_head_atom *asyh = 1044 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base)); 1045 struct nv50_mstc *mstc = NULL; 1046 struct nv50_mstm *mstm = NULL; 1047 struct drm_connector *connector; 1048 struct drm_connector_list_iter conn_iter; 1049 u8 proto; 1050 1051 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 1052 drm_for_each_connector_iter(connector, &conn_iter) { 1053 if (connector->state->best_encoder == &msto->encoder) { 1054 mstc = nv50_mstc(connector); 1055 mstm = mstc->mstm; 1056 break; 1057 } 1058 } 1059 drm_connector_list_iter_end(&conn_iter); 1060 1061 if (WARN_ON(!mstc)) 1062 return; 1063 1064 if (!mstm->links++) { 1065 /*XXX: MST audio. */ 1066 nvif_outp_acquire_dp(&mstm->outp->outp, false); 1067 } 1068 1069 if (mstm->outp->outp.or.link & 1) 1070 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1071 else 1072 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1073 1074 mstm->outp->update(mstm->outp, head->base.index, asyh, proto, 1075 nv50_dp_bpc_to_depth(asyh->or.bpc)); 1076 1077 msto->mstc = mstc; 1078 msto->enabled = true; 1079 mstm->modified = true; 1080 } 1081 1082 static void 1083 nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1084 { 1085 struct nv50_msto *msto = nv50_msto(encoder); 1086 struct nv50_mstc *mstc = msto->mstc; 1087 struct nv50_mstm *mstm = mstc->mstm; 1088 1089 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 1090 mstm->modified = true; 1091 if (!--mstm->links) 1092 mstm->disabled = true; 1093 msto->disabled = true; 1094 } 1095 1096 static const struct drm_encoder_helper_funcs 1097 nv50_msto_help = { 1098 .atomic_disable = nv50_msto_atomic_disable, 1099 .atomic_enable = nv50_msto_atomic_enable, 1100 .atomic_check = nv50_msto_atomic_check, 1101 }; 1102 1103 static void 1104 nv50_msto_destroy(struct drm_encoder *encoder) 1105 { 1106 struct nv50_msto *msto = nv50_msto(encoder); 1107 drm_encoder_cleanup(&msto->encoder); 1108 kfree(msto); 1109 } 1110 1111 static const struct drm_encoder_funcs 1112 nv50_msto = { 1113 .destroy = nv50_msto_destroy, 1114 }; 1115 1116 static struct nv50_msto * 1117 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) 1118 { 1119 struct nv50_msto *msto; 1120 int ret; 1121 1122 msto = kzalloc(sizeof(*msto), GFP_KERNEL); 1123 if (!msto) 1124 return ERR_PTR(-ENOMEM); 1125 1126 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 1127 DRM_MODE_ENCODER_DPMST, "mst-%d", id); 1128 if (ret) { 1129 kfree(msto); 1130 return ERR_PTR(ret); 1131 } 1132 1133 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 1134 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base); 1135 msto->head = head; 1136 return msto; 1137 } 1138 1139 static struct drm_encoder * 1140 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 1141 struct drm_atomic_state *state) 1142 { 1143 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 1144 connector); 1145 struct nv50_mstc *mstc = nv50_mstc(connector); 1146 struct drm_crtc *crtc = connector_state->crtc; 1147 1148 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1149 return NULL; 1150 1151 return &nv50_head(crtc)->msto->encoder; 1152 } 1153 1154 static enum drm_mode_status 1155 nv50_mstc_mode_valid(struct drm_connector *connector, 1156 struct drm_display_mode *mode) 1157 { 1158 struct nv50_mstc *mstc = nv50_mstc(connector); 1159 struct nouveau_encoder *outp = mstc->mstm->outp; 1160 1161 /* TODO: calculate the PBN from the dotclock and validate against the 1162 * MSTB's max possible PBN 1163 */ 1164 1165 return nv50_dp_mode_valid(connector, outp, mode, NULL); 1166 } 1167 1168 static int 1169 nv50_mstc_get_modes(struct drm_connector *connector) 1170 { 1171 struct nv50_mstc *mstc = nv50_mstc(connector); 1172 int ret = 0; 1173 1174 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 1175 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 1176 if (mstc->edid) 1177 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 1178 1179 /* 1180 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc 1181 * to 8 to save bandwidth on the topology. In the future, we'll want 1182 * to properly fix this by dynamically selecting the highest possible 1183 * bpc that would fit in the topology 1184 */ 1185 if (connector->display_info.bpc) 1186 connector->display_info.bpc = 1187 clamp(connector->display_info.bpc, 6U, 8U); 1188 else 1189 connector->display_info.bpc = 8; 1190 1191 if (mstc->native) 1192 drm_mode_destroy(mstc->connector.dev, mstc->native); 1193 mstc->native = nouveau_conn_native_mode(&mstc->connector); 1194 return ret; 1195 } 1196 1197 static int 1198 nv50_mstc_atomic_check(struct drm_connector *connector, 1199 struct drm_atomic_state *state) 1200 { 1201 struct nv50_mstc *mstc = nv50_mstc(connector); 1202 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 1203 1204 return drm_dp_atomic_release_time_slots(state, mgr, mstc->port); 1205 } 1206 1207 static int 1208 nv50_mstc_detect(struct drm_connector *connector, 1209 struct drm_modeset_acquire_ctx *ctx, bool force) 1210 { 1211 struct nv50_mstc *mstc = nv50_mstc(connector); 1212 int ret; 1213 1214 if (drm_connector_is_unregistered(connector)) 1215 return connector_status_disconnected; 1216 1217 ret = pm_runtime_get_sync(connector->dev->dev); 1218 if (ret < 0 && ret != -EACCES) { 1219 pm_runtime_put_autosuspend(connector->dev->dev); 1220 return connector_status_disconnected; 1221 } 1222 1223 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr, 1224 mstc->port); 1225 if (ret != connector_status_connected) 1226 goto out; 1227 1228 out: 1229 pm_runtime_mark_last_busy(connector->dev->dev); 1230 pm_runtime_put_autosuspend(connector->dev->dev); 1231 return ret; 1232 } 1233 1234 static const struct drm_connector_helper_funcs 1235 nv50_mstc_help = { 1236 .get_modes = nv50_mstc_get_modes, 1237 .mode_valid = nv50_mstc_mode_valid, 1238 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 1239 .atomic_check = nv50_mstc_atomic_check, 1240 .detect_ctx = nv50_mstc_detect, 1241 }; 1242 1243 static void 1244 nv50_mstc_destroy(struct drm_connector *connector) 1245 { 1246 struct nv50_mstc *mstc = nv50_mstc(connector); 1247 1248 drm_connector_cleanup(&mstc->connector); 1249 drm_dp_mst_put_port_malloc(mstc->port); 1250 1251 kfree(mstc); 1252 } 1253 1254 static const struct drm_connector_funcs 1255 nv50_mstc = { 1256 .reset = nouveau_conn_reset, 1257 .fill_modes = drm_helper_probe_single_connector_modes, 1258 .destroy = nv50_mstc_destroy, 1259 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1260 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1261 .atomic_set_property = nouveau_conn_atomic_set_property, 1262 .atomic_get_property = nouveau_conn_atomic_get_property, 1263 }; 1264 1265 static int 1266 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1267 const char *path, struct nv50_mstc **pmstc) 1268 { 1269 struct drm_device *dev = mstm->outp->base.base.dev; 1270 struct drm_crtc *crtc; 1271 struct nv50_mstc *mstc; 1272 int ret; 1273 1274 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1275 return -ENOMEM; 1276 mstc->mstm = mstm; 1277 mstc->port = port; 1278 1279 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1280 DRM_MODE_CONNECTOR_DisplayPort); 1281 if (ret) { 1282 kfree(*pmstc); 1283 *pmstc = NULL; 1284 return ret; 1285 } 1286 1287 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1288 1289 mstc->connector.funcs->reset(&mstc->connector); 1290 nouveau_conn_attach_properties(&mstc->connector); 1291 1292 drm_for_each_crtc(crtc, dev) { 1293 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1294 continue; 1295 1296 drm_connector_attach_encoder(&mstc->connector, 1297 &nv50_head(crtc)->msto->encoder); 1298 } 1299 1300 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1301 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1302 drm_connector_set_path_property(&mstc->connector, path); 1303 drm_dp_mst_get_port_malloc(port); 1304 return 0; 1305 } 1306 1307 static void 1308 nv50_mstm_cleanup(struct drm_atomic_state *state, 1309 struct drm_dp_mst_topology_state *mst_state, 1310 struct nv50_mstm *mstm) 1311 { 1312 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1313 struct drm_encoder *encoder; 1314 1315 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1316 drm_dp_check_act_status(&mstm->mgr); 1317 1318 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1319 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1320 struct nv50_msto *msto = nv50_msto(encoder); 1321 struct nv50_mstc *mstc = msto->mstc; 1322 if (mstc && mstc->mstm == mstm) 1323 nv50_msto_cleanup(state, mst_state, &mstm->mgr, msto); 1324 } 1325 } 1326 1327 mstm->modified = false; 1328 } 1329 1330 static void 1331 nv50_mstm_prepare(struct drm_atomic_state *state, 1332 struct drm_dp_mst_topology_state *mst_state, 1333 struct nv50_mstm *mstm) 1334 { 1335 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1336 struct drm_encoder *encoder; 1337 1338 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1339 1340 /* Disable payloads first */ 1341 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1342 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1343 struct nv50_msto *msto = nv50_msto(encoder); 1344 struct nv50_mstc *mstc = msto->mstc; 1345 if (mstc && mstc->mstm == mstm && msto->disabled) 1346 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto); 1347 } 1348 } 1349 1350 /* Add payloads for new heads, while also updating the start slots of any unmodified (but 1351 * active) heads that may have had their VC slots shifted left after the previous step 1352 */ 1353 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1354 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1355 struct nv50_msto *msto = nv50_msto(encoder); 1356 struct nv50_mstc *mstc = msto->mstc; 1357 if (mstc && mstc->mstm == mstm && !msto->disabled) 1358 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto); 1359 } 1360 } 1361 1362 if (mstm->disabled) { 1363 if (!mstm->links) 1364 nvif_outp_release(&mstm->outp->outp); 1365 mstm->disabled = false; 1366 } 1367 } 1368 1369 static struct drm_connector * 1370 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1371 struct drm_dp_mst_port *port, const char *path) 1372 { 1373 struct nv50_mstm *mstm = nv50_mstm(mgr); 1374 struct nv50_mstc *mstc; 1375 int ret; 1376 1377 ret = nv50_mstc_new(mstm, port, path, &mstc); 1378 if (ret) 1379 return NULL; 1380 1381 return &mstc->connector; 1382 } 1383 1384 static const struct drm_dp_mst_topology_cbs 1385 nv50_mstm = { 1386 .add_connector = nv50_mstm_add_connector, 1387 }; 1388 1389 bool 1390 nv50_mstm_service(struct nouveau_drm *drm, 1391 struct nouveau_connector *nv_connector, 1392 struct nv50_mstm *mstm) 1393 { 1394 struct drm_dp_aux *aux = &nv_connector->aux; 1395 bool handled = true, ret = true; 1396 int rc; 1397 u8 esi[8] = {}; 1398 1399 while (handled) { 1400 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1401 if (rc != 8) { 1402 ret = false; 1403 break; 1404 } 1405 1406 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1407 if (!handled) 1408 break; 1409 1410 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 1411 3); 1412 if (rc != 3) { 1413 ret = false; 1414 break; 1415 } 1416 } 1417 1418 if (!ret) 1419 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n", 1420 nv_connector->base.name, rc); 1421 1422 return ret; 1423 } 1424 1425 void 1426 nv50_mstm_remove(struct nv50_mstm *mstm) 1427 { 1428 mstm->is_mst = false; 1429 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1430 } 1431 1432 static int 1433 nv50_mstm_enable(struct nv50_mstm *mstm, int state) 1434 { 1435 struct nouveau_encoder *outp = mstm->outp; 1436 struct { 1437 struct nv50_disp_mthd_v1 base; 1438 struct nv50_disp_sor_dp_mst_link_v0 mst; 1439 } args = { 1440 .base.version = 1, 1441 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1442 .base.hasht = outp->dcb->hasht, 1443 .base.hashm = outp->dcb->hashm, 1444 .mst.state = state, 1445 }; 1446 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1447 struct nvif_object *disp = &drm->display->disp.object; 1448 1449 return nvif_mthd(disp, 0, &args, sizeof(args)); 1450 } 1451 1452 int 1453 nv50_mstm_detect(struct nouveau_encoder *outp) 1454 { 1455 struct nv50_mstm *mstm = outp->dp.mstm; 1456 struct drm_dp_aux *aux; 1457 int ret; 1458 1459 if (!mstm || !mstm->can_mst) 1460 return 0; 1461 1462 aux = mstm->mgr.aux; 1463 1464 /* Clear any leftover MST state we didn't set ourselves by first 1465 * disabling MST if it was already enabled 1466 */ 1467 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1468 if (ret < 0) 1469 return ret; 1470 1471 /* And start enabling */ 1472 ret = nv50_mstm_enable(mstm, true); 1473 if (ret) 1474 return ret; 1475 1476 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true); 1477 if (ret) { 1478 nv50_mstm_enable(mstm, false); 1479 return ret; 1480 } 1481 1482 mstm->is_mst = true; 1483 return 1; 1484 } 1485 1486 static void 1487 nv50_mstm_fini(struct nouveau_encoder *outp) 1488 { 1489 struct nv50_mstm *mstm = outp->dp.mstm; 1490 1491 if (!mstm) 1492 return; 1493 1494 /* Don't change the MST state of this connector until we've finished 1495 * resuming, since we can't safely grab hpd_irq_lock in our resume 1496 * path to protect mstm->is_mst without potentially deadlocking 1497 */ 1498 mutex_lock(&outp->dp.hpd_irq_lock); 1499 mstm->suspended = true; 1500 mutex_unlock(&outp->dp.hpd_irq_lock); 1501 1502 if (mstm->is_mst) 1503 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1504 } 1505 1506 static void 1507 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime) 1508 { 1509 struct nv50_mstm *mstm = outp->dp.mstm; 1510 int ret = 0; 1511 1512 if (!mstm) 1513 return; 1514 1515 if (mstm->is_mst) { 1516 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime); 1517 if (ret == -1) 1518 nv50_mstm_remove(mstm); 1519 } 1520 1521 mutex_lock(&outp->dp.hpd_irq_lock); 1522 mstm->suspended = false; 1523 mutex_unlock(&outp->dp.hpd_irq_lock); 1524 1525 if (ret == -1) 1526 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1527 } 1528 1529 static void 1530 nv50_mstm_del(struct nv50_mstm **pmstm) 1531 { 1532 struct nv50_mstm *mstm = *pmstm; 1533 if (mstm) { 1534 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1535 kfree(*pmstm); 1536 *pmstm = NULL; 1537 } 1538 } 1539 1540 static int 1541 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1542 int conn_base_id, struct nv50_mstm **pmstm) 1543 { 1544 const int max_payloads = hweight8(outp->dcb->heads); 1545 struct drm_device *dev = outp->base.base.dev; 1546 struct nv50_mstm *mstm; 1547 int ret; 1548 1549 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1550 return -ENOMEM; 1551 mstm->outp = outp; 1552 mstm->mgr.cbs = &nv50_mstm; 1553 1554 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1555 max_payloads, conn_base_id); 1556 if (ret) 1557 return ret; 1558 1559 return 0; 1560 } 1561 1562 /****************************************************************************** 1563 * SOR 1564 *****************************************************************************/ 1565 static void 1566 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1567 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1568 { 1569 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1570 struct nv50_core *core = disp->core; 1571 1572 if (!asyh) { 1573 nv_encoder->ctrl &= ~BIT(head); 1574 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE)) 1575 nv_encoder->ctrl = 0; 1576 } else { 1577 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto); 1578 nv_encoder->ctrl |= BIT(head); 1579 asyh->or.depth = depth; 1580 } 1581 1582 core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh); 1583 } 1584 1585 /* TODO: Should we extend this to PWM-only backlights? 1586 * As well, should we add a DRM helper for waiting for the backlight to acknowledge 1587 * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a 1588 * fixed time delay from the vbios… 1589 */ 1590 static void 1591 nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1592 { 1593 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1594 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1595 struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder); 1596 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1597 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 1598 struct nouveau_backlight *backlight = nv_connector->backlight; 1599 #endif 1600 struct drm_dp_aux *aux = &nv_connector->aux; 1601 int ret; 1602 u8 pwr; 1603 1604 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1605 if (backlight && backlight->uses_dpcd) { 1606 ret = drm_edp_backlight_disable(aux, &backlight->edp_info); 1607 if (ret < 0) 1608 NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n", 1609 nv_connector->base.base.id, nv_connector->base.name, ret); 1610 } 1611 #endif 1612 1613 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { 1614 ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr); 1615 1616 if (ret == 0) { 1617 pwr &= ~DP_SET_POWER_MASK; 1618 pwr |= DP_SET_POWER_D3; 1619 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr); 1620 } 1621 } 1622 1623 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1624 nv50_audio_disable(encoder, nv_crtc); 1625 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1626 nvif_outp_release(&nv_encoder->outp); 1627 nv_encoder->crtc = NULL; 1628 } 1629 1630 static void 1631 nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1632 { 1633 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1634 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 1635 struct nv50_head_atom *asyh = 1636 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 1637 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1638 struct { 1639 struct nv50_disp_mthd_v1 base; 1640 struct nv50_disp_sor_lvds_script_v0 lvds; 1641 } lvds = { 1642 .base.version = 1, 1643 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1644 .base.hasht = nv_encoder->dcb->hasht, 1645 .base.hashm = nv_encoder->dcb->hashm, 1646 }; 1647 struct nv50_disp *disp = nv50_disp(encoder->dev); 1648 struct drm_device *dev = encoder->dev; 1649 struct nouveau_drm *drm = nouveau_drm(dev); 1650 struct nouveau_connector *nv_connector; 1651 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1652 struct nouveau_backlight *backlight; 1653 #endif 1654 struct nvbios *bios = &drm->vbios; 1655 bool hda = false; 1656 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM; 1657 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; 1658 1659 nv_connector = nv50_outp_get_new_connector(state, nv_encoder); 1660 nv_encoder->crtc = &nv_crtc->base; 1661 1662 if ((disp->disp->object.oclass == GT214_DISP || 1663 disp->disp->object.oclass >= GF110_DISP) && 1664 drm_detect_monitor_audio(nv_connector->edid)) 1665 hda = true; 1666 1667 switch (nv_encoder->dcb->type) { 1668 case DCB_OUTPUT_TMDS: 1669 nvif_outp_acquire_tmds(&nv_encoder->outp, hda); 1670 if (nv_encoder->outp.or.link & 1) { 1671 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A; 1672 /* Only enable dual-link if: 1673 * - Need to (i.e. rate > 165MHz) 1674 * - DCB says we can 1675 * - Not an HDMI monitor, since there's no dual-link 1676 * on HDMI. 1677 */ 1678 if (mode->clock >= 165000 && 1679 nv_encoder->dcb->duallink_possible && 1680 !drm_detect_hdmi_monitor(nv_connector->edid)) 1681 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS; 1682 } else { 1683 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B; 1684 } 1685 1686 nv50_hdmi_enable(&nv_encoder->base.base, nv_crtc, nv_connector, state, mode); 1687 break; 1688 case DCB_OUTPUT_LVDS: 1689 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM; 1690 1691 if (bios->fp_no_ddc) { 1692 if (bios->fp.dual_link) 1693 lvds.lvds.script |= 0x0100; 1694 if (bios->fp.if_is_24bit) 1695 lvds.lvds.script |= 0x0200; 1696 } else { 1697 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1698 if (((u8 *)nv_connector->edid)[121] == 2) 1699 lvds.lvds.script |= 0x0100; 1700 } else 1701 if (mode->clock >= bios->fp.duallink_transition_clk) { 1702 lvds.lvds.script |= 0x0100; 1703 } 1704 1705 if (lvds.lvds.script & 0x0100) { 1706 if (bios->fp.strapless_is_24bit & 2) 1707 lvds.lvds.script |= 0x0200; 1708 } else { 1709 if (bios->fp.strapless_is_24bit & 1) 1710 lvds.lvds.script |= 0x0200; 1711 } 1712 1713 if (asyh->or.bpc == 8) 1714 lvds.lvds.script |= 0x0200; 1715 } 1716 1717 nvif_outp_acquire_lvds(&nv_encoder->outp); 1718 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1719 break; 1720 case DCB_OUTPUT_DP: 1721 nvif_outp_acquire_dp(&nv_encoder->outp, hda); 1722 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); 1723 1724 if (nv_encoder->outp.or.link & 1) 1725 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1726 else 1727 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1728 1729 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); 1730 1731 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1732 backlight = nv_connector->backlight; 1733 if (backlight && backlight->uses_dpcd) 1734 drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info, 1735 (u16)backlight->dev->props.brightness); 1736 #endif 1737 1738 break; 1739 default: 1740 BUG(); 1741 break; 1742 } 1743 1744 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1745 } 1746 1747 static const struct drm_encoder_helper_funcs 1748 nv50_sor_help = { 1749 .atomic_check = nv50_outp_atomic_check, 1750 .atomic_enable = nv50_sor_atomic_enable, 1751 .atomic_disable = nv50_sor_atomic_disable, 1752 }; 1753 1754 static void 1755 nv50_sor_destroy(struct drm_encoder *encoder) 1756 { 1757 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1758 1759 nvif_outp_dtor(&nv_encoder->outp); 1760 1761 nv50_mstm_del(&nv_encoder->dp.mstm); 1762 drm_encoder_cleanup(encoder); 1763 1764 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) 1765 mutex_destroy(&nv_encoder->dp.hpd_irq_lock); 1766 1767 kfree(encoder); 1768 } 1769 1770 static const struct drm_encoder_funcs 1771 nv50_sor_func = { 1772 .destroy = nv50_sor_destroy, 1773 }; 1774 1775 bool nv50_has_mst(struct nouveau_drm *drm) 1776 { 1777 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1778 u32 data; 1779 u8 ver, hdr, cnt, len; 1780 1781 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len); 1782 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04); 1783 } 1784 1785 static int 1786 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1787 { 1788 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1789 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1790 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1791 struct nouveau_encoder *nv_encoder; 1792 struct drm_encoder *encoder; 1793 struct nv50_disp *disp = nv50_disp(connector->dev); 1794 int type, ret; 1795 1796 switch (dcbe->type) { 1797 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1798 case DCB_OUTPUT_TMDS: 1799 case DCB_OUTPUT_DP: 1800 default: 1801 type = DRM_MODE_ENCODER_TMDS; 1802 break; 1803 } 1804 1805 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1806 if (!nv_encoder) 1807 return -ENOMEM; 1808 nv_encoder->dcb = dcbe; 1809 nv_encoder->update = nv50_sor_update; 1810 1811 encoder = to_drm_encoder(nv_encoder); 1812 encoder->possible_crtcs = dcbe->heads; 1813 encoder->possible_clones = 0; 1814 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1815 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1816 drm_encoder_helper_add(encoder, &nv50_sor_help); 1817 1818 drm_connector_attach_encoder(connector, encoder); 1819 1820 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1821 nv50_outp_dump_caps(drm, nv_encoder); 1822 1823 if (dcbe->type == DCB_OUTPUT_DP) { 1824 struct nvkm_i2c_aux *aux = 1825 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1826 1827 mutex_init(&nv_encoder->dp.hpd_irq_lock); 1828 1829 if (aux) { 1830 if (disp->disp->object.oclass < GF110_DISP) { 1831 /* HW has no support for address-only 1832 * transactions, so we're required to 1833 * use custom I2C-over-AUX code. 1834 */ 1835 nv_encoder->i2c = &aux->i2c; 1836 } else { 1837 nv_encoder->i2c = &nv_connector->aux.ddc; 1838 } 1839 nv_encoder->aux = aux; 1840 } 1841 1842 if (nv_connector->type != DCB_CONNECTOR_eDP && 1843 nv50_has_mst(drm)) { 1844 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 1845 16, nv_connector->base.base.id, 1846 &nv_encoder->dp.mstm); 1847 if (ret) 1848 return ret; 1849 } 1850 } else { 1851 struct nvkm_i2c_bus *bus = 1852 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1853 if (bus) 1854 nv_encoder->i2c = &bus->i2c; 1855 } 1856 1857 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp); 1858 } 1859 1860 /****************************************************************************** 1861 * PIOR 1862 *****************************************************************************/ 1863 static int 1864 nv50_pior_atomic_check(struct drm_encoder *encoder, 1865 struct drm_crtc_state *crtc_state, 1866 struct drm_connector_state *conn_state) 1867 { 1868 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1869 if (ret) 1870 return ret; 1871 crtc_state->adjusted_mode.clock *= 2; 1872 return 0; 1873 } 1874 1875 static void 1876 nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1877 { 1878 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1879 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1880 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE); 1881 1882 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL); 1883 nv_encoder->crtc = NULL; 1884 nvif_outp_release(&nv_encoder->outp); 1885 } 1886 1887 static void 1888 nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1889 { 1890 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1891 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 1892 struct nv50_head_atom *asyh = 1893 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 1894 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1895 u32 ctrl = 0; 1896 1897 switch (nv_crtc->index) { 1898 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; 1899 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break; 1900 default: 1901 WARN_ON(1); 1902 break; 1903 } 1904 1905 switch (asyh->or.bpc) { 1906 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; 1907 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; 1908 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; 1909 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; 1910 } 1911 1912 switch (nv_encoder->dcb->type) { 1913 case DCB_OUTPUT_TMDS: 1914 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC); 1915 nvif_outp_acquire_tmds(&nv_encoder->outp, false); 1916 break; 1917 case DCB_OUTPUT_DP: 1918 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC); 1919 nvif_outp_acquire_dp(&nv_encoder->outp, false); 1920 break; 1921 default: 1922 BUG(); 1923 break; 1924 } 1925 1926 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh); 1927 nv_encoder->crtc = &nv_crtc->base; 1928 } 1929 1930 static const struct drm_encoder_helper_funcs 1931 nv50_pior_help = { 1932 .atomic_check = nv50_pior_atomic_check, 1933 .atomic_enable = nv50_pior_atomic_enable, 1934 .atomic_disable = nv50_pior_atomic_disable, 1935 }; 1936 1937 static void 1938 nv50_pior_destroy(struct drm_encoder *encoder) 1939 { 1940 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1941 1942 nvif_outp_dtor(&nv_encoder->outp); 1943 1944 drm_encoder_cleanup(encoder); 1945 kfree(encoder); 1946 } 1947 1948 static const struct drm_encoder_funcs 1949 nv50_pior_func = { 1950 .destroy = nv50_pior_destroy, 1951 }; 1952 1953 static int 1954 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1955 { 1956 struct drm_device *dev = connector->dev; 1957 struct nouveau_drm *drm = nouveau_drm(dev); 1958 struct nv50_disp *disp = nv50_disp(dev); 1959 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1960 struct nvkm_i2c_bus *bus = NULL; 1961 struct nvkm_i2c_aux *aux = NULL; 1962 struct i2c_adapter *ddc; 1963 struct nouveau_encoder *nv_encoder; 1964 struct drm_encoder *encoder; 1965 int type; 1966 1967 switch (dcbe->type) { 1968 case DCB_OUTPUT_TMDS: 1969 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1970 ddc = bus ? &bus->i2c : NULL; 1971 type = DRM_MODE_ENCODER_TMDS; 1972 break; 1973 case DCB_OUTPUT_DP: 1974 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1975 ddc = aux ? &aux->i2c : NULL; 1976 type = DRM_MODE_ENCODER_TMDS; 1977 break; 1978 default: 1979 return -ENODEV; 1980 } 1981 1982 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1983 if (!nv_encoder) 1984 return -ENOMEM; 1985 nv_encoder->dcb = dcbe; 1986 nv_encoder->i2c = ddc; 1987 nv_encoder->aux = aux; 1988 1989 encoder = to_drm_encoder(nv_encoder); 1990 encoder->possible_crtcs = dcbe->heads; 1991 encoder->possible_clones = 0; 1992 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1993 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1994 drm_encoder_helper_add(encoder, &nv50_pior_help); 1995 1996 drm_connector_attach_encoder(connector, encoder); 1997 1998 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1999 nv50_outp_dump_caps(drm, nv_encoder); 2000 2001 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp); 2002 } 2003 2004 /****************************************************************************** 2005 * Atomic 2006 *****************************************************************************/ 2007 2008 static void 2009 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 2010 { 2011 struct drm_dp_mst_topology_mgr *mgr; 2012 struct drm_dp_mst_topology_state *mst_state; 2013 struct nouveau_drm *drm = nouveau_drm(state->dev); 2014 struct nv50_disp *disp = nv50_disp(drm->dev); 2015 struct nv50_core *core = disp->core; 2016 struct nv50_mstm *mstm; 2017 int i; 2018 2019 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 2020 2021 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 2022 mstm = nv50_mstm(mgr); 2023 if (mstm->modified) 2024 nv50_mstm_prepare(state, mst_state, mstm); 2025 } 2026 2027 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 2028 core->func->update(core, interlock, true); 2029 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 2030 disp->core->chan.base.device)) 2031 NV_ERROR(drm, "core notifier timeout\n"); 2032 2033 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 2034 mstm = nv50_mstm(mgr); 2035 if (mstm->modified) 2036 nv50_mstm_cleanup(state, mst_state, mstm); 2037 } 2038 } 2039 2040 static void 2041 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 2042 { 2043 struct drm_plane_state *new_plane_state; 2044 struct drm_plane *plane; 2045 int i; 2046 2047 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2048 struct nv50_wndw *wndw = nv50_wndw(plane); 2049 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 2050 if (wndw->func->update) 2051 wndw->func->update(wndw, interlock); 2052 } 2053 } 2054 } 2055 2056 static void 2057 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 2058 { 2059 struct drm_device *dev = state->dev; 2060 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 2061 struct drm_crtc *crtc; 2062 struct drm_plane_state *new_plane_state; 2063 struct drm_plane *plane; 2064 struct nouveau_drm *drm = nouveau_drm(dev); 2065 struct nv50_disp *disp = nv50_disp(dev); 2066 struct nv50_atom *atom = nv50_atom(state); 2067 struct nv50_core *core = disp->core; 2068 struct nv50_outp_atom *outp, *outt; 2069 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 2070 int i; 2071 bool flushed = false; 2072 2073 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 2074 nv50_crc_atomic_stop_reporting(state); 2075 drm_atomic_helper_wait_for_fences(dev, state, false); 2076 drm_atomic_helper_wait_for_dependencies(state); 2077 drm_dp_mst_atomic_wait_for_dependencies(state); 2078 drm_atomic_helper_update_legacy_modeset_state(dev, state); 2079 drm_atomic_helper_calc_timestamping_constants(state); 2080 2081 if (atom->lock_core) 2082 mutex_lock(&disp->mutex); 2083 2084 /* Disable head(s). */ 2085 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2086 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2087 struct nv50_head *head = nv50_head(crtc); 2088 2089 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 2090 asyh->clr.mask, asyh->set.mask); 2091 2092 if (old_crtc_state->active && !new_crtc_state->active) { 2093 pm_runtime_put_noidle(dev->dev); 2094 drm_crtc_vblank_off(crtc); 2095 } 2096 2097 if (asyh->clr.mask) { 2098 nv50_head_flush_clr(head, asyh, atom->flush_disable); 2099 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2100 } 2101 } 2102 2103 /* Disable plane(s). */ 2104 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2105 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2106 struct nv50_wndw *wndw = nv50_wndw(plane); 2107 2108 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 2109 asyw->clr.mask, asyw->set.mask); 2110 if (!asyw->clr.mask) 2111 continue; 2112 2113 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 2114 } 2115 2116 /* Disable output path(s). */ 2117 list_for_each_entry(outp, &atom->outp, head) { 2118 const struct drm_encoder_helper_funcs *help; 2119 struct drm_encoder *encoder; 2120 2121 encoder = outp->encoder; 2122 help = encoder->helper_private; 2123 2124 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 2125 outp->clr.mask, outp->set.mask); 2126 2127 if (outp->clr.mask) { 2128 help->atomic_disable(encoder, state); 2129 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2130 if (outp->flush_disable) { 2131 nv50_disp_atomic_commit_wndw(state, interlock); 2132 nv50_disp_atomic_commit_core(state, interlock); 2133 memset(interlock, 0x00, sizeof(interlock)); 2134 2135 flushed = true; 2136 } 2137 } 2138 } 2139 2140 /* Flush disable. */ 2141 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2142 if (atom->flush_disable) { 2143 nv50_disp_atomic_commit_wndw(state, interlock); 2144 nv50_disp_atomic_commit_core(state, interlock); 2145 memset(interlock, 0x00, sizeof(interlock)); 2146 2147 flushed = true; 2148 } 2149 } 2150 2151 if (flushed) 2152 nv50_crc_atomic_release_notifier_contexts(state); 2153 nv50_crc_atomic_init_notifier_contexts(state); 2154 2155 /* Update output path(s). */ 2156 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2157 const struct drm_encoder_helper_funcs *help; 2158 struct drm_encoder *encoder; 2159 2160 encoder = outp->encoder; 2161 help = encoder->helper_private; 2162 2163 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 2164 outp->set.mask, outp->clr.mask); 2165 2166 if (outp->set.mask) { 2167 help->atomic_enable(encoder, state); 2168 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2169 } 2170 2171 list_del(&outp->head); 2172 kfree(outp); 2173 } 2174 2175 /* Update head(s). */ 2176 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2177 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2178 struct nv50_head *head = nv50_head(crtc); 2179 2180 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2181 asyh->set.mask, asyh->clr.mask); 2182 2183 if (asyh->set.mask) { 2184 nv50_head_flush_set(head, asyh); 2185 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2186 } 2187 2188 if (new_crtc_state->active) { 2189 if (!old_crtc_state->active) { 2190 drm_crtc_vblank_on(crtc); 2191 pm_runtime_get_noresume(dev->dev); 2192 } 2193 if (new_crtc_state->event) 2194 drm_crtc_vblank_get(crtc); 2195 } 2196 } 2197 2198 /* Update window->head assignment. 2199 * 2200 * This has to happen in an update that's not interlocked with 2201 * any window channels to avoid hitting HW error checks. 2202 * 2203 *TODO: Proper handling of window ownership (Turing apparently 2204 * supports non-fixed mappings). 2205 */ 2206 if (core->assign_windows) { 2207 core->func->wndw.owner(core); 2208 nv50_disp_atomic_commit_core(state, interlock); 2209 core->assign_windows = false; 2210 interlock[NV50_DISP_INTERLOCK_CORE] = 0; 2211 } 2212 2213 /* Finish updating head(s)... 2214 * 2215 * NVD is rather picky about both where window assignments can change, 2216 * *and* about certain core and window channel states matching. 2217 * 2218 * The EFI GOP driver on newer GPUs configures window channels with a 2219 * different output format to what we do, and the core channel update 2220 * in the assign_windows case above would result in a state mismatch. 2221 * 2222 * Delay some of the head update until after that point to workaround 2223 * the issue. This only affects the initial modeset. 2224 * 2225 * TODO: handle this better when adding flexible window mapping 2226 */ 2227 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2228 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2229 struct nv50_head *head = nv50_head(crtc); 2230 2231 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2232 asyh->set.mask, asyh->clr.mask); 2233 2234 if (asyh->set.mask) { 2235 nv50_head_flush_set_wndw(head, asyh); 2236 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2237 } 2238 } 2239 2240 /* Update plane(s). */ 2241 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2242 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2243 struct nv50_wndw *wndw = nv50_wndw(plane); 2244 2245 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 2246 asyw->set.mask, asyw->clr.mask); 2247 if ( !asyw->set.mask && 2248 (!asyw->clr.mask || atom->flush_disable)) 2249 continue; 2250 2251 nv50_wndw_flush_set(wndw, interlock, asyw); 2252 } 2253 2254 /* Flush update. */ 2255 nv50_disp_atomic_commit_wndw(state, interlock); 2256 2257 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2258 if (interlock[NV50_DISP_INTERLOCK_BASE] || 2259 interlock[NV50_DISP_INTERLOCK_OVLY] || 2260 interlock[NV50_DISP_INTERLOCK_WNDW] || 2261 !atom->state.legacy_cursor_update) 2262 nv50_disp_atomic_commit_core(state, interlock); 2263 else 2264 disp->core->func->update(disp->core, interlock, false); 2265 } 2266 2267 if (atom->lock_core) 2268 mutex_unlock(&disp->mutex); 2269 2270 /* Wait for HW to signal completion. */ 2271 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2272 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2273 struct nv50_wndw *wndw = nv50_wndw(plane); 2274 int ret = nv50_wndw_wait_armed(wndw, asyw); 2275 if (ret) 2276 NV_ERROR(drm, "%s: timeout\n", plane->name); 2277 } 2278 2279 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2280 if (new_crtc_state->event) { 2281 unsigned long flags; 2282 /* Get correct count/ts if racing with vblank irq */ 2283 if (new_crtc_state->active) 2284 drm_crtc_accurate_vblank_count(crtc); 2285 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2286 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 2287 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2288 2289 new_crtc_state->event = NULL; 2290 if (new_crtc_state->active) 2291 drm_crtc_vblank_put(crtc); 2292 } 2293 } 2294 2295 nv50_crc_atomic_start_reporting(state); 2296 if (!flushed) 2297 nv50_crc_atomic_release_notifier_contexts(state); 2298 2299 drm_atomic_helper_commit_hw_done(state); 2300 drm_atomic_helper_cleanup_planes(dev, state); 2301 drm_atomic_helper_commit_cleanup_done(state); 2302 drm_atomic_state_put(state); 2303 2304 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ 2305 pm_runtime_mark_last_busy(dev->dev); 2306 pm_runtime_put_autosuspend(dev->dev); 2307 } 2308 2309 static void 2310 nv50_disp_atomic_commit_work(struct work_struct *work) 2311 { 2312 struct drm_atomic_state *state = 2313 container_of(work, typeof(*state), commit_work); 2314 nv50_disp_atomic_commit_tail(state); 2315 } 2316 2317 static int 2318 nv50_disp_atomic_commit(struct drm_device *dev, 2319 struct drm_atomic_state *state, bool nonblock) 2320 { 2321 struct drm_plane_state *new_plane_state; 2322 struct drm_plane *plane; 2323 int ret, i; 2324 2325 ret = pm_runtime_get_sync(dev->dev); 2326 if (ret < 0 && ret != -EACCES) { 2327 pm_runtime_put_autosuspend(dev->dev); 2328 return ret; 2329 } 2330 2331 ret = drm_atomic_helper_setup_commit(state, nonblock); 2332 if (ret) 2333 goto done; 2334 2335 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2336 2337 ret = drm_atomic_helper_prepare_planes(dev, state); 2338 if (ret) 2339 goto done; 2340 2341 if (!nonblock) { 2342 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2343 if (ret) 2344 goto err_cleanup; 2345 } 2346 2347 ret = drm_atomic_helper_swap_state(state, true); 2348 if (ret) 2349 goto err_cleanup; 2350 2351 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2352 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2353 struct nv50_wndw *wndw = nv50_wndw(plane); 2354 2355 if (asyw->set.image) 2356 nv50_wndw_ntfy_enable(wndw, asyw); 2357 } 2358 2359 drm_atomic_state_get(state); 2360 2361 /* 2362 * Grab another RPM ref for the commit tail, which will release the 2363 * ref when it's finished 2364 */ 2365 pm_runtime_get_noresume(dev->dev); 2366 2367 if (nonblock) 2368 queue_work(system_unbound_wq, &state->commit_work); 2369 else 2370 nv50_disp_atomic_commit_tail(state); 2371 2372 err_cleanup: 2373 if (ret) 2374 drm_atomic_helper_cleanup_planes(dev, state); 2375 done: 2376 pm_runtime_put_autosuspend(dev->dev); 2377 return ret; 2378 } 2379 2380 static struct nv50_outp_atom * 2381 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2382 { 2383 struct nv50_outp_atom *outp; 2384 2385 list_for_each_entry(outp, &atom->outp, head) { 2386 if (outp->encoder == encoder) 2387 return outp; 2388 } 2389 2390 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2391 if (!outp) 2392 return ERR_PTR(-ENOMEM); 2393 2394 list_add(&outp->head, &atom->outp); 2395 outp->encoder = encoder; 2396 return outp; 2397 } 2398 2399 static int 2400 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2401 struct drm_connector_state *old_connector_state) 2402 { 2403 struct drm_encoder *encoder = old_connector_state->best_encoder; 2404 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2405 struct drm_crtc *crtc; 2406 struct nv50_outp_atom *outp; 2407 2408 if (!(crtc = old_connector_state->crtc)) 2409 return 0; 2410 2411 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2412 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2413 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2414 outp = nv50_disp_outp_atomic_add(atom, encoder); 2415 if (IS_ERR(outp)) 2416 return PTR_ERR(outp); 2417 2418 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2419 outp->flush_disable = true; 2420 atom->flush_disable = true; 2421 } 2422 outp->clr.ctrl = true; 2423 atom->lock_core = true; 2424 } 2425 2426 return 0; 2427 } 2428 2429 static int 2430 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2431 struct drm_connector_state *connector_state) 2432 { 2433 struct drm_encoder *encoder = connector_state->best_encoder; 2434 struct drm_crtc_state *new_crtc_state; 2435 struct drm_crtc *crtc; 2436 struct nv50_outp_atom *outp; 2437 2438 if (!(crtc = connector_state->crtc)) 2439 return 0; 2440 2441 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2442 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2443 outp = nv50_disp_outp_atomic_add(atom, encoder); 2444 if (IS_ERR(outp)) 2445 return PTR_ERR(outp); 2446 2447 outp->set.ctrl = true; 2448 atom->lock_core = true; 2449 } 2450 2451 return 0; 2452 } 2453 2454 static int 2455 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2456 { 2457 struct nv50_atom *atom = nv50_atom(state); 2458 struct nv50_core *core = nv50_disp(dev)->core; 2459 struct drm_connector_state *old_connector_state, *new_connector_state; 2460 struct drm_connector *connector; 2461 struct drm_crtc_state *new_crtc_state; 2462 struct drm_crtc *crtc; 2463 struct nv50_head *head; 2464 struct nv50_head_atom *asyh; 2465 int ret, i; 2466 2467 if (core->assign_windows && core->func->head->static_wndw_map) { 2468 drm_for_each_crtc(crtc, dev) { 2469 new_crtc_state = drm_atomic_get_crtc_state(state, 2470 crtc); 2471 if (IS_ERR(new_crtc_state)) 2472 return PTR_ERR(new_crtc_state); 2473 2474 head = nv50_head(crtc); 2475 asyh = nv50_head_atom(new_crtc_state); 2476 core->func->head->static_wndw_map(head, asyh); 2477 } 2478 } 2479 2480 /* We need to handle colour management on a per-plane basis. */ 2481 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2482 if (new_crtc_state->color_mgmt_changed) { 2483 ret = drm_atomic_add_affected_planes(state, crtc); 2484 if (ret) 2485 return ret; 2486 } 2487 } 2488 2489 ret = drm_atomic_helper_check(dev, state); 2490 if (ret) 2491 return ret; 2492 2493 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2494 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2495 if (ret) 2496 return ret; 2497 2498 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2499 if (ret) 2500 return ret; 2501 } 2502 2503 ret = drm_dp_mst_atomic_check(state); 2504 if (ret) 2505 return ret; 2506 2507 nv50_crc_atomic_check_outp(atom); 2508 2509 return 0; 2510 } 2511 2512 static void 2513 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2514 { 2515 struct nv50_atom *atom = nv50_atom(state); 2516 struct nv50_outp_atom *outp, *outt; 2517 2518 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2519 list_del(&outp->head); 2520 kfree(outp); 2521 } 2522 2523 drm_atomic_state_default_clear(state); 2524 } 2525 2526 static void 2527 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2528 { 2529 struct nv50_atom *atom = nv50_atom(state); 2530 drm_atomic_state_default_release(&atom->state); 2531 kfree(atom); 2532 } 2533 2534 static struct drm_atomic_state * 2535 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2536 { 2537 struct nv50_atom *atom; 2538 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2539 drm_atomic_state_init(dev, &atom->state) < 0) { 2540 kfree(atom); 2541 return NULL; 2542 } 2543 INIT_LIST_HEAD(&atom->outp); 2544 return &atom->state; 2545 } 2546 2547 static const struct drm_mode_config_funcs 2548 nv50_disp_func = { 2549 .fb_create = nouveau_user_framebuffer_create, 2550 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2551 .atomic_check = nv50_disp_atomic_check, 2552 .atomic_commit = nv50_disp_atomic_commit, 2553 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2554 .atomic_state_clear = nv50_disp_atomic_state_clear, 2555 .atomic_state_free = nv50_disp_atomic_state_free, 2556 }; 2557 2558 static const struct drm_mode_config_helper_funcs 2559 nv50_disp_helper_func = { 2560 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 2561 }; 2562 2563 /****************************************************************************** 2564 * Init 2565 *****************************************************************************/ 2566 2567 static void 2568 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend) 2569 { 2570 struct nouveau_drm *drm = nouveau_drm(dev); 2571 struct drm_encoder *encoder; 2572 2573 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2574 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 2575 nv50_mstm_fini(nouveau_encoder(encoder)); 2576 } 2577 2578 if (!runtime) 2579 cancel_work_sync(&drm->hpd_work); 2580 } 2581 2582 static int 2583 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2584 { 2585 struct nv50_core *core = nv50_disp(dev)->core; 2586 struct drm_encoder *encoder; 2587 2588 if (resume || runtime) 2589 core->func->init(core); 2590 2591 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2592 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2593 struct nouveau_encoder *nv_encoder = 2594 nouveau_encoder(encoder); 2595 nv50_mstm_init(nv_encoder, runtime); 2596 } 2597 } 2598 2599 return 0; 2600 } 2601 2602 static void 2603 nv50_display_destroy(struct drm_device *dev) 2604 { 2605 struct nv50_disp *disp = nv50_disp(dev); 2606 2607 nv50_audio_component_fini(nouveau_drm(dev)); 2608 2609 nvif_object_unmap(&disp->caps); 2610 nvif_object_dtor(&disp->caps); 2611 nv50_core_del(&disp->core); 2612 2613 nouveau_bo_unmap(disp->sync); 2614 if (disp->sync) 2615 nouveau_bo_unpin(disp->sync); 2616 nouveau_bo_ref(NULL, &disp->sync); 2617 2618 nouveau_display(dev)->priv = NULL; 2619 kfree(disp); 2620 } 2621 2622 int 2623 nv50_display_create(struct drm_device *dev) 2624 { 2625 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2626 struct nouveau_drm *drm = nouveau_drm(dev); 2627 struct dcb_table *dcb = &drm->vbios.dcb; 2628 struct drm_connector *connector, *tmp; 2629 struct nv50_disp *disp; 2630 struct dcb_output *dcbe; 2631 int crtcs, ret, i; 2632 bool has_mst = nv50_has_mst(drm); 2633 2634 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2635 if (!disp) 2636 return -ENOMEM; 2637 2638 mutex_init(&disp->mutex); 2639 2640 nouveau_display(dev)->priv = disp; 2641 nouveau_display(dev)->dtor = nv50_display_destroy; 2642 nouveau_display(dev)->init = nv50_display_init; 2643 nouveau_display(dev)->fini = nv50_display_fini; 2644 disp->disp = &nouveau_display(dev)->disp; 2645 dev->mode_config.funcs = &nv50_disp_func; 2646 dev->mode_config.helper_private = &nv50_disp_helper_func; 2647 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2648 dev->mode_config.normalize_zpos = true; 2649 2650 /* small shared memory area we use for notifiers and semaphores */ 2651 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, 2652 NOUVEAU_GEM_DOMAIN_VRAM, 2653 0, 0x0000, NULL, NULL, &disp->sync); 2654 if (!ret) { 2655 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true); 2656 if (!ret) { 2657 ret = nouveau_bo_map(disp->sync); 2658 if (ret) 2659 nouveau_bo_unpin(disp->sync); 2660 } 2661 if (ret) 2662 nouveau_bo_ref(NULL, &disp->sync); 2663 } 2664 2665 if (ret) 2666 goto out; 2667 2668 /* allocate master evo channel */ 2669 ret = nv50_core_new(drm, &disp->core); 2670 if (ret) 2671 goto out; 2672 2673 disp->core->func->init(disp->core); 2674 if (disp->core->func->caps_init) { 2675 ret = disp->core->func->caps_init(drm, disp); 2676 if (ret) 2677 goto out; 2678 } 2679 2680 /* Assign the correct format modifiers */ 2681 if (disp->disp->object.oclass >= TU102_DISP) 2682 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; 2683 else 2684 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) 2685 nouveau_display(dev)->format_modifiers = disp90xx_modifiers; 2686 else 2687 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; 2688 2689 /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later 2690 * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The 2691 * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to 2692 * small page allocations in prepare_fb(). When this is implemented, we should also force 2693 * large pages (128K) for ovly fbs in order to fix Kepler ovlys. 2694 * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using 2695 * large pages. 2696 */ 2697 if (disp->disp->object.oclass >= GM107_DISP) { 2698 dev->mode_config.cursor_width = 256; 2699 dev->mode_config.cursor_height = 256; 2700 } else if (disp->disp->object.oclass >= GK104_DISP) { 2701 dev->mode_config.cursor_width = 128; 2702 dev->mode_config.cursor_height = 128; 2703 } else { 2704 dev->mode_config.cursor_width = 64; 2705 dev->mode_config.cursor_height = 64; 2706 } 2707 2708 /* create crtc objects to represent the hw heads */ 2709 if (disp->disp->object.oclass >= GV100_DISP) 2710 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2711 else 2712 if (disp->disp->object.oclass >= GF110_DISP) 2713 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2714 else 2715 crtcs = 0x3; 2716 2717 for (i = 0; i < fls(crtcs); i++) { 2718 struct nv50_head *head; 2719 2720 if (!(crtcs & (1 << i))) 2721 continue; 2722 2723 head = nv50_head_create(dev, i); 2724 if (IS_ERR(head)) { 2725 ret = PTR_ERR(head); 2726 goto out; 2727 } 2728 2729 if (has_mst) { 2730 head->msto = nv50_msto_new(dev, head, i); 2731 if (IS_ERR(head->msto)) { 2732 ret = PTR_ERR(head->msto); 2733 head->msto = NULL; 2734 goto out; 2735 } 2736 2737 /* 2738 * FIXME: This is a hack to workaround the following 2739 * issues: 2740 * 2741 * https://gitlab.gnome.org/GNOME/mutter/issues/759 2742 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277 2743 * 2744 * Once these issues are closed, this should be 2745 * removed 2746 */ 2747 head->msto->encoder.possible_crtcs = crtcs; 2748 } 2749 } 2750 2751 /* create encoder/connector objects based on VBIOS DCB table */ 2752 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2753 connector = nouveau_connector_create(dev, dcbe); 2754 if (IS_ERR(connector)) 2755 continue; 2756 2757 if (dcbe->location == DCB_LOC_ON_CHIP) { 2758 switch (dcbe->type) { 2759 case DCB_OUTPUT_TMDS: 2760 case DCB_OUTPUT_LVDS: 2761 case DCB_OUTPUT_DP: 2762 ret = nv50_sor_create(connector, dcbe); 2763 break; 2764 case DCB_OUTPUT_ANALOG: 2765 ret = nv50_dac_create(connector, dcbe); 2766 break; 2767 default: 2768 ret = -ENODEV; 2769 break; 2770 } 2771 } else { 2772 ret = nv50_pior_create(connector, dcbe); 2773 } 2774 2775 if (ret) { 2776 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2777 dcbe->location, dcbe->type, 2778 ffs(dcbe->or) - 1, ret); 2779 ret = 0; 2780 } 2781 } 2782 2783 /* cull any connectors we created that don't have an encoder */ 2784 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2785 if (connector->possible_encoders) 2786 continue; 2787 2788 NV_WARN(drm, "%s has no encoders, removing\n", 2789 connector->name); 2790 connector->funcs->destroy(connector); 2791 } 2792 2793 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2794 dev->vblank_disable_immediate = true; 2795 2796 nv50_audio_component_init(drm); 2797 2798 out: 2799 if (ret) 2800 nv50_display_destroy(dev); 2801 return ret; 2802 } 2803 2804 /****************************************************************************** 2805 * Format modifiers 2806 *****************************************************************************/ 2807 2808 /**************************************************************** 2809 * Log2(block height) ----------------------------+ * 2810 * Page Kind ----------------------------------+ | * 2811 * Gob Height/Page Kind Generation ------+ | | * 2812 * Sector layout -------+ | | | * 2813 * Compression ------+ | | | | */ 2814 const u64 disp50xx_modifiers[] = { /* | | | | | */ 2815 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0), 2816 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1), 2817 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2), 2818 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3), 2819 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4), 2820 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5), 2821 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0), 2822 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1), 2823 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2), 2824 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3), 2825 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4), 2826 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5), 2827 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0), 2828 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1), 2829 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2), 2830 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3), 2831 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4), 2832 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5), 2833 DRM_FORMAT_MOD_LINEAR, 2834 DRM_FORMAT_MOD_INVALID 2835 }; 2836 2837 /**************************************************************** 2838 * Log2(block height) ----------------------------+ * 2839 * Page Kind ----------------------------------+ | * 2840 * Gob Height/Page Kind Generation ------+ | | * 2841 * Sector layout -------+ | | | * 2842 * Compression ------+ | | | | */ 2843 const u64 disp90xx_modifiers[] = { /* | | | | | */ 2844 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0), 2845 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1), 2846 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2), 2847 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3), 2848 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4), 2849 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5), 2850 DRM_FORMAT_MOD_LINEAR, 2851 DRM_FORMAT_MOD_INVALID 2852 }; 2853