11a646342SBen Skeggs /* 21a646342SBen Skeggs * Copyright (C) 2009 Francisco Jerez. 31a646342SBen Skeggs * All Rights Reserved. 41a646342SBen Skeggs * 51a646342SBen Skeggs * Permission is hereby granted, free of charge, to any person obtaining 61a646342SBen Skeggs * a copy of this software and associated documentation files (the 71a646342SBen Skeggs * "Software"), to deal in the Software without restriction, including 81a646342SBen Skeggs * without limitation the rights to use, copy, modify, merge, publish, 91a646342SBen Skeggs * distribute, sublicense, and/or sell copies of the Software, and to 101a646342SBen Skeggs * permit persons to whom the Software is furnished to do so, subject to 111a646342SBen Skeggs * the following conditions: 121a646342SBen Skeggs * 131a646342SBen Skeggs * The above copyright notice and this permission notice (including the 141a646342SBen Skeggs * next paragraph) shall be included in all copies or substantial 151a646342SBen Skeggs * portions of the Software. 161a646342SBen Skeggs * 171a646342SBen Skeggs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 181a646342SBen Skeggs * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 191a646342SBen Skeggs * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 201a646342SBen Skeggs * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 211a646342SBen Skeggs * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 221a646342SBen Skeggs * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 231a646342SBen Skeggs * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 241a646342SBen Skeggs * 251a646342SBen Skeggs */ 261a646342SBen Skeggs 271a646342SBen Skeggs #include <drm/drmP.h> 281a646342SBen Skeggs #include <drm/drm_crtc_helper.h> 291a646342SBen Skeggs #include "nouveau_drm.h" 301a646342SBen Skeggs #include "nouveau_reg.h" 311a646342SBen Skeggs #include "nouveau_encoder.h" 321a646342SBen Skeggs #include "nouveau_connector.h" 331a646342SBen Skeggs #include "nouveau_crtc.h" 341a646342SBen Skeggs #include "hw.h" 351a646342SBen Skeggs #include "tvnv17.h" 361a646342SBen Skeggs 371a646342SBen Skeggs #include <core/device.h> 381a646342SBen Skeggs 391a646342SBen Skeggs #include <subdev/bios/gpio.h> 401a646342SBen Skeggs #include <subdev/gpio.h> 411a646342SBen Skeggs 421a646342SBen Skeggs MODULE_PARM_DESC(tv_norm, "Default TV norm.\n" 431a646342SBen Skeggs "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n" 441a646342SBen Skeggs "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n" 451a646342SBen Skeggs "\t\tDefault: PAL\n" 461a646342SBen Skeggs "\t\t*NOTE* Ignored for cards with external TV encoders."); 471a646342SBen Skeggs static char *nouveau_tv_norm; 481a646342SBen Skeggs module_param_named(tv_norm, nouveau_tv_norm, charp, 0400); 491a646342SBen Skeggs 501a646342SBen Skeggs static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) 511a646342SBen Skeggs { 521a646342SBen Skeggs struct drm_device *dev = encoder->dev; 531a646342SBen Skeggs struct nouveau_drm *drm = nouveau_drm(dev); 541a646342SBen Skeggs struct nouveau_gpio *gpio = nouveau_gpio(drm->device); 551a646342SBen Skeggs uint32_t testval, regoffset = nv04_dac_output_offset(encoder); 561a646342SBen Skeggs uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, 571a646342SBen Skeggs fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c; 581a646342SBen Skeggs uint32_t sample = 0; 591a646342SBen Skeggs int head; 601a646342SBen Skeggs 611a646342SBen Skeggs #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) 621a646342SBen Skeggs testval = RGB_TEST_DATA(0x82, 0xeb, 0x82); 631a646342SBen Skeggs if (drm->vbios.tvdactestval) 641a646342SBen Skeggs testval = drm->vbios.tvdactestval; 651a646342SBen Skeggs 661a646342SBen Skeggs dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); 671a646342SBen Skeggs head = (dacclk & 0x100) >> 8; 681a646342SBen Skeggs 691a646342SBen Skeggs /* Save the previous state. */ 701a646342SBen Skeggs gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff); 711a646342SBen Skeggs gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff); 721a646342SBen Skeggs fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL); 731a646342SBen Skeggs fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START); 741a646342SBen Skeggs fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END); 751a646342SBen Skeggs fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); 761a646342SBen Skeggs test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); 771a646342SBen Skeggs ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c); 781a646342SBen Skeggs ctv_14 = NVReadRAMDAC(dev, head, 0x680c14); 791a646342SBen Skeggs ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c); 801a646342SBen Skeggs 811a646342SBen Skeggs /* Prepare the DAC for load detection. */ 821a646342SBen Skeggs gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true); 831a646342SBen Skeggs gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true); 841a646342SBen Skeggs 851a646342SBen Skeggs NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343); 861a646342SBen Skeggs NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047); 871a646342SBen Skeggs NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183); 881a646342SBen Skeggs NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, 891a646342SBen Skeggs NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | 901a646342SBen Skeggs NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 | 911a646342SBen Skeggs NV_PRAMDAC_FP_TG_CONTROL_READ_PROG | 921a646342SBen Skeggs NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | 931a646342SBen Skeggs NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS); 941a646342SBen Skeggs 951a646342SBen Skeggs NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0); 961a646342SBen Skeggs 971a646342SBen Skeggs NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, 981a646342SBen Skeggs (dacclk & ~0xff) | 0x22); 991a646342SBen Skeggs msleep(1); 1001a646342SBen Skeggs NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, 1011a646342SBen Skeggs (dacclk & ~0xff) | 0x21); 1021a646342SBen Skeggs 1031a646342SBen Skeggs NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20); 1041a646342SBen Skeggs NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16); 1051a646342SBen Skeggs 1061a646342SBen Skeggs /* Sample pin 0x4 (usually S-video luma). */ 1071a646342SBen Skeggs NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff); 1081a646342SBen Skeggs msleep(20); 1091a646342SBen Skeggs sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) 1101a646342SBen Skeggs & 0x4 << 28; 1111a646342SBen Skeggs 1121a646342SBen Skeggs /* Sample the remaining pins. */ 1131a646342SBen Skeggs NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff); 1141a646342SBen Skeggs msleep(20); 1151a646342SBen Skeggs sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) 1161a646342SBen Skeggs & 0xa << 28; 1171a646342SBen Skeggs 1181a646342SBen Skeggs /* Restore the previous state. */ 1191a646342SBen Skeggs NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c); 1201a646342SBen Skeggs NVWriteRAMDAC(dev, head, 0x680c14, ctv_14); 1211a646342SBen Skeggs NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c); 1221a646342SBen Skeggs NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk); 1231a646342SBen Skeggs NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl); 1241a646342SBen Skeggs NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control); 1251a646342SBen Skeggs NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end); 1261a646342SBen Skeggs NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start); 1271a646342SBen Skeggs NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal); 1281a646342SBen Skeggs gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1); 1291a646342SBen Skeggs gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0); 1301a646342SBen Skeggs 1311a646342SBen Skeggs return sample; 1321a646342SBen Skeggs } 1331a646342SBen Skeggs 1341a646342SBen Skeggs static bool 1351a646342SBen Skeggs get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) 1361a646342SBen Skeggs { 1371a646342SBen Skeggs struct nouveau_drm *drm = nouveau_drm(dev); 1381a646342SBen Skeggs struct nouveau_object *device = drm->device; 1391a646342SBen Skeggs 1401a646342SBen Skeggs /* Zotac FX5200 */ 1411a646342SBen Skeggs if (nv_device_match(device, 0x0322, 0x19da, 0x1035) || 1421a646342SBen Skeggs nv_device_match(device, 0x0322, 0x19da, 0x2035)) { 1431a646342SBen Skeggs *pin_mask = 0xc; 1441a646342SBen Skeggs return false; 1451a646342SBen Skeggs } 1461a646342SBen Skeggs 1471a646342SBen Skeggs /* MSI nForce2 IGP */ 1481a646342SBen Skeggs if (nv_device_match(device, 0x01f0, 0x1462, 0x5710)) { 1491a646342SBen Skeggs *pin_mask = 0xc; 1501a646342SBen Skeggs return false; 1511a646342SBen Skeggs } 1521a646342SBen Skeggs 1531a646342SBen Skeggs return true; 1541a646342SBen Skeggs } 1551a646342SBen Skeggs 1561a646342SBen Skeggs static enum drm_connector_status 1571a646342SBen Skeggs nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1581a646342SBen Skeggs { 1591a646342SBen Skeggs struct drm_device *dev = encoder->dev; 1601a646342SBen Skeggs struct nouveau_drm *drm = nouveau_drm(dev); 1611a646342SBen Skeggs struct drm_mode_config *conf = &dev->mode_config; 1621a646342SBen Skeggs struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 1631a646342SBen Skeggs struct dcb_output *dcb = tv_enc->base.dcb; 1641a646342SBen Skeggs bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask); 1651a646342SBen Skeggs 1661a646342SBen Skeggs if (nv04_dac_in_use(encoder)) 1671a646342SBen Skeggs return connector_status_disconnected; 1681a646342SBen Skeggs 1691a646342SBen Skeggs if (reliable) { 1701a646342SBen Skeggs if (nv_device(drm->device)->chipset == 0x42 || 1711a646342SBen Skeggs nv_device(drm->device)->chipset == 0x43) 1721a646342SBen Skeggs tv_enc->pin_mask = 1731a646342SBen Skeggs nv42_tv_sample_load(encoder) >> 28 & 0xe; 1741a646342SBen Skeggs else 1751a646342SBen Skeggs tv_enc->pin_mask = 1761a646342SBen Skeggs nv17_dac_sample_load(encoder) >> 28 & 0xe; 1771a646342SBen Skeggs } 1781a646342SBen Skeggs 1791a646342SBen Skeggs switch (tv_enc->pin_mask) { 1801a646342SBen Skeggs case 0x2: 1811a646342SBen Skeggs case 0x4: 1821a646342SBen Skeggs tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite; 1831a646342SBen Skeggs break; 1841a646342SBen Skeggs case 0xc: 1851a646342SBen Skeggs tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO; 1861a646342SBen Skeggs break; 1871a646342SBen Skeggs case 0xe: 1881a646342SBen Skeggs if (dcb->tvconf.has_component_output) 1891a646342SBen Skeggs tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component; 1901a646342SBen Skeggs else 1911a646342SBen Skeggs tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART; 1921a646342SBen Skeggs break; 1931a646342SBen Skeggs default: 1941a646342SBen Skeggs tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 1951a646342SBen Skeggs break; 1961a646342SBen Skeggs } 1971a646342SBen Skeggs 1981a646342SBen Skeggs drm_object_property_set_value(&connector->base, 1991a646342SBen Skeggs conf->tv_subconnector_property, 2001a646342SBen Skeggs tv_enc->subconnector); 2011a646342SBen Skeggs 2021a646342SBen Skeggs if (!reliable) { 2031a646342SBen Skeggs return connector_status_unknown; 2041a646342SBen Skeggs } else if (tv_enc->subconnector) { 2051a646342SBen Skeggs NV_INFO(drm, "Load detected on output %c\n", 2061a646342SBen Skeggs '@' + ffs(dcb->or)); 2071a646342SBen Skeggs return connector_status_connected; 2081a646342SBen Skeggs } else { 2091a646342SBen Skeggs return connector_status_disconnected; 2101a646342SBen Skeggs } 2111a646342SBen Skeggs } 2121a646342SBen Skeggs 2131a646342SBen Skeggs static int nv17_tv_get_ld_modes(struct drm_encoder *encoder, 2141a646342SBen Skeggs struct drm_connector *connector) 2151a646342SBen Skeggs { 2161a646342SBen Skeggs struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 2171a646342SBen Skeggs const struct drm_display_mode *tv_mode; 2181a646342SBen Skeggs int n = 0; 2191a646342SBen Skeggs 2201a646342SBen Skeggs for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) { 2211a646342SBen Skeggs struct drm_display_mode *mode; 2221a646342SBen Skeggs 2231a646342SBen Skeggs mode = drm_mode_duplicate(encoder->dev, tv_mode); 2241a646342SBen Skeggs 2251a646342SBen Skeggs mode->clock = tv_norm->tv_enc_mode.vrefresh * 2261a646342SBen Skeggs mode->htotal / 1000 * 2271a646342SBen Skeggs mode->vtotal / 1000; 2281a646342SBen Skeggs 2291a646342SBen Skeggs if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 2301a646342SBen Skeggs mode->clock *= 2; 2311a646342SBen Skeggs 2321a646342SBen Skeggs if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay && 2331a646342SBen Skeggs mode->vdisplay == tv_norm->tv_enc_mode.vdisplay) 2341a646342SBen Skeggs mode->type |= DRM_MODE_TYPE_PREFERRED; 2351a646342SBen Skeggs 2361a646342SBen Skeggs drm_mode_probed_add(connector, mode); 2371a646342SBen Skeggs n++; 2381a646342SBen Skeggs } 2391a646342SBen Skeggs 2401a646342SBen Skeggs return n; 2411a646342SBen Skeggs } 2421a646342SBen Skeggs 2431a646342SBen Skeggs static int nv17_tv_get_hd_modes(struct drm_encoder *encoder, 2441a646342SBen Skeggs struct drm_connector *connector) 2451a646342SBen Skeggs { 2461a646342SBen Skeggs struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 2471a646342SBen Skeggs struct drm_display_mode *output_mode = &tv_norm->ctv_enc_mode.mode; 2481a646342SBen Skeggs struct drm_display_mode *mode; 2491a646342SBen Skeggs const struct { 2501a646342SBen Skeggs int hdisplay; 2511a646342SBen Skeggs int vdisplay; 2521a646342SBen Skeggs } modes[] = { 2531a646342SBen Skeggs { 640, 400 }, 2541a646342SBen Skeggs { 640, 480 }, 2551a646342SBen Skeggs { 720, 480 }, 2561a646342SBen Skeggs { 720, 576 }, 2571a646342SBen Skeggs { 800, 600 }, 2581a646342SBen Skeggs { 1024, 768 }, 2591a646342SBen Skeggs { 1280, 720 }, 2601a646342SBen Skeggs { 1280, 1024 }, 2611a646342SBen Skeggs { 1920, 1080 } 2621a646342SBen Skeggs }; 2631a646342SBen Skeggs int i, n = 0; 2641a646342SBen Skeggs 2651a646342SBen Skeggs for (i = 0; i < ARRAY_SIZE(modes); i++) { 2661a646342SBen Skeggs if (modes[i].hdisplay > output_mode->hdisplay || 2671a646342SBen Skeggs modes[i].vdisplay > output_mode->vdisplay) 2681a646342SBen Skeggs continue; 2691a646342SBen Skeggs 2701a646342SBen Skeggs if (modes[i].hdisplay == output_mode->hdisplay && 2711a646342SBen Skeggs modes[i].vdisplay == output_mode->vdisplay) { 2721a646342SBen Skeggs mode = drm_mode_duplicate(encoder->dev, output_mode); 2731a646342SBen Skeggs mode->type |= DRM_MODE_TYPE_PREFERRED; 2741a646342SBen Skeggs 2751a646342SBen Skeggs } else { 2761a646342SBen Skeggs mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay, 2771a646342SBen Skeggs modes[i].vdisplay, 60, false, 2781a646342SBen Skeggs (output_mode->flags & 2791a646342SBen Skeggs DRM_MODE_FLAG_INTERLACE), false); 2801a646342SBen Skeggs } 2811a646342SBen Skeggs 2821a646342SBen Skeggs /* CVT modes are sometimes unsuitable... */ 2831a646342SBen Skeggs if (output_mode->hdisplay <= 720 2841a646342SBen Skeggs || output_mode->hdisplay >= 1920) { 2851a646342SBen Skeggs mode->htotal = output_mode->htotal; 2861a646342SBen Skeggs mode->hsync_start = (mode->hdisplay + (mode->htotal 2871a646342SBen Skeggs - mode->hdisplay) * 9 / 10) & ~7; 2881a646342SBen Skeggs mode->hsync_end = mode->hsync_start + 8; 2891a646342SBen Skeggs } 2901a646342SBen Skeggs 2911a646342SBen Skeggs if (output_mode->vdisplay >= 1024) { 2921a646342SBen Skeggs mode->vtotal = output_mode->vtotal; 2931a646342SBen Skeggs mode->vsync_start = output_mode->vsync_start; 2941a646342SBen Skeggs mode->vsync_end = output_mode->vsync_end; 2951a646342SBen Skeggs } 2961a646342SBen Skeggs 2971a646342SBen Skeggs mode->type |= DRM_MODE_TYPE_DRIVER; 2981a646342SBen Skeggs drm_mode_probed_add(connector, mode); 2991a646342SBen Skeggs n++; 3001a646342SBen Skeggs } 3011a646342SBen Skeggs 3021a646342SBen Skeggs return n; 3031a646342SBen Skeggs } 3041a646342SBen Skeggs 3051a646342SBen Skeggs static int nv17_tv_get_modes(struct drm_encoder *encoder, 3061a646342SBen Skeggs struct drm_connector *connector) 3071a646342SBen Skeggs { 3081a646342SBen Skeggs struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 3091a646342SBen Skeggs 3101a646342SBen Skeggs if (tv_norm->kind == CTV_ENC_MODE) 3111a646342SBen Skeggs return nv17_tv_get_hd_modes(encoder, connector); 3121a646342SBen Skeggs else 3131a646342SBen Skeggs return nv17_tv_get_ld_modes(encoder, connector); 3141a646342SBen Skeggs } 3151a646342SBen Skeggs 3161a646342SBen Skeggs static int nv17_tv_mode_valid(struct drm_encoder *encoder, 3171a646342SBen Skeggs struct drm_display_mode *mode) 3181a646342SBen Skeggs { 3191a646342SBen Skeggs struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 3201a646342SBen Skeggs 3211a646342SBen Skeggs if (tv_norm->kind == CTV_ENC_MODE) { 3221a646342SBen Skeggs struct drm_display_mode *output_mode = 3231a646342SBen Skeggs &tv_norm->ctv_enc_mode.mode; 3241a646342SBen Skeggs 3251a646342SBen Skeggs if (mode->clock > 400000) 3261a646342SBen Skeggs return MODE_CLOCK_HIGH; 3271a646342SBen Skeggs 3281a646342SBen Skeggs if (mode->hdisplay > output_mode->hdisplay || 3291a646342SBen Skeggs mode->vdisplay > output_mode->vdisplay) 3301a646342SBen Skeggs return MODE_BAD; 3311a646342SBen Skeggs 3321a646342SBen Skeggs if ((mode->flags & DRM_MODE_FLAG_INTERLACE) != 3331a646342SBen Skeggs (output_mode->flags & DRM_MODE_FLAG_INTERLACE)) 3341a646342SBen Skeggs return MODE_NO_INTERLACE; 3351a646342SBen Skeggs 3361a646342SBen Skeggs if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 3371a646342SBen Skeggs return MODE_NO_DBLESCAN; 3381a646342SBen Skeggs 3391a646342SBen Skeggs } else { 3401a646342SBen Skeggs const int vsync_tolerance = 600; 3411a646342SBen Skeggs 3421a646342SBen Skeggs if (mode->clock > 70000) 3431a646342SBen Skeggs return MODE_CLOCK_HIGH; 3441a646342SBen Skeggs 3451a646342SBen Skeggs if (abs(drm_mode_vrefresh(mode) * 1000 - 3461a646342SBen Skeggs tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance) 3471a646342SBen Skeggs return MODE_VSYNC; 3481a646342SBen Skeggs 3491a646342SBen Skeggs /* The encoder takes care of the actual interlacing */ 3501a646342SBen Skeggs if (mode->flags & DRM_MODE_FLAG_INTERLACE) 3511a646342SBen Skeggs return MODE_NO_INTERLACE; 3521a646342SBen Skeggs } 3531a646342SBen Skeggs 3541a646342SBen Skeggs return MODE_OK; 3551a646342SBen Skeggs } 3561a646342SBen Skeggs 3571a646342SBen Skeggs static bool nv17_tv_mode_fixup(struct drm_encoder *encoder, 3581a646342SBen Skeggs const struct drm_display_mode *mode, 3591a646342SBen Skeggs struct drm_display_mode *adjusted_mode) 3601a646342SBen Skeggs { 3611a646342SBen Skeggs struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 3621a646342SBen Skeggs 3631a646342SBen Skeggs if (nv04_dac_in_use(encoder)) 3641a646342SBen Skeggs return false; 3651a646342SBen Skeggs 3661a646342SBen Skeggs if (tv_norm->kind == CTV_ENC_MODE) 3671a646342SBen Skeggs adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock; 3681a646342SBen Skeggs else 3691a646342SBen Skeggs adjusted_mode->clock = 90000; 3701a646342SBen Skeggs 3711a646342SBen Skeggs return true; 3721a646342SBen Skeggs } 3731a646342SBen Skeggs 3741a646342SBen Skeggs static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) 3751a646342SBen Skeggs { 3761a646342SBen Skeggs struct drm_device *dev = encoder->dev; 3771a646342SBen Skeggs struct nouveau_drm *drm = nouveau_drm(dev); 3781a646342SBen Skeggs struct nouveau_gpio *gpio = nouveau_gpio(drm->device); 3791a646342SBen Skeggs struct nv17_tv_state *regs = &to_tv_enc(encoder)->state; 3801a646342SBen Skeggs struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 3811a646342SBen Skeggs 3821a646342SBen Skeggs if (nouveau_encoder(encoder)->last_dpms == mode) 3831a646342SBen Skeggs return; 3841a646342SBen Skeggs nouveau_encoder(encoder)->last_dpms = mode; 3851a646342SBen Skeggs 3861a646342SBen Skeggs NV_INFO(drm, "Setting dpms mode %d on TV encoder (output %d)\n", 3871a646342SBen Skeggs mode, nouveau_encoder(encoder)->dcb->index); 3881a646342SBen Skeggs 3891a646342SBen Skeggs regs->ptv_200 &= ~1; 3901a646342SBen Skeggs 3911a646342SBen Skeggs if (tv_norm->kind == CTV_ENC_MODE) { 3921a646342SBen Skeggs nv04_dfp_update_fp_control(encoder, mode); 3931a646342SBen Skeggs 3941a646342SBen Skeggs } else { 3951a646342SBen Skeggs nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF); 3961a646342SBen Skeggs 3971a646342SBen Skeggs if (mode == DRM_MODE_DPMS_ON) 3981a646342SBen Skeggs regs->ptv_200 |= 1; 3991a646342SBen Skeggs } 4001a646342SBen Skeggs 4011a646342SBen Skeggs nv_load_ptv(dev, regs, 200); 4021a646342SBen Skeggs 4031a646342SBen Skeggs gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON); 4041a646342SBen Skeggs gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON); 4051a646342SBen Skeggs 4061a646342SBen Skeggs nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); 4071a646342SBen Skeggs } 4081a646342SBen Skeggs 4091a646342SBen Skeggs static void nv17_tv_prepare(struct drm_encoder *encoder) 4101a646342SBen Skeggs { 4111a646342SBen Skeggs struct drm_device *dev = encoder->dev; 4121a646342SBen Skeggs struct nouveau_drm *drm = nouveau_drm(dev); 4131a646342SBen Skeggs struct drm_encoder_helper_funcs *helper = encoder->helper_private; 4141a646342SBen Skeggs struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 4151a646342SBen Skeggs int head = nouveau_crtc(encoder->crtc)->index; 4161a646342SBen Skeggs uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[ 4171a646342SBen Skeggs NV_CIO_CRE_LCD__INDEX]; 4181a646342SBen Skeggs uint32_t dacclk_off = NV_PRAMDAC_DACCLK + 4191a646342SBen Skeggs nv04_dac_output_offset(encoder); 4201a646342SBen Skeggs uint32_t dacclk; 4211a646342SBen Skeggs 4221a646342SBen Skeggs helper->dpms(encoder, DRM_MODE_DPMS_OFF); 4231a646342SBen Skeggs 4241a646342SBen Skeggs nv04_dfp_disable(dev, head); 4251a646342SBen Skeggs 4261a646342SBen Skeggs /* Unbind any FP encoders from this head if we need the FP 4271a646342SBen Skeggs * stuff enabled. */ 4281a646342SBen Skeggs if (tv_norm->kind == CTV_ENC_MODE) { 4291a646342SBen Skeggs struct drm_encoder *enc; 4301a646342SBen Skeggs 4311a646342SBen Skeggs list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { 4321a646342SBen Skeggs struct dcb_output *dcb = nouveau_encoder(enc)->dcb; 4331a646342SBen Skeggs 4341a646342SBen Skeggs if ((dcb->type == DCB_OUTPUT_TMDS || 4351a646342SBen Skeggs dcb->type == DCB_OUTPUT_LVDS) && 4361a646342SBen Skeggs !enc->crtc && 4371a646342SBen Skeggs nv04_dfp_get_bound_head(dev, dcb) == head) { 4381a646342SBen Skeggs nv04_dfp_bind_head(dev, dcb, head ^ 1, 4391a646342SBen Skeggs drm->vbios.fp.dual_link); 4401a646342SBen Skeggs } 4411a646342SBen Skeggs } 4421a646342SBen Skeggs 4431a646342SBen Skeggs } 4441a646342SBen Skeggs 4451a646342SBen Skeggs if (tv_norm->kind == CTV_ENC_MODE) 4461a646342SBen Skeggs *cr_lcd |= 0x1 | (head ? 0x0 : 0x8); 4471a646342SBen Skeggs 4481a646342SBen Skeggs /* Set the DACCLK register */ 4491a646342SBen Skeggs dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1; 4501a646342SBen Skeggs 4511a646342SBen Skeggs if (nv_device(drm->device)->card_type == NV_40) 4521a646342SBen Skeggs dacclk |= 0x1a << 16; 4531a646342SBen Skeggs 4541a646342SBen Skeggs if (tv_norm->kind == CTV_ENC_MODE) { 4551a646342SBen Skeggs dacclk |= 0x20; 4561a646342SBen Skeggs 4571a646342SBen Skeggs if (head) 4581a646342SBen Skeggs dacclk |= 0x100; 4591a646342SBen Skeggs else 4601a646342SBen Skeggs dacclk &= ~0x100; 4611a646342SBen Skeggs 4621a646342SBen Skeggs } else { 4631a646342SBen Skeggs dacclk |= 0x10; 4641a646342SBen Skeggs 4651a646342SBen Skeggs } 4661a646342SBen Skeggs 4671a646342SBen Skeggs NVWriteRAMDAC(dev, 0, dacclk_off, dacclk); 4681a646342SBen Skeggs } 4691a646342SBen Skeggs 4701a646342SBen Skeggs static void nv17_tv_mode_set(struct drm_encoder *encoder, 4711a646342SBen Skeggs struct drm_display_mode *drm_mode, 4721a646342SBen Skeggs struct drm_display_mode *adjusted_mode) 4731a646342SBen Skeggs { 4741a646342SBen Skeggs struct drm_device *dev = encoder->dev; 4751a646342SBen Skeggs struct nouveau_drm *drm = nouveau_drm(dev); 4761a646342SBen Skeggs int head = nouveau_crtc(encoder->crtc)->index; 4771a646342SBen Skeggs struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; 4781a646342SBen Skeggs struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state; 4791a646342SBen Skeggs struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 4801a646342SBen Skeggs int i; 4811a646342SBen Skeggs 4821a646342SBen Skeggs regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */ 4831a646342SBen Skeggs regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */ 4841a646342SBen Skeggs regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */ 4851a646342SBen Skeggs regs->tv_setup = 1; 4861a646342SBen Skeggs regs->ramdac_8c0 = 0x0; 4871a646342SBen Skeggs 4881a646342SBen Skeggs if (tv_norm->kind == TV_ENC_MODE) { 4891a646342SBen Skeggs tv_regs->ptv_200 = 0x13111100; 4901a646342SBen Skeggs if (head) 4911a646342SBen Skeggs tv_regs->ptv_200 |= 0x10; 4921a646342SBen Skeggs 4931a646342SBen Skeggs tv_regs->ptv_20c = 0x808010; 4941a646342SBen Skeggs tv_regs->ptv_304 = 0x2d00000; 4951a646342SBen Skeggs tv_regs->ptv_600 = 0x0; 4961a646342SBen Skeggs tv_regs->ptv_60c = 0x0; 4971a646342SBen Skeggs tv_regs->ptv_610 = 0x1e00000; 4981a646342SBen Skeggs 4991a646342SBen Skeggs if (tv_norm->tv_enc_mode.vdisplay == 576) { 5001a646342SBen Skeggs tv_regs->ptv_508 = 0x1200000; 5011a646342SBen Skeggs tv_regs->ptv_614 = 0x33; 5021a646342SBen Skeggs 5031a646342SBen Skeggs } else if (tv_norm->tv_enc_mode.vdisplay == 480) { 5041a646342SBen Skeggs tv_regs->ptv_508 = 0xf00000; 5051a646342SBen Skeggs tv_regs->ptv_614 = 0x13; 5061a646342SBen Skeggs } 5071a646342SBen Skeggs 5081a646342SBen Skeggs if (nv_device(drm->device)->card_type >= NV_30) { 5091a646342SBen Skeggs tv_regs->ptv_500 = 0xe8e0; 5101a646342SBen Skeggs tv_regs->ptv_504 = 0x1710; 5111a646342SBen Skeggs tv_regs->ptv_604 = 0x0; 5121a646342SBen Skeggs tv_regs->ptv_608 = 0x0; 5131a646342SBen Skeggs } else { 5141a646342SBen Skeggs if (tv_norm->tv_enc_mode.vdisplay == 576) { 5151a646342SBen Skeggs tv_regs->ptv_604 = 0x20; 5161a646342SBen Skeggs tv_regs->ptv_608 = 0x10; 5171a646342SBen Skeggs tv_regs->ptv_500 = 0x19710; 5181a646342SBen Skeggs tv_regs->ptv_504 = 0x68f0; 5191a646342SBen Skeggs 5201a646342SBen Skeggs } else if (tv_norm->tv_enc_mode.vdisplay == 480) { 5211a646342SBen Skeggs tv_regs->ptv_604 = 0x10; 5221a646342SBen Skeggs tv_regs->ptv_608 = 0x20; 5231a646342SBen Skeggs tv_regs->ptv_500 = 0x4b90; 5241a646342SBen Skeggs tv_regs->ptv_504 = 0x1b480; 5251a646342SBen Skeggs } 5261a646342SBen Skeggs } 5271a646342SBen Skeggs 5281a646342SBen Skeggs for (i = 0; i < 0x40; i++) 5291a646342SBen Skeggs tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i]; 5301a646342SBen Skeggs 5311a646342SBen Skeggs } else { 5321a646342SBen Skeggs struct drm_display_mode *output_mode = 5331a646342SBen Skeggs &tv_norm->ctv_enc_mode.mode; 5341a646342SBen Skeggs 5351a646342SBen Skeggs /* The registers in PRAMDAC+0xc00 control some timings and CSC 5361a646342SBen Skeggs * parameters for the CTV encoder (It's only used for "HD" TV 5371a646342SBen Skeggs * modes, I don't think I have enough working to guess what 5381a646342SBen Skeggs * they exactly mean...), it's probably connected at the 5391a646342SBen Skeggs * output of the FP encoder, but it also needs the analog 5401a646342SBen Skeggs * encoder in its OR enabled and routed to the head it's 5411a646342SBen Skeggs * using. It's enabled with the DACCLK register, bits [5:4]. 5421a646342SBen Skeggs */ 5431a646342SBen Skeggs for (i = 0; i < 38; i++) 5441a646342SBen Skeggs regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i]; 5451a646342SBen Skeggs 5461a646342SBen Skeggs regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; 5471a646342SBen Skeggs regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; 5481a646342SBen Skeggs regs->fp_horiz_regs[FP_SYNC_START] = 5491a646342SBen Skeggs output_mode->hsync_start - 1; 5501a646342SBen Skeggs regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; 5511a646342SBen Skeggs regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay + 5521a646342SBen Skeggs max((output_mode->hdisplay-600)/40 - 1, 1); 5531a646342SBen Skeggs 5541a646342SBen Skeggs regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; 5551a646342SBen Skeggs regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; 5561a646342SBen Skeggs regs->fp_vert_regs[FP_SYNC_START] = 5571a646342SBen Skeggs output_mode->vsync_start - 1; 5581a646342SBen Skeggs regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; 5591a646342SBen Skeggs regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1; 5601a646342SBen Skeggs 5611a646342SBen Skeggs regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | 5621a646342SBen Skeggs NV_PRAMDAC_FP_TG_CONTROL_READ_PROG | 5631a646342SBen Skeggs NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; 5641a646342SBen Skeggs 5651a646342SBen Skeggs if (output_mode->flags & DRM_MODE_FLAG_PVSYNC) 5661a646342SBen Skeggs regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS; 5671a646342SBen Skeggs if (output_mode->flags & DRM_MODE_FLAG_PHSYNC) 5681a646342SBen Skeggs regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS; 5691a646342SBen Skeggs 5701a646342SBen Skeggs regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND | 5711a646342SBen Skeggs NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND | 5721a646342SBen Skeggs NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR | 5731a646342SBen Skeggs NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR | 5741a646342SBen Skeggs NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED | 5751a646342SBen Skeggs NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE | 5761a646342SBen Skeggs NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE; 5771a646342SBen Skeggs 5781a646342SBen Skeggs regs->fp_debug_2 = 0; 5791a646342SBen Skeggs 5801a646342SBen Skeggs regs->fp_margin_color = 0x801080; 5811a646342SBen Skeggs 5821a646342SBen Skeggs } 5831a646342SBen Skeggs } 5841a646342SBen Skeggs 5851a646342SBen Skeggs static void nv17_tv_commit(struct drm_encoder *encoder) 5861a646342SBen Skeggs { 5871a646342SBen Skeggs struct drm_device *dev = encoder->dev; 5881a646342SBen Skeggs struct nouveau_drm *drm = nouveau_drm(dev); 5891a646342SBen Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 5901a646342SBen Skeggs struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 5911a646342SBen Skeggs struct drm_encoder_helper_funcs *helper = encoder->helper_private; 5921a646342SBen Skeggs 5931a646342SBen Skeggs if (get_tv_norm(encoder)->kind == TV_ENC_MODE) { 5941a646342SBen Skeggs nv17_tv_update_rescaler(encoder); 5951a646342SBen Skeggs nv17_tv_update_properties(encoder); 5961a646342SBen Skeggs } else { 5971a646342SBen Skeggs nv17_ctv_update_rescaler(encoder); 5981a646342SBen Skeggs } 5991a646342SBen Skeggs 6001a646342SBen Skeggs nv17_tv_state_load(dev, &to_tv_enc(encoder)->state); 6011a646342SBen Skeggs 6021a646342SBen Skeggs /* This could use refinement for flatpanels, but it should work */ 6031a646342SBen Skeggs if (nv_device(drm->device)->chipset < 0x44) 6041a646342SBen Skeggs NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + 6051a646342SBen Skeggs nv04_dac_output_offset(encoder), 6061a646342SBen Skeggs 0xf0000000); 6071a646342SBen Skeggs else 6081a646342SBen Skeggs NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + 6091a646342SBen Skeggs nv04_dac_output_offset(encoder), 6101a646342SBen Skeggs 0x00100000); 6111a646342SBen Skeggs 6121a646342SBen Skeggs helper->dpms(encoder, DRM_MODE_DPMS_ON); 6131a646342SBen Skeggs 6141a646342SBen Skeggs NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n", 615*8c6c361aSJani Nikula nouveau_encoder_connector_get(nv_encoder)->base.name, 6161a646342SBen Skeggs nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); 6171a646342SBen Skeggs } 6181a646342SBen Skeggs 6191a646342SBen Skeggs static void nv17_tv_save(struct drm_encoder *encoder) 6201a646342SBen Skeggs { 6211a646342SBen Skeggs struct drm_device *dev = encoder->dev; 6221a646342SBen Skeggs struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 6231a646342SBen Skeggs 6241a646342SBen Skeggs nouveau_encoder(encoder)->restore.output = 6251a646342SBen Skeggs NVReadRAMDAC(dev, 0, 6261a646342SBen Skeggs NV_PRAMDAC_DACCLK + 6271a646342SBen Skeggs nv04_dac_output_offset(encoder)); 6281a646342SBen Skeggs 6291a646342SBen Skeggs nv17_tv_state_save(dev, &tv_enc->saved_state); 6301a646342SBen Skeggs 6311a646342SBen Skeggs tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200; 6321a646342SBen Skeggs } 6331a646342SBen Skeggs 6341a646342SBen Skeggs static void nv17_tv_restore(struct drm_encoder *encoder) 6351a646342SBen Skeggs { 6361a646342SBen Skeggs struct drm_device *dev = encoder->dev; 6371a646342SBen Skeggs 6381a646342SBen Skeggs NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + 6391a646342SBen Skeggs nv04_dac_output_offset(encoder), 6401a646342SBen Skeggs nouveau_encoder(encoder)->restore.output); 6411a646342SBen Skeggs 6421a646342SBen Skeggs nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state); 6431a646342SBen Skeggs 6441a646342SBen Skeggs nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED; 6451a646342SBen Skeggs } 6461a646342SBen Skeggs 6471a646342SBen Skeggs static int nv17_tv_create_resources(struct drm_encoder *encoder, 6481a646342SBen Skeggs struct drm_connector *connector) 6491a646342SBen Skeggs { 6501a646342SBen Skeggs struct drm_device *dev = encoder->dev; 6511a646342SBen Skeggs struct nouveau_drm *drm = nouveau_drm(dev); 6521a646342SBen Skeggs struct drm_mode_config *conf = &dev->mode_config; 6531a646342SBen Skeggs struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 6541a646342SBen Skeggs struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; 6551a646342SBen Skeggs int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS : 6561a646342SBen Skeggs NUM_LD_TV_NORMS; 6571a646342SBen Skeggs int i; 6581a646342SBen Skeggs 6591a646342SBen Skeggs if (nouveau_tv_norm) { 6601a646342SBen Skeggs for (i = 0; i < num_tv_norms; i++) { 6611a646342SBen Skeggs if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) { 6621a646342SBen Skeggs tv_enc->tv_norm = i; 6631a646342SBen Skeggs break; 6641a646342SBen Skeggs } 6651a646342SBen Skeggs } 6661a646342SBen Skeggs 6671a646342SBen Skeggs if (i == num_tv_norms) 6681a646342SBen Skeggs NV_WARN(drm, "Invalid TV norm setting \"%s\"\n", 6691a646342SBen Skeggs nouveau_tv_norm); 6701a646342SBen Skeggs } 6711a646342SBen Skeggs 6721a646342SBen Skeggs drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names); 6731a646342SBen Skeggs 6741a646342SBen Skeggs drm_object_attach_property(&connector->base, 6751a646342SBen Skeggs conf->tv_select_subconnector_property, 6761a646342SBen Skeggs tv_enc->select_subconnector); 6771a646342SBen Skeggs drm_object_attach_property(&connector->base, 6781a646342SBen Skeggs conf->tv_subconnector_property, 6791a646342SBen Skeggs tv_enc->subconnector); 6801a646342SBen Skeggs drm_object_attach_property(&connector->base, 6811a646342SBen Skeggs conf->tv_mode_property, 6821a646342SBen Skeggs tv_enc->tv_norm); 6831a646342SBen Skeggs drm_object_attach_property(&connector->base, 6841a646342SBen Skeggs conf->tv_flicker_reduction_property, 6851a646342SBen Skeggs tv_enc->flicker); 6861a646342SBen Skeggs drm_object_attach_property(&connector->base, 6871a646342SBen Skeggs conf->tv_saturation_property, 6881a646342SBen Skeggs tv_enc->saturation); 6891a646342SBen Skeggs drm_object_attach_property(&connector->base, 6901a646342SBen Skeggs conf->tv_hue_property, 6911a646342SBen Skeggs tv_enc->hue); 6921a646342SBen Skeggs drm_object_attach_property(&connector->base, 6931a646342SBen Skeggs conf->tv_overscan_property, 6941a646342SBen Skeggs tv_enc->overscan); 6951a646342SBen Skeggs 6961a646342SBen Skeggs return 0; 6971a646342SBen Skeggs } 6981a646342SBen Skeggs 6991a646342SBen Skeggs static int nv17_tv_set_property(struct drm_encoder *encoder, 7001a646342SBen Skeggs struct drm_connector *connector, 7011a646342SBen Skeggs struct drm_property *property, 7021a646342SBen Skeggs uint64_t val) 7031a646342SBen Skeggs { 7041a646342SBen Skeggs struct drm_mode_config *conf = &encoder->dev->mode_config; 7051a646342SBen Skeggs struct drm_crtc *crtc = encoder->crtc; 7061a646342SBen Skeggs struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 7071a646342SBen Skeggs struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 7081a646342SBen Skeggs bool modes_changed = false; 7091a646342SBen Skeggs 7101a646342SBen Skeggs if (property == conf->tv_overscan_property) { 7111a646342SBen Skeggs tv_enc->overscan = val; 7121a646342SBen Skeggs if (encoder->crtc) { 7131a646342SBen Skeggs if (tv_norm->kind == CTV_ENC_MODE) 7141a646342SBen Skeggs nv17_ctv_update_rescaler(encoder); 7151a646342SBen Skeggs else 7161a646342SBen Skeggs nv17_tv_update_rescaler(encoder); 7171a646342SBen Skeggs } 7181a646342SBen Skeggs 7191a646342SBen Skeggs } else if (property == conf->tv_saturation_property) { 7201a646342SBen Skeggs if (tv_norm->kind != TV_ENC_MODE) 7211a646342SBen Skeggs return -EINVAL; 7221a646342SBen Skeggs 7231a646342SBen Skeggs tv_enc->saturation = val; 7241a646342SBen Skeggs nv17_tv_update_properties(encoder); 7251a646342SBen Skeggs 7261a646342SBen Skeggs } else if (property == conf->tv_hue_property) { 7271a646342SBen Skeggs if (tv_norm->kind != TV_ENC_MODE) 7281a646342SBen Skeggs return -EINVAL; 7291a646342SBen Skeggs 7301a646342SBen Skeggs tv_enc->hue = val; 7311a646342SBen Skeggs nv17_tv_update_properties(encoder); 7321a646342SBen Skeggs 7331a646342SBen Skeggs } else if (property == conf->tv_flicker_reduction_property) { 7341a646342SBen Skeggs if (tv_norm->kind != TV_ENC_MODE) 7351a646342SBen Skeggs return -EINVAL; 7361a646342SBen Skeggs 7371a646342SBen Skeggs tv_enc->flicker = val; 7381a646342SBen Skeggs if (encoder->crtc) 7391a646342SBen Skeggs nv17_tv_update_rescaler(encoder); 7401a646342SBen Skeggs 7411a646342SBen Skeggs } else if (property == conf->tv_mode_property) { 7421a646342SBen Skeggs if (connector->dpms != DRM_MODE_DPMS_OFF) 7431a646342SBen Skeggs return -EINVAL; 7441a646342SBen Skeggs 7451a646342SBen Skeggs tv_enc->tv_norm = val; 7461a646342SBen Skeggs 7471a646342SBen Skeggs modes_changed = true; 7481a646342SBen Skeggs 7491a646342SBen Skeggs } else if (property == conf->tv_select_subconnector_property) { 7501a646342SBen Skeggs if (tv_norm->kind != TV_ENC_MODE) 7511a646342SBen Skeggs return -EINVAL; 7521a646342SBen Skeggs 7531a646342SBen Skeggs tv_enc->select_subconnector = val; 7541a646342SBen Skeggs nv17_tv_update_properties(encoder); 7551a646342SBen Skeggs 7561a646342SBen Skeggs } else { 7571a646342SBen Skeggs return -EINVAL; 7581a646342SBen Skeggs } 7591a646342SBen Skeggs 7601a646342SBen Skeggs if (modes_changed) { 7611a646342SBen Skeggs drm_helper_probe_single_connector_modes(connector, 0, 0); 7621a646342SBen Skeggs 7631a646342SBen Skeggs /* Disable the crtc to ensure a full modeset is 7641a646342SBen Skeggs * performed whenever it's turned on again. */ 7651a646342SBen Skeggs if (crtc) { 7661a646342SBen Skeggs struct drm_mode_set modeset = { 7671a646342SBen Skeggs .crtc = crtc, 7681a646342SBen Skeggs }; 7691a646342SBen Skeggs 7701a646342SBen Skeggs drm_mode_set_config_internal(&modeset); 7711a646342SBen Skeggs } 7721a646342SBen Skeggs } 7731a646342SBen Skeggs 7741a646342SBen Skeggs return 0; 7751a646342SBen Skeggs } 7761a646342SBen Skeggs 7771a646342SBen Skeggs static void nv17_tv_destroy(struct drm_encoder *encoder) 7781a646342SBen Skeggs { 7791a646342SBen Skeggs struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 7801a646342SBen Skeggs 7811a646342SBen Skeggs drm_encoder_cleanup(encoder); 7821a646342SBen Skeggs kfree(tv_enc); 7831a646342SBen Skeggs } 7841a646342SBen Skeggs 7851a646342SBen Skeggs static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = { 7861a646342SBen Skeggs .dpms = nv17_tv_dpms, 7871a646342SBen Skeggs .save = nv17_tv_save, 7881a646342SBen Skeggs .restore = nv17_tv_restore, 7891a646342SBen Skeggs .mode_fixup = nv17_tv_mode_fixup, 7901a646342SBen Skeggs .prepare = nv17_tv_prepare, 7911a646342SBen Skeggs .commit = nv17_tv_commit, 7921a646342SBen Skeggs .mode_set = nv17_tv_mode_set, 7931a646342SBen Skeggs .detect = nv17_tv_detect, 7941a646342SBen Skeggs }; 7951a646342SBen Skeggs 7961a646342SBen Skeggs static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = { 7971a646342SBen Skeggs .get_modes = nv17_tv_get_modes, 7981a646342SBen Skeggs .mode_valid = nv17_tv_mode_valid, 7991a646342SBen Skeggs .create_resources = nv17_tv_create_resources, 8001a646342SBen Skeggs .set_property = nv17_tv_set_property, 8011a646342SBen Skeggs }; 8021a646342SBen Skeggs 8031a646342SBen Skeggs static struct drm_encoder_funcs nv17_tv_funcs = { 8041a646342SBen Skeggs .destroy = nv17_tv_destroy, 8051a646342SBen Skeggs }; 8061a646342SBen Skeggs 8071a646342SBen Skeggs int 8081a646342SBen Skeggs nv17_tv_create(struct drm_connector *connector, struct dcb_output *entry) 8091a646342SBen Skeggs { 8101a646342SBen Skeggs struct drm_device *dev = connector->dev; 8111a646342SBen Skeggs struct drm_encoder *encoder; 8121a646342SBen Skeggs struct nv17_tv_encoder *tv_enc = NULL; 8131a646342SBen Skeggs 8141a646342SBen Skeggs tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL); 8151a646342SBen Skeggs if (!tv_enc) 8161a646342SBen Skeggs return -ENOMEM; 8171a646342SBen Skeggs 8181a646342SBen Skeggs tv_enc->overscan = 50; 8191a646342SBen Skeggs tv_enc->flicker = 50; 8201a646342SBen Skeggs tv_enc->saturation = 50; 8211a646342SBen Skeggs tv_enc->hue = 0; 8221a646342SBen Skeggs tv_enc->tv_norm = TV_NORM_PAL; 8231a646342SBen Skeggs tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 8241a646342SBen Skeggs tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic; 8251a646342SBen Skeggs tv_enc->pin_mask = 0; 8261a646342SBen Skeggs 8271a646342SBen Skeggs encoder = to_drm_encoder(&tv_enc->base); 8281a646342SBen Skeggs 8291a646342SBen Skeggs tv_enc->base.dcb = entry; 8301a646342SBen Skeggs tv_enc->base.or = ffs(entry->or) - 1; 8311a646342SBen Skeggs 8321a646342SBen Skeggs drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC); 8331a646342SBen Skeggs drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs); 8341a646342SBen Skeggs to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs; 8351a646342SBen Skeggs 8361a646342SBen Skeggs encoder->possible_crtcs = entry->heads; 8371a646342SBen Skeggs encoder->possible_clones = 0; 8381a646342SBen Skeggs 8391a646342SBen Skeggs nv17_tv_create_resources(encoder, connector); 8401a646342SBen Skeggs drm_mode_connector_attach_encoder(connector, encoder); 8411a646342SBen Skeggs return 0; 8421a646342SBen Skeggs } 843