1*f8946e2bSNancy.Lin /* SPDX-License-Identifier: GPL-2.0-only */ 2*f8946e2bSNancy.Lin /* 3*f8946e2bSNancy.Lin * Copyright (c) 2021 MediaTek Inc. 4*f8946e2bSNancy.Lin */ 5*f8946e2bSNancy.Lin 6*f8946e2bSNancy.Lin #ifndef __MTK_MDP_RDMA_H__ 7*f8946e2bSNancy.Lin #define __MTK_MDP_RDMA_H__ 8*f8946e2bSNancy.Lin 9*f8946e2bSNancy.Lin struct mtk_mdp_rdma_cfg { 10*f8946e2bSNancy.Lin unsigned int pitch; 11*f8946e2bSNancy.Lin unsigned int addr0; 12*f8946e2bSNancy.Lin unsigned int width; 13*f8946e2bSNancy.Lin unsigned int height; 14*f8946e2bSNancy.Lin unsigned int x_left; 15*f8946e2bSNancy.Lin unsigned int y_top; 16*f8946e2bSNancy.Lin int fmt; 17*f8946e2bSNancy.Lin int color_encoding; 18*f8946e2bSNancy.Lin }; 19*f8946e2bSNancy.Lin 20*f8946e2bSNancy.Lin #endif // __MTK_MDP_RDMA_H__ 21