1*f052febdSJani Nikula /* SPDX-License-Identifier: MIT */ 2*f052febdSJani Nikula /* 3*f052febdSJani Nikula * Copyright 2019 Intel Corporation. 4*f052febdSJani Nikula */ 5*f052febdSJani Nikula 6*f052febdSJani Nikula #ifndef __INTEL_PCH__ 7*f052febdSJani Nikula #define __INTEL_PCH__ 8*f052febdSJani Nikula 9*f052febdSJani Nikula struct drm_i915_private; 10*f052febdSJani Nikula 11*f052febdSJani Nikula /* 12*f052febdSJani Nikula * Sorted by south display engine compatibility. 13*f052febdSJani Nikula * If the new PCH comes with a south display engine that is not 14*f052febdSJani Nikula * inherited from the latest item, please do not add it to the 15*f052febdSJani Nikula * end. Instead, add it right after its "parent" PCH. 16*f052febdSJani Nikula */ 17*f052febdSJani Nikula enum intel_pch { 18*f052febdSJani Nikula PCH_NOP = -1, /* PCH without south display */ 19*f052febdSJani Nikula PCH_NONE = 0, /* No PCH present */ 20*f052febdSJani Nikula PCH_IBX, /* Ibexpeak PCH */ 21*f052febdSJani Nikula PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ 22*f052febdSJani Nikula PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ 23*f052febdSJani Nikula PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */ 24*f052febdSJani Nikula PCH_CNP, /* Cannon/Comet Lake PCH */ 25*f052febdSJani Nikula PCH_ICP, /* Ice Lake/Jasper Lake PCH */ 26*f052febdSJani Nikula PCH_TGP, /* Tiger Lake/Mule Creek Canyon PCH */ 27*f052febdSJani Nikula PCH_ADP, /* Alder Lake PCH */ 28*f052febdSJani Nikula PCH_MTP, /* Meteor Lake PCH */ 29*f052febdSJani Nikula 30*f052febdSJani Nikula /* Fake PCHs, functionality handled on the same PCI dev */ 31*f052febdSJani Nikula PCH_DG1 = 1024, 32*f052febdSJani Nikula PCH_DG2, 33*f052febdSJani Nikula }; 34*f052febdSJani Nikula 35*f052febdSJani Nikula #define INTEL_PCH_DEVICE_ID_MASK 0xff80 36*f052febdSJani Nikula #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 37*f052febdSJani Nikula #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 38*f052febdSJani Nikula #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 39*f052febdSJani Nikula #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 40*f052febdSJani Nikula #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 41*f052febdSJani Nikula #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 42*f052febdSJani Nikula #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 43*f052febdSJani Nikula #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 44*f052febdSJani Nikula #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 45*f052febdSJani Nikula #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 46*f052febdSJani Nikula #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 47*f052febdSJani Nikula #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 48*f052febdSJani Nikula #define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280 49*f052febdSJani Nikula #define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680 50*f052febdSJani Nikula #define INTEL_PCH_CMP_V_DEVICE_ID_TYPE 0xA380 51*f052febdSJani Nikula #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 52*f052febdSJani Nikula #define INTEL_PCH_ICP2_DEVICE_ID_TYPE 0x3880 53*f052febdSJani Nikula #define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00 54*f052febdSJani Nikula #define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080 55*f052febdSJani Nikula #define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380 56*f052febdSJani Nikula #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80 57*f052febdSJani Nikula #define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80 58*f052febdSJani Nikula #define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180 59*f052febdSJani Nikula #define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00 60*f052febdSJani Nikula #define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x5480 61*f052febdSJani Nikula #define INTEL_PCH_MTP_DEVICE_ID_TYPE 0x7E00 62*f052febdSJani Nikula #define INTEL_PCH_MTP2_DEVICE_ID_TYPE 0xAE00 63*f052febdSJani Nikula #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 64*f052febdSJani Nikula #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 65*f052febdSJani Nikula #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ 66*f052febdSJani Nikula 67*f052febdSJani Nikula #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) 68*f052febdSJani Nikula #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) 69*f052febdSJani Nikula #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP) 70*f052febdSJani Nikula #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) 71*f052febdSJani Nikula #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) 72*f052febdSJani Nikula #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) 73*f052febdSJani Nikula #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) 74*f052febdSJani Nikula #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) 75*f052febdSJani Nikula #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) 76*f052febdSJani Nikula #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) 77*f052febdSJani Nikula #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) 78*f052febdSJani Nikula #define HAS_PCH_LPT_LP(dev_priv) \ 79*f052febdSJani Nikula (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ 80*f052febdSJani Nikula INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) 81*f052febdSJani Nikula #define HAS_PCH_LPT_H(dev_priv) \ 82*f052febdSJani Nikula (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ 83*f052febdSJani Nikula INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE) 84*f052febdSJani Nikula #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) 85*f052febdSJani Nikula #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) 86*f052febdSJani Nikula #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) 87*f052febdSJani Nikula #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) 88*f052febdSJani Nikula 89*f052febdSJani Nikula void intel_detect_pch(struct drm_i915_private *dev_priv); 90*f052febdSJani Nikula 91*f052febdSJani Nikula #endif /* __INTEL_PCH__ */ 92