1887a193bSTomas Winkler // SPDX-License-Identifier: MIT
2887a193bSTomas Winkler /*
3887a193bSTomas Winkler * Copyright(c) 2021-2022, Intel Corporation. All rights reserved.
4887a193bSTomas Winkler */
5887a193bSTomas Winkler
6887a193bSTomas Winkler #include "i915_drv.h"
7887a193bSTomas Winkler
8887a193bSTomas Winkler #include "gem/i915_gem_region.h"
9887a193bSTomas Winkler #include "gt/intel_gt.h"
10887a193bSTomas Winkler
11887a193bSTomas Winkler #include "intel_pxp.h"
12887a193bSTomas Winkler #include "intel_pxp_huc.h"
13887a193bSTomas Winkler #include "intel_pxp_tee.h"
14887a193bSTomas Winkler #include "intel_pxp_types.h"
1507db5bd2SAlan Previn #include "intel_pxp_cmd_interface_43.h"
16887a193bSTomas Winkler
intel_pxp_huc_load_and_auth(struct intel_pxp * pxp)17887a193bSTomas Winkler int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
18887a193bSTomas Winkler {
19f67986b0SAlan Previn struct intel_gt *gt;
20f67986b0SAlan Previn struct intel_huc *huc;
2107db5bd2SAlan Previn struct pxp43_start_huc_auth_in huc_in = {0};
2207db5bd2SAlan Previn struct pxp43_huc_auth_out huc_out = {0};
23887a193bSTomas Winkler dma_addr_t huc_phys_addr;
24887a193bSTomas Winkler u8 client_id = 0;
25887a193bSTomas Winkler u8 fence_id = 0;
26887a193bSTomas Winkler int err;
27887a193bSTomas Winkler
28f67986b0SAlan Previn if (!pxp || !pxp->pxp_component)
29887a193bSTomas Winkler return -ENODEV;
30887a193bSTomas Winkler
31f67986b0SAlan Previn gt = pxp->ctrl_gt;
32f67986b0SAlan Previn huc = >->uc.huc;
33f67986b0SAlan Previn
34887a193bSTomas Winkler huc_phys_addr = i915_gem_object_get_dma_address(huc->fw.obj, 0);
35887a193bSTomas Winkler
36887a193bSTomas Winkler /* write the PXP message into the lmem (the sg list) */
3707db5bd2SAlan Previn huc_in.header.api_version = PXP_APIVER(4, 3);
3807db5bd2SAlan Previn huc_in.header.command_id = PXP43_CMDID_START_HUC_AUTH;
39887a193bSTomas Winkler huc_in.header.status = 0;
40887a193bSTomas Winkler huc_in.header.buffer_len = sizeof(huc_in.huc_base_address);
41*9310dba4SJani Nikula huc_in.huc_base_address = cpu_to_le64(huc_phys_addr);
42887a193bSTomas Winkler
43887a193bSTomas Winkler err = intel_pxp_tee_stream_message(pxp, client_id, fence_id,
44887a193bSTomas Winkler &huc_in, sizeof(huc_in),
45887a193bSTomas Winkler &huc_out, sizeof(huc_out));
46887a193bSTomas Winkler if (err < 0) {
47887a193bSTomas Winkler drm_err(>->i915->drm,
48887a193bSTomas Winkler "Failed to send HuC load and auth command to GSC [%d]!\n",
49887a193bSTomas Winkler err);
50887a193bSTomas Winkler return err;
51887a193bSTomas Winkler }
52887a193bSTomas Winkler
53887a193bSTomas Winkler /*
54887a193bSTomas Winkler * HuC does sometimes survive suspend/resume (it depends on how "deep"
55887a193bSTomas Winkler * a sleep state the device reaches) so we can end up here on resume
56887a193bSTomas Winkler * with HuC already loaded, in which case the GSC will return
57887a193bSTomas Winkler * PXP_STATUS_OP_NOT_PERMITTED. We can therefore consider the GuC
58887a193bSTomas Winkler * correctly transferred in this scenario; if the same error is ever
59887a193bSTomas Winkler * returned with HuC not loaded we'll still catch it when we check the
60887a193bSTomas Winkler * authentication bit later.
61887a193bSTomas Winkler */
62887a193bSTomas Winkler if (huc_out.header.status != PXP_STATUS_SUCCESS &&
63887a193bSTomas Winkler huc_out.header.status != PXP_STATUS_OP_NOT_PERMITTED) {
64887a193bSTomas Winkler drm_err(>->i915->drm,
65887a193bSTomas Winkler "HuC load failed with GSC error = 0x%x\n",
66887a193bSTomas Winkler huc_out.header.status);
67887a193bSTomas Winkler return -EPROTO;
68887a193bSTomas Winkler }
69887a193bSTomas Winkler
70887a193bSTomas Winkler return 0;
71887a193bSTomas Winkler }
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