1c0e09200SDave Airlie /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2c0e09200SDave Airlie */ 3c0e09200SDave Airlie /* 4c0e09200SDave Airlie * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5c0e09200SDave Airlie * All Rights Reserved. 6c0e09200SDave Airlie * 7c0e09200SDave Airlie * Permission is hereby granted, free of charge, to any person obtaining a 8c0e09200SDave Airlie * copy of this software and associated documentation files (the 9c0e09200SDave Airlie * "Software"), to deal in the Software without restriction, including 10c0e09200SDave Airlie * without limitation the rights to use, copy, modify, merge, publish, 11c0e09200SDave Airlie * distribute, sub license, and/or sell copies of the Software, and to 12c0e09200SDave Airlie * permit persons to whom the Software is furnished to do so, subject to 13c0e09200SDave Airlie * the following conditions: 14c0e09200SDave Airlie * 15c0e09200SDave Airlie * The above copyright notice and this permission notice (including the 16c0e09200SDave Airlie * next paragraph) shall be included in all copies or substantial portions 17c0e09200SDave Airlie * of the Software. 18c0e09200SDave Airlie * 19c0e09200SDave Airlie * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20c0e09200SDave Airlie * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21c0e09200SDave Airlie * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22c0e09200SDave Airlie * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23c0e09200SDave Airlie * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24c0e09200SDave Airlie * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25c0e09200SDave Airlie * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26c0e09200SDave Airlie * 27c0e09200SDave Airlie */ 28c0e09200SDave Airlie 29a70491ccSJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30a70491ccSJoe Perches 3163eeaf38SJesse Barnes #include <linux/sysrq.h> 325a0e3ad6STejun Heo #include <linux/slab.h> 33b2c88f5bSDamien Lespiau #include <linux/circ_buf.h> 34760285e7SDavid Howells #include <drm/drmP.h> 35760285e7SDavid Howells #include <drm/i915_drm.h> 36c0e09200SDave Airlie #include "i915_drv.h" 371c5d22f7SChris Wilson #include "i915_trace.h" 3879e53945SJesse Barnes #include "intel_drv.h" 39c0e09200SDave Airlie 40e5868a31SEgbert Eich static const u32 hpd_ibx[] = { 41e5868a31SEgbert Eich [HPD_CRT] = SDE_CRT_HOTPLUG, 42e5868a31SEgbert Eich [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, 43e5868a31SEgbert Eich [HPD_PORT_B] = SDE_PORTB_HOTPLUG, 44e5868a31SEgbert Eich [HPD_PORT_C] = SDE_PORTC_HOTPLUG, 45e5868a31SEgbert Eich [HPD_PORT_D] = SDE_PORTD_HOTPLUG 46e5868a31SEgbert Eich }; 47e5868a31SEgbert Eich 48e5868a31SEgbert Eich static const u32 hpd_cpt[] = { 49e5868a31SEgbert Eich [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, 5073c352a2SDaniel Vetter [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, 51e5868a31SEgbert Eich [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 52e5868a31SEgbert Eich [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 53e5868a31SEgbert Eich [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT 54e5868a31SEgbert Eich }; 55e5868a31SEgbert Eich 56e5868a31SEgbert Eich static const u32 hpd_mask_i915[] = { 57e5868a31SEgbert Eich [HPD_CRT] = CRT_HOTPLUG_INT_EN, 58e5868a31SEgbert Eich [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, 59e5868a31SEgbert Eich [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, 60e5868a31SEgbert Eich [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, 61e5868a31SEgbert Eich [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, 62e5868a31SEgbert Eich [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN 63e5868a31SEgbert Eich }; 64e5868a31SEgbert Eich 65704cfb87SDaniel Vetter static const u32 hpd_status_g4x[] = { 66e5868a31SEgbert Eich [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 67e5868a31SEgbert Eich [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, 68e5868a31SEgbert Eich [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, 69e5868a31SEgbert Eich [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 70e5868a31SEgbert Eich [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 71e5868a31SEgbert Eich [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS 72e5868a31SEgbert Eich }; 73e5868a31SEgbert Eich 74e5868a31SEgbert Eich static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ 75e5868a31SEgbert Eich [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 76e5868a31SEgbert Eich [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, 77e5868a31SEgbert Eich [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, 78e5868a31SEgbert Eich [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 79e5868a31SEgbert Eich [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 80e5868a31SEgbert Eich [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS 81e5868a31SEgbert Eich }; 82e5868a31SEgbert Eich 83036a4a7dSZhenyu Wang /* For display hotplug interrupt */ 84995b6762SChris Wilson static void 85f2b115e6SAdam Jackson ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 86036a4a7dSZhenyu Wang { 874bc9d430SDaniel Vetter assert_spin_locked(&dev_priv->irq_lock); 884bc9d430SDaniel Vetter 89c67a470bSPaulo Zanoni if (dev_priv->pc8.irqs_disabled) { 90c67a470bSPaulo Zanoni WARN(1, "IRQs disabled\n"); 91c67a470bSPaulo Zanoni dev_priv->pc8.regsave.deimr &= ~mask; 92c67a470bSPaulo Zanoni return; 93c67a470bSPaulo Zanoni } 94c67a470bSPaulo Zanoni 951ec14ad3SChris Wilson if ((dev_priv->irq_mask & mask) != 0) { 961ec14ad3SChris Wilson dev_priv->irq_mask &= ~mask; 971ec14ad3SChris Wilson I915_WRITE(DEIMR, dev_priv->irq_mask); 983143a2bfSChris Wilson POSTING_READ(DEIMR); 99036a4a7dSZhenyu Wang } 100036a4a7dSZhenyu Wang } 101036a4a7dSZhenyu Wang 1020ff9800aSPaulo Zanoni static void 103f2b115e6SAdam Jackson ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 104036a4a7dSZhenyu Wang { 1054bc9d430SDaniel Vetter assert_spin_locked(&dev_priv->irq_lock); 1064bc9d430SDaniel Vetter 107c67a470bSPaulo Zanoni if (dev_priv->pc8.irqs_disabled) { 108c67a470bSPaulo Zanoni WARN(1, "IRQs disabled\n"); 109c67a470bSPaulo Zanoni dev_priv->pc8.regsave.deimr |= mask; 110c67a470bSPaulo Zanoni return; 111c67a470bSPaulo Zanoni } 112c67a470bSPaulo Zanoni 1131ec14ad3SChris Wilson if ((dev_priv->irq_mask & mask) != mask) { 1141ec14ad3SChris Wilson dev_priv->irq_mask |= mask; 1151ec14ad3SChris Wilson I915_WRITE(DEIMR, dev_priv->irq_mask); 1163143a2bfSChris Wilson POSTING_READ(DEIMR); 117036a4a7dSZhenyu Wang } 118036a4a7dSZhenyu Wang } 119036a4a7dSZhenyu Wang 12043eaea13SPaulo Zanoni /** 12143eaea13SPaulo Zanoni * ilk_update_gt_irq - update GTIMR 12243eaea13SPaulo Zanoni * @dev_priv: driver private 12343eaea13SPaulo Zanoni * @interrupt_mask: mask of interrupt bits to update 12443eaea13SPaulo Zanoni * @enabled_irq_mask: mask of interrupt bits to enable 12543eaea13SPaulo Zanoni */ 12643eaea13SPaulo Zanoni static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, 12743eaea13SPaulo Zanoni uint32_t interrupt_mask, 12843eaea13SPaulo Zanoni uint32_t enabled_irq_mask) 12943eaea13SPaulo Zanoni { 13043eaea13SPaulo Zanoni assert_spin_locked(&dev_priv->irq_lock); 13143eaea13SPaulo Zanoni 132c67a470bSPaulo Zanoni if (dev_priv->pc8.irqs_disabled) { 133c67a470bSPaulo Zanoni WARN(1, "IRQs disabled\n"); 134c67a470bSPaulo Zanoni dev_priv->pc8.regsave.gtimr &= ~interrupt_mask; 135c67a470bSPaulo Zanoni dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask & 136c67a470bSPaulo Zanoni interrupt_mask); 137c67a470bSPaulo Zanoni return; 138c67a470bSPaulo Zanoni } 139c67a470bSPaulo Zanoni 14043eaea13SPaulo Zanoni dev_priv->gt_irq_mask &= ~interrupt_mask; 14143eaea13SPaulo Zanoni dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); 14243eaea13SPaulo Zanoni I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 14343eaea13SPaulo Zanoni POSTING_READ(GTIMR); 14443eaea13SPaulo Zanoni } 14543eaea13SPaulo Zanoni 14643eaea13SPaulo Zanoni void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) 14743eaea13SPaulo Zanoni { 14843eaea13SPaulo Zanoni ilk_update_gt_irq(dev_priv, mask, mask); 14943eaea13SPaulo Zanoni } 15043eaea13SPaulo Zanoni 15143eaea13SPaulo Zanoni void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) 15243eaea13SPaulo Zanoni { 15343eaea13SPaulo Zanoni ilk_update_gt_irq(dev_priv, mask, 0); 15443eaea13SPaulo Zanoni } 15543eaea13SPaulo Zanoni 156edbfdb45SPaulo Zanoni /** 157edbfdb45SPaulo Zanoni * snb_update_pm_irq - update GEN6_PMIMR 158edbfdb45SPaulo Zanoni * @dev_priv: driver private 159edbfdb45SPaulo Zanoni * @interrupt_mask: mask of interrupt bits to update 160edbfdb45SPaulo Zanoni * @enabled_irq_mask: mask of interrupt bits to enable 161edbfdb45SPaulo Zanoni */ 162edbfdb45SPaulo Zanoni static void snb_update_pm_irq(struct drm_i915_private *dev_priv, 163edbfdb45SPaulo Zanoni uint32_t interrupt_mask, 164edbfdb45SPaulo Zanoni uint32_t enabled_irq_mask) 165edbfdb45SPaulo Zanoni { 166605cd25bSPaulo Zanoni uint32_t new_val; 167edbfdb45SPaulo Zanoni 168edbfdb45SPaulo Zanoni assert_spin_locked(&dev_priv->irq_lock); 169edbfdb45SPaulo Zanoni 170c67a470bSPaulo Zanoni if (dev_priv->pc8.irqs_disabled) { 171c67a470bSPaulo Zanoni WARN(1, "IRQs disabled\n"); 172c67a470bSPaulo Zanoni dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask; 173c67a470bSPaulo Zanoni dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask & 174c67a470bSPaulo Zanoni interrupt_mask); 175c67a470bSPaulo Zanoni return; 176c67a470bSPaulo Zanoni } 177c67a470bSPaulo Zanoni 178605cd25bSPaulo Zanoni new_val = dev_priv->pm_irq_mask; 179f52ecbcfSPaulo Zanoni new_val &= ~interrupt_mask; 180f52ecbcfSPaulo Zanoni new_val |= (~enabled_irq_mask & interrupt_mask); 181f52ecbcfSPaulo Zanoni 182605cd25bSPaulo Zanoni if (new_val != dev_priv->pm_irq_mask) { 183605cd25bSPaulo Zanoni dev_priv->pm_irq_mask = new_val; 184605cd25bSPaulo Zanoni I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); 185edbfdb45SPaulo Zanoni POSTING_READ(GEN6_PMIMR); 186edbfdb45SPaulo Zanoni } 187f52ecbcfSPaulo Zanoni } 188edbfdb45SPaulo Zanoni 189edbfdb45SPaulo Zanoni void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) 190edbfdb45SPaulo Zanoni { 191edbfdb45SPaulo Zanoni snb_update_pm_irq(dev_priv, mask, mask); 192edbfdb45SPaulo Zanoni } 193edbfdb45SPaulo Zanoni 194edbfdb45SPaulo Zanoni void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) 195edbfdb45SPaulo Zanoni { 196edbfdb45SPaulo Zanoni snb_update_pm_irq(dev_priv, mask, 0); 197edbfdb45SPaulo Zanoni } 198edbfdb45SPaulo Zanoni 1998664281bSPaulo Zanoni static bool ivb_can_enable_err_int(struct drm_device *dev) 2008664281bSPaulo Zanoni { 2018664281bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 2028664281bSPaulo Zanoni struct intel_crtc *crtc; 2038664281bSPaulo Zanoni enum pipe pipe; 2048664281bSPaulo Zanoni 2054bc9d430SDaniel Vetter assert_spin_locked(&dev_priv->irq_lock); 2064bc9d430SDaniel Vetter 2078664281bSPaulo Zanoni for_each_pipe(pipe) { 2088664281bSPaulo Zanoni crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 2098664281bSPaulo Zanoni 2108664281bSPaulo Zanoni if (crtc->cpu_fifo_underrun_disabled) 2118664281bSPaulo Zanoni return false; 2128664281bSPaulo Zanoni } 2138664281bSPaulo Zanoni 2148664281bSPaulo Zanoni return true; 2158664281bSPaulo Zanoni } 2168664281bSPaulo Zanoni 2178664281bSPaulo Zanoni static bool cpt_can_enable_serr_int(struct drm_device *dev) 2188664281bSPaulo Zanoni { 2198664281bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 2208664281bSPaulo Zanoni enum pipe pipe; 2218664281bSPaulo Zanoni struct intel_crtc *crtc; 2228664281bSPaulo Zanoni 223fee884edSDaniel Vetter assert_spin_locked(&dev_priv->irq_lock); 224fee884edSDaniel Vetter 2258664281bSPaulo Zanoni for_each_pipe(pipe) { 2268664281bSPaulo Zanoni crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 2278664281bSPaulo Zanoni 2288664281bSPaulo Zanoni if (crtc->pch_fifo_underrun_disabled) 2298664281bSPaulo Zanoni return false; 2308664281bSPaulo Zanoni } 2318664281bSPaulo Zanoni 2328664281bSPaulo Zanoni return true; 2338664281bSPaulo Zanoni } 2348664281bSPaulo Zanoni 235*2d9d2b0bSVille Syrjälä static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe) 236*2d9d2b0bSVille Syrjälä { 237*2d9d2b0bSVille Syrjälä struct drm_i915_private *dev_priv = dev->dev_private; 238*2d9d2b0bSVille Syrjälä u32 reg = PIPESTAT(pipe); 239*2d9d2b0bSVille Syrjälä u32 pipestat = I915_READ(reg) & 0x7fff0000; 240*2d9d2b0bSVille Syrjälä 241*2d9d2b0bSVille Syrjälä assert_spin_locked(&dev_priv->irq_lock); 242*2d9d2b0bSVille Syrjälä 243*2d9d2b0bSVille Syrjälä I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); 244*2d9d2b0bSVille Syrjälä POSTING_READ(reg); 245*2d9d2b0bSVille Syrjälä } 246*2d9d2b0bSVille Syrjälä 2478664281bSPaulo Zanoni static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, 2488664281bSPaulo Zanoni enum pipe pipe, bool enable) 2498664281bSPaulo Zanoni { 2508664281bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 2518664281bSPaulo Zanoni uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : 2528664281bSPaulo Zanoni DE_PIPEB_FIFO_UNDERRUN; 2538664281bSPaulo Zanoni 2548664281bSPaulo Zanoni if (enable) 2558664281bSPaulo Zanoni ironlake_enable_display_irq(dev_priv, bit); 2568664281bSPaulo Zanoni else 2578664281bSPaulo Zanoni ironlake_disable_display_irq(dev_priv, bit); 2588664281bSPaulo Zanoni } 2598664281bSPaulo Zanoni 2608664281bSPaulo Zanoni static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, 2617336df65SDaniel Vetter enum pipe pipe, bool enable) 2628664281bSPaulo Zanoni { 2638664281bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 2648664281bSPaulo Zanoni if (enable) { 2657336df65SDaniel Vetter I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 2667336df65SDaniel Vetter 2678664281bSPaulo Zanoni if (!ivb_can_enable_err_int(dev)) 2688664281bSPaulo Zanoni return; 2698664281bSPaulo Zanoni 2708664281bSPaulo Zanoni ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); 2718664281bSPaulo Zanoni } else { 2727336df65SDaniel Vetter bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); 2737336df65SDaniel Vetter 2747336df65SDaniel Vetter /* Change the state _after_ we've read out the current one. */ 2758664281bSPaulo Zanoni ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); 2767336df65SDaniel Vetter 2777336df65SDaniel Vetter if (!was_enabled && 2787336df65SDaniel Vetter (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { 2797336df65SDaniel Vetter DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", 2807336df65SDaniel Vetter pipe_name(pipe)); 2817336df65SDaniel Vetter } 2828664281bSPaulo Zanoni } 2838664281bSPaulo Zanoni } 2848664281bSPaulo Zanoni 28538d83c96SDaniel Vetter static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, 28638d83c96SDaniel Vetter enum pipe pipe, bool enable) 28738d83c96SDaniel Vetter { 28838d83c96SDaniel Vetter struct drm_i915_private *dev_priv = dev->dev_private; 28938d83c96SDaniel Vetter 29038d83c96SDaniel Vetter assert_spin_locked(&dev_priv->irq_lock); 29138d83c96SDaniel Vetter 29238d83c96SDaniel Vetter if (enable) 29338d83c96SDaniel Vetter dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; 29438d83c96SDaniel Vetter else 29538d83c96SDaniel Vetter dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; 29638d83c96SDaniel Vetter I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 29738d83c96SDaniel Vetter POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); 29838d83c96SDaniel Vetter } 29938d83c96SDaniel Vetter 300fee884edSDaniel Vetter /** 301fee884edSDaniel Vetter * ibx_display_interrupt_update - update SDEIMR 302fee884edSDaniel Vetter * @dev_priv: driver private 303fee884edSDaniel Vetter * @interrupt_mask: mask of interrupt bits to update 304fee884edSDaniel Vetter * @enabled_irq_mask: mask of interrupt bits to enable 305fee884edSDaniel Vetter */ 306fee884edSDaniel Vetter static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 307fee884edSDaniel Vetter uint32_t interrupt_mask, 308fee884edSDaniel Vetter uint32_t enabled_irq_mask) 309fee884edSDaniel Vetter { 310fee884edSDaniel Vetter uint32_t sdeimr = I915_READ(SDEIMR); 311fee884edSDaniel Vetter sdeimr &= ~interrupt_mask; 312fee884edSDaniel Vetter sdeimr |= (~enabled_irq_mask & interrupt_mask); 313fee884edSDaniel Vetter 314fee884edSDaniel Vetter assert_spin_locked(&dev_priv->irq_lock); 315fee884edSDaniel Vetter 316c67a470bSPaulo Zanoni if (dev_priv->pc8.irqs_disabled && 317c67a470bSPaulo Zanoni (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { 318c67a470bSPaulo Zanoni WARN(1, "IRQs disabled\n"); 319c67a470bSPaulo Zanoni dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask; 320c67a470bSPaulo Zanoni dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask & 321c67a470bSPaulo Zanoni interrupt_mask); 322c67a470bSPaulo Zanoni return; 323c67a470bSPaulo Zanoni } 324c67a470bSPaulo Zanoni 325fee884edSDaniel Vetter I915_WRITE(SDEIMR, sdeimr); 326fee884edSDaniel Vetter POSTING_READ(SDEIMR); 327fee884edSDaniel Vetter } 328fee884edSDaniel Vetter #define ibx_enable_display_interrupt(dev_priv, bits) \ 329fee884edSDaniel Vetter ibx_display_interrupt_update((dev_priv), (bits), (bits)) 330fee884edSDaniel Vetter #define ibx_disable_display_interrupt(dev_priv, bits) \ 331fee884edSDaniel Vetter ibx_display_interrupt_update((dev_priv), (bits), 0) 332fee884edSDaniel Vetter 333de28075dSDaniel Vetter static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, 334de28075dSDaniel Vetter enum transcoder pch_transcoder, 3358664281bSPaulo Zanoni bool enable) 3368664281bSPaulo Zanoni { 3378664281bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 338de28075dSDaniel Vetter uint32_t bit = (pch_transcoder == TRANSCODER_A) ? 339de28075dSDaniel Vetter SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; 3408664281bSPaulo Zanoni 3418664281bSPaulo Zanoni if (enable) 342fee884edSDaniel Vetter ibx_enable_display_interrupt(dev_priv, bit); 3438664281bSPaulo Zanoni else 344fee884edSDaniel Vetter ibx_disable_display_interrupt(dev_priv, bit); 3458664281bSPaulo Zanoni } 3468664281bSPaulo Zanoni 3478664281bSPaulo Zanoni static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, 3488664281bSPaulo Zanoni enum transcoder pch_transcoder, 3498664281bSPaulo Zanoni bool enable) 3508664281bSPaulo Zanoni { 3518664281bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 3528664281bSPaulo Zanoni 3538664281bSPaulo Zanoni if (enable) { 3541dd246fbSDaniel Vetter I915_WRITE(SERR_INT, 3551dd246fbSDaniel Vetter SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 3561dd246fbSDaniel Vetter 3578664281bSPaulo Zanoni if (!cpt_can_enable_serr_int(dev)) 3588664281bSPaulo Zanoni return; 3598664281bSPaulo Zanoni 360fee884edSDaniel Vetter ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); 3618664281bSPaulo Zanoni } else { 3621dd246fbSDaniel Vetter uint32_t tmp = I915_READ(SERR_INT); 3631dd246fbSDaniel Vetter bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); 3641dd246fbSDaniel Vetter 3651dd246fbSDaniel Vetter /* Change the state _after_ we've read out the current one. */ 366fee884edSDaniel Vetter ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); 3671dd246fbSDaniel Vetter 3681dd246fbSDaniel Vetter if (!was_enabled && 3691dd246fbSDaniel Vetter (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { 3701dd246fbSDaniel Vetter DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", 3711dd246fbSDaniel Vetter transcoder_name(pch_transcoder)); 3721dd246fbSDaniel Vetter } 3738664281bSPaulo Zanoni } 3748664281bSPaulo Zanoni } 3758664281bSPaulo Zanoni 3768664281bSPaulo Zanoni /** 3778664281bSPaulo Zanoni * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages 3788664281bSPaulo Zanoni * @dev: drm device 3798664281bSPaulo Zanoni * @pipe: pipe 3808664281bSPaulo Zanoni * @enable: true if we want to report FIFO underrun errors, false otherwise 3818664281bSPaulo Zanoni * 3828664281bSPaulo Zanoni * This function makes us disable or enable CPU fifo underruns for a specific 3838664281bSPaulo Zanoni * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun 3848664281bSPaulo Zanoni * reporting for one pipe may also disable all the other CPU error interruts for 3858664281bSPaulo Zanoni * the other pipes, due to the fact that there's just one interrupt mask/enable 3868664281bSPaulo Zanoni * bit for all the pipes. 3878664281bSPaulo Zanoni * 3888664281bSPaulo Zanoni * Returns the previous state of underrun reporting. 3898664281bSPaulo Zanoni */ 3908664281bSPaulo Zanoni bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 3918664281bSPaulo Zanoni enum pipe pipe, bool enable) 3928664281bSPaulo Zanoni { 3938664281bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 3948664281bSPaulo Zanoni struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 3958664281bSPaulo Zanoni struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3968664281bSPaulo Zanoni unsigned long flags; 3978664281bSPaulo Zanoni bool ret; 3988664281bSPaulo Zanoni 3998664281bSPaulo Zanoni spin_lock_irqsave(&dev_priv->irq_lock, flags); 4008664281bSPaulo Zanoni 4018664281bSPaulo Zanoni ret = !intel_crtc->cpu_fifo_underrun_disabled; 4028664281bSPaulo Zanoni 4038664281bSPaulo Zanoni if (enable == ret) 4048664281bSPaulo Zanoni goto done; 4058664281bSPaulo Zanoni 4068664281bSPaulo Zanoni intel_crtc->cpu_fifo_underrun_disabled = !enable; 4078664281bSPaulo Zanoni 408*2d9d2b0bSVille Syrjälä if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))) 409*2d9d2b0bSVille Syrjälä i9xx_clear_fifo_underrun(dev, pipe); 410*2d9d2b0bSVille Syrjälä else if (IS_GEN5(dev) || IS_GEN6(dev)) 4118664281bSPaulo Zanoni ironlake_set_fifo_underrun_reporting(dev, pipe, enable); 4128664281bSPaulo Zanoni else if (IS_GEN7(dev)) 4137336df65SDaniel Vetter ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); 41438d83c96SDaniel Vetter else if (IS_GEN8(dev)) 41538d83c96SDaniel Vetter broadwell_set_fifo_underrun_reporting(dev, pipe, enable); 4168664281bSPaulo Zanoni 4178664281bSPaulo Zanoni done: 4188664281bSPaulo Zanoni spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 4198664281bSPaulo Zanoni return ret; 4208664281bSPaulo Zanoni } 4218664281bSPaulo Zanoni 4228664281bSPaulo Zanoni /** 4238664281bSPaulo Zanoni * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages 4248664281bSPaulo Zanoni * @dev: drm device 4258664281bSPaulo Zanoni * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 4268664281bSPaulo Zanoni * @enable: true if we want to report FIFO underrun errors, false otherwise 4278664281bSPaulo Zanoni * 4288664281bSPaulo Zanoni * This function makes us disable or enable PCH fifo underruns for a specific 4298664281bSPaulo Zanoni * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO 4308664281bSPaulo Zanoni * underrun reporting for one transcoder may also disable all the other PCH 4318664281bSPaulo Zanoni * error interruts for the other transcoders, due to the fact that there's just 4328664281bSPaulo Zanoni * one interrupt mask/enable bit for all the transcoders. 4338664281bSPaulo Zanoni * 4348664281bSPaulo Zanoni * Returns the previous state of underrun reporting. 4358664281bSPaulo Zanoni */ 4368664281bSPaulo Zanoni bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, 4378664281bSPaulo Zanoni enum transcoder pch_transcoder, 4388664281bSPaulo Zanoni bool enable) 4398664281bSPaulo Zanoni { 4408664281bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 441de28075dSDaniel Vetter struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; 442de28075dSDaniel Vetter struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4438664281bSPaulo Zanoni unsigned long flags; 4448664281bSPaulo Zanoni bool ret; 4458664281bSPaulo Zanoni 446de28075dSDaniel Vetter /* 447de28075dSDaniel Vetter * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT 448de28075dSDaniel Vetter * has only one pch transcoder A that all pipes can use. To avoid racy 449de28075dSDaniel Vetter * pch transcoder -> pipe lookups from interrupt code simply store the 450de28075dSDaniel Vetter * underrun statistics in crtc A. Since we never expose this anywhere 451de28075dSDaniel Vetter * nor use it outside of the fifo underrun code here using the "wrong" 452de28075dSDaniel Vetter * crtc on LPT won't cause issues. 453de28075dSDaniel Vetter */ 4548664281bSPaulo Zanoni 4558664281bSPaulo Zanoni spin_lock_irqsave(&dev_priv->irq_lock, flags); 4568664281bSPaulo Zanoni 4578664281bSPaulo Zanoni ret = !intel_crtc->pch_fifo_underrun_disabled; 4588664281bSPaulo Zanoni 4598664281bSPaulo Zanoni if (enable == ret) 4608664281bSPaulo Zanoni goto done; 4618664281bSPaulo Zanoni 4628664281bSPaulo Zanoni intel_crtc->pch_fifo_underrun_disabled = !enable; 4638664281bSPaulo Zanoni 4648664281bSPaulo Zanoni if (HAS_PCH_IBX(dev)) 465de28075dSDaniel Vetter ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); 4668664281bSPaulo Zanoni else 4678664281bSPaulo Zanoni cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); 4688664281bSPaulo Zanoni 4698664281bSPaulo Zanoni done: 4708664281bSPaulo Zanoni spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 4718664281bSPaulo Zanoni return ret; 4728664281bSPaulo Zanoni } 4738664281bSPaulo Zanoni 4748664281bSPaulo Zanoni 4757c463586SKeith Packard void 4763b6c42e8SDaniel Vetter i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask) 4777c463586SKeith Packard { 4789db4a9c7SJesse Barnes u32 reg = PIPESTAT(pipe); 47946c06a30SVille Syrjälä u32 pipestat = I915_READ(reg) & 0x7fff0000; 4807c463586SKeith Packard 481b79480baSDaniel Vetter assert_spin_locked(&dev_priv->irq_lock); 482b79480baSDaniel Vetter 48346c06a30SVille Syrjälä if ((pipestat & mask) == mask) 48446c06a30SVille Syrjälä return; 48546c06a30SVille Syrjälä 4867c463586SKeith Packard /* Enable the interrupt, clear any pending status */ 48746c06a30SVille Syrjälä pipestat |= mask | (mask >> 16); 48846c06a30SVille Syrjälä I915_WRITE(reg, pipestat); 4893143a2bfSChris Wilson POSTING_READ(reg); 4907c463586SKeith Packard } 4917c463586SKeith Packard 4927c463586SKeith Packard void 4933b6c42e8SDaniel Vetter i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask) 4947c463586SKeith Packard { 4959db4a9c7SJesse Barnes u32 reg = PIPESTAT(pipe); 49646c06a30SVille Syrjälä u32 pipestat = I915_READ(reg) & 0x7fff0000; 4977c463586SKeith Packard 498b79480baSDaniel Vetter assert_spin_locked(&dev_priv->irq_lock); 499b79480baSDaniel Vetter 50046c06a30SVille Syrjälä if ((pipestat & mask) == 0) 50146c06a30SVille Syrjälä return; 50246c06a30SVille Syrjälä 50346c06a30SVille Syrjälä pipestat &= ~mask; 50446c06a30SVille Syrjälä I915_WRITE(reg, pipestat); 5053143a2bfSChris Wilson POSTING_READ(reg); 5067c463586SKeith Packard } 5077c463586SKeith Packard 508c0e09200SDave Airlie /** 509f49e38ddSJani Nikula * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion 51001c66889SZhao Yakui */ 511f49e38ddSJani Nikula static void i915_enable_asle_pipestat(struct drm_device *dev) 51201c66889SZhao Yakui { 5131ec14ad3SChris Wilson drm_i915_private_t *dev_priv = dev->dev_private; 5141ec14ad3SChris Wilson unsigned long irqflags; 5151ec14ad3SChris Wilson 516f49e38ddSJani Nikula if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) 517f49e38ddSJani Nikula return; 518f49e38ddSJani Nikula 5191ec14ad3SChris Wilson spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 52001c66889SZhao Yakui 5213b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE); 522a6c45cf0SChris Wilson if (INTEL_INFO(dev)->gen >= 4) 5233b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_A, 5243b6c42e8SDaniel Vetter PIPE_LEGACY_BLC_EVENT_ENABLE); 5251ec14ad3SChris Wilson 5261ec14ad3SChris Wilson spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 52701c66889SZhao Yakui } 52801c66889SZhao Yakui 52901c66889SZhao Yakui /** 5300a3e67a4SJesse Barnes * i915_pipe_enabled - check if a pipe is enabled 5310a3e67a4SJesse Barnes * @dev: DRM device 5320a3e67a4SJesse Barnes * @pipe: pipe to check 5330a3e67a4SJesse Barnes * 5340a3e67a4SJesse Barnes * Reading certain registers when the pipe is disabled can hang the chip. 5350a3e67a4SJesse Barnes * Use this routine to make sure the PLL is running and the pipe is active 5360a3e67a4SJesse Barnes * before reading such registers if unsure. 5370a3e67a4SJesse Barnes */ 5380a3e67a4SJesse Barnes static int 5390a3e67a4SJesse Barnes i915_pipe_enabled(struct drm_device *dev, int pipe) 5400a3e67a4SJesse Barnes { 5410a3e67a4SJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 542702e7a56SPaulo Zanoni 543a01025afSDaniel Vetter if (drm_core_check_feature(dev, DRIVER_MODESET)) { 544a01025afSDaniel Vetter /* Locking is horribly broken here, but whatever. */ 545a01025afSDaniel Vetter struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 546a01025afSDaniel Vetter struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 54771f8ba6bSPaulo Zanoni 548a01025afSDaniel Vetter return intel_crtc->active; 549a01025afSDaniel Vetter } else { 550a01025afSDaniel Vetter return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; 551a01025afSDaniel Vetter } 5520a3e67a4SJesse Barnes } 5530a3e67a4SJesse Barnes 5544cdb83ecSVille Syrjälä static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) 5554cdb83ecSVille Syrjälä { 5564cdb83ecSVille Syrjälä /* Gen2 doesn't have a hardware frame counter */ 5574cdb83ecSVille Syrjälä return 0; 5584cdb83ecSVille Syrjälä } 5594cdb83ecSVille Syrjälä 56042f52ef8SKeith Packard /* Called from drm generic code, passed a 'crtc', which 56142f52ef8SKeith Packard * we use as a pipe index 56242f52ef8SKeith Packard */ 563f71d4af4SJesse Barnes static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 5640a3e67a4SJesse Barnes { 5650a3e67a4SJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 5660a3e67a4SJesse Barnes unsigned long high_frame; 5670a3e67a4SJesse Barnes unsigned long low_frame; 568391f75e2SVille Syrjälä u32 high1, high2, low, pixel, vbl_start; 5690a3e67a4SJesse Barnes 5700a3e67a4SJesse Barnes if (!i915_pipe_enabled(dev, pipe)) { 57144d98a61SZhao Yakui DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 5729db4a9c7SJesse Barnes "pipe %c\n", pipe_name(pipe)); 5730a3e67a4SJesse Barnes return 0; 5740a3e67a4SJesse Barnes } 5750a3e67a4SJesse Barnes 576391f75e2SVille Syrjälä if (drm_core_check_feature(dev, DRIVER_MODESET)) { 577391f75e2SVille Syrjälä struct intel_crtc *intel_crtc = 578391f75e2SVille Syrjälä to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 579391f75e2SVille Syrjälä const struct drm_display_mode *mode = 580391f75e2SVille Syrjälä &intel_crtc->config.adjusted_mode; 581391f75e2SVille Syrjälä 582391f75e2SVille Syrjälä vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; 583391f75e2SVille Syrjälä } else { 584391f75e2SVille Syrjälä enum transcoder cpu_transcoder = 585391f75e2SVille Syrjälä intel_pipe_to_cpu_transcoder(dev_priv, pipe); 586391f75e2SVille Syrjälä u32 htotal; 587391f75e2SVille Syrjälä 588391f75e2SVille Syrjälä htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; 589391f75e2SVille Syrjälä vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; 590391f75e2SVille Syrjälä 591391f75e2SVille Syrjälä vbl_start *= htotal; 592391f75e2SVille Syrjälä } 593391f75e2SVille Syrjälä 5949db4a9c7SJesse Barnes high_frame = PIPEFRAME(pipe); 5959db4a9c7SJesse Barnes low_frame = PIPEFRAMEPIXEL(pipe); 5965eddb70bSChris Wilson 5970a3e67a4SJesse Barnes /* 5980a3e67a4SJesse Barnes * High & low register fields aren't synchronized, so make sure 5990a3e67a4SJesse Barnes * we get a low value that's stable across two reads of the high 6000a3e67a4SJesse Barnes * register. 6010a3e67a4SJesse Barnes */ 6020a3e67a4SJesse Barnes do { 6035eddb70bSChris Wilson high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 604391f75e2SVille Syrjälä low = I915_READ(low_frame); 6055eddb70bSChris Wilson high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 6060a3e67a4SJesse Barnes } while (high1 != high2); 6070a3e67a4SJesse Barnes 6085eddb70bSChris Wilson high1 >>= PIPE_FRAME_HIGH_SHIFT; 609391f75e2SVille Syrjälä pixel = low & PIPE_PIXEL_MASK; 6105eddb70bSChris Wilson low >>= PIPE_FRAME_LOW_SHIFT; 611391f75e2SVille Syrjälä 612391f75e2SVille Syrjälä /* 613391f75e2SVille Syrjälä * The frame counter increments at beginning of active. 614391f75e2SVille Syrjälä * Cook up a vblank counter by also checking the pixel 615391f75e2SVille Syrjälä * counter against vblank start. 616391f75e2SVille Syrjälä */ 617edc08d0aSVille Syrjälä return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; 6180a3e67a4SJesse Barnes } 6190a3e67a4SJesse Barnes 620f71d4af4SJesse Barnes static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 6219880b7a5SJesse Barnes { 6229880b7a5SJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 6239db4a9c7SJesse Barnes int reg = PIPE_FRMCOUNT_GM45(pipe); 6249880b7a5SJesse Barnes 6259880b7a5SJesse Barnes if (!i915_pipe_enabled(dev, pipe)) { 62644d98a61SZhao Yakui DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 6279db4a9c7SJesse Barnes "pipe %c\n", pipe_name(pipe)); 6289880b7a5SJesse Barnes return 0; 6299880b7a5SJesse Barnes } 6309880b7a5SJesse Barnes 6319880b7a5SJesse Barnes return I915_READ(reg); 6329880b7a5SJesse Barnes } 6339880b7a5SJesse Barnes 634ad3543edSMario Kleiner /* raw reads, only for fast reads of display block, no need for forcewake etc. */ 635ad3543edSMario Kleiner #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) 636ad3543edSMario Kleiner #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) 637ad3543edSMario Kleiner 638095163baSVille Syrjälä static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe) 63954ddcbd2SVille Syrjälä { 64054ddcbd2SVille Syrjälä struct drm_i915_private *dev_priv = dev->dev_private; 64154ddcbd2SVille Syrjälä uint32_t status; 64254ddcbd2SVille Syrjälä 643095163baSVille Syrjälä if (INTEL_INFO(dev)->gen < 7) { 64454ddcbd2SVille Syrjälä status = pipe == PIPE_A ? 64554ddcbd2SVille Syrjälä DE_PIPEA_VBLANK : 64654ddcbd2SVille Syrjälä DE_PIPEB_VBLANK; 64754ddcbd2SVille Syrjälä } else { 64854ddcbd2SVille Syrjälä switch (pipe) { 64954ddcbd2SVille Syrjälä default: 65054ddcbd2SVille Syrjälä case PIPE_A: 65154ddcbd2SVille Syrjälä status = DE_PIPEA_VBLANK_IVB; 65254ddcbd2SVille Syrjälä break; 65354ddcbd2SVille Syrjälä case PIPE_B: 65454ddcbd2SVille Syrjälä status = DE_PIPEB_VBLANK_IVB; 65554ddcbd2SVille Syrjälä break; 65654ddcbd2SVille Syrjälä case PIPE_C: 65754ddcbd2SVille Syrjälä status = DE_PIPEC_VBLANK_IVB; 65854ddcbd2SVille Syrjälä break; 65954ddcbd2SVille Syrjälä } 66054ddcbd2SVille Syrjälä } 661ad3543edSMario Kleiner 662095163baSVille Syrjälä return __raw_i915_read32(dev_priv, DEISR) & status; 66354ddcbd2SVille Syrjälä } 66454ddcbd2SVille Syrjälä 665f71d4af4SJesse Barnes static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 666abca9e45SVille Syrjälä unsigned int flags, int *vpos, int *hpos, 667abca9e45SVille Syrjälä ktime_t *stime, ktime_t *etime) 6680af7e4dfSMario Kleiner { 669c2baf4b7SVille Syrjälä struct drm_i915_private *dev_priv = dev->dev_private; 670c2baf4b7SVille Syrjälä struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 671c2baf4b7SVille Syrjälä struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 672c2baf4b7SVille Syrjälä const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; 6733aa18df8SVille Syrjälä int position; 6740af7e4dfSMario Kleiner int vbl_start, vbl_end, htotal, vtotal; 6750af7e4dfSMario Kleiner bool in_vbl = true; 6760af7e4dfSMario Kleiner int ret = 0; 677ad3543edSMario Kleiner unsigned long irqflags; 6780af7e4dfSMario Kleiner 679c2baf4b7SVille Syrjälä if (!intel_crtc->active) { 6800af7e4dfSMario Kleiner DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " 6819db4a9c7SJesse Barnes "pipe %c\n", pipe_name(pipe)); 6820af7e4dfSMario Kleiner return 0; 6830af7e4dfSMario Kleiner } 6840af7e4dfSMario Kleiner 685c2baf4b7SVille Syrjälä htotal = mode->crtc_htotal; 686c2baf4b7SVille Syrjälä vtotal = mode->crtc_vtotal; 687c2baf4b7SVille Syrjälä vbl_start = mode->crtc_vblank_start; 688c2baf4b7SVille Syrjälä vbl_end = mode->crtc_vblank_end; 6890af7e4dfSMario Kleiner 690d31faf65SVille Syrjälä if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 691d31faf65SVille Syrjälä vbl_start = DIV_ROUND_UP(vbl_start, 2); 692d31faf65SVille Syrjälä vbl_end /= 2; 693d31faf65SVille Syrjälä vtotal /= 2; 694d31faf65SVille Syrjälä } 695d31faf65SVille Syrjälä 696c2baf4b7SVille Syrjälä ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; 697c2baf4b7SVille Syrjälä 698ad3543edSMario Kleiner /* 699ad3543edSMario Kleiner * Lock uncore.lock, as we will do multiple timing critical raw 700ad3543edSMario Kleiner * register reads, potentially with preemption disabled, so the 701ad3543edSMario Kleiner * following code must not block on uncore.lock. 702ad3543edSMario Kleiner */ 703ad3543edSMario Kleiner spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 704ad3543edSMario Kleiner 705ad3543edSMario Kleiner /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 706ad3543edSMario Kleiner 707ad3543edSMario Kleiner /* Get optional system timestamp before query. */ 708ad3543edSMario Kleiner if (stime) 709ad3543edSMario Kleiner *stime = ktime_get(); 710ad3543edSMario Kleiner 7117c06b08aSVille Syrjälä if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 7120af7e4dfSMario Kleiner /* No obvious pixelcount register. Only query vertical 7130af7e4dfSMario Kleiner * scanout position from Display scan line register. 7140af7e4dfSMario Kleiner */ 7157c06b08aSVille Syrjälä if (IS_GEN2(dev)) 716ad3543edSMario Kleiner position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; 7177c06b08aSVille Syrjälä else 718ad3543edSMario Kleiner position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; 71954ddcbd2SVille Syrjälä 720095163baSVille Syrjälä if (HAS_PCH_SPLIT(dev)) { 72154ddcbd2SVille Syrjälä /* 72254ddcbd2SVille Syrjälä * The scanline counter increments at the leading edge 72354ddcbd2SVille Syrjälä * of hsync, ie. it completely misses the active portion 72454ddcbd2SVille Syrjälä * of the line. Fix up the counter at both edges of vblank 72554ddcbd2SVille Syrjälä * to get a more accurate picture whether we're in vblank 72654ddcbd2SVille Syrjälä * or not. 72754ddcbd2SVille Syrjälä */ 728095163baSVille Syrjälä in_vbl = ilk_pipe_in_vblank_locked(dev, pipe); 72954ddcbd2SVille Syrjälä if ((in_vbl && position == vbl_start - 1) || 73054ddcbd2SVille Syrjälä (!in_vbl && position == vbl_end - 1)) 73154ddcbd2SVille Syrjälä position = (position + 1) % vtotal; 7320af7e4dfSMario Kleiner } else { 733095163baSVille Syrjälä /* 734095163baSVille Syrjälä * ISR vblank status bits don't work the way we'd want 735095163baSVille Syrjälä * them to work on non-PCH platforms (for 736095163baSVille Syrjälä * ilk_pipe_in_vblank_locked()), and there doesn't 737095163baSVille Syrjälä * appear any other way to determine if we're currently 738095163baSVille Syrjälä * in vblank. 739095163baSVille Syrjälä * 740095163baSVille Syrjälä * Instead let's assume that we're already in vblank if 741095163baSVille Syrjälä * we got called from the vblank interrupt and the 742095163baSVille Syrjälä * scanline counter value indicates that we're on the 743095163baSVille Syrjälä * line just prior to vblank start. This should result 744095163baSVille Syrjälä * in the correct answer, unless the vblank interrupt 745095163baSVille Syrjälä * delivery really got delayed for almost exactly one 746095163baSVille Syrjälä * full frame/field. 747095163baSVille Syrjälä */ 748095163baSVille Syrjälä if (flags & DRM_CALLED_FROM_VBLIRQ && 749095163baSVille Syrjälä position == vbl_start - 1) { 750095163baSVille Syrjälä position = (position + 1) % vtotal; 751095163baSVille Syrjälä 752095163baSVille Syrjälä /* Signal this correction as "applied". */ 753095163baSVille Syrjälä ret |= 0x8; 754095163baSVille Syrjälä } 755095163baSVille Syrjälä } 756095163baSVille Syrjälä } else { 7570af7e4dfSMario Kleiner /* Have access to pixelcount since start of frame. 7580af7e4dfSMario Kleiner * We can split this into vertical and horizontal 7590af7e4dfSMario Kleiner * scanout position. 7600af7e4dfSMario Kleiner */ 761ad3543edSMario Kleiner position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 7620af7e4dfSMario Kleiner 7633aa18df8SVille Syrjälä /* convert to pixel counts */ 7643aa18df8SVille Syrjälä vbl_start *= htotal; 7653aa18df8SVille Syrjälä vbl_end *= htotal; 7663aa18df8SVille Syrjälä vtotal *= htotal; 7673aa18df8SVille Syrjälä } 7683aa18df8SVille Syrjälä 769ad3543edSMario Kleiner /* Get optional system timestamp after query. */ 770ad3543edSMario Kleiner if (etime) 771ad3543edSMario Kleiner *etime = ktime_get(); 772ad3543edSMario Kleiner 773ad3543edSMario Kleiner /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 774ad3543edSMario Kleiner 775ad3543edSMario Kleiner spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 776ad3543edSMario Kleiner 7773aa18df8SVille Syrjälä in_vbl = position >= vbl_start && position < vbl_end; 7783aa18df8SVille Syrjälä 7793aa18df8SVille Syrjälä /* 7803aa18df8SVille Syrjälä * While in vblank, position will be negative 7813aa18df8SVille Syrjälä * counting up towards 0 at vbl_end. And outside 7823aa18df8SVille Syrjälä * vblank, position will be positive counting 7833aa18df8SVille Syrjälä * up since vbl_end. 7843aa18df8SVille Syrjälä */ 7853aa18df8SVille Syrjälä if (position >= vbl_start) 7863aa18df8SVille Syrjälä position -= vbl_end; 7873aa18df8SVille Syrjälä else 7883aa18df8SVille Syrjälä position += vtotal - vbl_end; 7893aa18df8SVille Syrjälä 7907c06b08aSVille Syrjälä if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 7913aa18df8SVille Syrjälä *vpos = position; 7923aa18df8SVille Syrjälä *hpos = 0; 7933aa18df8SVille Syrjälä } else { 7940af7e4dfSMario Kleiner *vpos = position / htotal; 7950af7e4dfSMario Kleiner *hpos = position - (*vpos * htotal); 7960af7e4dfSMario Kleiner } 7970af7e4dfSMario Kleiner 7980af7e4dfSMario Kleiner /* In vblank? */ 7990af7e4dfSMario Kleiner if (in_vbl) 8000af7e4dfSMario Kleiner ret |= DRM_SCANOUTPOS_INVBL; 8010af7e4dfSMario Kleiner 8020af7e4dfSMario Kleiner return ret; 8030af7e4dfSMario Kleiner } 8040af7e4dfSMario Kleiner 805f71d4af4SJesse Barnes static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 8060af7e4dfSMario Kleiner int *max_error, 8070af7e4dfSMario Kleiner struct timeval *vblank_time, 8080af7e4dfSMario Kleiner unsigned flags) 8090af7e4dfSMario Kleiner { 8104041b853SChris Wilson struct drm_crtc *crtc; 8110af7e4dfSMario Kleiner 8127eb552aeSBen Widawsky if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { 8134041b853SChris Wilson DRM_ERROR("Invalid crtc %d\n", pipe); 8140af7e4dfSMario Kleiner return -EINVAL; 8150af7e4dfSMario Kleiner } 8160af7e4dfSMario Kleiner 8170af7e4dfSMario Kleiner /* Get drm_crtc to timestamp: */ 8184041b853SChris Wilson crtc = intel_get_crtc_for_pipe(dev, pipe); 8194041b853SChris Wilson if (crtc == NULL) { 8204041b853SChris Wilson DRM_ERROR("Invalid crtc %d\n", pipe); 8214041b853SChris Wilson return -EINVAL; 8224041b853SChris Wilson } 8234041b853SChris Wilson 8244041b853SChris Wilson if (!crtc->enabled) { 8254041b853SChris Wilson DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 8264041b853SChris Wilson return -EBUSY; 8274041b853SChris Wilson } 8280af7e4dfSMario Kleiner 8290af7e4dfSMario Kleiner /* Helper routine in DRM core does all the work: */ 8304041b853SChris Wilson return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 8314041b853SChris Wilson vblank_time, flags, 8327da903efSVille Syrjälä crtc, 8337da903efSVille Syrjälä &to_intel_crtc(crtc)->config.adjusted_mode); 8340af7e4dfSMario Kleiner } 8350af7e4dfSMario Kleiner 83667c347ffSJani Nikula static bool intel_hpd_irq_event(struct drm_device *dev, 83767c347ffSJani Nikula struct drm_connector *connector) 838321a1b30SEgbert Eich { 839321a1b30SEgbert Eich enum drm_connector_status old_status; 840321a1b30SEgbert Eich 841321a1b30SEgbert Eich WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 842321a1b30SEgbert Eich old_status = connector->status; 843321a1b30SEgbert Eich 844321a1b30SEgbert Eich connector->status = connector->funcs->detect(connector, false); 84567c347ffSJani Nikula if (old_status == connector->status) 84667c347ffSJani Nikula return false; 84767c347ffSJani Nikula 84867c347ffSJani Nikula DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", 849321a1b30SEgbert Eich connector->base.id, 850321a1b30SEgbert Eich drm_get_connector_name(connector), 85167c347ffSJani Nikula drm_get_connector_status_name(old_status), 85267c347ffSJani Nikula drm_get_connector_status_name(connector->status)); 85367c347ffSJani Nikula 85467c347ffSJani Nikula return true; 855321a1b30SEgbert Eich } 856321a1b30SEgbert Eich 8575ca58282SJesse Barnes /* 8585ca58282SJesse Barnes * Handle hotplug events outside the interrupt handler proper. 8595ca58282SJesse Barnes */ 860ac4c16c5SEgbert Eich #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) 861ac4c16c5SEgbert Eich 8625ca58282SJesse Barnes static void i915_hotplug_work_func(struct work_struct *work) 8635ca58282SJesse Barnes { 8645ca58282SJesse Barnes drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 8655ca58282SJesse Barnes hotplug_work); 8665ca58282SJesse Barnes struct drm_device *dev = dev_priv->dev; 867c31c4ba3SKeith Packard struct drm_mode_config *mode_config = &dev->mode_config; 868cd569aedSEgbert Eich struct intel_connector *intel_connector; 869cd569aedSEgbert Eich struct intel_encoder *intel_encoder; 870cd569aedSEgbert Eich struct drm_connector *connector; 871cd569aedSEgbert Eich unsigned long irqflags; 872cd569aedSEgbert Eich bool hpd_disabled = false; 873321a1b30SEgbert Eich bool changed = false; 874142e2398SEgbert Eich u32 hpd_event_bits; 8755ca58282SJesse Barnes 87652d7ecedSDaniel Vetter /* HPD irq before everything is fully set up. */ 87752d7ecedSDaniel Vetter if (!dev_priv->enable_hotplug_processing) 87852d7ecedSDaniel Vetter return; 87952d7ecedSDaniel Vetter 880a65e34c7SKeith Packard mutex_lock(&mode_config->mutex); 881e67189abSJesse Barnes DRM_DEBUG_KMS("running encoder hotplug functions\n"); 882e67189abSJesse Barnes 883cd569aedSEgbert Eich spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 884142e2398SEgbert Eich 885142e2398SEgbert Eich hpd_event_bits = dev_priv->hpd_event_bits; 886142e2398SEgbert Eich dev_priv->hpd_event_bits = 0; 887cd569aedSEgbert Eich list_for_each_entry(connector, &mode_config->connector_list, head) { 888cd569aedSEgbert Eich intel_connector = to_intel_connector(connector); 889cd569aedSEgbert Eich intel_encoder = intel_connector->encoder; 890cd569aedSEgbert Eich if (intel_encoder->hpd_pin > HPD_NONE && 891cd569aedSEgbert Eich dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && 892cd569aedSEgbert Eich connector->polled == DRM_CONNECTOR_POLL_HPD) { 893cd569aedSEgbert Eich DRM_INFO("HPD interrupt storm detected on connector %s: " 894cd569aedSEgbert Eich "switching from hotplug detection to polling\n", 895cd569aedSEgbert Eich drm_get_connector_name(connector)); 896cd569aedSEgbert Eich dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; 897cd569aedSEgbert Eich connector->polled = DRM_CONNECTOR_POLL_CONNECT 898cd569aedSEgbert Eich | DRM_CONNECTOR_POLL_DISCONNECT; 899cd569aedSEgbert Eich hpd_disabled = true; 900cd569aedSEgbert Eich } 901142e2398SEgbert Eich if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { 902142e2398SEgbert Eich DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", 903142e2398SEgbert Eich drm_get_connector_name(connector), intel_encoder->hpd_pin); 904142e2398SEgbert Eich } 905cd569aedSEgbert Eich } 906cd569aedSEgbert Eich /* if there were no outputs to poll, poll was disabled, 907cd569aedSEgbert Eich * therefore make sure it's enabled when disabling HPD on 908cd569aedSEgbert Eich * some connectors */ 909ac4c16c5SEgbert Eich if (hpd_disabled) { 910cd569aedSEgbert Eich drm_kms_helper_poll_enable(dev); 911ac4c16c5SEgbert Eich mod_timer(&dev_priv->hotplug_reenable_timer, 912ac4c16c5SEgbert Eich jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); 913ac4c16c5SEgbert Eich } 914cd569aedSEgbert Eich 915cd569aedSEgbert Eich spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 916cd569aedSEgbert Eich 917321a1b30SEgbert Eich list_for_each_entry(connector, &mode_config->connector_list, head) { 918321a1b30SEgbert Eich intel_connector = to_intel_connector(connector); 919321a1b30SEgbert Eich intel_encoder = intel_connector->encoder; 920321a1b30SEgbert Eich if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { 921cd569aedSEgbert Eich if (intel_encoder->hot_plug) 922cd569aedSEgbert Eich intel_encoder->hot_plug(intel_encoder); 923321a1b30SEgbert Eich if (intel_hpd_irq_event(dev, connector)) 924321a1b30SEgbert Eich changed = true; 925321a1b30SEgbert Eich } 926321a1b30SEgbert Eich } 92740ee3381SKeith Packard mutex_unlock(&mode_config->mutex); 92840ee3381SKeith Packard 929321a1b30SEgbert Eich if (changed) 930321a1b30SEgbert Eich drm_kms_helper_hotplug_event(dev); 9315ca58282SJesse Barnes } 9325ca58282SJesse Barnes 9333ca1ccedSVille Syrjälä static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv) 9343ca1ccedSVille Syrjälä { 9353ca1ccedSVille Syrjälä del_timer_sync(&dev_priv->hotplug_reenable_timer); 9363ca1ccedSVille Syrjälä } 9373ca1ccedSVille Syrjälä 938d0ecd7e2SDaniel Vetter static void ironlake_rps_change_irq_handler(struct drm_device *dev) 939f97108d1SJesse Barnes { 940f97108d1SJesse Barnes drm_i915_private_t *dev_priv = dev->dev_private; 941b5b72e89SMatthew Garrett u32 busy_up, busy_down, max_avg, min_avg; 9429270388eSDaniel Vetter u8 new_delay; 9439270388eSDaniel Vetter 944d0ecd7e2SDaniel Vetter spin_lock(&mchdev_lock); 945f97108d1SJesse Barnes 94673edd18fSDaniel Vetter I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); 94773edd18fSDaniel Vetter 94820e4d407SDaniel Vetter new_delay = dev_priv->ips.cur_delay; 9499270388eSDaniel Vetter 9507648fa99SJesse Barnes I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); 951b5b72e89SMatthew Garrett busy_up = I915_READ(RCPREVBSYTUPAVG); 952b5b72e89SMatthew Garrett busy_down = I915_READ(RCPREVBSYTDNAVG); 953f97108d1SJesse Barnes max_avg = I915_READ(RCBMAXAVG); 954f97108d1SJesse Barnes min_avg = I915_READ(RCBMINAVG); 955f97108d1SJesse Barnes 956f97108d1SJesse Barnes /* Handle RCS change request from hw */ 957b5b72e89SMatthew Garrett if (busy_up > max_avg) { 95820e4d407SDaniel Vetter if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) 95920e4d407SDaniel Vetter new_delay = dev_priv->ips.cur_delay - 1; 96020e4d407SDaniel Vetter if (new_delay < dev_priv->ips.max_delay) 96120e4d407SDaniel Vetter new_delay = dev_priv->ips.max_delay; 962b5b72e89SMatthew Garrett } else if (busy_down < min_avg) { 96320e4d407SDaniel Vetter if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) 96420e4d407SDaniel Vetter new_delay = dev_priv->ips.cur_delay + 1; 96520e4d407SDaniel Vetter if (new_delay > dev_priv->ips.min_delay) 96620e4d407SDaniel Vetter new_delay = dev_priv->ips.min_delay; 967f97108d1SJesse Barnes } 968f97108d1SJesse Barnes 9697648fa99SJesse Barnes if (ironlake_set_drps(dev, new_delay)) 97020e4d407SDaniel Vetter dev_priv->ips.cur_delay = new_delay; 971f97108d1SJesse Barnes 972d0ecd7e2SDaniel Vetter spin_unlock(&mchdev_lock); 9739270388eSDaniel Vetter 974f97108d1SJesse Barnes return; 975f97108d1SJesse Barnes } 976f97108d1SJesse Barnes 977549f7365SChris Wilson static void notify_ring(struct drm_device *dev, 978549f7365SChris Wilson struct intel_ring_buffer *ring) 979549f7365SChris Wilson { 980475553deSChris Wilson if (ring->obj == NULL) 981475553deSChris Wilson return; 982475553deSChris Wilson 983814e9b57SChris Wilson trace_i915_gem_request_complete(ring); 9849862e600SChris Wilson 985549f7365SChris Wilson wake_up_all(&ring->irq_queue); 98610cd45b6SMika Kuoppala i915_queue_hangcheck(dev); 987549f7365SChris Wilson } 988549f7365SChris Wilson 9894912d041SBen Widawsky static void gen6_pm_rps_work(struct work_struct *work) 9903b8d8d91SJesse Barnes { 9914912d041SBen Widawsky drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 992c6a828d3SDaniel Vetter rps.work); 993edbfdb45SPaulo Zanoni u32 pm_iir; 994dd75fdc8SChris Wilson int new_delay, adj; 9953b8d8d91SJesse Barnes 99659cdb63dSDaniel Vetter spin_lock_irq(&dev_priv->irq_lock); 997c6a828d3SDaniel Vetter pm_iir = dev_priv->rps.pm_iir; 998c6a828d3SDaniel Vetter dev_priv->rps.pm_iir = 0; 9994848405cSBen Widawsky /* Make sure not to corrupt PMIMR state used by ringbuffer code */ 1000edbfdb45SPaulo Zanoni snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); 100159cdb63dSDaniel Vetter spin_unlock_irq(&dev_priv->irq_lock); 10024912d041SBen Widawsky 100360611c13SPaulo Zanoni /* Make sure we didn't queue anything we're not going to process. */ 100460611c13SPaulo Zanoni WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS); 100560611c13SPaulo Zanoni 10064848405cSBen Widawsky if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) 10073b8d8d91SJesse Barnes return; 10083b8d8d91SJesse Barnes 10094fc688ceSJesse Barnes mutex_lock(&dev_priv->rps.hw_lock); 10107b9e0ae6SChris Wilson 1011dd75fdc8SChris Wilson adj = dev_priv->rps.last_adj; 10127425034aSVille Syrjälä if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 1013dd75fdc8SChris Wilson if (adj > 0) 1014dd75fdc8SChris Wilson adj *= 2; 1015dd75fdc8SChris Wilson else 1016dd75fdc8SChris Wilson adj = 1; 1017dd75fdc8SChris Wilson new_delay = dev_priv->rps.cur_delay + adj; 10187425034aSVille Syrjälä 10197425034aSVille Syrjälä /* 10207425034aSVille Syrjälä * For better performance, jump directly 10217425034aSVille Syrjälä * to RPe if we're below it. 10227425034aSVille Syrjälä */ 1023dd75fdc8SChris Wilson if (new_delay < dev_priv->rps.rpe_delay) 10247425034aSVille Syrjälä new_delay = dev_priv->rps.rpe_delay; 1025dd75fdc8SChris Wilson } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { 1026dd75fdc8SChris Wilson if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) 1027dd75fdc8SChris Wilson new_delay = dev_priv->rps.rpe_delay; 1028dd75fdc8SChris Wilson else 1029dd75fdc8SChris Wilson new_delay = dev_priv->rps.min_delay; 1030dd75fdc8SChris Wilson adj = 0; 1031dd75fdc8SChris Wilson } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { 1032dd75fdc8SChris Wilson if (adj < 0) 1033dd75fdc8SChris Wilson adj *= 2; 1034dd75fdc8SChris Wilson else 1035dd75fdc8SChris Wilson adj = -1; 1036dd75fdc8SChris Wilson new_delay = dev_priv->rps.cur_delay + adj; 1037dd75fdc8SChris Wilson } else { /* unknown event */ 1038dd75fdc8SChris Wilson new_delay = dev_priv->rps.cur_delay; 1039dd75fdc8SChris Wilson } 10403b8d8d91SJesse Barnes 104179249636SBen Widawsky /* sysfs frequency interfaces may have snuck in while servicing the 104279249636SBen Widawsky * interrupt 104379249636SBen Widawsky */ 10441272e7b8SVille Syrjälä new_delay = clamp_t(int, new_delay, 10451272e7b8SVille Syrjälä dev_priv->rps.min_delay, dev_priv->rps.max_delay); 1046dd75fdc8SChris Wilson dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; 1047dd75fdc8SChris Wilson 10480a073b84SJesse Barnes if (IS_VALLEYVIEW(dev_priv->dev)) 10490a073b84SJesse Barnes valleyview_set_rps(dev_priv->dev, new_delay); 10500a073b84SJesse Barnes else 10514912d041SBen Widawsky gen6_set_rps(dev_priv->dev, new_delay); 10523b8d8d91SJesse Barnes 10534fc688ceSJesse Barnes mutex_unlock(&dev_priv->rps.hw_lock); 10543b8d8d91SJesse Barnes } 10553b8d8d91SJesse Barnes 1056e3689190SBen Widawsky 1057e3689190SBen Widawsky /** 1058e3689190SBen Widawsky * ivybridge_parity_work - Workqueue called when a parity error interrupt 1059e3689190SBen Widawsky * occurred. 1060e3689190SBen Widawsky * @work: workqueue struct 1061e3689190SBen Widawsky * 1062e3689190SBen Widawsky * Doesn't actually do anything except notify userspace. As a consequence of 1063e3689190SBen Widawsky * this event, userspace should try to remap the bad rows since statistically 1064e3689190SBen Widawsky * it is likely the same row is more likely to go bad again. 1065e3689190SBen Widawsky */ 1066e3689190SBen Widawsky static void ivybridge_parity_work(struct work_struct *work) 1067e3689190SBen Widawsky { 1068e3689190SBen Widawsky drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 1069a4da4fa4SDaniel Vetter l3_parity.error_work); 1070e3689190SBen Widawsky u32 error_status, row, bank, subbank; 107135a85ac6SBen Widawsky char *parity_event[6]; 1072e3689190SBen Widawsky uint32_t misccpctl; 1073e3689190SBen Widawsky unsigned long flags; 107435a85ac6SBen Widawsky uint8_t slice = 0; 1075e3689190SBen Widawsky 1076e3689190SBen Widawsky /* We must turn off DOP level clock gating to access the L3 registers. 1077e3689190SBen Widawsky * In order to prevent a get/put style interface, acquire struct mutex 1078e3689190SBen Widawsky * any time we access those registers. 1079e3689190SBen Widawsky */ 1080e3689190SBen Widawsky mutex_lock(&dev_priv->dev->struct_mutex); 1081e3689190SBen Widawsky 108235a85ac6SBen Widawsky /* If we've screwed up tracking, just let the interrupt fire again */ 108335a85ac6SBen Widawsky if (WARN_ON(!dev_priv->l3_parity.which_slice)) 108435a85ac6SBen Widawsky goto out; 108535a85ac6SBen Widawsky 1086e3689190SBen Widawsky misccpctl = I915_READ(GEN7_MISCCPCTL); 1087e3689190SBen Widawsky I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 1088e3689190SBen Widawsky POSTING_READ(GEN7_MISCCPCTL); 1089e3689190SBen Widawsky 109035a85ac6SBen Widawsky while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { 109135a85ac6SBen Widawsky u32 reg; 109235a85ac6SBen Widawsky 109335a85ac6SBen Widawsky slice--; 109435a85ac6SBen Widawsky if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) 109535a85ac6SBen Widawsky break; 109635a85ac6SBen Widawsky 109735a85ac6SBen Widawsky dev_priv->l3_parity.which_slice &= ~(1<<slice); 109835a85ac6SBen Widawsky 109935a85ac6SBen Widawsky reg = GEN7_L3CDERRST1 + (slice * 0x200); 110035a85ac6SBen Widawsky 110135a85ac6SBen Widawsky error_status = I915_READ(reg); 1102e3689190SBen Widawsky row = GEN7_PARITY_ERROR_ROW(error_status); 1103e3689190SBen Widawsky bank = GEN7_PARITY_ERROR_BANK(error_status); 1104e3689190SBen Widawsky subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 1105e3689190SBen Widawsky 110635a85ac6SBen Widawsky I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); 110735a85ac6SBen Widawsky POSTING_READ(reg); 1108e3689190SBen Widawsky 1109cce723edSBen Widawsky parity_event[0] = I915_L3_PARITY_UEVENT "=1"; 1110e3689190SBen Widawsky parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); 1111e3689190SBen Widawsky parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); 1112e3689190SBen Widawsky parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); 111335a85ac6SBen Widawsky parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); 111435a85ac6SBen Widawsky parity_event[5] = NULL; 1115e3689190SBen Widawsky 11165bdebb18SDave Airlie kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, 1117e3689190SBen Widawsky KOBJ_CHANGE, parity_event); 1118e3689190SBen Widawsky 111935a85ac6SBen Widawsky DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", 112035a85ac6SBen Widawsky slice, row, bank, subbank); 1121e3689190SBen Widawsky 112235a85ac6SBen Widawsky kfree(parity_event[4]); 1123e3689190SBen Widawsky kfree(parity_event[3]); 1124e3689190SBen Widawsky kfree(parity_event[2]); 1125e3689190SBen Widawsky kfree(parity_event[1]); 1126e3689190SBen Widawsky } 1127e3689190SBen Widawsky 112835a85ac6SBen Widawsky I915_WRITE(GEN7_MISCCPCTL, misccpctl); 112935a85ac6SBen Widawsky 113035a85ac6SBen Widawsky out: 113135a85ac6SBen Widawsky WARN_ON(dev_priv->l3_parity.which_slice); 113235a85ac6SBen Widawsky spin_lock_irqsave(&dev_priv->irq_lock, flags); 113335a85ac6SBen Widawsky ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); 113435a85ac6SBen Widawsky spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 113535a85ac6SBen Widawsky 113635a85ac6SBen Widawsky mutex_unlock(&dev_priv->dev->struct_mutex); 113735a85ac6SBen Widawsky } 113835a85ac6SBen Widawsky 113935a85ac6SBen Widawsky static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) 1140e3689190SBen Widawsky { 1141e3689190SBen Widawsky drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1142e3689190SBen Widawsky 1143040d2baaSBen Widawsky if (!HAS_L3_DPF(dev)) 1144e3689190SBen Widawsky return; 1145e3689190SBen Widawsky 1146d0ecd7e2SDaniel Vetter spin_lock(&dev_priv->irq_lock); 114735a85ac6SBen Widawsky ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); 1148d0ecd7e2SDaniel Vetter spin_unlock(&dev_priv->irq_lock); 1149e3689190SBen Widawsky 115035a85ac6SBen Widawsky iir &= GT_PARITY_ERROR(dev); 115135a85ac6SBen Widawsky if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) 115235a85ac6SBen Widawsky dev_priv->l3_parity.which_slice |= 1 << 1; 115335a85ac6SBen Widawsky 115435a85ac6SBen Widawsky if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) 115535a85ac6SBen Widawsky dev_priv->l3_parity.which_slice |= 1 << 0; 115635a85ac6SBen Widawsky 1157a4da4fa4SDaniel Vetter queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); 1158e3689190SBen Widawsky } 1159e3689190SBen Widawsky 1160f1af8fc1SPaulo Zanoni static void ilk_gt_irq_handler(struct drm_device *dev, 1161f1af8fc1SPaulo Zanoni struct drm_i915_private *dev_priv, 1162f1af8fc1SPaulo Zanoni u32 gt_iir) 1163f1af8fc1SPaulo Zanoni { 1164f1af8fc1SPaulo Zanoni if (gt_iir & 1165f1af8fc1SPaulo Zanoni (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) 1166f1af8fc1SPaulo Zanoni notify_ring(dev, &dev_priv->ring[RCS]); 1167f1af8fc1SPaulo Zanoni if (gt_iir & ILK_BSD_USER_INTERRUPT) 1168f1af8fc1SPaulo Zanoni notify_ring(dev, &dev_priv->ring[VCS]); 1169f1af8fc1SPaulo Zanoni } 1170f1af8fc1SPaulo Zanoni 1171e7b4c6b1SDaniel Vetter static void snb_gt_irq_handler(struct drm_device *dev, 1172e7b4c6b1SDaniel Vetter struct drm_i915_private *dev_priv, 1173e7b4c6b1SDaniel Vetter u32 gt_iir) 1174e7b4c6b1SDaniel Vetter { 1175e7b4c6b1SDaniel Vetter 1176cc609d5dSBen Widawsky if (gt_iir & 1177cc609d5dSBen Widawsky (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) 1178e7b4c6b1SDaniel Vetter notify_ring(dev, &dev_priv->ring[RCS]); 1179cc609d5dSBen Widawsky if (gt_iir & GT_BSD_USER_INTERRUPT) 1180e7b4c6b1SDaniel Vetter notify_ring(dev, &dev_priv->ring[VCS]); 1181cc609d5dSBen Widawsky if (gt_iir & GT_BLT_USER_INTERRUPT) 1182e7b4c6b1SDaniel Vetter notify_ring(dev, &dev_priv->ring[BCS]); 1183e7b4c6b1SDaniel Vetter 1184cc609d5dSBen Widawsky if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | 1185cc609d5dSBen Widawsky GT_BSD_CS_ERROR_INTERRUPT | 1186cc609d5dSBen Widawsky GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { 1187e7b4c6b1SDaniel Vetter DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); 1188e7b4c6b1SDaniel Vetter i915_handle_error(dev, false); 1189e7b4c6b1SDaniel Vetter } 1190e3689190SBen Widawsky 119135a85ac6SBen Widawsky if (gt_iir & GT_PARITY_ERROR(dev)) 119235a85ac6SBen Widawsky ivybridge_parity_error_irq_handler(dev, gt_iir); 1193e7b4c6b1SDaniel Vetter } 1194e7b4c6b1SDaniel Vetter 1195abd58f01SBen Widawsky static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, 1196abd58f01SBen Widawsky struct drm_i915_private *dev_priv, 1197abd58f01SBen Widawsky u32 master_ctl) 1198abd58f01SBen Widawsky { 1199abd58f01SBen Widawsky u32 rcs, bcs, vcs; 1200abd58f01SBen Widawsky uint32_t tmp = 0; 1201abd58f01SBen Widawsky irqreturn_t ret = IRQ_NONE; 1202abd58f01SBen Widawsky 1203abd58f01SBen Widawsky if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { 1204abd58f01SBen Widawsky tmp = I915_READ(GEN8_GT_IIR(0)); 1205abd58f01SBen Widawsky if (tmp) { 1206abd58f01SBen Widawsky ret = IRQ_HANDLED; 1207abd58f01SBen Widawsky rcs = tmp >> GEN8_RCS_IRQ_SHIFT; 1208abd58f01SBen Widawsky bcs = tmp >> GEN8_BCS_IRQ_SHIFT; 1209abd58f01SBen Widawsky if (rcs & GT_RENDER_USER_INTERRUPT) 1210abd58f01SBen Widawsky notify_ring(dev, &dev_priv->ring[RCS]); 1211abd58f01SBen Widawsky if (bcs & GT_RENDER_USER_INTERRUPT) 1212abd58f01SBen Widawsky notify_ring(dev, &dev_priv->ring[BCS]); 1213abd58f01SBen Widawsky I915_WRITE(GEN8_GT_IIR(0), tmp); 1214abd58f01SBen Widawsky } else 1215abd58f01SBen Widawsky DRM_ERROR("The master control interrupt lied (GT0)!\n"); 1216abd58f01SBen Widawsky } 1217abd58f01SBen Widawsky 1218abd58f01SBen Widawsky if (master_ctl & GEN8_GT_VCS1_IRQ) { 1219abd58f01SBen Widawsky tmp = I915_READ(GEN8_GT_IIR(1)); 1220abd58f01SBen Widawsky if (tmp) { 1221abd58f01SBen Widawsky ret = IRQ_HANDLED; 1222abd58f01SBen Widawsky vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; 1223abd58f01SBen Widawsky if (vcs & GT_RENDER_USER_INTERRUPT) 1224abd58f01SBen Widawsky notify_ring(dev, &dev_priv->ring[VCS]); 1225abd58f01SBen Widawsky I915_WRITE(GEN8_GT_IIR(1), tmp); 1226abd58f01SBen Widawsky } else 1227abd58f01SBen Widawsky DRM_ERROR("The master control interrupt lied (GT1)!\n"); 1228abd58f01SBen Widawsky } 1229abd58f01SBen Widawsky 1230abd58f01SBen Widawsky if (master_ctl & GEN8_GT_VECS_IRQ) { 1231abd58f01SBen Widawsky tmp = I915_READ(GEN8_GT_IIR(3)); 1232abd58f01SBen Widawsky if (tmp) { 1233abd58f01SBen Widawsky ret = IRQ_HANDLED; 1234abd58f01SBen Widawsky vcs = tmp >> GEN8_VECS_IRQ_SHIFT; 1235abd58f01SBen Widawsky if (vcs & GT_RENDER_USER_INTERRUPT) 1236abd58f01SBen Widawsky notify_ring(dev, &dev_priv->ring[VECS]); 1237abd58f01SBen Widawsky I915_WRITE(GEN8_GT_IIR(3), tmp); 1238abd58f01SBen Widawsky } else 1239abd58f01SBen Widawsky DRM_ERROR("The master control interrupt lied (GT3)!\n"); 1240abd58f01SBen Widawsky } 1241abd58f01SBen Widawsky 1242abd58f01SBen Widawsky return ret; 1243abd58f01SBen Widawsky } 1244abd58f01SBen Widawsky 1245b543fb04SEgbert Eich #define HPD_STORM_DETECT_PERIOD 1000 1246b543fb04SEgbert Eich #define HPD_STORM_THRESHOLD 5 1247b543fb04SEgbert Eich 124810a504deSDaniel Vetter static inline void intel_hpd_irq_handler(struct drm_device *dev, 1249b543fb04SEgbert Eich u32 hotplug_trigger, 1250b543fb04SEgbert Eich const u32 *hpd) 1251b543fb04SEgbert Eich { 1252b543fb04SEgbert Eich drm_i915_private_t *dev_priv = dev->dev_private; 1253b543fb04SEgbert Eich int i; 125410a504deSDaniel Vetter bool storm_detected = false; 1255b543fb04SEgbert Eich 125691d131d2SDaniel Vetter if (!hotplug_trigger) 125791d131d2SDaniel Vetter return; 125891d131d2SDaniel Vetter 1259cc9bd499SImre Deak DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 1260cc9bd499SImre Deak hotplug_trigger); 1261cc9bd499SImre Deak 1262b5ea2d56SDaniel Vetter spin_lock(&dev_priv->irq_lock); 1263b543fb04SEgbert Eich for (i = 1; i < HPD_NUM_PINS; i++) { 1264821450c6SEgbert Eich 12653432087eSChris Wilson WARN_ONCE(hpd[i] & hotplug_trigger && 12668b5565b8SChris Wilson dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED, 1267cba1c073SChris Wilson "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", 1268cba1c073SChris Wilson hotplug_trigger, i, hpd[i]); 1269b8f102e8SEgbert Eich 1270b543fb04SEgbert Eich if (!(hpd[i] & hotplug_trigger) || 1271b543fb04SEgbert Eich dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) 1272b543fb04SEgbert Eich continue; 1273b543fb04SEgbert Eich 1274bc5ead8cSJani Nikula dev_priv->hpd_event_bits |= (1 << i); 1275b543fb04SEgbert Eich if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, 1276b543fb04SEgbert Eich dev_priv->hpd_stats[i].hpd_last_jiffies 1277b543fb04SEgbert Eich + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { 1278b543fb04SEgbert Eich dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; 1279b543fb04SEgbert Eich dev_priv->hpd_stats[i].hpd_cnt = 0; 1280b8f102e8SEgbert Eich DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); 1281b543fb04SEgbert Eich } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { 1282b543fb04SEgbert Eich dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; 1283142e2398SEgbert Eich dev_priv->hpd_event_bits &= ~(1 << i); 1284b543fb04SEgbert Eich DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); 128510a504deSDaniel Vetter storm_detected = true; 1286b543fb04SEgbert Eich } else { 1287b543fb04SEgbert Eich dev_priv->hpd_stats[i].hpd_cnt++; 1288b8f102e8SEgbert Eich DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, 1289b8f102e8SEgbert Eich dev_priv->hpd_stats[i].hpd_cnt); 1290b543fb04SEgbert Eich } 1291b543fb04SEgbert Eich } 1292b543fb04SEgbert Eich 129310a504deSDaniel Vetter if (storm_detected) 129410a504deSDaniel Vetter dev_priv->display.hpd_irq_setup(dev); 1295b5ea2d56SDaniel Vetter spin_unlock(&dev_priv->irq_lock); 12965876fa0dSDaniel Vetter 1297645416f5SDaniel Vetter /* 1298645416f5SDaniel Vetter * Our hotplug handler can grab modeset locks (by calling down into the 1299645416f5SDaniel Vetter * fb helpers). Hence it must not be run on our own dev-priv->wq work 1300645416f5SDaniel Vetter * queue for otherwise the flush_work in the pageflip code will 1301645416f5SDaniel Vetter * deadlock. 1302645416f5SDaniel Vetter */ 1303645416f5SDaniel Vetter schedule_work(&dev_priv->hotplug_work); 1304b543fb04SEgbert Eich } 1305b543fb04SEgbert Eich 1306515ac2bbSDaniel Vetter static void gmbus_irq_handler(struct drm_device *dev) 1307515ac2bbSDaniel Vetter { 130828c70f16SDaniel Vetter struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; 130928c70f16SDaniel Vetter 131028c70f16SDaniel Vetter wake_up_all(&dev_priv->gmbus_wait_queue); 1311515ac2bbSDaniel Vetter } 1312515ac2bbSDaniel Vetter 1313ce99c256SDaniel Vetter static void dp_aux_irq_handler(struct drm_device *dev) 1314ce99c256SDaniel Vetter { 13159ee32feaSDaniel Vetter struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; 13169ee32feaSDaniel Vetter 13179ee32feaSDaniel Vetter wake_up_all(&dev_priv->gmbus_wait_queue); 1318ce99c256SDaniel Vetter } 1319ce99c256SDaniel Vetter 13208bf1e9f1SShuang He #if defined(CONFIG_DEBUG_FS) 1321277de95eSDaniel Vetter static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, 1322eba94eb9SDaniel Vetter uint32_t crc0, uint32_t crc1, 1323eba94eb9SDaniel Vetter uint32_t crc2, uint32_t crc3, 13248bc5e955SDaniel Vetter uint32_t crc4) 13258bf1e9f1SShuang He { 13268bf1e9f1SShuang He struct drm_i915_private *dev_priv = dev->dev_private; 13278bf1e9f1SShuang He struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 13288bf1e9f1SShuang He struct intel_pipe_crc_entry *entry; 1329ac2300d4SDamien Lespiau int head, tail; 1330b2c88f5bSDamien Lespiau 1331d538bbdfSDamien Lespiau spin_lock(&pipe_crc->lock); 1332d538bbdfSDamien Lespiau 13330c912c79SDamien Lespiau if (!pipe_crc->entries) { 1334d538bbdfSDamien Lespiau spin_unlock(&pipe_crc->lock); 13350c912c79SDamien Lespiau DRM_ERROR("spurious interrupt\n"); 13360c912c79SDamien Lespiau return; 13370c912c79SDamien Lespiau } 13380c912c79SDamien Lespiau 1339d538bbdfSDamien Lespiau head = pipe_crc->head; 1340d538bbdfSDamien Lespiau tail = pipe_crc->tail; 1341b2c88f5bSDamien Lespiau 1342b2c88f5bSDamien Lespiau if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { 1343d538bbdfSDamien Lespiau spin_unlock(&pipe_crc->lock); 1344b2c88f5bSDamien Lespiau DRM_ERROR("CRC buffer overflowing\n"); 1345b2c88f5bSDamien Lespiau return; 1346b2c88f5bSDamien Lespiau } 1347b2c88f5bSDamien Lespiau 1348b2c88f5bSDamien Lespiau entry = &pipe_crc->entries[head]; 13498bf1e9f1SShuang He 13508bc5e955SDaniel Vetter entry->frame = dev->driver->get_vblank_counter(dev, pipe); 1351eba94eb9SDaniel Vetter entry->crc[0] = crc0; 1352eba94eb9SDaniel Vetter entry->crc[1] = crc1; 1353eba94eb9SDaniel Vetter entry->crc[2] = crc2; 1354eba94eb9SDaniel Vetter entry->crc[3] = crc3; 1355eba94eb9SDaniel Vetter entry->crc[4] = crc4; 1356b2c88f5bSDamien Lespiau 1357b2c88f5bSDamien Lespiau head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); 1358d538bbdfSDamien Lespiau pipe_crc->head = head; 1359d538bbdfSDamien Lespiau 1360d538bbdfSDamien Lespiau spin_unlock(&pipe_crc->lock); 136107144428SDamien Lespiau 136207144428SDamien Lespiau wake_up_interruptible(&pipe_crc->wq); 13638bf1e9f1SShuang He } 1364277de95eSDaniel Vetter #else 1365277de95eSDaniel Vetter static inline void 1366277de95eSDaniel Vetter display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, 1367277de95eSDaniel Vetter uint32_t crc0, uint32_t crc1, 1368277de95eSDaniel Vetter uint32_t crc2, uint32_t crc3, 1369277de95eSDaniel Vetter uint32_t crc4) {} 1370277de95eSDaniel Vetter #endif 1371eba94eb9SDaniel Vetter 1372277de95eSDaniel Vetter 1373277de95eSDaniel Vetter static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) 13745a69b89fSDaniel Vetter { 13755a69b89fSDaniel Vetter struct drm_i915_private *dev_priv = dev->dev_private; 13765a69b89fSDaniel Vetter 1377277de95eSDaniel Vetter display_pipe_crc_irq_handler(dev, pipe, 13785a69b89fSDaniel Vetter I915_READ(PIPE_CRC_RES_1_IVB(pipe)), 13795a69b89fSDaniel Vetter 0, 0, 0, 0); 13805a69b89fSDaniel Vetter } 13815a69b89fSDaniel Vetter 1382277de95eSDaniel Vetter static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) 1383eba94eb9SDaniel Vetter { 1384eba94eb9SDaniel Vetter struct drm_i915_private *dev_priv = dev->dev_private; 1385eba94eb9SDaniel Vetter 1386277de95eSDaniel Vetter display_pipe_crc_irq_handler(dev, pipe, 1387eba94eb9SDaniel Vetter I915_READ(PIPE_CRC_RES_1_IVB(pipe)), 1388eba94eb9SDaniel Vetter I915_READ(PIPE_CRC_RES_2_IVB(pipe)), 1389eba94eb9SDaniel Vetter I915_READ(PIPE_CRC_RES_3_IVB(pipe)), 1390eba94eb9SDaniel Vetter I915_READ(PIPE_CRC_RES_4_IVB(pipe)), 13918bc5e955SDaniel Vetter I915_READ(PIPE_CRC_RES_5_IVB(pipe))); 1392eba94eb9SDaniel Vetter } 13935b3a856bSDaniel Vetter 1394277de95eSDaniel Vetter static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) 13955b3a856bSDaniel Vetter { 13965b3a856bSDaniel Vetter struct drm_i915_private *dev_priv = dev->dev_private; 13970b5c5ed0SDaniel Vetter uint32_t res1, res2; 13980b5c5ed0SDaniel Vetter 13990b5c5ed0SDaniel Vetter if (INTEL_INFO(dev)->gen >= 3) 14000b5c5ed0SDaniel Vetter res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); 14010b5c5ed0SDaniel Vetter else 14020b5c5ed0SDaniel Vetter res1 = 0; 14030b5c5ed0SDaniel Vetter 14040b5c5ed0SDaniel Vetter if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) 14050b5c5ed0SDaniel Vetter res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); 14060b5c5ed0SDaniel Vetter else 14070b5c5ed0SDaniel Vetter res2 = 0; 14085b3a856bSDaniel Vetter 1409277de95eSDaniel Vetter display_pipe_crc_irq_handler(dev, pipe, 14100b5c5ed0SDaniel Vetter I915_READ(PIPE_CRC_RES_RED(pipe)), 14110b5c5ed0SDaniel Vetter I915_READ(PIPE_CRC_RES_GREEN(pipe)), 14120b5c5ed0SDaniel Vetter I915_READ(PIPE_CRC_RES_BLUE(pipe)), 14130b5c5ed0SDaniel Vetter res1, res2); 14145b3a856bSDaniel Vetter } 14158bf1e9f1SShuang He 14161403c0d4SPaulo Zanoni /* The RPS events need forcewake, so we add them to a work queue and mask their 14171403c0d4SPaulo Zanoni * IMR bits until the work is done. Other interrupts can be processed without 14181403c0d4SPaulo Zanoni * the work queue. */ 14191403c0d4SPaulo Zanoni static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) 1420baf02a1fSBen Widawsky { 142141a05a3aSDaniel Vetter if (pm_iir & GEN6_PM_RPS_EVENTS) { 142259cdb63dSDaniel Vetter spin_lock(&dev_priv->irq_lock); 14234848405cSBen Widawsky dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; 14244d3b3d5fSPaulo Zanoni snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS); 142559cdb63dSDaniel Vetter spin_unlock(&dev_priv->irq_lock); 14262adbee62SDaniel Vetter 14272adbee62SDaniel Vetter queue_work(dev_priv->wq, &dev_priv->rps.work); 142841a05a3aSDaniel Vetter } 1429baf02a1fSBen Widawsky 14301403c0d4SPaulo Zanoni if (HAS_VEBOX(dev_priv->dev)) { 143112638c57SBen Widawsky if (pm_iir & PM_VEBOX_USER_INTERRUPT) 143212638c57SBen Widawsky notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); 143312638c57SBen Widawsky 143412638c57SBen Widawsky if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { 143512638c57SBen Widawsky DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir); 143612638c57SBen Widawsky i915_handle_error(dev_priv->dev, false); 143712638c57SBen Widawsky } 143812638c57SBen Widawsky } 14391403c0d4SPaulo Zanoni } 1440baf02a1fSBen Widawsky 1441ff1f525eSDaniel Vetter static irqreturn_t valleyview_irq_handler(int irq, void *arg) 14427e231dbeSJesse Barnes { 14437e231dbeSJesse Barnes struct drm_device *dev = (struct drm_device *) arg; 14447e231dbeSJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 14457e231dbeSJesse Barnes u32 iir, gt_iir, pm_iir; 14467e231dbeSJesse Barnes irqreturn_t ret = IRQ_NONE; 14477e231dbeSJesse Barnes unsigned long irqflags; 14487e231dbeSJesse Barnes int pipe; 14497e231dbeSJesse Barnes u32 pipe_stats[I915_MAX_PIPES]; 14507e231dbeSJesse Barnes 14517e231dbeSJesse Barnes while (true) { 14527e231dbeSJesse Barnes iir = I915_READ(VLV_IIR); 14537e231dbeSJesse Barnes gt_iir = I915_READ(GTIIR); 14547e231dbeSJesse Barnes pm_iir = I915_READ(GEN6_PMIIR); 14557e231dbeSJesse Barnes 14567e231dbeSJesse Barnes if (gt_iir == 0 && pm_iir == 0 && iir == 0) 14577e231dbeSJesse Barnes goto out; 14587e231dbeSJesse Barnes 14597e231dbeSJesse Barnes ret = IRQ_HANDLED; 14607e231dbeSJesse Barnes 1461e7b4c6b1SDaniel Vetter snb_gt_irq_handler(dev, dev_priv, gt_iir); 14627e231dbeSJesse Barnes 14637e231dbeSJesse Barnes spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 14647e231dbeSJesse Barnes for_each_pipe(pipe) { 14657e231dbeSJesse Barnes int reg = PIPESTAT(pipe); 14667e231dbeSJesse Barnes pipe_stats[pipe] = I915_READ(reg); 14677e231dbeSJesse Barnes 14687e231dbeSJesse Barnes /* 14697e231dbeSJesse Barnes * Clear the PIPE*STAT regs before the IIR 14707e231dbeSJesse Barnes */ 1471*2d9d2b0bSVille Syrjälä if (pipe_stats[pipe] & 0x8000ffff) 14727e231dbeSJesse Barnes I915_WRITE(reg, pipe_stats[pipe]); 14737e231dbeSJesse Barnes } 14747e231dbeSJesse Barnes spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 14757e231dbeSJesse Barnes 147631acc7f5SJesse Barnes for_each_pipe(pipe) { 14777b5562d4SJesse Barnes if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 147831acc7f5SJesse Barnes drm_handle_vblank(dev, pipe); 147931acc7f5SJesse Barnes 148031acc7f5SJesse Barnes if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { 148131acc7f5SJesse Barnes intel_prepare_page_flip(dev, pipe); 148231acc7f5SJesse Barnes intel_finish_page_flip(dev, pipe); 148331acc7f5SJesse Barnes } 14844356d586SDaniel Vetter 14854356d586SDaniel Vetter if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1486277de95eSDaniel Vetter i9xx_pipe_crc_irq_handler(dev, pipe); 1487*2d9d2b0bSVille Syrjälä 1488*2d9d2b0bSVille Syrjälä if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 1489*2d9d2b0bSVille Syrjälä intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 1490*2d9d2b0bSVille Syrjälä DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe)); 149131acc7f5SJesse Barnes } 149231acc7f5SJesse Barnes 14937e231dbeSJesse Barnes /* Consume port. Then clear IIR or we'll miss events */ 14947e231dbeSJesse Barnes if (iir & I915_DISPLAY_PORT_INTERRUPT) { 14957e231dbeSJesse Barnes u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 1496b543fb04SEgbert Eich u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 14977e231dbeSJesse Barnes 149810a504deSDaniel Vetter intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); 149991d131d2SDaniel Vetter 15004aeebd74SDaniel Vetter if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) 15014aeebd74SDaniel Vetter dp_aux_irq_handler(dev); 15024aeebd74SDaniel Vetter 15037e231dbeSJesse Barnes I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 15047e231dbeSJesse Barnes I915_READ(PORT_HOTPLUG_STAT); 15057e231dbeSJesse Barnes } 15067e231dbeSJesse Barnes 1507515ac2bbSDaniel Vetter if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 1508515ac2bbSDaniel Vetter gmbus_irq_handler(dev); 15097e231dbeSJesse Barnes 151060611c13SPaulo Zanoni if (pm_iir) 1511d0ecd7e2SDaniel Vetter gen6_rps_irq_handler(dev_priv, pm_iir); 15127e231dbeSJesse Barnes 15137e231dbeSJesse Barnes I915_WRITE(GTIIR, gt_iir); 15147e231dbeSJesse Barnes I915_WRITE(GEN6_PMIIR, pm_iir); 15157e231dbeSJesse Barnes I915_WRITE(VLV_IIR, iir); 15167e231dbeSJesse Barnes } 15177e231dbeSJesse Barnes 15187e231dbeSJesse Barnes out: 15197e231dbeSJesse Barnes return ret; 15207e231dbeSJesse Barnes } 15217e231dbeSJesse Barnes 152223e81d69SAdam Jackson static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) 1523776ad806SJesse Barnes { 1524776ad806SJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 15259db4a9c7SJesse Barnes int pipe; 1526b543fb04SEgbert Eich u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 1527776ad806SJesse Barnes 152810a504deSDaniel Vetter intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); 152991d131d2SDaniel Vetter 1530cfc33bf7SVille Syrjälä if (pch_iir & SDE_AUDIO_POWER_MASK) { 1531cfc33bf7SVille Syrjälä int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> 1532776ad806SJesse Barnes SDE_AUDIO_POWER_SHIFT); 1533cfc33bf7SVille Syrjälä DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 1534cfc33bf7SVille Syrjälä port_name(port)); 1535cfc33bf7SVille Syrjälä } 1536776ad806SJesse Barnes 1537ce99c256SDaniel Vetter if (pch_iir & SDE_AUX_MASK) 1538ce99c256SDaniel Vetter dp_aux_irq_handler(dev); 1539ce99c256SDaniel Vetter 1540776ad806SJesse Barnes if (pch_iir & SDE_GMBUS) 1541515ac2bbSDaniel Vetter gmbus_irq_handler(dev); 1542776ad806SJesse Barnes 1543776ad806SJesse Barnes if (pch_iir & SDE_AUDIO_HDCP_MASK) 1544776ad806SJesse Barnes DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); 1545776ad806SJesse Barnes 1546776ad806SJesse Barnes if (pch_iir & SDE_AUDIO_TRANS_MASK) 1547776ad806SJesse Barnes DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); 1548776ad806SJesse Barnes 1549776ad806SJesse Barnes if (pch_iir & SDE_POISON) 1550776ad806SJesse Barnes DRM_ERROR("PCH poison interrupt\n"); 1551776ad806SJesse Barnes 15529db4a9c7SJesse Barnes if (pch_iir & SDE_FDI_MASK) 15539db4a9c7SJesse Barnes for_each_pipe(pipe) 15549db4a9c7SJesse Barnes DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 15559db4a9c7SJesse Barnes pipe_name(pipe), 15569db4a9c7SJesse Barnes I915_READ(FDI_RX_IIR(pipe))); 1557776ad806SJesse Barnes 1558776ad806SJesse Barnes if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 1559776ad806SJesse Barnes DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 1560776ad806SJesse Barnes 1561776ad806SJesse Barnes if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 1562776ad806SJesse Barnes DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 1563776ad806SJesse Barnes 1564776ad806SJesse Barnes if (pch_iir & SDE_TRANSA_FIFO_UNDER) 15658664281bSPaulo Zanoni if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, 15668664281bSPaulo Zanoni false)) 15678664281bSPaulo Zanoni DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); 15688664281bSPaulo Zanoni 15698664281bSPaulo Zanoni if (pch_iir & SDE_TRANSB_FIFO_UNDER) 15708664281bSPaulo Zanoni if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, 15718664281bSPaulo Zanoni false)) 15728664281bSPaulo Zanoni DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); 15738664281bSPaulo Zanoni } 15748664281bSPaulo Zanoni 15758664281bSPaulo Zanoni static void ivb_err_int_handler(struct drm_device *dev) 15768664281bSPaulo Zanoni { 15778664281bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 15788664281bSPaulo Zanoni u32 err_int = I915_READ(GEN7_ERR_INT); 15795a69b89fSDaniel Vetter enum pipe pipe; 15808664281bSPaulo Zanoni 1581de032bf4SPaulo Zanoni if (err_int & ERR_INT_POISON) 1582de032bf4SPaulo Zanoni DRM_ERROR("Poison interrupt\n"); 1583de032bf4SPaulo Zanoni 15845a69b89fSDaniel Vetter for_each_pipe(pipe) { 15855a69b89fSDaniel Vetter if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { 15865a69b89fSDaniel Vetter if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, 15875a69b89fSDaniel Vetter false)) 15885a69b89fSDaniel Vetter DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", 15895a69b89fSDaniel Vetter pipe_name(pipe)); 15905a69b89fSDaniel Vetter } 15918664281bSPaulo Zanoni 15925a69b89fSDaniel Vetter if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 15935a69b89fSDaniel Vetter if (IS_IVYBRIDGE(dev)) 1594277de95eSDaniel Vetter ivb_pipe_crc_irq_handler(dev, pipe); 15955a69b89fSDaniel Vetter else 1596277de95eSDaniel Vetter hsw_pipe_crc_irq_handler(dev, pipe); 15975a69b89fSDaniel Vetter } 15985a69b89fSDaniel Vetter } 15998bf1e9f1SShuang He 16008664281bSPaulo Zanoni I915_WRITE(GEN7_ERR_INT, err_int); 16018664281bSPaulo Zanoni } 16028664281bSPaulo Zanoni 16038664281bSPaulo Zanoni static void cpt_serr_int_handler(struct drm_device *dev) 16048664281bSPaulo Zanoni { 16058664281bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 16068664281bSPaulo Zanoni u32 serr_int = I915_READ(SERR_INT); 16078664281bSPaulo Zanoni 1608de032bf4SPaulo Zanoni if (serr_int & SERR_INT_POISON) 1609de032bf4SPaulo Zanoni DRM_ERROR("PCH poison interrupt\n"); 1610de032bf4SPaulo Zanoni 16118664281bSPaulo Zanoni if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) 16128664281bSPaulo Zanoni if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, 16138664281bSPaulo Zanoni false)) 16148664281bSPaulo Zanoni DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); 16158664281bSPaulo Zanoni 16168664281bSPaulo Zanoni if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) 16178664281bSPaulo Zanoni if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, 16188664281bSPaulo Zanoni false)) 16198664281bSPaulo Zanoni DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); 16208664281bSPaulo Zanoni 16218664281bSPaulo Zanoni if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) 16228664281bSPaulo Zanoni if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, 16238664281bSPaulo Zanoni false)) 16248664281bSPaulo Zanoni DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n"); 16258664281bSPaulo Zanoni 16268664281bSPaulo Zanoni I915_WRITE(SERR_INT, serr_int); 1627776ad806SJesse Barnes } 1628776ad806SJesse Barnes 162923e81d69SAdam Jackson static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) 163023e81d69SAdam Jackson { 163123e81d69SAdam Jackson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 163223e81d69SAdam Jackson int pipe; 1633b543fb04SEgbert Eich u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 163423e81d69SAdam Jackson 163510a504deSDaniel Vetter intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); 163691d131d2SDaniel Vetter 1637cfc33bf7SVille Syrjälä if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 1638cfc33bf7SVille Syrjälä int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 163923e81d69SAdam Jackson SDE_AUDIO_POWER_SHIFT_CPT); 1640cfc33bf7SVille Syrjälä DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", 1641cfc33bf7SVille Syrjälä port_name(port)); 1642cfc33bf7SVille Syrjälä } 164323e81d69SAdam Jackson 164423e81d69SAdam Jackson if (pch_iir & SDE_AUX_MASK_CPT) 1645ce99c256SDaniel Vetter dp_aux_irq_handler(dev); 164623e81d69SAdam Jackson 164723e81d69SAdam Jackson if (pch_iir & SDE_GMBUS_CPT) 1648515ac2bbSDaniel Vetter gmbus_irq_handler(dev); 164923e81d69SAdam Jackson 165023e81d69SAdam Jackson if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 165123e81d69SAdam Jackson DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); 165223e81d69SAdam Jackson 165323e81d69SAdam Jackson if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 165423e81d69SAdam Jackson DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); 165523e81d69SAdam Jackson 165623e81d69SAdam Jackson if (pch_iir & SDE_FDI_MASK_CPT) 165723e81d69SAdam Jackson for_each_pipe(pipe) 165823e81d69SAdam Jackson DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 165923e81d69SAdam Jackson pipe_name(pipe), 166023e81d69SAdam Jackson I915_READ(FDI_RX_IIR(pipe))); 16618664281bSPaulo Zanoni 16628664281bSPaulo Zanoni if (pch_iir & SDE_ERROR_CPT) 16638664281bSPaulo Zanoni cpt_serr_int_handler(dev); 166423e81d69SAdam Jackson } 166523e81d69SAdam Jackson 1666c008bc6eSPaulo Zanoni static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) 1667c008bc6eSPaulo Zanoni { 1668c008bc6eSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 166940da17c2SDaniel Vetter enum pipe pipe; 1670c008bc6eSPaulo Zanoni 1671c008bc6eSPaulo Zanoni if (de_iir & DE_AUX_CHANNEL_A) 1672c008bc6eSPaulo Zanoni dp_aux_irq_handler(dev); 1673c008bc6eSPaulo Zanoni 1674c008bc6eSPaulo Zanoni if (de_iir & DE_GSE) 1675c008bc6eSPaulo Zanoni intel_opregion_asle_intr(dev); 1676c008bc6eSPaulo Zanoni 1677c008bc6eSPaulo Zanoni if (de_iir & DE_POISON) 1678c008bc6eSPaulo Zanoni DRM_ERROR("Poison interrupt\n"); 1679c008bc6eSPaulo Zanoni 168040da17c2SDaniel Vetter for_each_pipe(pipe) { 168140da17c2SDaniel Vetter if (de_iir & DE_PIPE_VBLANK(pipe)) 168240da17c2SDaniel Vetter drm_handle_vblank(dev, pipe); 1683c008bc6eSPaulo Zanoni 168440da17c2SDaniel Vetter if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 168540da17c2SDaniel Vetter if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 168640da17c2SDaniel Vetter DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", 168740da17c2SDaniel Vetter pipe_name(pipe)); 1688c008bc6eSPaulo Zanoni 168940da17c2SDaniel Vetter if (de_iir & DE_PIPE_CRC_DONE(pipe)) 169040da17c2SDaniel Vetter i9xx_pipe_crc_irq_handler(dev, pipe); 16915b3a856bSDaniel Vetter 169240da17c2SDaniel Vetter /* plane/pipes map 1:1 on ilk+ */ 169340da17c2SDaniel Vetter if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { 169440da17c2SDaniel Vetter intel_prepare_page_flip(dev, pipe); 169540da17c2SDaniel Vetter intel_finish_page_flip_plane(dev, pipe); 1696c008bc6eSPaulo Zanoni } 1697c008bc6eSPaulo Zanoni } 1698c008bc6eSPaulo Zanoni 1699c008bc6eSPaulo Zanoni /* check event from PCH */ 1700c008bc6eSPaulo Zanoni if (de_iir & DE_PCH_EVENT) { 1701c008bc6eSPaulo Zanoni u32 pch_iir = I915_READ(SDEIIR); 1702c008bc6eSPaulo Zanoni 1703c008bc6eSPaulo Zanoni if (HAS_PCH_CPT(dev)) 1704c008bc6eSPaulo Zanoni cpt_irq_handler(dev, pch_iir); 1705c008bc6eSPaulo Zanoni else 1706c008bc6eSPaulo Zanoni ibx_irq_handler(dev, pch_iir); 1707c008bc6eSPaulo Zanoni 1708c008bc6eSPaulo Zanoni /* should clear PCH hotplug event before clear CPU irq */ 1709c008bc6eSPaulo Zanoni I915_WRITE(SDEIIR, pch_iir); 1710c008bc6eSPaulo Zanoni } 1711c008bc6eSPaulo Zanoni 1712c008bc6eSPaulo Zanoni if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) 1713c008bc6eSPaulo Zanoni ironlake_rps_change_irq_handler(dev); 1714c008bc6eSPaulo Zanoni } 1715c008bc6eSPaulo Zanoni 17169719fb98SPaulo Zanoni static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) 17179719fb98SPaulo Zanoni { 17189719fb98SPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 17193b6c42e8SDaniel Vetter enum pipe i; 17209719fb98SPaulo Zanoni 17219719fb98SPaulo Zanoni if (de_iir & DE_ERR_INT_IVB) 17229719fb98SPaulo Zanoni ivb_err_int_handler(dev); 17239719fb98SPaulo Zanoni 17249719fb98SPaulo Zanoni if (de_iir & DE_AUX_CHANNEL_A_IVB) 17259719fb98SPaulo Zanoni dp_aux_irq_handler(dev); 17269719fb98SPaulo Zanoni 17279719fb98SPaulo Zanoni if (de_iir & DE_GSE_IVB) 17289719fb98SPaulo Zanoni intel_opregion_asle_intr(dev); 17299719fb98SPaulo Zanoni 17303b6c42e8SDaniel Vetter for_each_pipe(i) { 173140da17c2SDaniel Vetter if (de_iir & (DE_PIPE_VBLANK_IVB(i))) 17329719fb98SPaulo Zanoni drm_handle_vblank(dev, i); 173340da17c2SDaniel Vetter 173440da17c2SDaniel Vetter /* plane/pipes map 1:1 on ilk+ */ 173540da17c2SDaniel Vetter if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) { 17369719fb98SPaulo Zanoni intel_prepare_page_flip(dev, i); 17379719fb98SPaulo Zanoni intel_finish_page_flip_plane(dev, i); 17389719fb98SPaulo Zanoni } 17399719fb98SPaulo Zanoni } 17409719fb98SPaulo Zanoni 17419719fb98SPaulo Zanoni /* check event from PCH */ 17429719fb98SPaulo Zanoni if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { 17439719fb98SPaulo Zanoni u32 pch_iir = I915_READ(SDEIIR); 17449719fb98SPaulo Zanoni 17459719fb98SPaulo Zanoni cpt_irq_handler(dev, pch_iir); 17469719fb98SPaulo Zanoni 17479719fb98SPaulo Zanoni /* clear PCH hotplug event before clear CPU irq */ 17489719fb98SPaulo Zanoni I915_WRITE(SDEIIR, pch_iir); 17499719fb98SPaulo Zanoni } 17509719fb98SPaulo Zanoni } 17519719fb98SPaulo Zanoni 1752f1af8fc1SPaulo Zanoni static irqreturn_t ironlake_irq_handler(int irq, void *arg) 1753b1f14ad0SJesse Barnes { 1754b1f14ad0SJesse Barnes struct drm_device *dev = (struct drm_device *) arg; 1755b1f14ad0SJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1756f1af8fc1SPaulo Zanoni u32 de_iir, gt_iir, de_ier, sde_ier = 0; 17570e43406bSChris Wilson irqreturn_t ret = IRQ_NONE; 1758b1f14ad0SJesse Barnes 17598664281bSPaulo Zanoni /* We get interrupts on unclaimed registers, so check for this before we 17608664281bSPaulo Zanoni * do any I915_{READ,WRITE}. */ 1761907b28c5SChris Wilson intel_uncore_check_errors(dev); 17628664281bSPaulo Zanoni 1763b1f14ad0SJesse Barnes /* disable master interrupt before clearing iir */ 1764b1f14ad0SJesse Barnes de_ier = I915_READ(DEIER); 1765b1f14ad0SJesse Barnes I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 176623a78516SPaulo Zanoni POSTING_READ(DEIER); 17670e43406bSChris Wilson 176844498aeaSPaulo Zanoni /* Disable south interrupts. We'll only write to SDEIIR once, so further 176944498aeaSPaulo Zanoni * interrupts will will be stored on its back queue, and then we'll be 177044498aeaSPaulo Zanoni * able to process them after we restore SDEIER (as soon as we restore 177144498aeaSPaulo Zanoni * it, we'll get an interrupt if SDEIIR still has something to process 177244498aeaSPaulo Zanoni * due to its back queue). */ 1773ab5c608bSBen Widawsky if (!HAS_PCH_NOP(dev)) { 177444498aeaSPaulo Zanoni sde_ier = I915_READ(SDEIER); 177544498aeaSPaulo Zanoni I915_WRITE(SDEIER, 0); 177644498aeaSPaulo Zanoni POSTING_READ(SDEIER); 1777ab5c608bSBen Widawsky } 177844498aeaSPaulo Zanoni 17790e43406bSChris Wilson gt_iir = I915_READ(GTIIR); 17800e43406bSChris Wilson if (gt_iir) { 1781d8fc8a47SPaulo Zanoni if (INTEL_INFO(dev)->gen >= 6) 17820e43406bSChris Wilson snb_gt_irq_handler(dev, dev_priv, gt_iir); 1783d8fc8a47SPaulo Zanoni else 1784d8fc8a47SPaulo Zanoni ilk_gt_irq_handler(dev, dev_priv, gt_iir); 17850e43406bSChris Wilson I915_WRITE(GTIIR, gt_iir); 17860e43406bSChris Wilson ret = IRQ_HANDLED; 17870e43406bSChris Wilson } 1788b1f14ad0SJesse Barnes 1789b1f14ad0SJesse Barnes de_iir = I915_READ(DEIIR); 17900e43406bSChris Wilson if (de_iir) { 1791f1af8fc1SPaulo Zanoni if (INTEL_INFO(dev)->gen >= 7) 17929719fb98SPaulo Zanoni ivb_display_irq_handler(dev, de_iir); 1793f1af8fc1SPaulo Zanoni else 1794f1af8fc1SPaulo Zanoni ilk_display_irq_handler(dev, de_iir); 17950e43406bSChris Wilson I915_WRITE(DEIIR, de_iir); 17960e43406bSChris Wilson ret = IRQ_HANDLED; 17970e43406bSChris Wilson } 17980e43406bSChris Wilson 1799f1af8fc1SPaulo Zanoni if (INTEL_INFO(dev)->gen >= 6) { 1800f1af8fc1SPaulo Zanoni u32 pm_iir = I915_READ(GEN6_PMIIR); 18010e43406bSChris Wilson if (pm_iir) { 1802d0ecd7e2SDaniel Vetter gen6_rps_irq_handler(dev_priv, pm_iir); 1803b1f14ad0SJesse Barnes I915_WRITE(GEN6_PMIIR, pm_iir); 18040e43406bSChris Wilson ret = IRQ_HANDLED; 18050e43406bSChris Wilson } 1806f1af8fc1SPaulo Zanoni } 1807b1f14ad0SJesse Barnes 1808b1f14ad0SJesse Barnes I915_WRITE(DEIER, de_ier); 1809b1f14ad0SJesse Barnes POSTING_READ(DEIER); 1810ab5c608bSBen Widawsky if (!HAS_PCH_NOP(dev)) { 181144498aeaSPaulo Zanoni I915_WRITE(SDEIER, sde_ier); 181244498aeaSPaulo Zanoni POSTING_READ(SDEIER); 1813ab5c608bSBen Widawsky } 1814b1f14ad0SJesse Barnes 1815b1f14ad0SJesse Barnes return ret; 1816b1f14ad0SJesse Barnes } 1817b1f14ad0SJesse Barnes 1818abd58f01SBen Widawsky static irqreturn_t gen8_irq_handler(int irq, void *arg) 1819abd58f01SBen Widawsky { 1820abd58f01SBen Widawsky struct drm_device *dev = arg; 1821abd58f01SBen Widawsky struct drm_i915_private *dev_priv = dev->dev_private; 1822abd58f01SBen Widawsky u32 master_ctl; 1823abd58f01SBen Widawsky irqreturn_t ret = IRQ_NONE; 1824abd58f01SBen Widawsky uint32_t tmp = 0; 1825c42664ccSDaniel Vetter enum pipe pipe; 1826abd58f01SBen Widawsky 1827abd58f01SBen Widawsky master_ctl = I915_READ(GEN8_MASTER_IRQ); 1828abd58f01SBen Widawsky master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; 1829abd58f01SBen Widawsky if (!master_ctl) 1830abd58f01SBen Widawsky return IRQ_NONE; 1831abd58f01SBen Widawsky 1832abd58f01SBen Widawsky I915_WRITE(GEN8_MASTER_IRQ, 0); 1833abd58f01SBen Widawsky POSTING_READ(GEN8_MASTER_IRQ); 1834abd58f01SBen Widawsky 1835abd58f01SBen Widawsky ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); 1836abd58f01SBen Widawsky 1837abd58f01SBen Widawsky if (master_ctl & GEN8_DE_MISC_IRQ) { 1838abd58f01SBen Widawsky tmp = I915_READ(GEN8_DE_MISC_IIR); 1839abd58f01SBen Widawsky if (tmp & GEN8_DE_MISC_GSE) 1840abd58f01SBen Widawsky intel_opregion_asle_intr(dev); 1841abd58f01SBen Widawsky else if (tmp) 1842abd58f01SBen Widawsky DRM_ERROR("Unexpected DE Misc interrupt\n"); 1843abd58f01SBen Widawsky else 1844abd58f01SBen Widawsky DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); 1845abd58f01SBen Widawsky 1846abd58f01SBen Widawsky if (tmp) { 1847abd58f01SBen Widawsky I915_WRITE(GEN8_DE_MISC_IIR, tmp); 1848abd58f01SBen Widawsky ret = IRQ_HANDLED; 1849abd58f01SBen Widawsky } 1850abd58f01SBen Widawsky } 1851abd58f01SBen Widawsky 18526d766f02SDaniel Vetter if (master_ctl & GEN8_DE_PORT_IRQ) { 18536d766f02SDaniel Vetter tmp = I915_READ(GEN8_DE_PORT_IIR); 18546d766f02SDaniel Vetter if (tmp & GEN8_AUX_CHANNEL_A) 18556d766f02SDaniel Vetter dp_aux_irq_handler(dev); 18566d766f02SDaniel Vetter else if (tmp) 18576d766f02SDaniel Vetter DRM_ERROR("Unexpected DE Port interrupt\n"); 18586d766f02SDaniel Vetter else 18596d766f02SDaniel Vetter DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); 18606d766f02SDaniel Vetter 18616d766f02SDaniel Vetter if (tmp) { 18626d766f02SDaniel Vetter I915_WRITE(GEN8_DE_PORT_IIR, tmp); 18636d766f02SDaniel Vetter ret = IRQ_HANDLED; 18646d766f02SDaniel Vetter } 18656d766f02SDaniel Vetter } 18666d766f02SDaniel Vetter 1867abd58f01SBen Widawsky for_each_pipe(pipe) { 1868abd58f01SBen Widawsky uint32_t pipe_iir; 1869abd58f01SBen Widawsky 1870c42664ccSDaniel Vetter if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 1871c42664ccSDaniel Vetter continue; 1872c42664ccSDaniel Vetter 1873abd58f01SBen Widawsky pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); 1874abd58f01SBen Widawsky if (pipe_iir & GEN8_PIPE_VBLANK) 1875abd58f01SBen Widawsky drm_handle_vblank(dev, pipe); 1876abd58f01SBen Widawsky 1877abd58f01SBen Widawsky if (pipe_iir & GEN8_PIPE_FLIP_DONE) { 1878abd58f01SBen Widawsky intel_prepare_page_flip(dev, pipe); 1879abd58f01SBen Widawsky intel_finish_page_flip_plane(dev, pipe); 1880abd58f01SBen Widawsky } 1881abd58f01SBen Widawsky 18820fbe7870SDaniel Vetter if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) 18830fbe7870SDaniel Vetter hsw_pipe_crc_irq_handler(dev, pipe); 18840fbe7870SDaniel Vetter 188538d83c96SDaniel Vetter if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { 188638d83c96SDaniel Vetter if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, 188738d83c96SDaniel Vetter false)) 188838d83c96SDaniel Vetter DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", 188938d83c96SDaniel Vetter pipe_name(pipe)); 189038d83c96SDaniel Vetter } 189138d83c96SDaniel Vetter 189230100f2bSDaniel Vetter if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { 189330100f2bSDaniel Vetter DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", 189430100f2bSDaniel Vetter pipe_name(pipe), 189530100f2bSDaniel Vetter pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); 189630100f2bSDaniel Vetter } 1897abd58f01SBen Widawsky 1898abd58f01SBen Widawsky if (pipe_iir) { 1899abd58f01SBen Widawsky ret = IRQ_HANDLED; 1900abd58f01SBen Widawsky I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); 1901c42664ccSDaniel Vetter } else 1902abd58f01SBen Widawsky DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); 1903abd58f01SBen Widawsky } 1904abd58f01SBen Widawsky 190592d03a80SDaniel Vetter if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { 190692d03a80SDaniel Vetter /* 190792d03a80SDaniel Vetter * FIXME(BDW): Assume for now that the new interrupt handling 190892d03a80SDaniel Vetter * scheme also closed the SDE interrupt handling race we've seen 190992d03a80SDaniel Vetter * on older pch-split platforms. But this needs testing. 191092d03a80SDaniel Vetter */ 191192d03a80SDaniel Vetter u32 pch_iir = I915_READ(SDEIIR); 191292d03a80SDaniel Vetter 191392d03a80SDaniel Vetter cpt_irq_handler(dev, pch_iir); 191492d03a80SDaniel Vetter 191592d03a80SDaniel Vetter if (pch_iir) { 191692d03a80SDaniel Vetter I915_WRITE(SDEIIR, pch_iir); 191792d03a80SDaniel Vetter ret = IRQ_HANDLED; 191892d03a80SDaniel Vetter } 191992d03a80SDaniel Vetter } 192092d03a80SDaniel Vetter 1921abd58f01SBen Widawsky I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 1922abd58f01SBen Widawsky POSTING_READ(GEN8_MASTER_IRQ); 1923abd58f01SBen Widawsky 1924abd58f01SBen Widawsky return ret; 1925abd58f01SBen Widawsky } 1926abd58f01SBen Widawsky 192717e1df07SDaniel Vetter static void i915_error_wake_up(struct drm_i915_private *dev_priv, 192817e1df07SDaniel Vetter bool reset_completed) 192917e1df07SDaniel Vetter { 193017e1df07SDaniel Vetter struct intel_ring_buffer *ring; 193117e1df07SDaniel Vetter int i; 193217e1df07SDaniel Vetter 193317e1df07SDaniel Vetter /* 193417e1df07SDaniel Vetter * Notify all waiters for GPU completion events that reset state has 193517e1df07SDaniel Vetter * been changed, and that they need to restart their wait after 193617e1df07SDaniel Vetter * checking for potential errors (and bail out to drop locks if there is 193717e1df07SDaniel Vetter * a gpu reset pending so that i915_error_work_func can acquire them). 193817e1df07SDaniel Vetter */ 193917e1df07SDaniel Vetter 194017e1df07SDaniel Vetter /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ 194117e1df07SDaniel Vetter for_each_ring(ring, dev_priv, i) 194217e1df07SDaniel Vetter wake_up_all(&ring->irq_queue); 194317e1df07SDaniel Vetter 194417e1df07SDaniel Vetter /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ 194517e1df07SDaniel Vetter wake_up_all(&dev_priv->pending_flip_queue); 194617e1df07SDaniel Vetter 194717e1df07SDaniel Vetter /* 194817e1df07SDaniel Vetter * Signal tasks blocked in i915_gem_wait_for_error that the pending 194917e1df07SDaniel Vetter * reset state is cleared. 195017e1df07SDaniel Vetter */ 195117e1df07SDaniel Vetter if (reset_completed) 195217e1df07SDaniel Vetter wake_up_all(&dev_priv->gpu_error.reset_queue); 195317e1df07SDaniel Vetter } 195417e1df07SDaniel Vetter 19558a905236SJesse Barnes /** 19568a905236SJesse Barnes * i915_error_work_func - do process context error handling work 19578a905236SJesse Barnes * @work: work struct 19588a905236SJesse Barnes * 19598a905236SJesse Barnes * Fire an error uevent so userspace can see that a hang or error 19608a905236SJesse Barnes * was detected. 19618a905236SJesse Barnes */ 19628a905236SJesse Barnes static void i915_error_work_func(struct work_struct *work) 19638a905236SJesse Barnes { 19641f83fee0SDaniel Vetter struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, 19651f83fee0SDaniel Vetter work); 19661f83fee0SDaniel Vetter drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, 19671f83fee0SDaniel Vetter gpu_error); 19688a905236SJesse Barnes struct drm_device *dev = dev_priv->dev; 1969cce723edSBen Widawsky char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; 1970cce723edSBen Widawsky char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; 1971cce723edSBen Widawsky char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; 197217e1df07SDaniel Vetter int ret; 19738a905236SJesse Barnes 19745bdebb18SDave Airlie kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); 19758a905236SJesse Barnes 19767db0ba24SDaniel Vetter /* 19777db0ba24SDaniel Vetter * Note that there's only one work item which does gpu resets, so we 19787db0ba24SDaniel Vetter * need not worry about concurrent gpu resets potentially incrementing 19797db0ba24SDaniel Vetter * error->reset_counter twice. We only need to take care of another 19807db0ba24SDaniel Vetter * racing irq/hangcheck declaring the gpu dead for a second time. A 19817db0ba24SDaniel Vetter * quick check for that is good enough: schedule_work ensures the 19827db0ba24SDaniel Vetter * correct ordering between hang detection and this work item, and since 19837db0ba24SDaniel Vetter * the reset in-progress bit is only ever set by code outside of this 19847db0ba24SDaniel Vetter * work we don't need to worry about any other races. 19857db0ba24SDaniel Vetter */ 19867db0ba24SDaniel Vetter if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { 198744d98a61SZhao Yakui DRM_DEBUG_DRIVER("resetting chip\n"); 19885bdebb18SDave Airlie kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, 19897db0ba24SDaniel Vetter reset_event); 19901f83fee0SDaniel Vetter 199117e1df07SDaniel Vetter /* 199217e1df07SDaniel Vetter * All state reset _must_ be completed before we update the 199317e1df07SDaniel Vetter * reset counter, for otherwise waiters might miss the reset 199417e1df07SDaniel Vetter * pending state and not properly drop locks, resulting in 199517e1df07SDaniel Vetter * deadlocks with the reset work. 199617e1df07SDaniel Vetter */ 1997f69061beSDaniel Vetter ret = i915_reset(dev); 1998f69061beSDaniel Vetter 199917e1df07SDaniel Vetter intel_display_handle_reset(dev); 200017e1df07SDaniel Vetter 2001f69061beSDaniel Vetter if (ret == 0) { 2002f69061beSDaniel Vetter /* 2003f69061beSDaniel Vetter * After all the gem state is reset, increment the reset 2004f69061beSDaniel Vetter * counter and wake up everyone waiting for the reset to 2005f69061beSDaniel Vetter * complete. 2006f69061beSDaniel Vetter * 2007f69061beSDaniel Vetter * Since unlock operations are a one-sided barrier only, 2008f69061beSDaniel Vetter * we need to insert a barrier here to order any seqno 2009f69061beSDaniel Vetter * updates before 2010f69061beSDaniel Vetter * the counter increment. 2011f69061beSDaniel Vetter */ 2012f69061beSDaniel Vetter smp_mb__before_atomic_inc(); 2013f69061beSDaniel Vetter atomic_inc(&dev_priv->gpu_error.reset_counter); 2014f69061beSDaniel Vetter 20155bdebb18SDave Airlie kobject_uevent_env(&dev->primary->kdev->kobj, 2016f69061beSDaniel Vetter KOBJ_CHANGE, reset_done_event); 20171f83fee0SDaniel Vetter } else { 20182ac0f450SMika Kuoppala atomic_set_mask(I915_WEDGED, &error->reset_counter); 2019f316a42cSBen Gamari } 20201f83fee0SDaniel Vetter 202117e1df07SDaniel Vetter /* 202217e1df07SDaniel Vetter * Note: The wake_up also serves as a memory barrier so that 202317e1df07SDaniel Vetter * waiters see the update value of the reset counter atomic_t. 202417e1df07SDaniel Vetter */ 202517e1df07SDaniel Vetter i915_error_wake_up(dev_priv, true); 2026f316a42cSBen Gamari } 20278a905236SJesse Barnes } 20288a905236SJesse Barnes 202935aed2e6SChris Wilson static void i915_report_and_clear_eir(struct drm_device *dev) 2030c0e09200SDave Airlie { 20318a905236SJesse Barnes struct drm_i915_private *dev_priv = dev->dev_private; 2032bd9854f9SBen Widawsky uint32_t instdone[I915_NUM_INSTDONE_REG]; 203363eeaf38SJesse Barnes u32 eir = I915_READ(EIR); 2034050ee91fSBen Widawsky int pipe, i; 203563eeaf38SJesse Barnes 203635aed2e6SChris Wilson if (!eir) 203735aed2e6SChris Wilson return; 203863eeaf38SJesse Barnes 2039a70491ccSJoe Perches pr_err("render error detected, EIR: 0x%08x\n", eir); 20408a905236SJesse Barnes 2041bd9854f9SBen Widawsky i915_get_extra_instdone(dev, instdone); 2042bd9854f9SBen Widawsky 20438a905236SJesse Barnes if (IS_G4X(dev)) { 20448a905236SJesse Barnes if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 20458a905236SJesse Barnes u32 ipeir = I915_READ(IPEIR_I965); 20468a905236SJesse Barnes 2047a70491ccSJoe Perches pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 2048a70491ccSJoe Perches pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 2049050ee91fSBen Widawsky for (i = 0; i < ARRAY_SIZE(instdone); i++) 2050050ee91fSBen Widawsky pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 2051a70491ccSJoe Perches pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 2052a70491ccSJoe Perches pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 20538a905236SJesse Barnes I915_WRITE(IPEIR_I965, ipeir); 20543143a2bfSChris Wilson POSTING_READ(IPEIR_I965); 20558a905236SJesse Barnes } 20568a905236SJesse Barnes if (eir & GM45_ERROR_PAGE_TABLE) { 20578a905236SJesse Barnes u32 pgtbl_err = I915_READ(PGTBL_ER); 2058a70491ccSJoe Perches pr_err("page table error\n"); 2059a70491ccSJoe Perches pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); 20608a905236SJesse Barnes I915_WRITE(PGTBL_ER, pgtbl_err); 20613143a2bfSChris Wilson POSTING_READ(PGTBL_ER); 20628a905236SJesse Barnes } 20638a905236SJesse Barnes } 20648a905236SJesse Barnes 2065a6c45cf0SChris Wilson if (!IS_GEN2(dev)) { 206663eeaf38SJesse Barnes if (eir & I915_ERROR_PAGE_TABLE) { 206763eeaf38SJesse Barnes u32 pgtbl_err = I915_READ(PGTBL_ER); 2068a70491ccSJoe Perches pr_err("page table error\n"); 2069a70491ccSJoe Perches pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); 207063eeaf38SJesse Barnes I915_WRITE(PGTBL_ER, pgtbl_err); 20713143a2bfSChris Wilson POSTING_READ(PGTBL_ER); 207263eeaf38SJesse Barnes } 20738a905236SJesse Barnes } 20748a905236SJesse Barnes 207563eeaf38SJesse Barnes if (eir & I915_ERROR_MEMORY_REFRESH) { 2076a70491ccSJoe Perches pr_err("memory refresh error:\n"); 20779db4a9c7SJesse Barnes for_each_pipe(pipe) 2078a70491ccSJoe Perches pr_err("pipe %c stat: 0x%08x\n", 20799db4a9c7SJesse Barnes pipe_name(pipe), I915_READ(PIPESTAT(pipe))); 208063eeaf38SJesse Barnes /* pipestat has already been acked */ 208163eeaf38SJesse Barnes } 208263eeaf38SJesse Barnes if (eir & I915_ERROR_INSTRUCTION) { 2083a70491ccSJoe Perches pr_err("instruction error\n"); 2084a70491ccSJoe Perches pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); 2085050ee91fSBen Widawsky for (i = 0; i < ARRAY_SIZE(instdone); i++) 2086050ee91fSBen Widawsky pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 2087a6c45cf0SChris Wilson if (INTEL_INFO(dev)->gen < 4) { 208863eeaf38SJesse Barnes u32 ipeir = I915_READ(IPEIR); 208963eeaf38SJesse Barnes 2090a70491ccSJoe Perches pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); 2091a70491ccSJoe Perches pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); 2092a70491ccSJoe Perches pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); 209363eeaf38SJesse Barnes I915_WRITE(IPEIR, ipeir); 20943143a2bfSChris Wilson POSTING_READ(IPEIR); 209563eeaf38SJesse Barnes } else { 209663eeaf38SJesse Barnes u32 ipeir = I915_READ(IPEIR_I965); 209763eeaf38SJesse Barnes 2098a70491ccSJoe Perches pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 2099a70491ccSJoe Perches pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 2100a70491ccSJoe Perches pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 2101a70491ccSJoe Perches pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 210263eeaf38SJesse Barnes I915_WRITE(IPEIR_I965, ipeir); 21033143a2bfSChris Wilson POSTING_READ(IPEIR_I965); 210463eeaf38SJesse Barnes } 210563eeaf38SJesse Barnes } 210663eeaf38SJesse Barnes 210763eeaf38SJesse Barnes I915_WRITE(EIR, eir); 21083143a2bfSChris Wilson POSTING_READ(EIR); 210963eeaf38SJesse Barnes eir = I915_READ(EIR); 211063eeaf38SJesse Barnes if (eir) { 211163eeaf38SJesse Barnes /* 211263eeaf38SJesse Barnes * some errors might have become stuck, 211363eeaf38SJesse Barnes * mask them. 211463eeaf38SJesse Barnes */ 211563eeaf38SJesse Barnes DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); 211663eeaf38SJesse Barnes I915_WRITE(EMR, I915_READ(EMR) | eir); 211763eeaf38SJesse Barnes I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 211863eeaf38SJesse Barnes } 211935aed2e6SChris Wilson } 212035aed2e6SChris Wilson 212135aed2e6SChris Wilson /** 212235aed2e6SChris Wilson * i915_handle_error - handle an error interrupt 212335aed2e6SChris Wilson * @dev: drm device 212435aed2e6SChris Wilson * 212535aed2e6SChris Wilson * Do some basic checking of regsiter state at error interrupt time and 212635aed2e6SChris Wilson * dump it to the syslog. Also call i915_capture_error_state() to make 212735aed2e6SChris Wilson * sure we get a record and make it available in debugfs. Fire a uevent 212835aed2e6SChris Wilson * so userspace knows something bad happened (should trigger collection 212935aed2e6SChris Wilson * of a ring dump etc.). 213035aed2e6SChris Wilson */ 2131527f9e90SChris Wilson void i915_handle_error(struct drm_device *dev, bool wedged) 213235aed2e6SChris Wilson { 213335aed2e6SChris Wilson struct drm_i915_private *dev_priv = dev->dev_private; 213435aed2e6SChris Wilson 213535aed2e6SChris Wilson i915_capture_error_state(dev); 213635aed2e6SChris Wilson i915_report_and_clear_eir(dev); 21378a905236SJesse Barnes 2138ba1234d1SBen Gamari if (wedged) { 2139f69061beSDaniel Vetter atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, 2140f69061beSDaniel Vetter &dev_priv->gpu_error.reset_counter); 2141ba1234d1SBen Gamari 214211ed50ecSBen Gamari /* 214317e1df07SDaniel Vetter * Wakeup waiting processes so that the reset work function 214417e1df07SDaniel Vetter * i915_error_work_func doesn't deadlock trying to grab various 214517e1df07SDaniel Vetter * locks. By bumping the reset counter first, the woken 214617e1df07SDaniel Vetter * processes will see a reset in progress and back off, 214717e1df07SDaniel Vetter * releasing their locks and then wait for the reset completion. 214817e1df07SDaniel Vetter * We must do this for _all_ gpu waiters that might hold locks 214917e1df07SDaniel Vetter * that the reset work needs to acquire. 215017e1df07SDaniel Vetter * 215117e1df07SDaniel Vetter * Note: The wake_up serves as the required memory barrier to 215217e1df07SDaniel Vetter * ensure that the waiters see the updated value of the reset 215317e1df07SDaniel Vetter * counter atomic_t. 215411ed50ecSBen Gamari */ 215517e1df07SDaniel Vetter i915_error_wake_up(dev_priv, false); 215611ed50ecSBen Gamari } 215711ed50ecSBen Gamari 2158122f46baSDaniel Vetter /* 2159122f46baSDaniel Vetter * Our reset work can grab modeset locks (since it needs to reset the 2160122f46baSDaniel Vetter * state of outstanding pagelips). Hence it must not be run on our own 2161122f46baSDaniel Vetter * dev-priv->wq work queue for otherwise the flush_work in the pageflip 2162122f46baSDaniel Vetter * code will deadlock. 2163122f46baSDaniel Vetter */ 2164122f46baSDaniel Vetter schedule_work(&dev_priv->gpu_error.work); 21658a905236SJesse Barnes } 21668a905236SJesse Barnes 216721ad8330SVille Syrjälä static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) 21684e5359cdSSimon Farnsworth { 21694e5359cdSSimon Farnsworth drm_i915_private_t *dev_priv = dev->dev_private; 21704e5359cdSSimon Farnsworth struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 21714e5359cdSSimon Farnsworth struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 217205394f39SChris Wilson struct drm_i915_gem_object *obj; 21734e5359cdSSimon Farnsworth struct intel_unpin_work *work; 21744e5359cdSSimon Farnsworth unsigned long flags; 21754e5359cdSSimon Farnsworth bool stall_detected; 21764e5359cdSSimon Farnsworth 21774e5359cdSSimon Farnsworth /* Ignore early vblank irqs */ 21784e5359cdSSimon Farnsworth if (intel_crtc == NULL) 21794e5359cdSSimon Farnsworth return; 21804e5359cdSSimon Farnsworth 21814e5359cdSSimon Farnsworth spin_lock_irqsave(&dev->event_lock, flags); 21824e5359cdSSimon Farnsworth work = intel_crtc->unpin_work; 21834e5359cdSSimon Farnsworth 2184e7d841caSChris Wilson if (work == NULL || 2185e7d841caSChris Wilson atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || 2186e7d841caSChris Wilson !work->enable_stall_check) { 21874e5359cdSSimon Farnsworth /* Either the pending flip IRQ arrived, or we're too early. Don't check */ 21884e5359cdSSimon Farnsworth spin_unlock_irqrestore(&dev->event_lock, flags); 21894e5359cdSSimon Farnsworth return; 21904e5359cdSSimon Farnsworth } 21914e5359cdSSimon Farnsworth 21924e5359cdSSimon Farnsworth /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 219305394f39SChris Wilson obj = work->pending_flip_obj; 2194a6c45cf0SChris Wilson if (INTEL_INFO(dev)->gen >= 4) { 21959db4a9c7SJesse Barnes int dspsurf = DSPSURF(intel_crtc->plane); 2196446f2545SArmin Reese stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == 2197f343c5f6SBen Widawsky i915_gem_obj_ggtt_offset(obj); 21984e5359cdSSimon Farnsworth } else { 21999db4a9c7SJesse Barnes int dspaddr = DSPADDR(intel_crtc->plane); 2200f343c5f6SBen Widawsky stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + 220101f2c773SVille Syrjälä crtc->y * crtc->fb->pitches[0] + 22024e5359cdSSimon Farnsworth crtc->x * crtc->fb->bits_per_pixel/8); 22034e5359cdSSimon Farnsworth } 22044e5359cdSSimon Farnsworth 22054e5359cdSSimon Farnsworth spin_unlock_irqrestore(&dev->event_lock, flags); 22064e5359cdSSimon Farnsworth 22074e5359cdSSimon Farnsworth if (stall_detected) { 22084e5359cdSSimon Farnsworth DRM_DEBUG_DRIVER("Pageflip stall detected\n"); 22094e5359cdSSimon Farnsworth intel_prepare_page_flip(dev, intel_crtc->plane); 22104e5359cdSSimon Farnsworth } 22114e5359cdSSimon Farnsworth } 22124e5359cdSSimon Farnsworth 221342f52ef8SKeith Packard /* Called from drm generic code, passed 'crtc' which 221442f52ef8SKeith Packard * we use as a pipe index 221542f52ef8SKeith Packard */ 2216f71d4af4SJesse Barnes static int i915_enable_vblank(struct drm_device *dev, int pipe) 22170a3e67a4SJesse Barnes { 22180a3e67a4SJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2219e9d21d7fSKeith Packard unsigned long irqflags; 222071e0ffa5SJesse Barnes 22215eddb70bSChris Wilson if (!i915_pipe_enabled(dev, pipe)) 222271e0ffa5SJesse Barnes return -EINVAL; 22230a3e67a4SJesse Barnes 22241ec14ad3SChris Wilson spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2225f796cf8fSJesse Barnes if (INTEL_INFO(dev)->gen >= 4) 22267c463586SKeith Packard i915_enable_pipestat(dev_priv, pipe, 22277c463586SKeith Packard PIPE_START_VBLANK_INTERRUPT_ENABLE); 22280a3e67a4SJesse Barnes else 22297c463586SKeith Packard i915_enable_pipestat(dev_priv, pipe, 22307c463586SKeith Packard PIPE_VBLANK_INTERRUPT_ENABLE); 22318692d00eSChris Wilson 22328692d00eSChris Wilson /* maintain vblank delivery even in deep C-states */ 22338692d00eSChris Wilson if (dev_priv->info->gen == 3) 22346b26c86dSDaniel Vetter I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); 22351ec14ad3SChris Wilson spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 22368692d00eSChris Wilson 22370a3e67a4SJesse Barnes return 0; 22380a3e67a4SJesse Barnes } 22390a3e67a4SJesse Barnes 2240f71d4af4SJesse Barnes static int ironlake_enable_vblank(struct drm_device *dev, int pipe) 2241f796cf8fSJesse Barnes { 2242f796cf8fSJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2243f796cf8fSJesse Barnes unsigned long irqflags; 2244b518421fSPaulo Zanoni uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : 224540da17c2SDaniel Vetter DE_PIPE_VBLANK(pipe); 2246f796cf8fSJesse Barnes 2247f796cf8fSJesse Barnes if (!i915_pipe_enabled(dev, pipe)) 2248f796cf8fSJesse Barnes return -EINVAL; 2249f796cf8fSJesse Barnes 2250f796cf8fSJesse Barnes spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2251b518421fSPaulo Zanoni ironlake_enable_display_irq(dev_priv, bit); 2252b1f14ad0SJesse Barnes spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2253b1f14ad0SJesse Barnes 2254b1f14ad0SJesse Barnes return 0; 2255b1f14ad0SJesse Barnes } 2256b1f14ad0SJesse Barnes 22577e231dbeSJesse Barnes static int valleyview_enable_vblank(struct drm_device *dev, int pipe) 22587e231dbeSJesse Barnes { 22597e231dbeSJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 22607e231dbeSJesse Barnes unsigned long irqflags; 226131acc7f5SJesse Barnes u32 imr; 22627e231dbeSJesse Barnes 22637e231dbeSJesse Barnes if (!i915_pipe_enabled(dev, pipe)) 22647e231dbeSJesse Barnes return -EINVAL; 22657e231dbeSJesse Barnes 22667e231dbeSJesse Barnes spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 22677e231dbeSJesse Barnes imr = I915_READ(VLV_IMR); 22683b6c42e8SDaniel Vetter if (pipe == PIPE_A) 22697e231dbeSJesse Barnes imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; 227031acc7f5SJesse Barnes else 22717e231dbeSJesse Barnes imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 22727e231dbeSJesse Barnes I915_WRITE(VLV_IMR, imr); 227331acc7f5SJesse Barnes i915_enable_pipestat(dev_priv, pipe, 227431acc7f5SJesse Barnes PIPE_START_VBLANK_INTERRUPT_ENABLE); 22757e231dbeSJesse Barnes spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 22767e231dbeSJesse Barnes 22777e231dbeSJesse Barnes return 0; 22787e231dbeSJesse Barnes } 22797e231dbeSJesse Barnes 2280abd58f01SBen Widawsky static int gen8_enable_vblank(struct drm_device *dev, int pipe) 2281abd58f01SBen Widawsky { 2282abd58f01SBen Widawsky struct drm_i915_private *dev_priv = dev->dev_private; 2283abd58f01SBen Widawsky unsigned long irqflags; 2284abd58f01SBen Widawsky 2285abd58f01SBen Widawsky if (!i915_pipe_enabled(dev, pipe)) 2286abd58f01SBen Widawsky return -EINVAL; 2287abd58f01SBen Widawsky 2288abd58f01SBen Widawsky spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 22897167d7c6SDaniel Vetter dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; 22907167d7c6SDaniel Vetter I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 2291abd58f01SBen Widawsky POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); 2292abd58f01SBen Widawsky spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2293abd58f01SBen Widawsky return 0; 2294abd58f01SBen Widawsky } 2295abd58f01SBen Widawsky 229642f52ef8SKeith Packard /* Called from drm generic code, passed 'crtc' which 229742f52ef8SKeith Packard * we use as a pipe index 229842f52ef8SKeith Packard */ 2299f71d4af4SJesse Barnes static void i915_disable_vblank(struct drm_device *dev, int pipe) 23000a3e67a4SJesse Barnes { 23010a3e67a4SJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2302e9d21d7fSKeith Packard unsigned long irqflags; 23030a3e67a4SJesse Barnes 23041ec14ad3SChris Wilson spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 23058692d00eSChris Wilson if (dev_priv->info->gen == 3) 23066b26c86dSDaniel Vetter I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); 23078692d00eSChris Wilson 23087c463586SKeith Packard i915_disable_pipestat(dev_priv, pipe, 23097c463586SKeith Packard PIPE_VBLANK_INTERRUPT_ENABLE | 23107c463586SKeith Packard PIPE_START_VBLANK_INTERRUPT_ENABLE); 23111ec14ad3SChris Wilson spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 23120a3e67a4SJesse Barnes } 23130a3e67a4SJesse Barnes 2314f71d4af4SJesse Barnes static void ironlake_disable_vblank(struct drm_device *dev, int pipe) 2315f796cf8fSJesse Barnes { 2316f796cf8fSJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2317f796cf8fSJesse Barnes unsigned long irqflags; 2318b518421fSPaulo Zanoni uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : 231940da17c2SDaniel Vetter DE_PIPE_VBLANK(pipe); 2320f796cf8fSJesse Barnes 2321f796cf8fSJesse Barnes spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2322b518421fSPaulo Zanoni ironlake_disable_display_irq(dev_priv, bit); 2323b1f14ad0SJesse Barnes spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2324b1f14ad0SJesse Barnes } 2325b1f14ad0SJesse Barnes 23267e231dbeSJesse Barnes static void valleyview_disable_vblank(struct drm_device *dev, int pipe) 23277e231dbeSJesse Barnes { 23287e231dbeSJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 23297e231dbeSJesse Barnes unsigned long irqflags; 233031acc7f5SJesse Barnes u32 imr; 23317e231dbeSJesse Barnes 23327e231dbeSJesse Barnes spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 233331acc7f5SJesse Barnes i915_disable_pipestat(dev_priv, pipe, 233431acc7f5SJesse Barnes PIPE_START_VBLANK_INTERRUPT_ENABLE); 23357e231dbeSJesse Barnes imr = I915_READ(VLV_IMR); 23363b6c42e8SDaniel Vetter if (pipe == PIPE_A) 23377e231dbeSJesse Barnes imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; 233831acc7f5SJesse Barnes else 23397e231dbeSJesse Barnes imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 23407e231dbeSJesse Barnes I915_WRITE(VLV_IMR, imr); 23417e231dbeSJesse Barnes spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 23427e231dbeSJesse Barnes } 23437e231dbeSJesse Barnes 2344abd58f01SBen Widawsky static void gen8_disable_vblank(struct drm_device *dev, int pipe) 2345abd58f01SBen Widawsky { 2346abd58f01SBen Widawsky struct drm_i915_private *dev_priv = dev->dev_private; 2347abd58f01SBen Widawsky unsigned long irqflags; 2348abd58f01SBen Widawsky 2349abd58f01SBen Widawsky if (!i915_pipe_enabled(dev, pipe)) 2350abd58f01SBen Widawsky return; 2351abd58f01SBen Widawsky 2352abd58f01SBen Widawsky spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 23537167d7c6SDaniel Vetter dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; 23547167d7c6SDaniel Vetter I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 2355abd58f01SBen Widawsky POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); 2356abd58f01SBen Widawsky spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2357abd58f01SBen Widawsky } 2358abd58f01SBen Widawsky 2359893eead0SChris Wilson static u32 2360893eead0SChris Wilson ring_last_seqno(struct intel_ring_buffer *ring) 2361852835f3SZou Nan hai { 2362893eead0SChris Wilson return list_entry(ring->request_list.prev, 2363893eead0SChris Wilson struct drm_i915_gem_request, list)->seqno; 2364893eead0SChris Wilson } 2365893eead0SChris Wilson 23669107e9d2SChris Wilson static bool 23679107e9d2SChris Wilson ring_idle(struct intel_ring_buffer *ring, u32 seqno) 2368893eead0SChris Wilson { 23699107e9d2SChris Wilson return (list_empty(&ring->request_list) || 23709107e9d2SChris Wilson i915_seqno_passed(seqno, ring_last_seqno(ring))); 2371f65d9421SBen Gamari } 2372f65d9421SBen Gamari 23736274f212SChris Wilson static struct intel_ring_buffer * 23746274f212SChris Wilson semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) 2375a24a11e6SChris Wilson { 2376a24a11e6SChris Wilson struct drm_i915_private *dev_priv = ring->dev->dev_private; 23776274f212SChris Wilson u32 cmd, ipehr, acthd, acthd_min; 2378a24a11e6SChris Wilson 2379a24a11e6SChris Wilson ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 2380a24a11e6SChris Wilson if ((ipehr & ~(0x3 << 16)) != 2381a24a11e6SChris Wilson (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) 23826274f212SChris Wilson return NULL; 2383a24a11e6SChris Wilson 2384a24a11e6SChris Wilson /* ACTHD is likely pointing to the dword after the actual command, 2385a24a11e6SChris Wilson * so scan backwards until we find the MBOX. 2386a24a11e6SChris Wilson */ 23876274f212SChris Wilson acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; 2388a24a11e6SChris Wilson acthd_min = max((int)acthd - 3 * 4, 0); 2389a24a11e6SChris Wilson do { 2390a24a11e6SChris Wilson cmd = ioread32(ring->virtual_start + acthd); 2391a24a11e6SChris Wilson if (cmd == ipehr) 2392a24a11e6SChris Wilson break; 2393a24a11e6SChris Wilson 2394a24a11e6SChris Wilson acthd -= 4; 2395a24a11e6SChris Wilson if (acthd < acthd_min) 23966274f212SChris Wilson return NULL; 2397a24a11e6SChris Wilson } while (1); 2398a24a11e6SChris Wilson 23996274f212SChris Wilson *seqno = ioread32(ring->virtual_start+acthd+4)+1; 24006274f212SChris Wilson return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; 2401a24a11e6SChris Wilson } 2402a24a11e6SChris Wilson 24036274f212SChris Wilson static int semaphore_passed(struct intel_ring_buffer *ring) 24046274f212SChris Wilson { 24056274f212SChris Wilson struct drm_i915_private *dev_priv = ring->dev->dev_private; 24066274f212SChris Wilson struct intel_ring_buffer *signaller; 24076274f212SChris Wilson u32 seqno, ctl; 24086274f212SChris Wilson 24096274f212SChris Wilson ring->hangcheck.deadlock = true; 24106274f212SChris Wilson 24116274f212SChris Wilson signaller = semaphore_waits_for(ring, &seqno); 24126274f212SChris Wilson if (signaller == NULL || signaller->hangcheck.deadlock) 24136274f212SChris Wilson return -1; 24146274f212SChris Wilson 24156274f212SChris Wilson /* cursory check for an unkickable deadlock */ 24166274f212SChris Wilson ctl = I915_READ_CTL(signaller); 24176274f212SChris Wilson if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) 24186274f212SChris Wilson return -1; 24196274f212SChris Wilson 24206274f212SChris Wilson return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); 24216274f212SChris Wilson } 24226274f212SChris Wilson 24236274f212SChris Wilson static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) 24246274f212SChris Wilson { 24256274f212SChris Wilson struct intel_ring_buffer *ring; 24266274f212SChris Wilson int i; 24276274f212SChris Wilson 24286274f212SChris Wilson for_each_ring(ring, dev_priv, i) 24296274f212SChris Wilson ring->hangcheck.deadlock = false; 24306274f212SChris Wilson } 24316274f212SChris Wilson 2432ad8beaeaSMika Kuoppala static enum intel_ring_hangcheck_action 2433ad8beaeaSMika Kuoppala ring_stuck(struct intel_ring_buffer *ring, u32 acthd) 24341ec14ad3SChris Wilson { 24351ec14ad3SChris Wilson struct drm_device *dev = ring->dev; 24361ec14ad3SChris Wilson struct drm_i915_private *dev_priv = dev->dev_private; 24379107e9d2SChris Wilson u32 tmp; 24389107e9d2SChris Wilson 24396274f212SChris Wilson if (ring->hangcheck.acthd != acthd) 2440f2f4d82fSJani Nikula return HANGCHECK_ACTIVE; 24416274f212SChris Wilson 24429107e9d2SChris Wilson if (IS_GEN2(dev)) 2443f2f4d82fSJani Nikula return HANGCHECK_HUNG; 24449107e9d2SChris Wilson 24459107e9d2SChris Wilson /* Is the chip hanging on a WAIT_FOR_EVENT? 24469107e9d2SChris Wilson * If so we can simply poke the RB_WAIT bit 24479107e9d2SChris Wilson * and break the hang. This should work on 24489107e9d2SChris Wilson * all but the second generation chipsets. 24499107e9d2SChris Wilson */ 24509107e9d2SChris Wilson tmp = I915_READ_CTL(ring); 24511ec14ad3SChris Wilson if (tmp & RING_WAIT) { 24521ec14ad3SChris Wilson DRM_ERROR("Kicking stuck wait on %s\n", 24531ec14ad3SChris Wilson ring->name); 245409e14bf3SChris Wilson i915_handle_error(dev, false); 24551ec14ad3SChris Wilson I915_WRITE_CTL(ring, tmp); 2456f2f4d82fSJani Nikula return HANGCHECK_KICK; 24571ec14ad3SChris Wilson } 2458a24a11e6SChris Wilson 24596274f212SChris Wilson if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { 24606274f212SChris Wilson switch (semaphore_passed(ring)) { 24616274f212SChris Wilson default: 2462f2f4d82fSJani Nikula return HANGCHECK_HUNG; 24636274f212SChris Wilson case 1: 2464a24a11e6SChris Wilson DRM_ERROR("Kicking stuck semaphore on %s\n", 2465a24a11e6SChris Wilson ring->name); 246609e14bf3SChris Wilson i915_handle_error(dev, false); 2467a24a11e6SChris Wilson I915_WRITE_CTL(ring, tmp); 2468f2f4d82fSJani Nikula return HANGCHECK_KICK; 24696274f212SChris Wilson case 0: 2470f2f4d82fSJani Nikula return HANGCHECK_WAIT; 24716274f212SChris Wilson } 24729107e9d2SChris Wilson } 24739107e9d2SChris Wilson 2474f2f4d82fSJani Nikula return HANGCHECK_HUNG; 2475a24a11e6SChris Wilson } 2476d1e61e7fSChris Wilson 2477f65d9421SBen Gamari /** 2478f65d9421SBen Gamari * This is called when the chip hasn't reported back with completed 247905407ff8SMika Kuoppala * batchbuffers in a long time. We keep track per ring seqno progress and 248005407ff8SMika Kuoppala * if there are no progress, hangcheck score for that ring is increased. 248105407ff8SMika Kuoppala * Further, acthd is inspected to see if the ring is stuck. On stuck case 248205407ff8SMika Kuoppala * we kick the ring. If we see no progress on three subsequent calls 248305407ff8SMika Kuoppala * we assume chip is wedged and try to fix it by resetting the chip. 2484f65d9421SBen Gamari */ 2485a658b5d2SDamien Lespiau static void i915_hangcheck_elapsed(unsigned long data) 2486f65d9421SBen Gamari { 2487f65d9421SBen Gamari struct drm_device *dev = (struct drm_device *)data; 2488f65d9421SBen Gamari drm_i915_private_t *dev_priv = dev->dev_private; 2489b4519513SChris Wilson struct intel_ring_buffer *ring; 2490b4519513SChris Wilson int i; 249105407ff8SMika Kuoppala int busy_count = 0, rings_hung = 0; 24929107e9d2SChris Wilson bool stuck[I915_NUM_RINGS] = { 0 }; 24939107e9d2SChris Wilson #define BUSY 1 24949107e9d2SChris Wilson #define KICK 5 24959107e9d2SChris Wilson #define HUNG 20 24969107e9d2SChris Wilson #define FIRE 30 2497893eead0SChris Wilson 24983e0dc6b0SBen Widawsky if (!i915_enable_hangcheck) 24993e0dc6b0SBen Widawsky return; 25003e0dc6b0SBen Widawsky 2501b4519513SChris Wilson for_each_ring(ring, dev_priv, i) { 250205407ff8SMika Kuoppala u32 seqno, acthd; 25039107e9d2SChris Wilson bool busy = true; 2504b4519513SChris Wilson 25056274f212SChris Wilson semaphore_clear_deadlocks(dev_priv); 25066274f212SChris Wilson 250705407ff8SMika Kuoppala seqno = ring->get_seqno(ring, false); 250805407ff8SMika Kuoppala acthd = intel_ring_get_active_head(ring); 250905407ff8SMika Kuoppala 251005407ff8SMika Kuoppala if (ring->hangcheck.seqno == seqno) { 25119107e9d2SChris Wilson if (ring_idle(ring, seqno)) { 2512da661464SMika Kuoppala ring->hangcheck.action = HANGCHECK_IDLE; 2513da661464SMika Kuoppala 25149107e9d2SChris Wilson if (waitqueue_active(&ring->irq_queue)) { 25159107e9d2SChris Wilson /* Issue a wake-up to catch stuck h/w. */ 2516094f9a54SChris Wilson if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { 2517f4adcd24SDaniel Vetter if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) 25189107e9d2SChris Wilson DRM_ERROR("Hangcheck timer elapsed... %s idle\n", 25199107e9d2SChris Wilson ring->name); 2520f4adcd24SDaniel Vetter else 2521f4adcd24SDaniel Vetter DRM_INFO("Fake missed irq on %s\n", 2522f4adcd24SDaniel Vetter ring->name); 25239107e9d2SChris Wilson wake_up_all(&ring->irq_queue); 2524094f9a54SChris Wilson } 2525094f9a54SChris Wilson /* Safeguard against driver failure */ 2526094f9a54SChris Wilson ring->hangcheck.score += BUSY; 25279107e9d2SChris Wilson } else 25289107e9d2SChris Wilson busy = false; 252905407ff8SMika Kuoppala } else { 25306274f212SChris Wilson /* We always increment the hangcheck score 25316274f212SChris Wilson * if the ring is busy and still processing 25326274f212SChris Wilson * the same request, so that no single request 25336274f212SChris Wilson * can run indefinitely (such as a chain of 25346274f212SChris Wilson * batches). The only time we do not increment 25356274f212SChris Wilson * the hangcheck score on this ring, if this 25366274f212SChris Wilson * ring is in a legitimate wait for another 25376274f212SChris Wilson * ring. In that case the waiting ring is a 25386274f212SChris Wilson * victim and we want to be sure we catch the 25396274f212SChris Wilson * right culprit. Then every time we do kick 25406274f212SChris Wilson * the ring, add a small increment to the 25416274f212SChris Wilson * score so that we can catch a batch that is 25426274f212SChris Wilson * being repeatedly kicked and so responsible 25436274f212SChris Wilson * for stalling the machine. 25449107e9d2SChris Wilson */ 2545ad8beaeaSMika Kuoppala ring->hangcheck.action = ring_stuck(ring, 2546ad8beaeaSMika Kuoppala acthd); 2547ad8beaeaSMika Kuoppala 2548ad8beaeaSMika Kuoppala switch (ring->hangcheck.action) { 2549da661464SMika Kuoppala case HANGCHECK_IDLE: 2550f2f4d82fSJani Nikula case HANGCHECK_WAIT: 25516274f212SChris Wilson break; 2552f2f4d82fSJani Nikula case HANGCHECK_ACTIVE: 2553ea04cb31SJani Nikula ring->hangcheck.score += BUSY; 25546274f212SChris Wilson break; 2555f2f4d82fSJani Nikula case HANGCHECK_KICK: 2556ea04cb31SJani Nikula ring->hangcheck.score += KICK; 25576274f212SChris Wilson break; 2558f2f4d82fSJani Nikula case HANGCHECK_HUNG: 2559ea04cb31SJani Nikula ring->hangcheck.score += HUNG; 25606274f212SChris Wilson stuck[i] = true; 25616274f212SChris Wilson break; 25626274f212SChris Wilson } 256305407ff8SMika Kuoppala } 25649107e9d2SChris Wilson } else { 2565da661464SMika Kuoppala ring->hangcheck.action = HANGCHECK_ACTIVE; 2566da661464SMika Kuoppala 25679107e9d2SChris Wilson /* Gradually reduce the count so that we catch DoS 25689107e9d2SChris Wilson * attempts across multiple batches. 25699107e9d2SChris Wilson */ 25709107e9d2SChris Wilson if (ring->hangcheck.score > 0) 25719107e9d2SChris Wilson ring->hangcheck.score--; 2572cbb465e7SChris Wilson } 2573f65d9421SBen Gamari 257405407ff8SMika Kuoppala ring->hangcheck.seqno = seqno; 257505407ff8SMika Kuoppala ring->hangcheck.acthd = acthd; 25769107e9d2SChris Wilson busy_count += busy; 257705407ff8SMika Kuoppala } 257805407ff8SMika Kuoppala 257905407ff8SMika Kuoppala for_each_ring(ring, dev_priv, i) { 25809107e9d2SChris Wilson if (ring->hangcheck.score > FIRE) { 2581b8d88d1dSDaniel Vetter DRM_INFO("%s on %s\n", 258205407ff8SMika Kuoppala stuck[i] ? "stuck" : "no progress", 2583a43adf07SChris Wilson ring->name); 2584a43adf07SChris Wilson rings_hung++; 258505407ff8SMika Kuoppala } 258605407ff8SMika Kuoppala } 258705407ff8SMika Kuoppala 258805407ff8SMika Kuoppala if (rings_hung) 258905407ff8SMika Kuoppala return i915_handle_error(dev, true); 259005407ff8SMika Kuoppala 259105407ff8SMika Kuoppala if (busy_count) 259205407ff8SMika Kuoppala /* Reset timer case chip hangs without another request 259305407ff8SMika Kuoppala * being added */ 259410cd45b6SMika Kuoppala i915_queue_hangcheck(dev); 259510cd45b6SMika Kuoppala } 259610cd45b6SMika Kuoppala 259710cd45b6SMika Kuoppala void i915_queue_hangcheck(struct drm_device *dev) 259810cd45b6SMika Kuoppala { 259910cd45b6SMika Kuoppala struct drm_i915_private *dev_priv = dev->dev_private; 260010cd45b6SMika Kuoppala if (!i915_enable_hangcheck) 260110cd45b6SMika Kuoppala return; 260210cd45b6SMika Kuoppala 260399584db3SDaniel Vetter mod_timer(&dev_priv->gpu_error.hangcheck_timer, 260410cd45b6SMika Kuoppala round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 2605f65d9421SBen Gamari } 2606f65d9421SBen Gamari 260791738a95SPaulo Zanoni static void ibx_irq_preinstall(struct drm_device *dev) 260891738a95SPaulo Zanoni { 260991738a95SPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 261091738a95SPaulo Zanoni 261191738a95SPaulo Zanoni if (HAS_PCH_NOP(dev)) 261291738a95SPaulo Zanoni return; 261391738a95SPaulo Zanoni 261491738a95SPaulo Zanoni /* south display irq */ 261591738a95SPaulo Zanoni I915_WRITE(SDEIMR, 0xffffffff); 261691738a95SPaulo Zanoni /* 261791738a95SPaulo Zanoni * SDEIER is also touched by the interrupt handler to work around missed 261891738a95SPaulo Zanoni * PCH interrupts. Hence we can't update it after the interrupt handler 261991738a95SPaulo Zanoni * is enabled - instead we unconditionally enable all PCH interrupt 262091738a95SPaulo Zanoni * sources here, but then only unmask them as needed with SDEIMR. 262191738a95SPaulo Zanoni */ 262291738a95SPaulo Zanoni I915_WRITE(SDEIER, 0xffffffff); 262391738a95SPaulo Zanoni POSTING_READ(SDEIER); 262491738a95SPaulo Zanoni } 262591738a95SPaulo Zanoni 2626d18ea1b5SDaniel Vetter static void gen5_gt_irq_preinstall(struct drm_device *dev) 2627d18ea1b5SDaniel Vetter { 2628d18ea1b5SDaniel Vetter struct drm_i915_private *dev_priv = dev->dev_private; 2629d18ea1b5SDaniel Vetter 2630d18ea1b5SDaniel Vetter /* and GT */ 2631d18ea1b5SDaniel Vetter I915_WRITE(GTIMR, 0xffffffff); 2632d18ea1b5SDaniel Vetter I915_WRITE(GTIER, 0x0); 2633d18ea1b5SDaniel Vetter POSTING_READ(GTIER); 2634d18ea1b5SDaniel Vetter 2635d18ea1b5SDaniel Vetter if (INTEL_INFO(dev)->gen >= 6) { 2636d18ea1b5SDaniel Vetter /* and PM */ 2637d18ea1b5SDaniel Vetter I915_WRITE(GEN6_PMIMR, 0xffffffff); 2638d18ea1b5SDaniel Vetter I915_WRITE(GEN6_PMIER, 0x0); 2639d18ea1b5SDaniel Vetter POSTING_READ(GEN6_PMIER); 2640d18ea1b5SDaniel Vetter } 2641d18ea1b5SDaniel Vetter } 2642d18ea1b5SDaniel Vetter 2643c0e09200SDave Airlie /* drm_dma.h hooks 2644c0e09200SDave Airlie */ 2645f71d4af4SJesse Barnes static void ironlake_irq_preinstall(struct drm_device *dev) 2646036a4a7dSZhenyu Wang { 2647036a4a7dSZhenyu Wang drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2648036a4a7dSZhenyu Wang 2649036a4a7dSZhenyu Wang I915_WRITE(HWSTAM, 0xeffe); 2650bdfcdb63SDaniel Vetter 2651036a4a7dSZhenyu Wang I915_WRITE(DEIMR, 0xffffffff); 2652036a4a7dSZhenyu Wang I915_WRITE(DEIER, 0x0); 26533143a2bfSChris Wilson POSTING_READ(DEIER); 2654036a4a7dSZhenyu Wang 2655d18ea1b5SDaniel Vetter gen5_gt_irq_preinstall(dev); 2656c650156aSZhenyu Wang 265791738a95SPaulo Zanoni ibx_irq_preinstall(dev); 26587d99163dSBen Widawsky } 26597d99163dSBen Widawsky 26607e231dbeSJesse Barnes static void valleyview_irq_preinstall(struct drm_device *dev) 26617e231dbeSJesse Barnes { 26627e231dbeSJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 26637e231dbeSJesse Barnes int pipe; 26647e231dbeSJesse Barnes 26657e231dbeSJesse Barnes /* VLV magic */ 26667e231dbeSJesse Barnes I915_WRITE(VLV_IMR, 0); 26677e231dbeSJesse Barnes I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); 26687e231dbeSJesse Barnes I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); 26697e231dbeSJesse Barnes I915_WRITE(RING_IMR(BLT_RING_BASE), 0); 26707e231dbeSJesse Barnes 26717e231dbeSJesse Barnes /* and GT */ 26727e231dbeSJesse Barnes I915_WRITE(GTIIR, I915_READ(GTIIR)); 26737e231dbeSJesse Barnes I915_WRITE(GTIIR, I915_READ(GTIIR)); 2674d18ea1b5SDaniel Vetter 2675d18ea1b5SDaniel Vetter gen5_gt_irq_preinstall(dev); 26767e231dbeSJesse Barnes 26777e231dbeSJesse Barnes I915_WRITE(DPINVGTT, 0xff); 26787e231dbeSJesse Barnes 26797e231dbeSJesse Barnes I915_WRITE(PORT_HOTPLUG_EN, 0); 26807e231dbeSJesse Barnes I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 26817e231dbeSJesse Barnes for_each_pipe(pipe) 26827e231dbeSJesse Barnes I915_WRITE(PIPESTAT(pipe), 0xffff); 26837e231dbeSJesse Barnes I915_WRITE(VLV_IIR, 0xffffffff); 26847e231dbeSJesse Barnes I915_WRITE(VLV_IMR, 0xffffffff); 26857e231dbeSJesse Barnes I915_WRITE(VLV_IER, 0x0); 26867e231dbeSJesse Barnes POSTING_READ(VLV_IER); 26877e231dbeSJesse Barnes } 26887e231dbeSJesse Barnes 2689abd58f01SBen Widawsky static void gen8_irq_preinstall(struct drm_device *dev) 2690abd58f01SBen Widawsky { 2691abd58f01SBen Widawsky struct drm_i915_private *dev_priv = dev->dev_private; 2692abd58f01SBen Widawsky int pipe; 2693abd58f01SBen Widawsky 2694abd58f01SBen Widawsky I915_WRITE(GEN8_MASTER_IRQ, 0); 2695abd58f01SBen Widawsky POSTING_READ(GEN8_MASTER_IRQ); 2696abd58f01SBen Widawsky 2697abd58f01SBen Widawsky /* IIR can theoretically queue up two events. Be paranoid */ 2698abd58f01SBen Widawsky #define GEN8_IRQ_INIT_NDX(type, which) do { \ 2699abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ 2700abd58f01SBen Widawsky POSTING_READ(GEN8_##type##_IMR(which)); \ 2701abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IER(which), 0); \ 2702abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ 2703abd58f01SBen Widawsky POSTING_READ(GEN8_##type##_IIR(which)); \ 2704abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ 2705abd58f01SBen Widawsky } while (0) 2706abd58f01SBen Widawsky 2707abd58f01SBen Widawsky #define GEN8_IRQ_INIT(type) do { \ 2708abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ 2709abd58f01SBen Widawsky POSTING_READ(GEN8_##type##_IMR); \ 2710abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IER, 0); \ 2711abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ 2712abd58f01SBen Widawsky POSTING_READ(GEN8_##type##_IIR); \ 2713abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ 2714abd58f01SBen Widawsky } while (0) 2715abd58f01SBen Widawsky 2716abd58f01SBen Widawsky GEN8_IRQ_INIT_NDX(GT, 0); 2717abd58f01SBen Widawsky GEN8_IRQ_INIT_NDX(GT, 1); 2718abd58f01SBen Widawsky GEN8_IRQ_INIT_NDX(GT, 2); 2719abd58f01SBen Widawsky GEN8_IRQ_INIT_NDX(GT, 3); 2720abd58f01SBen Widawsky 2721abd58f01SBen Widawsky for_each_pipe(pipe) { 2722abd58f01SBen Widawsky GEN8_IRQ_INIT_NDX(DE_PIPE, pipe); 2723abd58f01SBen Widawsky } 2724abd58f01SBen Widawsky 2725abd58f01SBen Widawsky GEN8_IRQ_INIT(DE_PORT); 2726abd58f01SBen Widawsky GEN8_IRQ_INIT(DE_MISC); 2727abd58f01SBen Widawsky GEN8_IRQ_INIT(PCU); 2728abd58f01SBen Widawsky #undef GEN8_IRQ_INIT 2729abd58f01SBen Widawsky #undef GEN8_IRQ_INIT_NDX 2730abd58f01SBen Widawsky 2731abd58f01SBen Widawsky POSTING_READ(GEN8_PCU_IIR); 273209f2344dSJesse Barnes 273309f2344dSJesse Barnes ibx_irq_preinstall(dev); 2734abd58f01SBen Widawsky } 2735abd58f01SBen Widawsky 273682a28bcfSDaniel Vetter static void ibx_hpd_irq_setup(struct drm_device *dev) 273782a28bcfSDaniel Vetter { 273882a28bcfSDaniel Vetter drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 273982a28bcfSDaniel Vetter struct drm_mode_config *mode_config = &dev->mode_config; 274082a28bcfSDaniel Vetter struct intel_encoder *intel_encoder; 2741fee884edSDaniel Vetter u32 hotplug_irqs, hotplug, enabled_irqs = 0; 274282a28bcfSDaniel Vetter 274382a28bcfSDaniel Vetter if (HAS_PCH_IBX(dev)) { 2744fee884edSDaniel Vetter hotplug_irqs = SDE_HOTPLUG_MASK; 274582a28bcfSDaniel Vetter list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 2746cd569aedSEgbert Eich if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 2747fee884edSDaniel Vetter enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; 274882a28bcfSDaniel Vetter } else { 2749fee884edSDaniel Vetter hotplug_irqs = SDE_HOTPLUG_MASK_CPT; 275082a28bcfSDaniel Vetter list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 2751cd569aedSEgbert Eich if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 2752fee884edSDaniel Vetter enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; 275382a28bcfSDaniel Vetter } 275482a28bcfSDaniel Vetter 2755fee884edSDaniel Vetter ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 275682a28bcfSDaniel Vetter 27577fe0b973SKeith Packard /* 27587fe0b973SKeith Packard * Enable digital hotplug on the PCH, and configure the DP short pulse 27597fe0b973SKeith Packard * duration to 2ms (which is the minimum in the Display Port spec) 27607fe0b973SKeith Packard * 27617fe0b973SKeith Packard * This register is the same on all known PCH chips. 27627fe0b973SKeith Packard */ 27637fe0b973SKeith Packard hotplug = I915_READ(PCH_PORT_HOTPLUG); 27647fe0b973SKeith Packard hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); 27657fe0b973SKeith Packard hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; 27667fe0b973SKeith Packard hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; 27677fe0b973SKeith Packard hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; 27687fe0b973SKeith Packard I915_WRITE(PCH_PORT_HOTPLUG, hotplug); 27697fe0b973SKeith Packard } 27707fe0b973SKeith Packard 2771d46da437SPaulo Zanoni static void ibx_irq_postinstall(struct drm_device *dev) 2772d46da437SPaulo Zanoni { 2773d46da437SPaulo Zanoni drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 277482a28bcfSDaniel Vetter u32 mask; 2775d46da437SPaulo Zanoni 2776692a04cfSDaniel Vetter if (HAS_PCH_NOP(dev)) 2777692a04cfSDaniel Vetter return; 2778692a04cfSDaniel Vetter 27798664281bSPaulo Zanoni if (HAS_PCH_IBX(dev)) { 27808664281bSPaulo Zanoni mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER | 2781de032bf4SPaulo Zanoni SDE_TRANSA_FIFO_UNDER | SDE_POISON; 27828664281bSPaulo Zanoni } else { 27838664281bSPaulo Zanoni mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; 27848664281bSPaulo Zanoni 27858664281bSPaulo Zanoni I915_WRITE(SERR_INT, I915_READ(SERR_INT)); 27868664281bSPaulo Zanoni } 2787ab5c608bSBen Widawsky 2788d46da437SPaulo Zanoni I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 2789d46da437SPaulo Zanoni I915_WRITE(SDEIMR, ~mask); 2790d46da437SPaulo Zanoni } 2791d46da437SPaulo Zanoni 27920a9a8c91SDaniel Vetter static void gen5_gt_irq_postinstall(struct drm_device *dev) 27930a9a8c91SDaniel Vetter { 27940a9a8c91SDaniel Vetter struct drm_i915_private *dev_priv = dev->dev_private; 27950a9a8c91SDaniel Vetter u32 pm_irqs, gt_irqs; 27960a9a8c91SDaniel Vetter 27970a9a8c91SDaniel Vetter pm_irqs = gt_irqs = 0; 27980a9a8c91SDaniel Vetter 27990a9a8c91SDaniel Vetter dev_priv->gt_irq_mask = ~0; 2800040d2baaSBen Widawsky if (HAS_L3_DPF(dev)) { 28010a9a8c91SDaniel Vetter /* L3 parity interrupt is always unmasked. */ 280235a85ac6SBen Widawsky dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); 280335a85ac6SBen Widawsky gt_irqs |= GT_PARITY_ERROR(dev); 28040a9a8c91SDaniel Vetter } 28050a9a8c91SDaniel Vetter 28060a9a8c91SDaniel Vetter gt_irqs |= GT_RENDER_USER_INTERRUPT; 28070a9a8c91SDaniel Vetter if (IS_GEN5(dev)) { 28080a9a8c91SDaniel Vetter gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | 28090a9a8c91SDaniel Vetter ILK_BSD_USER_INTERRUPT; 28100a9a8c91SDaniel Vetter } else { 28110a9a8c91SDaniel Vetter gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; 28120a9a8c91SDaniel Vetter } 28130a9a8c91SDaniel Vetter 28140a9a8c91SDaniel Vetter I915_WRITE(GTIIR, I915_READ(GTIIR)); 28150a9a8c91SDaniel Vetter I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 28160a9a8c91SDaniel Vetter I915_WRITE(GTIER, gt_irqs); 28170a9a8c91SDaniel Vetter POSTING_READ(GTIER); 28180a9a8c91SDaniel Vetter 28190a9a8c91SDaniel Vetter if (INTEL_INFO(dev)->gen >= 6) { 28200a9a8c91SDaniel Vetter pm_irqs |= GEN6_PM_RPS_EVENTS; 28210a9a8c91SDaniel Vetter 28220a9a8c91SDaniel Vetter if (HAS_VEBOX(dev)) 28230a9a8c91SDaniel Vetter pm_irqs |= PM_VEBOX_USER_INTERRUPT; 28240a9a8c91SDaniel Vetter 2825605cd25bSPaulo Zanoni dev_priv->pm_irq_mask = 0xffffffff; 28260a9a8c91SDaniel Vetter I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); 2827605cd25bSPaulo Zanoni I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); 28280a9a8c91SDaniel Vetter I915_WRITE(GEN6_PMIER, pm_irqs); 28290a9a8c91SDaniel Vetter POSTING_READ(GEN6_PMIER); 28300a9a8c91SDaniel Vetter } 28310a9a8c91SDaniel Vetter } 28320a9a8c91SDaniel Vetter 2833f71d4af4SJesse Barnes static int ironlake_irq_postinstall(struct drm_device *dev) 2834036a4a7dSZhenyu Wang { 28354bc9d430SDaniel Vetter unsigned long irqflags; 2836036a4a7dSZhenyu Wang drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 28378e76f8dcSPaulo Zanoni u32 display_mask, extra_mask; 28388e76f8dcSPaulo Zanoni 28398e76f8dcSPaulo Zanoni if (INTEL_INFO(dev)->gen >= 7) { 28408e76f8dcSPaulo Zanoni display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 28418e76f8dcSPaulo Zanoni DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | 28428e76f8dcSPaulo Zanoni DE_PLANEB_FLIP_DONE_IVB | 28438e76f8dcSPaulo Zanoni DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB | 28448e76f8dcSPaulo Zanoni DE_ERR_INT_IVB); 28458e76f8dcSPaulo Zanoni extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | 28468e76f8dcSPaulo Zanoni DE_PIPEA_VBLANK_IVB); 28478e76f8dcSPaulo Zanoni 28488e76f8dcSPaulo Zanoni I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); 28498e76f8dcSPaulo Zanoni } else { 28508e76f8dcSPaulo Zanoni display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 2851ce99c256SDaniel Vetter DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | 28525b3a856bSDaniel Vetter DE_AUX_CHANNEL_A | 28535b3a856bSDaniel Vetter DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | 28545b3a856bSDaniel Vetter DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | 28555b3a856bSDaniel Vetter DE_POISON); 28568e76f8dcSPaulo Zanoni extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT; 28578e76f8dcSPaulo Zanoni } 2858036a4a7dSZhenyu Wang 28591ec14ad3SChris Wilson dev_priv->irq_mask = ~display_mask; 2860036a4a7dSZhenyu Wang 2861036a4a7dSZhenyu Wang /* should always can generate irq */ 2862036a4a7dSZhenyu Wang I915_WRITE(DEIIR, I915_READ(DEIIR)); 28631ec14ad3SChris Wilson I915_WRITE(DEIMR, dev_priv->irq_mask); 28648e76f8dcSPaulo Zanoni I915_WRITE(DEIER, display_mask | extra_mask); 28653143a2bfSChris Wilson POSTING_READ(DEIER); 2866036a4a7dSZhenyu Wang 28670a9a8c91SDaniel Vetter gen5_gt_irq_postinstall(dev); 2868036a4a7dSZhenyu Wang 2869d46da437SPaulo Zanoni ibx_irq_postinstall(dev); 28707fe0b973SKeith Packard 2871f97108d1SJesse Barnes if (IS_IRONLAKE_M(dev)) { 28726005ce42SDaniel Vetter /* Enable PCU event interrupts 28736005ce42SDaniel Vetter * 28746005ce42SDaniel Vetter * spinlocking not required here for correctness since interrupt 28754bc9d430SDaniel Vetter * setup is guaranteed to run in single-threaded context. But we 28764bc9d430SDaniel Vetter * need it to make the assert_spin_locked happy. */ 28774bc9d430SDaniel Vetter spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2878f97108d1SJesse Barnes ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); 28794bc9d430SDaniel Vetter spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2880f97108d1SJesse Barnes } 2881f97108d1SJesse Barnes 2882036a4a7dSZhenyu Wang return 0; 2883036a4a7dSZhenyu Wang } 2884036a4a7dSZhenyu Wang 28857e231dbeSJesse Barnes static int valleyview_irq_postinstall(struct drm_device *dev) 28867e231dbeSJesse Barnes { 28877e231dbeSJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 28887e231dbeSJesse Barnes u32 enable_mask; 2889379ef82dSDaniel Vetter u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV | 2890379ef82dSDaniel Vetter PIPE_CRC_DONE_ENABLE; 2891b79480baSDaniel Vetter unsigned long irqflags; 28927e231dbeSJesse Barnes 28937e231dbeSJesse Barnes enable_mask = I915_DISPLAY_PORT_INTERRUPT; 289431acc7f5SJesse Barnes enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 289531acc7f5SJesse Barnes I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | 289631acc7f5SJesse Barnes I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 28977e231dbeSJesse Barnes I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 28987e231dbeSJesse Barnes 289931acc7f5SJesse Barnes /* 290031acc7f5SJesse Barnes *Leave vblank interrupts masked initially. enable/disable will 290131acc7f5SJesse Barnes * toggle them based on usage. 290231acc7f5SJesse Barnes */ 290331acc7f5SJesse Barnes dev_priv->irq_mask = (~enable_mask) | 290431acc7f5SJesse Barnes I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | 290531acc7f5SJesse Barnes I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 29067e231dbeSJesse Barnes 290720afbda2SDaniel Vetter I915_WRITE(PORT_HOTPLUG_EN, 0); 290820afbda2SDaniel Vetter POSTING_READ(PORT_HOTPLUG_EN); 290920afbda2SDaniel Vetter 29107e231dbeSJesse Barnes I915_WRITE(VLV_IMR, dev_priv->irq_mask); 29117e231dbeSJesse Barnes I915_WRITE(VLV_IER, enable_mask); 29127e231dbeSJesse Barnes I915_WRITE(VLV_IIR, 0xffffffff); 29137e231dbeSJesse Barnes I915_WRITE(PIPESTAT(0), 0xffff); 29147e231dbeSJesse Barnes I915_WRITE(PIPESTAT(1), 0xffff); 29157e231dbeSJesse Barnes POSTING_READ(VLV_IER); 29167e231dbeSJesse Barnes 2917b79480baSDaniel Vetter /* Interrupt setup is already guaranteed to be single-threaded, this is 2918b79480baSDaniel Vetter * just to make the assert_spin_locked check happy. */ 2919b79480baSDaniel Vetter spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 29203b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable); 29213b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); 29223b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable); 2923b79480baSDaniel Vetter spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 292431acc7f5SJesse Barnes 29257e231dbeSJesse Barnes I915_WRITE(VLV_IIR, 0xffffffff); 29267e231dbeSJesse Barnes I915_WRITE(VLV_IIR, 0xffffffff); 29277e231dbeSJesse Barnes 29280a9a8c91SDaniel Vetter gen5_gt_irq_postinstall(dev); 29297e231dbeSJesse Barnes 29307e231dbeSJesse Barnes /* ack & enable invalid PTE error interrupts */ 29317e231dbeSJesse Barnes #if 0 /* FIXME: add support to irq handler for checking these bits */ 29327e231dbeSJesse Barnes I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); 29337e231dbeSJesse Barnes I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); 29347e231dbeSJesse Barnes #endif 29357e231dbeSJesse Barnes 29367e231dbeSJesse Barnes I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 293720afbda2SDaniel Vetter 293820afbda2SDaniel Vetter return 0; 293920afbda2SDaniel Vetter } 294020afbda2SDaniel Vetter 2941abd58f01SBen Widawsky static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) 2942abd58f01SBen Widawsky { 2943abd58f01SBen Widawsky int i; 2944abd58f01SBen Widawsky 2945abd58f01SBen Widawsky /* These are interrupts we'll toggle with the ring mask register */ 2946abd58f01SBen Widawsky uint32_t gt_interrupts[] = { 2947abd58f01SBen Widawsky GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | 2948abd58f01SBen Widawsky GT_RENDER_L3_PARITY_ERROR_INTERRUPT | 2949abd58f01SBen Widawsky GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, 2950abd58f01SBen Widawsky GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | 2951abd58f01SBen Widawsky GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, 2952abd58f01SBen Widawsky 0, 2953abd58f01SBen Widawsky GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT 2954abd58f01SBen Widawsky }; 2955abd58f01SBen Widawsky 2956abd58f01SBen Widawsky for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) { 2957abd58f01SBen Widawsky u32 tmp = I915_READ(GEN8_GT_IIR(i)); 2958abd58f01SBen Widawsky if (tmp) 2959abd58f01SBen Widawsky DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", 2960abd58f01SBen Widawsky i, tmp); 2961abd58f01SBen Widawsky I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]); 2962abd58f01SBen Widawsky I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]); 2963abd58f01SBen Widawsky } 2964abd58f01SBen Widawsky POSTING_READ(GEN8_GT_IER(0)); 2965abd58f01SBen Widawsky } 2966abd58f01SBen Widawsky 2967abd58f01SBen Widawsky static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 2968abd58f01SBen Widawsky { 2969abd58f01SBen Widawsky struct drm_device *dev = dev_priv->dev; 297013b3a0a7SDaniel Vetter uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE | 29710fbe7870SDaniel Vetter GEN8_PIPE_CDCLK_CRC_DONE | 297238d83c96SDaniel Vetter GEN8_PIPE_FIFO_UNDERRUN | 297330100f2bSDaniel Vetter GEN8_DE_PIPE_IRQ_FAULT_ERRORS; 297413b3a0a7SDaniel Vetter uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK; 2975abd58f01SBen Widawsky int pipe; 297613b3a0a7SDaniel Vetter dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; 297713b3a0a7SDaniel Vetter dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; 297813b3a0a7SDaniel Vetter dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; 2979abd58f01SBen Widawsky 2980abd58f01SBen Widawsky for_each_pipe(pipe) { 2981abd58f01SBen Widawsky u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe)); 2982abd58f01SBen Widawsky if (tmp) 2983abd58f01SBen Widawsky DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", 2984abd58f01SBen Widawsky pipe, tmp); 2985abd58f01SBen Widawsky I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 2986abd58f01SBen Widawsky I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables); 2987abd58f01SBen Widawsky } 2988abd58f01SBen Widawsky POSTING_READ(GEN8_DE_PIPE_ISR(0)); 2989abd58f01SBen Widawsky 29906d766f02SDaniel Vetter I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A); 29916d766f02SDaniel Vetter I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A); 2992abd58f01SBen Widawsky POSTING_READ(GEN8_DE_PORT_IER); 2993abd58f01SBen Widawsky } 2994abd58f01SBen Widawsky 2995abd58f01SBen Widawsky static int gen8_irq_postinstall(struct drm_device *dev) 2996abd58f01SBen Widawsky { 2997abd58f01SBen Widawsky struct drm_i915_private *dev_priv = dev->dev_private; 2998abd58f01SBen Widawsky 2999abd58f01SBen Widawsky gen8_gt_irq_postinstall(dev_priv); 3000abd58f01SBen Widawsky gen8_de_irq_postinstall(dev_priv); 3001abd58f01SBen Widawsky 3002abd58f01SBen Widawsky ibx_irq_postinstall(dev); 3003abd58f01SBen Widawsky 3004abd58f01SBen Widawsky I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); 3005abd58f01SBen Widawsky POSTING_READ(GEN8_MASTER_IRQ); 3006abd58f01SBen Widawsky 3007abd58f01SBen Widawsky return 0; 3008abd58f01SBen Widawsky } 3009abd58f01SBen Widawsky 3010abd58f01SBen Widawsky static void gen8_irq_uninstall(struct drm_device *dev) 3011abd58f01SBen Widawsky { 3012abd58f01SBen Widawsky struct drm_i915_private *dev_priv = dev->dev_private; 3013abd58f01SBen Widawsky int pipe; 3014abd58f01SBen Widawsky 3015abd58f01SBen Widawsky if (!dev_priv) 3016abd58f01SBen Widawsky return; 3017abd58f01SBen Widawsky 3018abd58f01SBen Widawsky I915_WRITE(GEN8_MASTER_IRQ, 0); 3019abd58f01SBen Widawsky 3020abd58f01SBen Widawsky #define GEN8_IRQ_FINI_NDX(type, which) do { \ 3021abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ 3022abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IER(which), 0); \ 3023abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ 3024abd58f01SBen Widawsky } while (0) 3025abd58f01SBen Widawsky 3026abd58f01SBen Widawsky #define GEN8_IRQ_FINI(type) do { \ 3027abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ 3028abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IER, 0); \ 3029abd58f01SBen Widawsky I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ 3030abd58f01SBen Widawsky } while (0) 3031abd58f01SBen Widawsky 3032abd58f01SBen Widawsky GEN8_IRQ_FINI_NDX(GT, 0); 3033abd58f01SBen Widawsky GEN8_IRQ_FINI_NDX(GT, 1); 3034abd58f01SBen Widawsky GEN8_IRQ_FINI_NDX(GT, 2); 3035abd58f01SBen Widawsky GEN8_IRQ_FINI_NDX(GT, 3); 3036abd58f01SBen Widawsky 3037abd58f01SBen Widawsky for_each_pipe(pipe) { 3038abd58f01SBen Widawsky GEN8_IRQ_FINI_NDX(DE_PIPE, pipe); 3039abd58f01SBen Widawsky } 3040abd58f01SBen Widawsky 3041abd58f01SBen Widawsky GEN8_IRQ_FINI(DE_PORT); 3042abd58f01SBen Widawsky GEN8_IRQ_FINI(DE_MISC); 3043abd58f01SBen Widawsky GEN8_IRQ_FINI(PCU); 3044abd58f01SBen Widawsky #undef GEN8_IRQ_FINI 3045abd58f01SBen Widawsky #undef GEN8_IRQ_FINI_NDX 3046abd58f01SBen Widawsky 3047abd58f01SBen Widawsky POSTING_READ(GEN8_PCU_IIR); 3048abd58f01SBen Widawsky } 3049abd58f01SBen Widawsky 30507e231dbeSJesse Barnes static void valleyview_irq_uninstall(struct drm_device *dev) 30517e231dbeSJesse Barnes { 30527e231dbeSJesse Barnes drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 30537e231dbeSJesse Barnes int pipe; 30547e231dbeSJesse Barnes 30557e231dbeSJesse Barnes if (!dev_priv) 30567e231dbeSJesse Barnes return; 30577e231dbeSJesse Barnes 30583ca1ccedSVille Syrjälä intel_hpd_irq_uninstall(dev_priv); 3059ac4c16c5SEgbert Eich 30607e231dbeSJesse Barnes for_each_pipe(pipe) 30617e231dbeSJesse Barnes I915_WRITE(PIPESTAT(pipe), 0xffff); 30627e231dbeSJesse Barnes 30637e231dbeSJesse Barnes I915_WRITE(HWSTAM, 0xffffffff); 30647e231dbeSJesse Barnes I915_WRITE(PORT_HOTPLUG_EN, 0); 30657e231dbeSJesse Barnes I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 30667e231dbeSJesse Barnes for_each_pipe(pipe) 30677e231dbeSJesse Barnes I915_WRITE(PIPESTAT(pipe), 0xffff); 30687e231dbeSJesse Barnes I915_WRITE(VLV_IIR, 0xffffffff); 30697e231dbeSJesse Barnes I915_WRITE(VLV_IMR, 0xffffffff); 30707e231dbeSJesse Barnes I915_WRITE(VLV_IER, 0x0); 30717e231dbeSJesse Barnes POSTING_READ(VLV_IER); 30727e231dbeSJesse Barnes } 30737e231dbeSJesse Barnes 3074f71d4af4SJesse Barnes static void ironlake_irq_uninstall(struct drm_device *dev) 3075036a4a7dSZhenyu Wang { 3076036a4a7dSZhenyu Wang drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 30774697995bSJesse Barnes 30784697995bSJesse Barnes if (!dev_priv) 30794697995bSJesse Barnes return; 30804697995bSJesse Barnes 30813ca1ccedSVille Syrjälä intel_hpd_irq_uninstall(dev_priv); 3082ac4c16c5SEgbert Eich 3083036a4a7dSZhenyu Wang I915_WRITE(HWSTAM, 0xffffffff); 3084036a4a7dSZhenyu Wang 3085036a4a7dSZhenyu Wang I915_WRITE(DEIMR, 0xffffffff); 3086036a4a7dSZhenyu Wang I915_WRITE(DEIER, 0x0); 3087036a4a7dSZhenyu Wang I915_WRITE(DEIIR, I915_READ(DEIIR)); 30888664281bSPaulo Zanoni if (IS_GEN7(dev)) 30898664281bSPaulo Zanoni I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); 3090036a4a7dSZhenyu Wang 3091036a4a7dSZhenyu Wang I915_WRITE(GTIMR, 0xffffffff); 3092036a4a7dSZhenyu Wang I915_WRITE(GTIER, 0x0); 3093036a4a7dSZhenyu Wang I915_WRITE(GTIIR, I915_READ(GTIIR)); 3094192aac1fSKeith Packard 3095ab5c608bSBen Widawsky if (HAS_PCH_NOP(dev)) 3096ab5c608bSBen Widawsky return; 3097ab5c608bSBen Widawsky 3098192aac1fSKeith Packard I915_WRITE(SDEIMR, 0xffffffff); 3099192aac1fSKeith Packard I915_WRITE(SDEIER, 0x0); 3100192aac1fSKeith Packard I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 31018664281bSPaulo Zanoni if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) 31028664281bSPaulo Zanoni I915_WRITE(SERR_INT, I915_READ(SERR_INT)); 3103036a4a7dSZhenyu Wang } 3104036a4a7dSZhenyu Wang 3105c2798b19SChris Wilson static void i8xx_irq_preinstall(struct drm_device * dev) 3106c2798b19SChris Wilson { 3107c2798b19SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3108c2798b19SChris Wilson int pipe; 3109c2798b19SChris Wilson 3110c2798b19SChris Wilson for_each_pipe(pipe) 3111c2798b19SChris Wilson I915_WRITE(PIPESTAT(pipe), 0); 3112c2798b19SChris Wilson I915_WRITE16(IMR, 0xffff); 3113c2798b19SChris Wilson I915_WRITE16(IER, 0x0); 3114c2798b19SChris Wilson POSTING_READ16(IER); 3115c2798b19SChris Wilson } 3116c2798b19SChris Wilson 3117c2798b19SChris Wilson static int i8xx_irq_postinstall(struct drm_device *dev) 3118c2798b19SChris Wilson { 3119c2798b19SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3120379ef82dSDaniel Vetter unsigned long irqflags; 3121c2798b19SChris Wilson 3122c2798b19SChris Wilson I915_WRITE16(EMR, 3123c2798b19SChris Wilson ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 3124c2798b19SChris Wilson 3125c2798b19SChris Wilson /* Unmask the interrupts that we always want on. */ 3126c2798b19SChris Wilson dev_priv->irq_mask = 3127c2798b19SChris Wilson ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3128c2798b19SChris Wilson I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3129c2798b19SChris Wilson I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3130c2798b19SChris Wilson I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 3131c2798b19SChris Wilson I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 3132c2798b19SChris Wilson I915_WRITE16(IMR, dev_priv->irq_mask); 3133c2798b19SChris Wilson 3134c2798b19SChris Wilson I915_WRITE16(IER, 3135c2798b19SChris Wilson I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3136c2798b19SChris Wilson I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3137c2798b19SChris Wilson I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 3138c2798b19SChris Wilson I915_USER_INTERRUPT); 3139c2798b19SChris Wilson POSTING_READ16(IER); 3140c2798b19SChris Wilson 3141379ef82dSDaniel Vetter /* Interrupt setup is already guaranteed to be single-threaded, this is 3142379ef82dSDaniel Vetter * just to make the assert_spin_locked check happy. */ 3143379ef82dSDaniel Vetter spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 31443b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); 31453b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); 3146379ef82dSDaniel Vetter spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3147379ef82dSDaniel Vetter 3148c2798b19SChris Wilson return 0; 3149c2798b19SChris Wilson } 3150c2798b19SChris Wilson 315190a72f87SVille Syrjälä /* 315290a72f87SVille Syrjälä * Returns true when a page flip has completed. 315390a72f87SVille Syrjälä */ 315490a72f87SVille Syrjälä static bool i8xx_handle_vblank(struct drm_device *dev, 31551f1c2e24SVille Syrjälä int plane, int pipe, u32 iir) 315690a72f87SVille Syrjälä { 315790a72f87SVille Syrjälä drm_i915_private_t *dev_priv = dev->dev_private; 31581f1c2e24SVille Syrjälä u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); 315990a72f87SVille Syrjälä 316090a72f87SVille Syrjälä if (!drm_handle_vblank(dev, pipe)) 316190a72f87SVille Syrjälä return false; 316290a72f87SVille Syrjälä 316390a72f87SVille Syrjälä if ((iir & flip_pending) == 0) 316490a72f87SVille Syrjälä return false; 316590a72f87SVille Syrjälä 31661f1c2e24SVille Syrjälä intel_prepare_page_flip(dev, plane); 316790a72f87SVille Syrjälä 316890a72f87SVille Syrjälä /* We detect FlipDone by looking for the change in PendingFlip from '1' 316990a72f87SVille Syrjälä * to '0' on the following vblank, i.e. IIR has the Pendingflip 317090a72f87SVille Syrjälä * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence 317190a72f87SVille Syrjälä * the flip is completed (no longer pending). Since this doesn't raise 317290a72f87SVille Syrjälä * an interrupt per se, we watch for the change at vblank. 317390a72f87SVille Syrjälä */ 317490a72f87SVille Syrjälä if (I915_READ16(ISR) & flip_pending) 317590a72f87SVille Syrjälä return false; 317690a72f87SVille Syrjälä 317790a72f87SVille Syrjälä intel_finish_page_flip(dev, pipe); 317890a72f87SVille Syrjälä 317990a72f87SVille Syrjälä return true; 318090a72f87SVille Syrjälä } 318190a72f87SVille Syrjälä 3182ff1f525eSDaniel Vetter static irqreturn_t i8xx_irq_handler(int irq, void *arg) 3183c2798b19SChris Wilson { 3184c2798b19SChris Wilson struct drm_device *dev = (struct drm_device *) arg; 3185c2798b19SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3186c2798b19SChris Wilson u16 iir, new_iir; 3187c2798b19SChris Wilson u32 pipe_stats[2]; 3188c2798b19SChris Wilson unsigned long irqflags; 3189c2798b19SChris Wilson int pipe; 3190c2798b19SChris Wilson u16 flip_mask = 3191c2798b19SChris Wilson I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3192c2798b19SChris Wilson I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3193c2798b19SChris Wilson 3194c2798b19SChris Wilson iir = I915_READ16(IIR); 3195c2798b19SChris Wilson if (iir == 0) 3196c2798b19SChris Wilson return IRQ_NONE; 3197c2798b19SChris Wilson 3198c2798b19SChris Wilson while (iir & ~flip_mask) { 3199c2798b19SChris Wilson /* Can't rely on pipestat interrupt bit in iir as it might 3200c2798b19SChris Wilson * have been cleared after the pipestat interrupt was received. 3201c2798b19SChris Wilson * It doesn't set the bit in iir again, but it still produces 3202c2798b19SChris Wilson * interrupts (for non-MSI). 3203c2798b19SChris Wilson */ 3204c2798b19SChris Wilson spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3205c2798b19SChris Wilson if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3206c2798b19SChris Wilson i915_handle_error(dev, false); 3207c2798b19SChris Wilson 3208c2798b19SChris Wilson for_each_pipe(pipe) { 3209c2798b19SChris Wilson int reg = PIPESTAT(pipe); 3210c2798b19SChris Wilson pipe_stats[pipe] = I915_READ(reg); 3211c2798b19SChris Wilson 3212c2798b19SChris Wilson /* 3213c2798b19SChris Wilson * Clear the PIPE*STAT regs before the IIR 3214c2798b19SChris Wilson */ 3215*2d9d2b0bSVille Syrjälä if (pipe_stats[pipe] & 0x8000ffff) 3216c2798b19SChris Wilson I915_WRITE(reg, pipe_stats[pipe]); 3217c2798b19SChris Wilson } 3218c2798b19SChris Wilson spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3219c2798b19SChris Wilson 3220c2798b19SChris Wilson I915_WRITE16(IIR, iir & ~flip_mask); 3221c2798b19SChris Wilson new_iir = I915_READ16(IIR); /* Flush posted writes */ 3222c2798b19SChris Wilson 3223d05c617eSDaniel Vetter i915_update_dri1_breadcrumb(dev); 3224c2798b19SChris Wilson 3225c2798b19SChris Wilson if (iir & I915_USER_INTERRUPT) 3226c2798b19SChris Wilson notify_ring(dev, &dev_priv->ring[RCS]); 3227c2798b19SChris Wilson 32284356d586SDaniel Vetter for_each_pipe(pipe) { 32291f1c2e24SVille Syrjälä int plane = pipe; 32303a77c4c4SDaniel Vetter if (HAS_FBC(dev)) 32311f1c2e24SVille Syrjälä plane = !plane; 32321f1c2e24SVille Syrjälä 32334356d586SDaniel Vetter if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 32341f1c2e24SVille Syrjälä i8xx_handle_vblank(dev, plane, pipe, iir)) 32351f1c2e24SVille Syrjälä flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); 3236c2798b19SChris Wilson 32374356d586SDaniel Vetter if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3238277de95eSDaniel Vetter i9xx_pipe_crc_irq_handler(dev, pipe); 3239*2d9d2b0bSVille Syrjälä 3240*2d9d2b0bSVille Syrjälä if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 3241*2d9d2b0bSVille Syrjälä intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 3242*2d9d2b0bSVille Syrjälä DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe)); 32434356d586SDaniel Vetter } 3244c2798b19SChris Wilson 3245c2798b19SChris Wilson iir = new_iir; 3246c2798b19SChris Wilson } 3247c2798b19SChris Wilson 3248c2798b19SChris Wilson return IRQ_HANDLED; 3249c2798b19SChris Wilson } 3250c2798b19SChris Wilson 3251c2798b19SChris Wilson static void i8xx_irq_uninstall(struct drm_device * dev) 3252c2798b19SChris Wilson { 3253c2798b19SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3254c2798b19SChris Wilson int pipe; 3255c2798b19SChris Wilson 3256c2798b19SChris Wilson for_each_pipe(pipe) { 3257c2798b19SChris Wilson /* Clear enable bits; then clear status bits */ 3258c2798b19SChris Wilson I915_WRITE(PIPESTAT(pipe), 0); 3259c2798b19SChris Wilson I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 3260c2798b19SChris Wilson } 3261c2798b19SChris Wilson I915_WRITE16(IMR, 0xffff); 3262c2798b19SChris Wilson I915_WRITE16(IER, 0x0); 3263c2798b19SChris Wilson I915_WRITE16(IIR, I915_READ16(IIR)); 3264c2798b19SChris Wilson } 3265c2798b19SChris Wilson 3266a266c7d5SChris Wilson static void i915_irq_preinstall(struct drm_device * dev) 3267a266c7d5SChris Wilson { 3268a266c7d5SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3269a266c7d5SChris Wilson int pipe; 3270a266c7d5SChris Wilson 3271a266c7d5SChris Wilson if (I915_HAS_HOTPLUG(dev)) { 3272a266c7d5SChris Wilson I915_WRITE(PORT_HOTPLUG_EN, 0); 3273a266c7d5SChris Wilson I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3274a266c7d5SChris Wilson } 3275a266c7d5SChris Wilson 327600d98ebdSChris Wilson I915_WRITE16(HWSTAM, 0xeffe); 3277a266c7d5SChris Wilson for_each_pipe(pipe) 3278a266c7d5SChris Wilson I915_WRITE(PIPESTAT(pipe), 0); 3279a266c7d5SChris Wilson I915_WRITE(IMR, 0xffffffff); 3280a266c7d5SChris Wilson I915_WRITE(IER, 0x0); 3281a266c7d5SChris Wilson POSTING_READ(IER); 3282a266c7d5SChris Wilson } 3283a266c7d5SChris Wilson 3284a266c7d5SChris Wilson static int i915_irq_postinstall(struct drm_device *dev) 3285a266c7d5SChris Wilson { 3286a266c7d5SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 328738bde180SChris Wilson u32 enable_mask; 3288379ef82dSDaniel Vetter unsigned long irqflags; 3289a266c7d5SChris Wilson 329038bde180SChris Wilson I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 329138bde180SChris Wilson 329238bde180SChris Wilson /* Unmask the interrupts that we always want on. */ 329338bde180SChris Wilson dev_priv->irq_mask = 329438bde180SChris Wilson ~(I915_ASLE_INTERRUPT | 329538bde180SChris Wilson I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 329638bde180SChris Wilson I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 329738bde180SChris Wilson I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 329838bde180SChris Wilson I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 329938bde180SChris Wilson I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 330038bde180SChris Wilson 330138bde180SChris Wilson enable_mask = 330238bde180SChris Wilson I915_ASLE_INTERRUPT | 330338bde180SChris Wilson I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 330438bde180SChris Wilson I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 330538bde180SChris Wilson I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 330638bde180SChris Wilson I915_USER_INTERRUPT; 330738bde180SChris Wilson 3308a266c7d5SChris Wilson if (I915_HAS_HOTPLUG(dev)) { 330920afbda2SDaniel Vetter I915_WRITE(PORT_HOTPLUG_EN, 0); 331020afbda2SDaniel Vetter POSTING_READ(PORT_HOTPLUG_EN); 331120afbda2SDaniel Vetter 3312a266c7d5SChris Wilson /* Enable in IER... */ 3313a266c7d5SChris Wilson enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 3314a266c7d5SChris Wilson /* and unmask in IMR */ 3315a266c7d5SChris Wilson dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 3316a266c7d5SChris Wilson } 3317a266c7d5SChris Wilson 3318a266c7d5SChris Wilson I915_WRITE(IMR, dev_priv->irq_mask); 3319a266c7d5SChris Wilson I915_WRITE(IER, enable_mask); 3320a266c7d5SChris Wilson POSTING_READ(IER); 3321a266c7d5SChris Wilson 3322f49e38ddSJani Nikula i915_enable_asle_pipestat(dev); 332320afbda2SDaniel Vetter 3324379ef82dSDaniel Vetter /* Interrupt setup is already guaranteed to be single-threaded, this is 3325379ef82dSDaniel Vetter * just to make the assert_spin_locked check happy. */ 3326379ef82dSDaniel Vetter spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 33273b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); 33283b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); 3329379ef82dSDaniel Vetter spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3330379ef82dSDaniel Vetter 333120afbda2SDaniel Vetter return 0; 333220afbda2SDaniel Vetter } 333320afbda2SDaniel Vetter 333490a72f87SVille Syrjälä /* 333590a72f87SVille Syrjälä * Returns true when a page flip has completed. 333690a72f87SVille Syrjälä */ 333790a72f87SVille Syrjälä static bool i915_handle_vblank(struct drm_device *dev, 333890a72f87SVille Syrjälä int plane, int pipe, u32 iir) 333990a72f87SVille Syrjälä { 334090a72f87SVille Syrjälä drm_i915_private_t *dev_priv = dev->dev_private; 334190a72f87SVille Syrjälä u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); 334290a72f87SVille Syrjälä 334390a72f87SVille Syrjälä if (!drm_handle_vblank(dev, pipe)) 334490a72f87SVille Syrjälä return false; 334590a72f87SVille Syrjälä 334690a72f87SVille Syrjälä if ((iir & flip_pending) == 0) 334790a72f87SVille Syrjälä return false; 334890a72f87SVille Syrjälä 334990a72f87SVille Syrjälä intel_prepare_page_flip(dev, plane); 335090a72f87SVille Syrjälä 335190a72f87SVille Syrjälä /* We detect FlipDone by looking for the change in PendingFlip from '1' 335290a72f87SVille Syrjälä * to '0' on the following vblank, i.e. IIR has the Pendingflip 335390a72f87SVille Syrjälä * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence 335490a72f87SVille Syrjälä * the flip is completed (no longer pending). Since this doesn't raise 335590a72f87SVille Syrjälä * an interrupt per se, we watch for the change at vblank. 335690a72f87SVille Syrjälä */ 335790a72f87SVille Syrjälä if (I915_READ(ISR) & flip_pending) 335890a72f87SVille Syrjälä return false; 335990a72f87SVille Syrjälä 336090a72f87SVille Syrjälä intel_finish_page_flip(dev, pipe); 336190a72f87SVille Syrjälä 336290a72f87SVille Syrjälä return true; 336390a72f87SVille Syrjälä } 336490a72f87SVille Syrjälä 3365ff1f525eSDaniel Vetter static irqreturn_t i915_irq_handler(int irq, void *arg) 3366a266c7d5SChris Wilson { 3367a266c7d5SChris Wilson struct drm_device *dev = (struct drm_device *) arg; 3368a266c7d5SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 33698291ee90SChris Wilson u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; 3370a266c7d5SChris Wilson unsigned long irqflags; 337138bde180SChris Wilson u32 flip_mask = 337238bde180SChris Wilson I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 337338bde180SChris Wilson I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 337438bde180SChris Wilson int pipe, ret = IRQ_NONE; 3375a266c7d5SChris Wilson 3376a266c7d5SChris Wilson iir = I915_READ(IIR); 337738bde180SChris Wilson do { 337838bde180SChris Wilson bool irq_received = (iir & ~flip_mask) != 0; 33798291ee90SChris Wilson bool blc_event = false; 3380a266c7d5SChris Wilson 3381a266c7d5SChris Wilson /* Can't rely on pipestat interrupt bit in iir as it might 3382a266c7d5SChris Wilson * have been cleared after the pipestat interrupt was received. 3383a266c7d5SChris Wilson * It doesn't set the bit in iir again, but it still produces 3384a266c7d5SChris Wilson * interrupts (for non-MSI). 3385a266c7d5SChris Wilson */ 3386a266c7d5SChris Wilson spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3387a266c7d5SChris Wilson if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3388a266c7d5SChris Wilson i915_handle_error(dev, false); 3389a266c7d5SChris Wilson 3390a266c7d5SChris Wilson for_each_pipe(pipe) { 3391a266c7d5SChris Wilson int reg = PIPESTAT(pipe); 3392a266c7d5SChris Wilson pipe_stats[pipe] = I915_READ(reg); 3393a266c7d5SChris Wilson 339438bde180SChris Wilson /* Clear the PIPE*STAT regs before the IIR */ 3395a266c7d5SChris Wilson if (pipe_stats[pipe] & 0x8000ffff) { 3396a266c7d5SChris Wilson I915_WRITE(reg, pipe_stats[pipe]); 339738bde180SChris Wilson irq_received = true; 3398a266c7d5SChris Wilson } 3399a266c7d5SChris Wilson } 3400a266c7d5SChris Wilson spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3401a266c7d5SChris Wilson 3402a266c7d5SChris Wilson if (!irq_received) 3403a266c7d5SChris Wilson break; 3404a266c7d5SChris Wilson 3405a266c7d5SChris Wilson /* Consume port. Then clear IIR or we'll miss events */ 3406a266c7d5SChris Wilson if ((I915_HAS_HOTPLUG(dev)) && 3407a266c7d5SChris Wilson (iir & I915_DISPLAY_PORT_INTERRUPT)) { 3408a266c7d5SChris Wilson u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 3409b543fb04SEgbert Eich u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 3410a266c7d5SChris Wilson 341110a504deSDaniel Vetter intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); 341291d131d2SDaniel Vetter 3413a266c7d5SChris Wilson I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 341438bde180SChris Wilson POSTING_READ(PORT_HOTPLUG_STAT); 3415a266c7d5SChris Wilson } 3416a266c7d5SChris Wilson 341738bde180SChris Wilson I915_WRITE(IIR, iir & ~flip_mask); 3418a266c7d5SChris Wilson new_iir = I915_READ(IIR); /* Flush posted writes */ 3419a266c7d5SChris Wilson 3420a266c7d5SChris Wilson if (iir & I915_USER_INTERRUPT) 3421a266c7d5SChris Wilson notify_ring(dev, &dev_priv->ring[RCS]); 3422a266c7d5SChris Wilson 3423a266c7d5SChris Wilson for_each_pipe(pipe) { 342438bde180SChris Wilson int plane = pipe; 34253a77c4c4SDaniel Vetter if (HAS_FBC(dev)) 342638bde180SChris Wilson plane = !plane; 34275e2032d4SVille Syrjälä 342890a72f87SVille Syrjälä if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 342990a72f87SVille Syrjälä i915_handle_vblank(dev, plane, pipe, iir)) 343090a72f87SVille Syrjälä flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); 3431a266c7d5SChris Wilson 3432a266c7d5SChris Wilson if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 3433a266c7d5SChris Wilson blc_event = true; 34344356d586SDaniel Vetter 34354356d586SDaniel Vetter if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3436277de95eSDaniel Vetter i9xx_pipe_crc_irq_handler(dev, pipe); 3437*2d9d2b0bSVille Syrjälä 3438*2d9d2b0bSVille Syrjälä if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 3439*2d9d2b0bSVille Syrjälä intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 3440*2d9d2b0bSVille Syrjälä DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe)); 3441a266c7d5SChris Wilson } 3442a266c7d5SChris Wilson 3443a266c7d5SChris Wilson if (blc_event || (iir & I915_ASLE_INTERRUPT)) 3444a266c7d5SChris Wilson intel_opregion_asle_intr(dev); 3445a266c7d5SChris Wilson 3446a266c7d5SChris Wilson /* With MSI, interrupts are only generated when iir 3447a266c7d5SChris Wilson * transitions from zero to nonzero. If another bit got 3448a266c7d5SChris Wilson * set while we were handling the existing iir bits, then 3449a266c7d5SChris Wilson * we would never get another interrupt. 3450a266c7d5SChris Wilson * 3451a266c7d5SChris Wilson * This is fine on non-MSI as well, as if we hit this path 3452a266c7d5SChris Wilson * we avoid exiting the interrupt handler only to generate 3453a266c7d5SChris Wilson * another one. 3454a266c7d5SChris Wilson * 3455a266c7d5SChris Wilson * Note that for MSI this could cause a stray interrupt report 3456a266c7d5SChris Wilson * if an interrupt landed in the time between writing IIR and 3457a266c7d5SChris Wilson * the posting read. This should be rare enough to never 3458a266c7d5SChris Wilson * trigger the 99% of 100,000 interrupts test for disabling 3459a266c7d5SChris Wilson * stray interrupts. 3460a266c7d5SChris Wilson */ 346138bde180SChris Wilson ret = IRQ_HANDLED; 3462a266c7d5SChris Wilson iir = new_iir; 346338bde180SChris Wilson } while (iir & ~flip_mask); 3464a266c7d5SChris Wilson 3465d05c617eSDaniel Vetter i915_update_dri1_breadcrumb(dev); 34668291ee90SChris Wilson 3467a266c7d5SChris Wilson return ret; 3468a266c7d5SChris Wilson } 3469a266c7d5SChris Wilson 3470a266c7d5SChris Wilson static void i915_irq_uninstall(struct drm_device * dev) 3471a266c7d5SChris Wilson { 3472a266c7d5SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3473a266c7d5SChris Wilson int pipe; 3474a266c7d5SChris Wilson 34753ca1ccedSVille Syrjälä intel_hpd_irq_uninstall(dev_priv); 3476ac4c16c5SEgbert Eich 3477a266c7d5SChris Wilson if (I915_HAS_HOTPLUG(dev)) { 3478a266c7d5SChris Wilson I915_WRITE(PORT_HOTPLUG_EN, 0); 3479a266c7d5SChris Wilson I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3480a266c7d5SChris Wilson } 3481a266c7d5SChris Wilson 348200d98ebdSChris Wilson I915_WRITE16(HWSTAM, 0xffff); 348355b39755SChris Wilson for_each_pipe(pipe) { 348455b39755SChris Wilson /* Clear enable bits; then clear status bits */ 3485a266c7d5SChris Wilson I915_WRITE(PIPESTAT(pipe), 0); 348655b39755SChris Wilson I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 348755b39755SChris Wilson } 3488a266c7d5SChris Wilson I915_WRITE(IMR, 0xffffffff); 3489a266c7d5SChris Wilson I915_WRITE(IER, 0x0); 3490a266c7d5SChris Wilson 3491a266c7d5SChris Wilson I915_WRITE(IIR, I915_READ(IIR)); 3492a266c7d5SChris Wilson } 3493a266c7d5SChris Wilson 3494a266c7d5SChris Wilson static void i965_irq_preinstall(struct drm_device * dev) 3495a266c7d5SChris Wilson { 3496a266c7d5SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3497a266c7d5SChris Wilson int pipe; 3498a266c7d5SChris Wilson 3499a266c7d5SChris Wilson I915_WRITE(PORT_HOTPLUG_EN, 0); 3500a266c7d5SChris Wilson I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3501a266c7d5SChris Wilson 3502a266c7d5SChris Wilson I915_WRITE(HWSTAM, 0xeffe); 3503a266c7d5SChris Wilson for_each_pipe(pipe) 3504a266c7d5SChris Wilson I915_WRITE(PIPESTAT(pipe), 0); 3505a266c7d5SChris Wilson I915_WRITE(IMR, 0xffffffff); 3506a266c7d5SChris Wilson I915_WRITE(IER, 0x0); 3507a266c7d5SChris Wilson POSTING_READ(IER); 3508a266c7d5SChris Wilson } 3509a266c7d5SChris Wilson 3510a266c7d5SChris Wilson static int i965_irq_postinstall(struct drm_device *dev) 3511a266c7d5SChris Wilson { 3512a266c7d5SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3513bbba0a97SChris Wilson u32 enable_mask; 3514a266c7d5SChris Wilson u32 error_mask; 3515b79480baSDaniel Vetter unsigned long irqflags; 3516a266c7d5SChris Wilson 3517a266c7d5SChris Wilson /* Unmask the interrupts that we always want on. */ 3518bbba0a97SChris Wilson dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | 3519adca4730SChris Wilson I915_DISPLAY_PORT_INTERRUPT | 3520bbba0a97SChris Wilson I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3521bbba0a97SChris Wilson I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3522bbba0a97SChris Wilson I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3523bbba0a97SChris Wilson I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 3524bbba0a97SChris Wilson I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 3525bbba0a97SChris Wilson 3526bbba0a97SChris Wilson enable_mask = ~dev_priv->irq_mask; 352721ad8330SVille Syrjälä enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 352821ad8330SVille Syrjälä I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); 3529bbba0a97SChris Wilson enable_mask |= I915_USER_INTERRUPT; 3530bbba0a97SChris Wilson 3531bbba0a97SChris Wilson if (IS_G4X(dev)) 3532bbba0a97SChris Wilson enable_mask |= I915_BSD_USER_INTERRUPT; 3533a266c7d5SChris Wilson 3534b79480baSDaniel Vetter /* Interrupt setup is already guaranteed to be single-threaded, this is 3535b79480baSDaniel Vetter * just to make the assert_spin_locked check happy. */ 3536b79480baSDaniel Vetter spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 35373b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); 35383b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); 35393b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); 3540b79480baSDaniel Vetter spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3541a266c7d5SChris Wilson 3542a266c7d5SChris Wilson /* 3543a266c7d5SChris Wilson * Enable some error detection, note the instruction error mask 3544a266c7d5SChris Wilson * bit is reserved, so we leave it masked. 3545a266c7d5SChris Wilson */ 3546a266c7d5SChris Wilson if (IS_G4X(dev)) { 3547a266c7d5SChris Wilson error_mask = ~(GM45_ERROR_PAGE_TABLE | 3548a266c7d5SChris Wilson GM45_ERROR_MEM_PRIV | 3549a266c7d5SChris Wilson GM45_ERROR_CP_PRIV | 3550a266c7d5SChris Wilson I915_ERROR_MEMORY_REFRESH); 3551a266c7d5SChris Wilson } else { 3552a266c7d5SChris Wilson error_mask = ~(I915_ERROR_PAGE_TABLE | 3553a266c7d5SChris Wilson I915_ERROR_MEMORY_REFRESH); 3554a266c7d5SChris Wilson } 3555a266c7d5SChris Wilson I915_WRITE(EMR, error_mask); 3556a266c7d5SChris Wilson 3557a266c7d5SChris Wilson I915_WRITE(IMR, dev_priv->irq_mask); 3558a266c7d5SChris Wilson I915_WRITE(IER, enable_mask); 3559a266c7d5SChris Wilson POSTING_READ(IER); 3560a266c7d5SChris Wilson 356120afbda2SDaniel Vetter I915_WRITE(PORT_HOTPLUG_EN, 0); 356220afbda2SDaniel Vetter POSTING_READ(PORT_HOTPLUG_EN); 356320afbda2SDaniel Vetter 3564f49e38ddSJani Nikula i915_enable_asle_pipestat(dev); 356520afbda2SDaniel Vetter 356620afbda2SDaniel Vetter return 0; 356720afbda2SDaniel Vetter } 356820afbda2SDaniel Vetter 3569bac56d5bSEgbert Eich static void i915_hpd_irq_setup(struct drm_device *dev) 357020afbda2SDaniel Vetter { 357120afbda2SDaniel Vetter drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3572e5868a31SEgbert Eich struct drm_mode_config *mode_config = &dev->mode_config; 3573cd569aedSEgbert Eich struct intel_encoder *intel_encoder; 357420afbda2SDaniel Vetter u32 hotplug_en; 357520afbda2SDaniel Vetter 3576b5ea2d56SDaniel Vetter assert_spin_locked(&dev_priv->irq_lock); 3577b5ea2d56SDaniel Vetter 3578bac56d5bSEgbert Eich if (I915_HAS_HOTPLUG(dev)) { 3579bac56d5bSEgbert Eich hotplug_en = I915_READ(PORT_HOTPLUG_EN); 3580bac56d5bSEgbert Eich hotplug_en &= ~HOTPLUG_INT_EN_MASK; 3581adca4730SChris Wilson /* Note HDMI and DP share hotplug bits */ 3582e5868a31SEgbert Eich /* enable bits are the same for all generations */ 3583cd569aedSEgbert Eich list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 3584cd569aedSEgbert Eich if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 3585cd569aedSEgbert Eich hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; 3586a266c7d5SChris Wilson /* Programming the CRT detection parameters tends 3587a266c7d5SChris Wilson to generate a spurious hotplug event about three 3588a266c7d5SChris Wilson seconds later. So just do it once. 3589a266c7d5SChris Wilson */ 3590a266c7d5SChris Wilson if (IS_G4X(dev)) 3591a266c7d5SChris Wilson hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 359285fc95baSDaniel Vetter hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; 3593a266c7d5SChris Wilson hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 3594a266c7d5SChris Wilson 3595a266c7d5SChris Wilson /* Ignore TV since it's buggy */ 3596a266c7d5SChris Wilson I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 3597a266c7d5SChris Wilson } 3598bac56d5bSEgbert Eich } 3599a266c7d5SChris Wilson 3600ff1f525eSDaniel Vetter static irqreturn_t i965_irq_handler(int irq, void *arg) 3601a266c7d5SChris Wilson { 3602a266c7d5SChris Wilson struct drm_device *dev = (struct drm_device *) arg; 3603a266c7d5SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3604a266c7d5SChris Wilson u32 iir, new_iir; 3605a266c7d5SChris Wilson u32 pipe_stats[I915_MAX_PIPES]; 3606a266c7d5SChris Wilson unsigned long irqflags; 3607a266c7d5SChris Wilson int ret = IRQ_NONE, pipe; 360821ad8330SVille Syrjälä u32 flip_mask = 360921ad8330SVille Syrjälä I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 361021ad8330SVille Syrjälä I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3611a266c7d5SChris Wilson 3612a266c7d5SChris Wilson iir = I915_READ(IIR); 3613a266c7d5SChris Wilson 3614a266c7d5SChris Wilson for (;;) { 3615501e01d7SVille Syrjälä bool irq_received = (iir & ~flip_mask) != 0; 36162c8ba29fSChris Wilson bool blc_event = false; 36172c8ba29fSChris Wilson 3618a266c7d5SChris Wilson /* Can't rely on pipestat interrupt bit in iir as it might 3619a266c7d5SChris Wilson * have been cleared after the pipestat interrupt was received. 3620a266c7d5SChris Wilson * It doesn't set the bit in iir again, but it still produces 3621a266c7d5SChris Wilson * interrupts (for non-MSI). 3622a266c7d5SChris Wilson */ 3623a266c7d5SChris Wilson spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3624a266c7d5SChris Wilson if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3625a266c7d5SChris Wilson i915_handle_error(dev, false); 3626a266c7d5SChris Wilson 3627a266c7d5SChris Wilson for_each_pipe(pipe) { 3628a266c7d5SChris Wilson int reg = PIPESTAT(pipe); 3629a266c7d5SChris Wilson pipe_stats[pipe] = I915_READ(reg); 3630a266c7d5SChris Wilson 3631a266c7d5SChris Wilson /* 3632a266c7d5SChris Wilson * Clear the PIPE*STAT regs before the IIR 3633a266c7d5SChris Wilson */ 3634a266c7d5SChris Wilson if (pipe_stats[pipe] & 0x8000ffff) { 3635a266c7d5SChris Wilson I915_WRITE(reg, pipe_stats[pipe]); 3636501e01d7SVille Syrjälä irq_received = true; 3637a266c7d5SChris Wilson } 3638a266c7d5SChris Wilson } 3639a266c7d5SChris Wilson spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3640a266c7d5SChris Wilson 3641a266c7d5SChris Wilson if (!irq_received) 3642a266c7d5SChris Wilson break; 3643a266c7d5SChris Wilson 3644a266c7d5SChris Wilson ret = IRQ_HANDLED; 3645a266c7d5SChris Wilson 3646a266c7d5SChris Wilson /* Consume port. Then clear IIR or we'll miss events */ 3647adca4730SChris Wilson if (iir & I915_DISPLAY_PORT_INTERRUPT) { 3648a266c7d5SChris Wilson u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 3649b543fb04SEgbert Eich u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? 3650b543fb04SEgbert Eich HOTPLUG_INT_STATUS_G4X : 36514f7fd709SDaniel Vetter HOTPLUG_INT_STATUS_I915); 3652a266c7d5SChris Wilson 365310a504deSDaniel Vetter intel_hpd_irq_handler(dev, hotplug_trigger, 3654704cfb87SDaniel Vetter IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915); 365591d131d2SDaniel Vetter 36564aeebd74SDaniel Vetter if (IS_G4X(dev) && 36574aeebd74SDaniel Vetter (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)) 36584aeebd74SDaniel Vetter dp_aux_irq_handler(dev); 36594aeebd74SDaniel Vetter 3660a266c7d5SChris Wilson I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 3661a266c7d5SChris Wilson I915_READ(PORT_HOTPLUG_STAT); 3662a266c7d5SChris Wilson } 3663a266c7d5SChris Wilson 366421ad8330SVille Syrjälä I915_WRITE(IIR, iir & ~flip_mask); 3665a266c7d5SChris Wilson new_iir = I915_READ(IIR); /* Flush posted writes */ 3666a266c7d5SChris Wilson 3667a266c7d5SChris Wilson if (iir & I915_USER_INTERRUPT) 3668a266c7d5SChris Wilson notify_ring(dev, &dev_priv->ring[RCS]); 3669a266c7d5SChris Wilson if (iir & I915_BSD_USER_INTERRUPT) 3670a266c7d5SChris Wilson notify_ring(dev, &dev_priv->ring[VCS]); 3671a266c7d5SChris Wilson 3672a266c7d5SChris Wilson for_each_pipe(pipe) { 36732c8ba29fSChris Wilson if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && 367490a72f87SVille Syrjälä i915_handle_vblank(dev, pipe, pipe, iir)) 367590a72f87SVille Syrjälä flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); 3676a266c7d5SChris Wilson 3677a266c7d5SChris Wilson if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 3678a266c7d5SChris Wilson blc_event = true; 36794356d586SDaniel Vetter 36804356d586SDaniel Vetter if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3681277de95eSDaniel Vetter i9xx_pipe_crc_irq_handler(dev, pipe); 3682a266c7d5SChris Wilson 3683*2d9d2b0bSVille Syrjälä if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 3684*2d9d2b0bSVille Syrjälä intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 3685*2d9d2b0bSVille Syrjälä DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe)); 3686*2d9d2b0bSVille Syrjälä } 3687a266c7d5SChris Wilson 3688a266c7d5SChris Wilson if (blc_event || (iir & I915_ASLE_INTERRUPT)) 3689a266c7d5SChris Wilson intel_opregion_asle_intr(dev); 3690a266c7d5SChris Wilson 3691515ac2bbSDaniel Vetter if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 3692515ac2bbSDaniel Vetter gmbus_irq_handler(dev); 3693515ac2bbSDaniel Vetter 3694a266c7d5SChris Wilson /* With MSI, interrupts are only generated when iir 3695a266c7d5SChris Wilson * transitions from zero to nonzero. If another bit got 3696a266c7d5SChris Wilson * set while we were handling the existing iir bits, then 3697a266c7d5SChris Wilson * we would never get another interrupt. 3698a266c7d5SChris Wilson * 3699a266c7d5SChris Wilson * This is fine on non-MSI as well, as if we hit this path 3700a266c7d5SChris Wilson * we avoid exiting the interrupt handler only to generate 3701a266c7d5SChris Wilson * another one. 3702a266c7d5SChris Wilson * 3703a266c7d5SChris Wilson * Note that for MSI this could cause a stray interrupt report 3704a266c7d5SChris Wilson * if an interrupt landed in the time between writing IIR and 3705a266c7d5SChris Wilson * the posting read. This should be rare enough to never 3706a266c7d5SChris Wilson * trigger the 99% of 100,000 interrupts test for disabling 3707a266c7d5SChris Wilson * stray interrupts. 3708a266c7d5SChris Wilson */ 3709a266c7d5SChris Wilson iir = new_iir; 3710a266c7d5SChris Wilson } 3711a266c7d5SChris Wilson 3712d05c617eSDaniel Vetter i915_update_dri1_breadcrumb(dev); 37132c8ba29fSChris Wilson 3714a266c7d5SChris Wilson return ret; 3715a266c7d5SChris Wilson } 3716a266c7d5SChris Wilson 3717a266c7d5SChris Wilson static void i965_irq_uninstall(struct drm_device * dev) 3718a266c7d5SChris Wilson { 3719a266c7d5SChris Wilson drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3720a266c7d5SChris Wilson int pipe; 3721a266c7d5SChris Wilson 3722a266c7d5SChris Wilson if (!dev_priv) 3723a266c7d5SChris Wilson return; 3724a266c7d5SChris Wilson 37253ca1ccedSVille Syrjälä intel_hpd_irq_uninstall(dev_priv); 3726ac4c16c5SEgbert Eich 3727a266c7d5SChris Wilson I915_WRITE(PORT_HOTPLUG_EN, 0); 3728a266c7d5SChris Wilson I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3729a266c7d5SChris Wilson 3730a266c7d5SChris Wilson I915_WRITE(HWSTAM, 0xffffffff); 3731a266c7d5SChris Wilson for_each_pipe(pipe) 3732a266c7d5SChris Wilson I915_WRITE(PIPESTAT(pipe), 0); 3733a266c7d5SChris Wilson I915_WRITE(IMR, 0xffffffff); 3734a266c7d5SChris Wilson I915_WRITE(IER, 0x0); 3735a266c7d5SChris Wilson 3736a266c7d5SChris Wilson for_each_pipe(pipe) 3737a266c7d5SChris Wilson I915_WRITE(PIPESTAT(pipe), 3738a266c7d5SChris Wilson I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 3739a266c7d5SChris Wilson I915_WRITE(IIR, I915_READ(IIR)); 3740a266c7d5SChris Wilson } 3741a266c7d5SChris Wilson 37423ca1ccedSVille Syrjälä static void intel_hpd_irq_reenable(unsigned long data) 3743ac4c16c5SEgbert Eich { 3744ac4c16c5SEgbert Eich drm_i915_private_t *dev_priv = (drm_i915_private_t *)data; 3745ac4c16c5SEgbert Eich struct drm_device *dev = dev_priv->dev; 3746ac4c16c5SEgbert Eich struct drm_mode_config *mode_config = &dev->mode_config; 3747ac4c16c5SEgbert Eich unsigned long irqflags; 3748ac4c16c5SEgbert Eich int i; 3749ac4c16c5SEgbert Eich 3750ac4c16c5SEgbert Eich spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3751ac4c16c5SEgbert Eich for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { 3752ac4c16c5SEgbert Eich struct drm_connector *connector; 3753ac4c16c5SEgbert Eich 3754ac4c16c5SEgbert Eich if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) 3755ac4c16c5SEgbert Eich continue; 3756ac4c16c5SEgbert Eich 3757ac4c16c5SEgbert Eich dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; 3758ac4c16c5SEgbert Eich 3759ac4c16c5SEgbert Eich list_for_each_entry(connector, &mode_config->connector_list, head) { 3760ac4c16c5SEgbert Eich struct intel_connector *intel_connector = to_intel_connector(connector); 3761ac4c16c5SEgbert Eich 3762ac4c16c5SEgbert Eich if (intel_connector->encoder->hpd_pin == i) { 3763ac4c16c5SEgbert Eich if (connector->polled != intel_connector->polled) 3764ac4c16c5SEgbert Eich DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", 3765ac4c16c5SEgbert Eich drm_get_connector_name(connector)); 3766ac4c16c5SEgbert Eich connector->polled = intel_connector->polled; 3767ac4c16c5SEgbert Eich if (!connector->polled) 3768ac4c16c5SEgbert Eich connector->polled = DRM_CONNECTOR_POLL_HPD; 3769ac4c16c5SEgbert Eich } 3770ac4c16c5SEgbert Eich } 3771ac4c16c5SEgbert Eich } 3772ac4c16c5SEgbert Eich if (dev_priv->display.hpd_irq_setup) 3773ac4c16c5SEgbert Eich dev_priv->display.hpd_irq_setup(dev); 3774ac4c16c5SEgbert Eich spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3775ac4c16c5SEgbert Eich } 3776ac4c16c5SEgbert Eich 3777f71d4af4SJesse Barnes void intel_irq_init(struct drm_device *dev) 3778f71d4af4SJesse Barnes { 37798b2e326dSChris Wilson struct drm_i915_private *dev_priv = dev->dev_private; 37808b2e326dSChris Wilson 37818b2e326dSChris Wilson INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 378299584db3SDaniel Vetter INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); 3783c6a828d3SDaniel Vetter INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); 3784a4da4fa4SDaniel Vetter INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); 37858b2e326dSChris Wilson 378699584db3SDaniel Vetter setup_timer(&dev_priv->gpu_error.hangcheck_timer, 378799584db3SDaniel Vetter i915_hangcheck_elapsed, 378861bac78eSDaniel Vetter (unsigned long) dev); 37893ca1ccedSVille Syrjälä setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable, 3790ac4c16c5SEgbert Eich (unsigned long) dev_priv); 379161bac78eSDaniel Vetter 379297a19a24STomas Janousek pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); 37939ee32feaSDaniel Vetter 37944cdb83ecSVille Syrjälä if (IS_GEN2(dev)) { 37954cdb83ecSVille Syrjälä dev->max_vblank_count = 0; 37964cdb83ecSVille Syrjälä dev->driver->get_vblank_counter = i8xx_get_vblank_counter; 37974cdb83ecSVille Syrjälä } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 3798f71d4af4SJesse Barnes dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 3799f71d4af4SJesse Barnes dev->driver->get_vblank_counter = gm45_get_vblank_counter; 3800391f75e2SVille Syrjälä } else { 3801391f75e2SVille Syrjälä dev->driver->get_vblank_counter = i915_get_vblank_counter; 3802391f75e2SVille Syrjälä dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 3803f71d4af4SJesse Barnes } 3804f71d4af4SJesse Barnes 3805c2baf4b7SVille Syrjälä if (drm_core_check_feature(dev, DRIVER_MODESET)) { 3806f71d4af4SJesse Barnes dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; 3807f71d4af4SJesse Barnes dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 3808c2baf4b7SVille Syrjälä } 3809f71d4af4SJesse Barnes 38107e231dbeSJesse Barnes if (IS_VALLEYVIEW(dev)) { 38117e231dbeSJesse Barnes dev->driver->irq_handler = valleyview_irq_handler; 38127e231dbeSJesse Barnes dev->driver->irq_preinstall = valleyview_irq_preinstall; 38137e231dbeSJesse Barnes dev->driver->irq_postinstall = valleyview_irq_postinstall; 38147e231dbeSJesse Barnes dev->driver->irq_uninstall = valleyview_irq_uninstall; 38157e231dbeSJesse Barnes dev->driver->enable_vblank = valleyview_enable_vblank; 38167e231dbeSJesse Barnes dev->driver->disable_vblank = valleyview_disable_vblank; 3817fa00abe0SEgbert Eich dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 3818abd58f01SBen Widawsky } else if (IS_GEN8(dev)) { 3819abd58f01SBen Widawsky dev->driver->irq_handler = gen8_irq_handler; 3820abd58f01SBen Widawsky dev->driver->irq_preinstall = gen8_irq_preinstall; 3821abd58f01SBen Widawsky dev->driver->irq_postinstall = gen8_irq_postinstall; 3822abd58f01SBen Widawsky dev->driver->irq_uninstall = gen8_irq_uninstall; 3823abd58f01SBen Widawsky dev->driver->enable_vblank = gen8_enable_vblank; 3824abd58f01SBen Widawsky dev->driver->disable_vblank = gen8_disable_vblank; 3825abd58f01SBen Widawsky dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; 3826f71d4af4SJesse Barnes } else if (HAS_PCH_SPLIT(dev)) { 3827f71d4af4SJesse Barnes dev->driver->irq_handler = ironlake_irq_handler; 3828f71d4af4SJesse Barnes dev->driver->irq_preinstall = ironlake_irq_preinstall; 3829f71d4af4SJesse Barnes dev->driver->irq_postinstall = ironlake_irq_postinstall; 3830f71d4af4SJesse Barnes dev->driver->irq_uninstall = ironlake_irq_uninstall; 3831f71d4af4SJesse Barnes dev->driver->enable_vblank = ironlake_enable_vblank; 3832f71d4af4SJesse Barnes dev->driver->disable_vblank = ironlake_disable_vblank; 383382a28bcfSDaniel Vetter dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; 3834f71d4af4SJesse Barnes } else { 3835c2798b19SChris Wilson if (INTEL_INFO(dev)->gen == 2) { 3836c2798b19SChris Wilson dev->driver->irq_preinstall = i8xx_irq_preinstall; 3837c2798b19SChris Wilson dev->driver->irq_postinstall = i8xx_irq_postinstall; 3838c2798b19SChris Wilson dev->driver->irq_handler = i8xx_irq_handler; 3839c2798b19SChris Wilson dev->driver->irq_uninstall = i8xx_irq_uninstall; 3840a266c7d5SChris Wilson } else if (INTEL_INFO(dev)->gen == 3) { 3841a266c7d5SChris Wilson dev->driver->irq_preinstall = i915_irq_preinstall; 3842a266c7d5SChris Wilson dev->driver->irq_postinstall = i915_irq_postinstall; 3843a266c7d5SChris Wilson dev->driver->irq_uninstall = i915_irq_uninstall; 3844a266c7d5SChris Wilson dev->driver->irq_handler = i915_irq_handler; 384520afbda2SDaniel Vetter dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 3846c2798b19SChris Wilson } else { 3847a266c7d5SChris Wilson dev->driver->irq_preinstall = i965_irq_preinstall; 3848a266c7d5SChris Wilson dev->driver->irq_postinstall = i965_irq_postinstall; 3849a266c7d5SChris Wilson dev->driver->irq_uninstall = i965_irq_uninstall; 3850a266c7d5SChris Wilson dev->driver->irq_handler = i965_irq_handler; 3851bac56d5bSEgbert Eich dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 3852c2798b19SChris Wilson } 3853f71d4af4SJesse Barnes dev->driver->enable_vblank = i915_enable_vblank; 3854f71d4af4SJesse Barnes dev->driver->disable_vblank = i915_disable_vblank; 3855f71d4af4SJesse Barnes } 3856f71d4af4SJesse Barnes } 385720afbda2SDaniel Vetter 385820afbda2SDaniel Vetter void intel_hpd_init(struct drm_device *dev) 385920afbda2SDaniel Vetter { 386020afbda2SDaniel Vetter struct drm_i915_private *dev_priv = dev->dev_private; 3861821450c6SEgbert Eich struct drm_mode_config *mode_config = &dev->mode_config; 3862821450c6SEgbert Eich struct drm_connector *connector; 3863b5ea2d56SDaniel Vetter unsigned long irqflags; 3864821450c6SEgbert Eich int i; 386520afbda2SDaniel Vetter 3866821450c6SEgbert Eich for (i = 1; i < HPD_NUM_PINS; i++) { 3867821450c6SEgbert Eich dev_priv->hpd_stats[i].hpd_cnt = 0; 3868821450c6SEgbert Eich dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; 3869821450c6SEgbert Eich } 3870821450c6SEgbert Eich list_for_each_entry(connector, &mode_config->connector_list, head) { 3871821450c6SEgbert Eich struct intel_connector *intel_connector = to_intel_connector(connector); 3872821450c6SEgbert Eich connector->polled = intel_connector->polled; 3873821450c6SEgbert Eich if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) 3874821450c6SEgbert Eich connector->polled = DRM_CONNECTOR_POLL_HPD; 3875821450c6SEgbert Eich } 3876b5ea2d56SDaniel Vetter 3877b5ea2d56SDaniel Vetter /* Interrupt setup is already guaranteed to be single-threaded, this is 3878b5ea2d56SDaniel Vetter * just to make the assert_spin_locked checks happy. */ 3879b5ea2d56SDaniel Vetter spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 388020afbda2SDaniel Vetter if (dev_priv->display.hpd_irq_setup) 388120afbda2SDaniel Vetter dev_priv->display.hpd_irq_setup(dev); 3882b5ea2d56SDaniel Vetter spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 388320afbda2SDaniel Vetter } 3884c67a470bSPaulo Zanoni 3885c67a470bSPaulo Zanoni /* Disable interrupts so we can allow Package C8+. */ 3886c67a470bSPaulo Zanoni void hsw_pc8_disable_interrupts(struct drm_device *dev) 3887c67a470bSPaulo Zanoni { 3888c67a470bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 3889c67a470bSPaulo Zanoni unsigned long irqflags; 3890c67a470bSPaulo Zanoni 3891c67a470bSPaulo Zanoni spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3892c67a470bSPaulo Zanoni 3893c67a470bSPaulo Zanoni dev_priv->pc8.regsave.deimr = I915_READ(DEIMR); 3894c67a470bSPaulo Zanoni dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR); 3895c67a470bSPaulo Zanoni dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR); 3896c67a470bSPaulo Zanoni dev_priv->pc8.regsave.gtier = I915_READ(GTIER); 3897c67a470bSPaulo Zanoni dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); 3898c67a470bSPaulo Zanoni 38991f2d4531SPaulo Zanoni ironlake_disable_display_irq(dev_priv, 0xffffffff); 39001f2d4531SPaulo Zanoni ibx_disable_display_interrupt(dev_priv, 0xffffffff); 3901c67a470bSPaulo Zanoni ilk_disable_gt_irq(dev_priv, 0xffffffff); 3902c67a470bSPaulo Zanoni snb_disable_pm_irq(dev_priv, 0xffffffff); 3903c67a470bSPaulo Zanoni 3904c67a470bSPaulo Zanoni dev_priv->pc8.irqs_disabled = true; 3905c67a470bSPaulo Zanoni 3906c67a470bSPaulo Zanoni spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3907c67a470bSPaulo Zanoni } 3908c67a470bSPaulo Zanoni 3909c67a470bSPaulo Zanoni /* Restore interrupts so we can recover from Package C8+. */ 3910c67a470bSPaulo Zanoni void hsw_pc8_restore_interrupts(struct drm_device *dev) 3911c67a470bSPaulo Zanoni { 3912c67a470bSPaulo Zanoni struct drm_i915_private *dev_priv = dev->dev_private; 3913c67a470bSPaulo Zanoni unsigned long irqflags; 39141f2d4531SPaulo Zanoni uint32_t val; 3915c67a470bSPaulo Zanoni 3916c67a470bSPaulo Zanoni spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3917c67a470bSPaulo Zanoni 3918c67a470bSPaulo Zanoni val = I915_READ(DEIMR); 39191f2d4531SPaulo Zanoni WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val); 3920c67a470bSPaulo Zanoni 39211f2d4531SPaulo Zanoni val = I915_READ(SDEIMR); 39221f2d4531SPaulo Zanoni WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val); 3923c67a470bSPaulo Zanoni 3924c67a470bSPaulo Zanoni val = I915_READ(GTIMR); 39251f2d4531SPaulo Zanoni WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val); 3926c67a470bSPaulo Zanoni 3927c67a470bSPaulo Zanoni val = I915_READ(GEN6_PMIMR); 39281f2d4531SPaulo Zanoni WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val); 3929c67a470bSPaulo Zanoni 3930c67a470bSPaulo Zanoni dev_priv->pc8.irqs_disabled = false; 3931c67a470bSPaulo Zanoni 3932c67a470bSPaulo Zanoni ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr); 39331f2d4531SPaulo Zanoni ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr); 3934c67a470bSPaulo Zanoni ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr); 3935c67a470bSPaulo Zanoni snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr); 3936c67a470bSPaulo Zanoni I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier); 3937c67a470bSPaulo Zanoni 3938c67a470bSPaulo Zanoni spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3939c67a470bSPaulo Zanoni } 3940