1c0e09200SDave Airlie /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2c0e09200SDave Airlie */ 3c0e09200SDave Airlie /* 4c0e09200SDave Airlie * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5c0e09200SDave Airlie * All Rights Reserved. 6c0e09200SDave Airlie * 7c0e09200SDave Airlie * Permission is hereby granted, free of charge, to any person obtaining a 8c0e09200SDave Airlie * copy of this software and associated documentation files (the 9c0e09200SDave Airlie * "Software"), to deal in the Software without restriction, including 10c0e09200SDave Airlie * without limitation the rights to use, copy, modify, merge, publish, 11c0e09200SDave Airlie * distribute, sub license, and/or sell copies of the Software, and to 12c0e09200SDave Airlie * permit persons to whom the Software is furnished to do so, subject to 13c0e09200SDave Airlie * the following conditions: 14c0e09200SDave Airlie * 15c0e09200SDave Airlie * The above copyright notice and this permission notice (including the 16c0e09200SDave Airlie * next paragraph) shall be included in all copies or substantial portions 17c0e09200SDave Airlie * of the Software. 18c0e09200SDave Airlie * 19c0e09200SDave Airlie * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20c0e09200SDave Airlie * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21c0e09200SDave Airlie * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22c0e09200SDave Airlie * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23c0e09200SDave Airlie * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24c0e09200SDave Airlie * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25c0e09200SDave Airlie * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26c0e09200SDave Airlie * 27c0e09200SDave Airlie */ 28c0e09200SDave Airlie 29a70491ccSJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30a70491ccSJoe Perches 31b2c88f5bSDamien Lespiau #include <linux/circ_buf.h> 3255367a27SJani Nikula #include <linux/slab.h> 3355367a27SJani Nikula #include <linux/sysrq.h> 3455367a27SJani Nikula 35fcd70cd3SDaniel Vetter #include <drm/drm_drv.h> 3655367a27SJani Nikula #include <drm/drm_irq.h> 3755367a27SJani Nikula 381d455f8dSJani Nikula #include "display/intel_display_types.h" 39df0566a6SJani Nikula #include "display/intel_fifo_underrun.h" 40df0566a6SJani Nikula #include "display/intel_hotplug.h" 41df0566a6SJani Nikula #include "display/intel_lpe_audio.h" 42df0566a6SJani Nikula #include "display/intel_psr.h" 43df0566a6SJani Nikula 44b3786b29SChris Wilson #include "gt/intel_breadcrumbs.h" 452239e6dfSDaniele Ceraolo Spurio #include "gt/intel_gt.h" 46cf1c97dcSAndi Shyti #include "gt/intel_gt_irq.h" 47d762043fSAndi Shyti #include "gt/intel_gt_pm_irq.h" 483e7abf81SAndi Shyti #include "gt/intel_rps.h" 492239e6dfSDaniele Ceraolo Spurio 50c0e09200SDave Airlie #include "i915_drv.h" 51440e2b3dSJani Nikula #include "i915_irq.h" 521c5d22f7SChris Wilson #include "i915_trace.h" 53d13616dbSJani Nikula #include "intel_pm.h" 54c0e09200SDave Airlie 55fca52a55SDaniel Vetter /** 56fca52a55SDaniel Vetter * DOC: interrupt handling 57fca52a55SDaniel Vetter * 58fca52a55SDaniel Vetter * These functions provide the basic support for enabling and disabling the 59fca52a55SDaniel Vetter * interrupt handling support. There's a lot more functionality in i915_irq.c 60fca52a55SDaniel Vetter * and related files, but that will be described in separate chapters. 61fca52a55SDaniel Vetter */ 62fca52a55SDaniel Vetter 639c6508b9SThomas Gleixner /* 649c6508b9SThomas Gleixner * Interrupt statistic for PMU. Increments the counter only if the 659c6508b9SThomas Gleixner * interrupt originated from the the GPU so interrupts from a device which 669c6508b9SThomas Gleixner * shares the interrupt line are not accounted. 679c6508b9SThomas Gleixner */ 689c6508b9SThomas Gleixner static inline void pmu_irq_stats(struct drm_i915_private *i915, 699c6508b9SThomas Gleixner irqreturn_t res) 709c6508b9SThomas Gleixner { 719c6508b9SThomas Gleixner if (unlikely(res != IRQ_HANDLED)) 729c6508b9SThomas Gleixner return; 739c6508b9SThomas Gleixner 749c6508b9SThomas Gleixner /* 759c6508b9SThomas Gleixner * A clever compiler translates that into INC. A not so clever one 769c6508b9SThomas Gleixner * should at least prevent store tearing. 779c6508b9SThomas Gleixner */ 789c6508b9SThomas Gleixner WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1); 799c6508b9SThomas Gleixner } 809c6508b9SThomas Gleixner 8148ef15d3SJosé Roberto de Souza typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val); 822ea63927SVille Syrjälä typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915, 832ea63927SVille Syrjälä enum hpd_pin pin); 8448ef15d3SJosé Roberto de Souza 85e4ce95aaSVille Syrjälä static const u32 hpd_ilk[HPD_NUM_PINS] = { 86e4ce95aaSVille Syrjälä [HPD_PORT_A] = DE_DP_A_HOTPLUG, 87e4ce95aaSVille Syrjälä }; 88e4ce95aaSVille Syrjälä 8923bb4cb5SVille Syrjälä static const u32 hpd_ivb[HPD_NUM_PINS] = { 9023bb4cb5SVille Syrjälä [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, 9123bb4cb5SVille Syrjälä }; 9223bb4cb5SVille Syrjälä 933a3b3c7dSVille Syrjälä static const u32 hpd_bdw[HPD_NUM_PINS] = { 94e5abaab3SVille Syrjälä [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 953a3b3c7dSVille Syrjälä }; 963a3b3c7dSVille Syrjälä 977c7e10dbSVille Syrjälä static const u32 hpd_ibx[HPD_NUM_PINS] = { 98e5868a31SEgbert Eich [HPD_CRT] = SDE_CRT_HOTPLUG, 99e5868a31SEgbert Eich [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, 100e5868a31SEgbert Eich [HPD_PORT_B] = SDE_PORTB_HOTPLUG, 101e5868a31SEgbert Eich [HPD_PORT_C] = SDE_PORTC_HOTPLUG, 1027203d49cSVille Syrjälä [HPD_PORT_D] = SDE_PORTD_HOTPLUG, 103e5868a31SEgbert Eich }; 104e5868a31SEgbert Eich 1057c7e10dbSVille Syrjälä static const u32 hpd_cpt[HPD_NUM_PINS] = { 106e5868a31SEgbert Eich [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, 10773c352a2SDaniel Vetter [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, 108e5868a31SEgbert Eich [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 109e5868a31SEgbert Eich [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 1107203d49cSVille Syrjälä [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 111e5868a31SEgbert Eich }; 112e5868a31SEgbert Eich 11326951cafSXiong Zhang static const u32 hpd_spt[HPD_NUM_PINS] = { 11474c0b395SVille Syrjälä [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, 11526951cafSXiong Zhang [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 11626951cafSXiong Zhang [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 11726951cafSXiong Zhang [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 1187203d49cSVille Syrjälä [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT, 11926951cafSXiong Zhang }; 12026951cafSXiong Zhang 1217c7e10dbSVille Syrjälä static const u32 hpd_mask_i915[HPD_NUM_PINS] = { 122e5868a31SEgbert Eich [HPD_CRT] = CRT_HOTPLUG_INT_EN, 123e5868a31SEgbert Eich [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, 124e5868a31SEgbert Eich [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, 125e5868a31SEgbert Eich [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, 126e5868a31SEgbert Eich [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, 1277203d49cSVille Syrjälä [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN, 128e5868a31SEgbert Eich }; 129e5868a31SEgbert Eich 1307c7e10dbSVille Syrjälä static const u32 hpd_status_g4x[HPD_NUM_PINS] = { 131e5868a31SEgbert Eich [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 132e5868a31SEgbert Eich [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, 133e5868a31SEgbert Eich [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, 134e5868a31SEgbert Eich [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 135e5868a31SEgbert Eich [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 1367203d49cSVille Syrjälä [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 137e5868a31SEgbert Eich }; 138e5868a31SEgbert Eich 1394bca26d0SVille Syrjälä static const u32 hpd_status_i915[HPD_NUM_PINS] = { 140e5868a31SEgbert Eich [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 141e5868a31SEgbert Eich [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, 142e5868a31SEgbert Eich [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, 143e5868a31SEgbert Eich [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 144e5868a31SEgbert Eich [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 1457203d49cSVille Syrjälä [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 146e5868a31SEgbert Eich }; 147e5868a31SEgbert Eich 148e0a20ad7SShashank Sharma static const u32 hpd_bxt[HPD_NUM_PINS] = { 149e5abaab3SVille Syrjälä [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 150e5abaab3SVille Syrjälä [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B), 151e5abaab3SVille Syrjälä [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C), 152e0a20ad7SShashank Sharma }; 153e0a20ad7SShashank Sharma 154b796b971SDhinakaran Pandiyan static const u32 hpd_gen11[HPD_NUM_PINS] = { 1555b76e860SVille Syrjälä [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1), 1565b76e860SVille Syrjälä [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2), 1575b76e860SVille Syrjälä [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3), 1585b76e860SVille Syrjälä [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4), 1595b76e860SVille Syrjälä [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5), 1605b76e860SVille Syrjälä [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6), 16148ef15d3SJosé Roberto de Souza }; 16248ef15d3SJosé Roberto de Souza 16331604222SAnusha Srivatsa static const u32 hpd_icp[HPD_NUM_PINS] = { 1645f371a81SVille Syrjälä [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 1655f371a81SVille Syrjälä [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 1665f371a81SVille Syrjälä [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 16797011359SVille Syrjälä [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1), 16897011359SVille Syrjälä [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2), 16997011359SVille Syrjälä [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3), 17097011359SVille Syrjälä [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), 17197011359SVille Syrjälä [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5), 17297011359SVille Syrjälä [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6), 17352dfdba0SLucas De Marchi }; 17452dfdba0SLucas De Marchi 175229f31e2SLucas De Marchi static const u32 hpd_sde_dg1[HPD_NUM_PINS] = { 1765f371a81SVille Syrjälä [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 1775f371a81SVille Syrjälä [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 1785f371a81SVille Syrjälä [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 1795f371a81SVille Syrjälä [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D), 180229f31e2SLucas De Marchi }; 181229f31e2SLucas De Marchi 1820398993bSVille Syrjälä static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) 1830398993bSVille Syrjälä { 1840398993bSVille Syrjälä struct i915_hotplug *hpd = &dev_priv->hotplug; 1850398993bSVille Syrjälä 1860398993bSVille Syrjälä if (HAS_GMCH(dev_priv)) { 1870398993bSVille Syrjälä if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 1880398993bSVille Syrjälä IS_CHERRYVIEW(dev_priv)) 1890398993bSVille Syrjälä hpd->hpd = hpd_status_g4x; 1900398993bSVille Syrjälä else 1910398993bSVille Syrjälä hpd->hpd = hpd_status_i915; 1920398993bSVille Syrjälä return; 1930398993bSVille Syrjälä } 1940398993bSVille Syrjälä 195da51e4baSVille Syrjälä if (INTEL_GEN(dev_priv) >= 11) 1960398993bSVille Syrjälä hpd->hpd = hpd_gen11; 1970398993bSVille Syrjälä else if (IS_GEN9_LP(dev_priv)) 1980398993bSVille Syrjälä hpd->hpd = hpd_bxt; 1990398993bSVille Syrjälä else if (INTEL_GEN(dev_priv) >= 8) 2000398993bSVille Syrjälä hpd->hpd = hpd_bdw; 2010398993bSVille Syrjälä else if (INTEL_GEN(dev_priv) >= 7) 2020398993bSVille Syrjälä hpd->hpd = hpd_ivb; 2030398993bSVille Syrjälä else 2040398993bSVille Syrjälä hpd->hpd = hpd_ilk; 2050398993bSVille Syrjälä 206229f31e2SLucas De Marchi if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && 207229f31e2SLucas De Marchi (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) 2080398993bSVille Syrjälä return; 2090398993bSVille Syrjälä 210229f31e2SLucas De Marchi if (HAS_PCH_DG1(dev_priv)) 211229f31e2SLucas De Marchi hpd->pch_hpd = hpd_sde_dg1; 212229f31e2SLucas De Marchi else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) || 213da51e4baSVille Syrjälä HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) 2140398993bSVille Syrjälä hpd->pch_hpd = hpd_icp; 2150398993bSVille Syrjälä else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) 2160398993bSVille Syrjälä hpd->pch_hpd = hpd_spt; 2170398993bSVille Syrjälä else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv)) 2180398993bSVille Syrjälä hpd->pch_hpd = hpd_cpt; 2190398993bSVille Syrjälä else if (HAS_PCH_IBX(dev_priv)) 2200398993bSVille Syrjälä hpd->pch_hpd = hpd_ibx; 2210398993bSVille Syrjälä else 2220398993bSVille Syrjälä MISSING_CASE(INTEL_PCH_TYPE(dev_priv)); 2230398993bSVille Syrjälä } 2240398993bSVille Syrjälä 225aca9310aSAnshuman Gupta static void 226aca9310aSAnshuman Gupta intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) 227aca9310aSAnshuman Gupta { 228aca9310aSAnshuman Gupta struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 229aca9310aSAnshuman Gupta 230aca9310aSAnshuman Gupta drm_crtc_handle_vblank(&crtc->base); 231aca9310aSAnshuman Gupta } 232aca9310aSAnshuman Gupta 233cf1c97dcSAndi Shyti void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, 23468eb49b1SPaulo Zanoni i915_reg_t iir, i915_reg_t ier) 23568eb49b1SPaulo Zanoni { 23665f42cdcSPaulo Zanoni intel_uncore_write(uncore, imr, 0xffffffff); 23765f42cdcSPaulo Zanoni intel_uncore_posting_read(uncore, imr); 23868eb49b1SPaulo Zanoni 23965f42cdcSPaulo Zanoni intel_uncore_write(uncore, ier, 0); 24068eb49b1SPaulo Zanoni 2415c502442SPaulo Zanoni /* IIR can theoretically queue up two events. Be paranoid. */ 24265f42cdcSPaulo Zanoni intel_uncore_write(uncore, iir, 0xffffffff); 24365f42cdcSPaulo Zanoni intel_uncore_posting_read(uncore, iir); 24465f42cdcSPaulo Zanoni intel_uncore_write(uncore, iir, 0xffffffff); 24565f42cdcSPaulo Zanoni intel_uncore_posting_read(uncore, iir); 24668eb49b1SPaulo Zanoni } 2475c502442SPaulo Zanoni 248cf1c97dcSAndi Shyti void gen2_irq_reset(struct intel_uncore *uncore) 24968eb49b1SPaulo Zanoni { 25065f42cdcSPaulo Zanoni intel_uncore_write16(uncore, GEN2_IMR, 0xffff); 25165f42cdcSPaulo Zanoni intel_uncore_posting_read16(uncore, GEN2_IMR); 252a9d356a6SPaulo Zanoni 25365f42cdcSPaulo Zanoni intel_uncore_write16(uncore, GEN2_IER, 0); 25468eb49b1SPaulo Zanoni 25568eb49b1SPaulo Zanoni /* IIR can theoretically queue up two events. Be paranoid. */ 25665f42cdcSPaulo Zanoni intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 25765f42cdcSPaulo Zanoni intel_uncore_posting_read16(uncore, GEN2_IIR); 25865f42cdcSPaulo Zanoni intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 25965f42cdcSPaulo Zanoni intel_uncore_posting_read16(uncore, GEN2_IIR); 26068eb49b1SPaulo Zanoni } 26168eb49b1SPaulo Zanoni 262337ba017SPaulo Zanoni /* 263337ba017SPaulo Zanoni * We should clear IMR at preinstall/uninstall, and just check at postinstall. 264337ba017SPaulo Zanoni */ 26565f42cdcSPaulo Zanoni static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) 266b51a2842SVille Syrjälä { 26765f42cdcSPaulo Zanoni u32 val = intel_uncore_read(uncore, reg); 268b51a2842SVille Syrjälä 269b51a2842SVille Syrjälä if (val == 0) 270b51a2842SVille Syrjälä return; 271b51a2842SVille Syrjälä 272a9f236d1SPankaj Bharadiya drm_WARN(&uncore->i915->drm, 1, 273a9f236d1SPankaj Bharadiya "Interrupt register 0x%x is not zero: 0x%08x\n", 274f0f59a00SVille Syrjälä i915_mmio_reg_offset(reg), val); 27565f42cdcSPaulo Zanoni intel_uncore_write(uncore, reg, 0xffffffff); 27665f42cdcSPaulo Zanoni intel_uncore_posting_read(uncore, reg); 27765f42cdcSPaulo Zanoni intel_uncore_write(uncore, reg, 0xffffffff); 27865f42cdcSPaulo Zanoni intel_uncore_posting_read(uncore, reg); 279b51a2842SVille Syrjälä } 280337ba017SPaulo Zanoni 28165f42cdcSPaulo Zanoni static void gen2_assert_iir_is_zero(struct intel_uncore *uncore) 282e9e9848aSVille Syrjälä { 28365f42cdcSPaulo Zanoni u16 val = intel_uncore_read16(uncore, GEN2_IIR); 284e9e9848aSVille Syrjälä 285e9e9848aSVille Syrjälä if (val == 0) 286e9e9848aSVille Syrjälä return; 287e9e9848aSVille Syrjälä 288a9f236d1SPankaj Bharadiya drm_WARN(&uncore->i915->drm, 1, 289a9f236d1SPankaj Bharadiya "Interrupt register 0x%x is not zero: 0x%08x\n", 2909d9523d8SPaulo Zanoni i915_mmio_reg_offset(GEN2_IIR), val); 29165f42cdcSPaulo Zanoni intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 29265f42cdcSPaulo Zanoni intel_uncore_posting_read16(uncore, GEN2_IIR); 29365f42cdcSPaulo Zanoni intel_uncore_write16(uncore, GEN2_IIR, 0xffff); 29465f42cdcSPaulo Zanoni intel_uncore_posting_read16(uncore, GEN2_IIR); 295e9e9848aSVille Syrjälä } 296e9e9848aSVille Syrjälä 297cf1c97dcSAndi Shyti void gen3_irq_init(struct intel_uncore *uncore, 29868eb49b1SPaulo Zanoni i915_reg_t imr, u32 imr_val, 29968eb49b1SPaulo Zanoni i915_reg_t ier, u32 ier_val, 30068eb49b1SPaulo Zanoni i915_reg_t iir) 30168eb49b1SPaulo Zanoni { 30265f42cdcSPaulo Zanoni gen3_assert_iir_is_zero(uncore, iir); 30335079899SPaulo Zanoni 30465f42cdcSPaulo Zanoni intel_uncore_write(uncore, ier, ier_val); 30565f42cdcSPaulo Zanoni intel_uncore_write(uncore, imr, imr_val); 30665f42cdcSPaulo Zanoni intel_uncore_posting_read(uncore, imr); 30768eb49b1SPaulo Zanoni } 30835079899SPaulo Zanoni 309cf1c97dcSAndi Shyti void gen2_irq_init(struct intel_uncore *uncore, 3102918c3caSPaulo Zanoni u32 imr_val, u32 ier_val) 31168eb49b1SPaulo Zanoni { 31265f42cdcSPaulo Zanoni gen2_assert_iir_is_zero(uncore); 31368eb49b1SPaulo Zanoni 31465f42cdcSPaulo Zanoni intel_uncore_write16(uncore, GEN2_IER, ier_val); 31565f42cdcSPaulo Zanoni intel_uncore_write16(uncore, GEN2_IMR, imr_val); 31665f42cdcSPaulo Zanoni intel_uncore_posting_read16(uncore, GEN2_IMR); 31768eb49b1SPaulo Zanoni } 31868eb49b1SPaulo Zanoni 3190706f17cSEgbert Eich /* For display hotplug interrupt */ 3200706f17cSEgbert Eich static inline void 3210706f17cSEgbert Eich i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, 322a9c287c9SJani Nikula u32 mask, 323a9c287c9SJani Nikula u32 bits) 3240706f17cSEgbert Eich { 325a9c287c9SJani Nikula u32 val; 3260706f17cSEgbert Eich 32767520415SChris Wilson lockdep_assert_held(&dev_priv->irq_lock); 32848a1b8d4SPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, bits & ~mask); 3290706f17cSEgbert Eich 3302939eb06SJani Nikula val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN); 3310706f17cSEgbert Eich val &= ~mask; 3320706f17cSEgbert Eich val |= bits; 3332939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val); 3340706f17cSEgbert Eich } 3350706f17cSEgbert Eich 3360706f17cSEgbert Eich /** 3370706f17cSEgbert Eich * i915_hotplug_interrupt_update - update hotplug interrupt enable 3380706f17cSEgbert Eich * @dev_priv: driver private 3390706f17cSEgbert Eich * @mask: bits to update 3400706f17cSEgbert Eich * @bits: bits to enable 3410706f17cSEgbert Eich * NOTE: the HPD enable bits are modified both inside and outside 3420706f17cSEgbert Eich * of an interrupt context. To avoid that read-modify-write cycles 3430706f17cSEgbert Eich * interfer, these bits are protected by a spinlock. Since this 3440706f17cSEgbert Eich * function is usually not called from a context where the lock is 3450706f17cSEgbert Eich * held already, this function acquires the lock itself. A non-locking 3460706f17cSEgbert Eich * version is also available. 3470706f17cSEgbert Eich */ 3480706f17cSEgbert Eich void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, 349a9c287c9SJani Nikula u32 mask, 350a9c287c9SJani Nikula u32 bits) 3510706f17cSEgbert Eich { 3520706f17cSEgbert Eich spin_lock_irq(&dev_priv->irq_lock); 3530706f17cSEgbert Eich i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); 3540706f17cSEgbert Eich spin_unlock_irq(&dev_priv->irq_lock); 3550706f17cSEgbert Eich } 3560706f17cSEgbert Eich 357d9dc34f1SVille Syrjälä /** 358d9dc34f1SVille Syrjälä * ilk_update_display_irq - update DEIMR 359d9dc34f1SVille Syrjälä * @dev_priv: driver private 360d9dc34f1SVille Syrjälä * @interrupt_mask: mask of interrupt bits to update 361d9dc34f1SVille Syrjälä * @enabled_irq_mask: mask of interrupt bits to enable 362d9dc34f1SVille Syrjälä */ 363fbdedaeaSVille Syrjälä void ilk_update_display_irq(struct drm_i915_private *dev_priv, 364a9c287c9SJani Nikula u32 interrupt_mask, 365a9c287c9SJani Nikula u32 enabled_irq_mask) 366036a4a7dSZhenyu Wang { 367a9c287c9SJani Nikula u32 new_val; 368d9dc34f1SVille Syrjälä 36967520415SChris Wilson lockdep_assert_held(&dev_priv->irq_lock); 37048a1b8d4SPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 371d9dc34f1SVille Syrjälä 372d9dc34f1SVille Syrjälä new_val = dev_priv->irq_mask; 373d9dc34f1SVille Syrjälä new_val &= ~interrupt_mask; 374d9dc34f1SVille Syrjälä new_val |= (~enabled_irq_mask & interrupt_mask); 375d9dc34f1SVille Syrjälä 376e44adb5dSChris Wilson if (new_val != dev_priv->irq_mask && 377e44adb5dSChris Wilson !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) { 378d9dc34f1SVille Syrjälä dev_priv->irq_mask = new_val; 3792939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); 3802939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, DEIMR); 381036a4a7dSZhenyu Wang } 382036a4a7dSZhenyu Wang } 383036a4a7dSZhenyu Wang 3840961021aSBen Widawsky /** 3853a3b3c7dSVille Syrjälä * bdw_update_port_irq - update DE port interrupt 3863a3b3c7dSVille Syrjälä * @dev_priv: driver private 3873a3b3c7dSVille Syrjälä * @interrupt_mask: mask of interrupt bits to update 3883a3b3c7dSVille Syrjälä * @enabled_irq_mask: mask of interrupt bits to enable 3893a3b3c7dSVille Syrjälä */ 3903a3b3c7dSVille Syrjälä static void bdw_update_port_irq(struct drm_i915_private *dev_priv, 391a9c287c9SJani Nikula u32 interrupt_mask, 392a9c287c9SJani Nikula u32 enabled_irq_mask) 3933a3b3c7dSVille Syrjälä { 394a9c287c9SJani Nikula u32 new_val; 395a9c287c9SJani Nikula u32 old_val; 3963a3b3c7dSVille Syrjälä 39767520415SChris Wilson lockdep_assert_held(&dev_priv->irq_lock); 3983a3b3c7dSVille Syrjälä 39948a1b8d4SPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 4003a3b3c7dSVille Syrjälä 40148a1b8d4SPankaj Bharadiya if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 4023a3b3c7dSVille Syrjälä return; 4033a3b3c7dSVille Syrjälä 4042939eb06SJani Nikula old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); 4053a3b3c7dSVille Syrjälä 4063a3b3c7dSVille Syrjälä new_val = old_val; 4073a3b3c7dSVille Syrjälä new_val &= ~interrupt_mask; 4083a3b3c7dSVille Syrjälä new_val |= (~enabled_irq_mask & interrupt_mask); 4093a3b3c7dSVille Syrjälä 4103a3b3c7dSVille Syrjälä if (new_val != old_val) { 4112939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val); 4122939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); 4133a3b3c7dSVille Syrjälä } 4143a3b3c7dSVille Syrjälä } 4153a3b3c7dSVille Syrjälä 4163a3b3c7dSVille Syrjälä /** 417013d3752SVille Syrjälä * bdw_update_pipe_irq - update DE pipe interrupt 418013d3752SVille Syrjälä * @dev_priv: driver private 419013d3752SVille Syrjälä * @pipe: pipe whose interrupt to update 420013d3752SVille Syrjälä * @interrupt_mask: mask of interrupt bits to update 421013d3752SVille Syrjälä * @enabled_irq_mask: mask of interrupt bits to enable 422013d3752SVille Syrjälä */ 423013d3752SVille Syrjälä void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, 424013d3752SVille Syrjälä enum pipe pipe, 425a9c287c9SJani Nikula u32 interrupt_mask, 426a9c287c9SJani Nikula u32 enabled_irq_mask) 427013d3752SVille Syrjälä { 428a9c287c9SJani Nikula u32 new_val; 429013d3752SVille Syrjälä 43067520415SChris Wilson lockdep_assert_held(&dev_priv->irq_lock); 431013d3752SVille Syrjälä 43248a1b8d4SPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 433013d3752SVille Syrjälä 43448a1b8d4SPankaj Bharadiya if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 435013d3752SVille Syrjälä return; 436013d3752SVille Syrjälä 437013d3752SVille Syrjälä new_val = dev_priv->de_irq_mask[pipe]; 438013d3752SVille Syrjälä new_val &= ~interrupt_mask; 439013d3752SVille Syrjälä new_val |= (~enabled_irq_mask & interrupt_mask); 440013d3752SVille Syrjälä 441013d3752SVille Syrjälä if (new_val != dev_priv->de_irq_mask[pipe]) { 442013d3752SVille Syrjälä dev_priv->de_irq_mask[pipe] = new_val; 4432939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 4442939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); 445013d3752SVille Syrjälä } 446013d3752SVille Syrjälä } 447013d3752SVille Syrjälä 448013d3752SVille Syrjälä /** 449fee884edSDaniel Vetter * ibx_display_interrupt_update - update SDEIMR 450fee884edSDaniel Vetter * @dev_priv: driver private 451fee884edSDaniel Vetter * @interrupt_mask: mask of interrupt bits to update 452fee884edSDaniel Vetter * @enabled_irq_mask: mask of interrupt bits to enable 453fee884edSDaniel Vetter */ 45447339cd9SDaniel Vetter void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 455a9c287c9SJani Nikula u32 interrupt_mask, 456a9c287c9SJani Nikula u32 enabled_irq_mask) 457fee884edSDaniel Vetter { 4582939eb06SJani Nikula u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR); 459fee884edSDaniel Vetter sdeimr &= ~interrupt_mask; 460fee884edSDaniel Vetter sdeimr |= (~enabled_irq_mask & interrupt_mask); 461fee884edSDaniel Vetter 46248a1b8d4SPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); 46315a17aaeSDaniel Vetter 46467520415SChris Wilson lockdep_assert_held(&dev_priv->irq_lock); 465fee884edSDaniel Vetter 46648a1b8d4SPankaj Bharadiya if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) 467c67a470bSPaulo Zanoni return; 468c67a470bSPaulo Zanoni 4692939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr); 4702939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, SDEIMR); 471fee884edSDaniel Vetter } 4728664281bSPaulo Zanoni 4736b12ca56SVille Syrjälä u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, 4746b12ca56SVille Syrjälä enum pipe pipe) 4757c463586SKeith Packard { 4766b12ca56SVille Syrjälä u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; 47710c59c51SImre Deak u32 enable_mask = status_mask << 16; 47810c59c51SImre Deak 4796b12ca56SVille Syrjälä lockdep_assert_held(&dev_priv->irq_lock); 4806b12ca56SVille Syrjälä 4816b12ca56SVille Syrjälä if (INTEL_GEN(dev_priv) < 5) 4826b12ca56SVille Syrjälä goto out; 4836b12ca56SVille Syrjälä 48410c59c51SImre Deak /* 485724a6905SVille Syrjälä * On pipe A we don't support the PSR interrupt yet, 486724a6905SVille Syrjälä * on pipe B and C the same bit MBZ. 48710c59c51SImre Deak */ 48848a1b8d4SPankaj Bharadiya if (drm_WARN_ON_ONCE(&dev_priv->drm, 48948a1b8d4SPankaj Bharadiya status_mask & PIPE_A_PSR_STATUS_VLV)) 49010c59c51SImre Deak return 0; 491724a6905SVille Syrjälä /* 492724a6905SVille Syrjälä * On pipe B and C we don't support the PSR interrupt yet, on pipe 493724a6905SVille Syrjälä * A the same bit is for perf counters which we don't use either. 494724a6905SVille Syrjälä */ 49548a1b8d4SPankaj Bharadiya if (drm_WARN_ON_ONCE(&dev_priv->drm, 49648a1b8d4SPankaj Bharadiya status_mask & PIPE_B_PSR_STATUS_VLV)) 497724a6905SVille Syrjälä return 0; 49810c59c51SImre Deak 49910c59c51SImre Deak enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | 50010c59c51SImre Deak SPRITE0_FLIP_DONE_INT_EN_VLV | 50110c59c51SImre Deak SPRITE1_FLIP_DONE_INT_EN_VLV); 50210c59c51SImre Deak if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) 50310c59c51SImre Deak enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; 50410c59c51SImre Deak if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) 50510c59c51SImre Deak enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; 50610c59c51SImre Deak 5076b12ca56SVille Syrjälä out: 50848a1b8d4SPankaj Bharadiya drm_WARN_ONCE(&dev_priv->drm, 50948a1b8d4SPankaj Bharadiya enable_mask & ~PIPESTAT_INT_ENABLE_MASK || 5106b12ca56SVille Syrjälä status_mask & ~PIPESTAT_INT_STATUS_MASK, 5116b12ca56SVille Syrjälä "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", 5126b12ca56SVille Syrjälä pipe_name(pipe), enable_mask, status_mask); 5136b12ca56SVille Syrjälä 51410c59c51SImre Deak return enable_mask; 51510c59c51SImre Deak } 51610c59c51SImre Deak 5176b12ca56SVille Syrjälä void i915_enable_pipestat(struct drm_i915_private *dev_priv, 5186b12ca56SVille Syrjälä enum pipe pipe, u32 status_mask) 519755e9019SImre Deak { 5206b12ca56SVille Syrjälä i915_reg_t reg = PIPESTAT(pipe); 521755e9019SImre Deak u32 enable_mask; 522755e9019SImre Deak 52348a1b8d4SPankaj Bharadiya drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 5246b12ca56SVille Syrjälä "pipe %c: status_mask=0x%x\n", 5256b12ca56SVille Syrjälä pipe_name(pipe), status_mask); 5266b12ca56SVille Syrjälä 5276b12ca56SVille Syrjälä lockdep_assert_held(&dev_priv->irq_lock); 52848a1b8d4SPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); 5296b12ca56SVille Syrjälä 5306b12ca56SVille Syrjälä if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask) 5316b12ca56SVille Syrjälä return; 5326b12ca56SVille Syrjälä 5336b12ca56SVille Syrjälä dev_priv->pipestat_irq_mask[pipe] |= status_mask; 5346b12ca56SVille Syrjälä enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 5356b12ca56SVille Syrjälä 5362939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); 5372939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, reg); 538755e9019SImre Deak } 539755e9019SImre Deak 5406b12ca56SVille Syrjälä void i915_disable_pipestat(struct drm_i915_private *dev_priv, 5416b12ca56SVille Syrjälä enum pipe pipe, u32 status_mask) 542755e9019SImre Deak { 5436b12ca56SVille Syrjälä i915_reg_t reg = PIPESTAT(pipe); 544755e9019SImre Deak u32 enable_mask; 545755e9019SImre Deak 54648a1b8d4SPankaj Bharadiya drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, 5476b12ca56SVille Syrjälä "pipe %c: status_mask=0x%x\n", 5486b12ca56SVille Syrjälä pipe_name(pipe), status_mask); 5496b12ca56SVille Syrjälä 5506b12ca56SVille Syrjälä lockdep_assert_held(&dev_priv->irq_lock); 55148a1b8d4SPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); 5526b12ca56SVille Syrjälä 5536b12ca56SVille Syrjälä if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0) 5546b12ca56SVille Syrjälä return; 5556b12ca56SVille Syrjälä 5566b12ca56SVille Syrjälä dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; 5576b12ca56SVille Syrjälä enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 5586b12ca56SVille Syrjälä 5592939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); 5602939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, reg); 561755e9019SImre Deak } 562755e9019SImre Deak 563f3e30485SVille Syrjälä static bool i915_has_asle(struct drm_i915_private *dev_priv) 564f3e30485SVille Syrjälä { 565f3e30485SVille Syrjälä if (!dev_priv->opregion.asle) 566f3e30485SVille Syrjälä return false; 567f3e30485SVille Syrjälä 568f3e30485SVille Syrjälä return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 569f3e30485SVille Syrjälä } 570f3e30485SVille Syrjälä 571c0e09200SDave Airlie /** 572f49e38ddSJani Nikula * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion 57314bb2c11STvrtko Ursulin * @dev_priv: i915 device private 57401c66889SZhao Yakui */ 57591d14251STvrtko Ursulin static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) 57601c66889SZhao Yakui { 577f3e30485SVille Syrjälä if (!i915_has_asle(dev_priv)) 578f49e38ddSJani Nikula return; 579f49e38ddSJani Nikula 58013321786SDaniel Vetter spin_lock_irq(&dev_priv->irq_lock); 58101c66889SZhao Yakui 582755e9019SImre Deak i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); 58391d14251STvrtko Ursulin if (INTEL_GEN(dev_priv) >= 4) 5843b6c42e8SDaniel Vetter i915_enable_pipestat(dev_priv, PIPE_A, 585755e9019SImre Deak PIPE_LEGACY_BLC_EVENT_STATUS); 5861ec14ad3SChris Wilson 58713321786SDaniel Vetter spin_unlock_irq(&dev_priv->irq_lock); 58801c66889SZhao Yakui } 58901c66889SZhao Yakui 590f75f3746SVille Syrjälä /* 591f75f3746SVille Syrjälä * This timing diagram depicts the video signal in and 592f75f3746SVille Syrjälä * around the vertical blanking period. 593f75f3746SVille Syrjälä * 594f75f3746SVille Syrjälä * Assumptions about the fictitious mode used in this example: 595f75f3746SVille Syrjälä * vblank_start >= 3 596f75f3746SVille Syrjälä * vsync_start = vblank_start + 1 597f75f3746SVille Syrjälä * vsync_end = vblank_start + 2 598f75f3746SVille Syrjälä * vtotal = vblank_start + 3 599f75f3746SVille Syrjälä * 600f75f3746SVille Syrjälä * start of vblank: 601f75f3746SVille Syrjälä * latch double buffered registers 602f75f3746SVille Syrjälä * increment frame counter (ctg+) 603f75f3746SVille Syrjälä * generate start of vblank interrupt (gen4+) 604f75f3746SVille Syrjälä * | 605f75f3746SVille Syrjälä * | frame start: 606f75f3746SVille Syrjälä * | generate frame start interrupt (aka. vblank interrupt) (gmch) 607f75f3746SVille Syrjälä * | may be shifted forward 1-3 extra lines via PIPECONF 608f75f3746SVille Syrjälä * | | 609f75f3746SVille Syrjälä * | | start of vsync: 610f75f3746SVille Syrjälä * | | generate vsync interrupt 611f75f3746SVille Syrjälä * | | | 612f75f3746SVille Syrjälä * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx 613f75f3746SVille Syrjälä * . \hs/ . \hs/ \hs/ \hs/ . \hs/ 614f75f3746SVille Syrjälä * ----va---> <-----------------vb--------------------> <--------va------------- 615f75f3746SVille Syrjälä * | | <----vs-----> | 616f75f3746SVille Syrjälä * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) 617f75f3746SVille Syrjälä * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) 618f75f3746SVille Syrjälä * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) 619f75f3746SVille Syrjälä * | | | 620f75f3746SVille Syrjälä * last visible pixel first visible pixel 621f75f3746SVille Syrjälä * | increment frame counter (gen3/4) 622f75f3746SVille Syrjälä * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) 623f75f3746SVille Syrjälä * 624f75f3746SVille Syrjälä * x = horizontal active 625f75f3746SVille Syrjälä * _ = horizontal blanking 626f75f3746SVille Syrjälä * hs = horizontal sync 627f75f3746SVille Syrjälä * va = vertical active 628f75f3746SVille Syrjälä * vb = vertical blanking 629f75f3746SVille Syrjälä * vs = vertical sync 630f75f3746SVille Syrjälä * vbs = vblank_start (number) 631f75f3746SVille Syrjälä * 632f75f3746SVille Syrjälä * Summary: 633f75f3746SVille Syrjälä * - most events happen at the start of horizontal sync 634f75f3746SVille Syrjälä * - frame start happens at the start of horizontal blank, 1-4 lines 635f75f3746SVille Syrjälä * (depending on PIPECONF settings) after the start of vblank 636f75f3746SVille Syrjälä * - gen3/4 pixel and frame counter are synchronized with the start 637f75f3746SVille Syrjälä * of horizontal active on the first line of vertical active 638f75f3746SVille Syrjälä */ 639f75f3746SVille Syrjälä 64042f52ef8SKeith Packard /* Called from drm generic code, passed a 'crtc', which 64142f52ef8SKeith Packard * we use as a pipe index 64242f52ef8SKeith Packard */ 64308fa8fd0SVille Syrjälä u32 i915_get_vblank_counter(struct drm_crtc *crtc) 6440a3e67a4SJesse Barnes { 64508fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 64608fa8fd0SVille Syrjälä struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; 64732db0b65SVille Syrjälä const struct drm_display_mode *mode = &vblank->hwmode; 64808fa8fd0SVille Syrjälä enum pipe pipe = to_intel_crtc(crtc)->pipe; 649f0f59a00SVille Syrjälä i915_reg_t high_frame, low_frame; 6500b2a8e09SVille Syrjälä u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; 651694e409dSVille Syrjälä unsigned long irqflags; 652391f75e2SVille Syrjälä 65332db0b65SVille Syrjälä /* 65432db0b65SVille Syrjälä * On i965gm TV output the frame counter only works up to 65532db0b65SVille Syrjälä * the point when we enable the TV encoder. After that the 65632db0b65SVille Syrjälä * frame counter ceases to work and reads zero. We need a 65732db0b65SVille Syrjälä * vblank wait before enabling the TV encoder and so we 65832db0b65SVille Syrjälä * have to enable vblank interrupts while the frame counter 65932db0b65SVille Syrjälä * is still in a working state. However the core vblank code 66032db0b65SVille Syrjälä * does not like us returning non-zero frame counter values 66132db0b65SVille Syrjälä * when we've told it that we don't have a working frame 66232db0b65SVille Syrjälä * counter. Thus we must stop non-zero values leaking out. 66332db0b65SVille Syrjälä */ 66432db0b65SVille Syrjälä if (!vblank->max_vblank_count) 66532db0b65SVille Syrjälä return 0; 66632db0b65SVille Syrjälä 6670b2a8e09SVille Syrjälä htotal = mode->crtc_htotal; 6680b2a8e09SVille Syrjälä hsync_start = mode->crtc_hsync_start; 6690b2a8e09SVille Syrjälä vbl_start = mode->crtc_vblank_start; 6700b2a8e09SVille Syrjälä if (mode->flags & DRM_MODE_FLAG_INTERLACE) 6710b2a8e09SVille Syrjälä vbl_start = DIV_ROUND_UP(vbl_start, 2); 672391f75e2SVille Syrjälä 6730b2a8e09SVille Syrjälä /* Convert to pixel count */ 6740b2a8e09SVille Syrjälä vbl_start *= htotal; 6750b2a8e09SVille Syrjälä 6760b2a8e09SVille Syrjälä /* Start of vblank event occurs at start of hsync */ 6770b2a8e09SVille Syrjälä vbl_start -= htotal - hsync_start; 6780b2a8e09SVille Syrjälä 6799db4a9c7SJesse Barnes high_frame = PIPEFRAME(pipe); 6809db4a9c7SJesse Barnes low_frame = PIPEFRAMEPIXEL(pipe); 6815eddb70bSChris Wilson 682694e409dSVille Syrjälä spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 683694e409dSVille Syrjälä 6840a3e67a4SJesse Barnes /* 6850a3e67a4SJesse Barnes * High & low register fields aren't synchronized, so make sure 6860a3e67a4SJesse Barnes * we get a low value that's stable across two reads of the high 6870a3e67a4SJesse Barnes * register. 6880a3e67a4SJesse Barnes */ 6890a3e67a4SJesse Barnes do { 6908cbda6b2SJani Nikula high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; 6918cbda6b2SJani Nikula low = intel_de_read_fw(dev_priv, low_frame); 6928cbda6b2SJani Nikula high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; 6930a3e67a4SJesse Barnes } while (high1 != high2); 6940a3e67a4SJesse Barnes 695694e409dSVille Syrjälä spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 696694e409dSVille Syrjälä 6975eddb70bSChris Wilson high1 >>= PIPE_FRAME_HIGH_SHIFT; 698391f75e2SVille Syrjälä pixel = low & PIPE_PIXEL_MASK; 6995eddb70bSChris Wilson low >>= PIPE_FRAME_LOW_SHIFT; 700391f75e2SVille Syrjälä 701391f75e2SVille Syrjälä /* 702391f75e2SVille Syrjälä * The frame counter increments at beginning of active. 703391f75e2SVille Syrjälä * Cook up a vblank counter by also checking the pixel 704391f75e2SVille Syrjälä * counter against vblank start. 705391f75e2SVille Syrjälä */ 706edc08d0aSVille Syrjälä return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; 7070a3e67a4SJesse Barnes } 7080a3e67a4SJesse Barnes 70908fa8fd0SVille Syrjälä u32 g4x_get_vblank_counter(struct drm_crtc *crtc) 7109880b7a5SJesse Barnes { 71108fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 71233267703SVandita Kulkarni struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; 71308fa8fd0SVille Syrjälä enum pipe pipe = to_intel_crtc(crtc)->pipe; 7149880b7a5SJesse Barnes 71533267703SVandita Kulkarni if (!vblank->max_vblank_count) 71633267703SVandita Kulkarni return 0; 71733267703SVandita Kulkarni 7182939eb06SJani Nikula return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe)); 7199880b7a5SJesse Barnes } 7209880b7a5SJesse Barnes 721*06d6fda5SVille Syrjälä static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc) 722aec0246fSUma Shankar { 723aec0246fSUma Shankar struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 724aec0246fSUma Shankar struct drm_vblank_crtc *vblank = 725aec0246fSUma Shankar &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; 726aec0246fSUma Shankar const struct drm_display_mode *mode = &vblank->hwmode; 727aec0246fSUma Shankar u32 htotal = mode->crtc_htotal; 728aec0246fSUma Shankar u32 clock = mode->crtc_clock; 729*06d6fda5SVille Syrjälä u32 scan_prev_time, scan_curr_time, scan_post_time; 730aec0246fSUma Shankar 731aec0246fSUma Shankar /* 732aec0246fSUma Shankar * To avoid the race condition where we might cross into the 733aec0246fSUma Shankar * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR 734aec0246fSUma Shankar * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR 735aec0246fSUma Shankar * during the same frame. 736aec0246fSUma Shankar */ 737aec0246fSUma Shankar do { 738aec0246fSUma Shankar /* 739aec0246fSUma Shankar * This field provides read back of the display 740aec0246fSUma Shankar * pipe frame time stamp. The time stamp value 741aec0246fSUma Shankar * is sampled at every start of vertical blank. 742aec0246fSUma Shankar */ 7438cbda6b2SJani Nikula scan_prev_time = intel_de_read_fw(dev_priv, 7448cbda6b2SJani Nikula PIPE_FRMTMSTMP(crtc->pipe)); 745aec0246fSUma Shankar 746aec0246fSUma Shankar /* 747aec0246fSUma Shankar * The TIMESTAMP_CTR register has the current 748aec0246fSUma Shankar * time stamp value. 749aec0246fSUma Shankar */ 7508cbda6b2SJani Nikula scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); 751aec0246fSUma Shankar 7528cbda6b2SJani Nikula scan_post_time = intel_de_read_fw(dev_priv, 7538cbda6b2SJani Nikula PIPE_FRMTMSTMP(crtc->pipe)); 754aec0246fSUma Shankar } while (scan_post_time != scan_prev_time); 755aec0246fSUma Shankar 756*06d6fda5SVille Syrjälä return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, 757aec0246fSUma Shankar clock), 1000 * htotal); 758*06d6fda5SVille Syrjälä } 759*06d6fda5SVille Syrjälä 760*06d6fda5SVille Syrjälä /* 761*06d6fda5SVille Syrjälä * On certain encoders on certain platforms, pipe 762*06d6fda5SVille Syrjälä * scanline register will not work to get the scanline, 763*06d6fda5SVille Syrjälä * since the timings are driven from the PORT or issues 764*06d6fda5SVille Syrjälä * with scanline register updates. 765*06d6fda5SVille Syrjälä * This function will use Framestamp and current 766*06d6fda5SVille Syrjälä * timestamp registers to calculate the scanline. 767*06d6fda5SVille Syrjälä */ 768*06d6fda5SVille Syrjälä static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) 769*06d6fda5SVille Syrjälä { 770*06d6fda5SVille Syrjälä struct drm_vblank_crtc *vblank = 771*06d6fda5SVille Syrjälä &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; 772*06d6fda5SVille Syrjälä const struct drm_display_mode *mode = &vblank->hwmode; 773*06d6fda5SVille Syrjälä u32 vblank_start = mode->crtc_vblank_start; 774*06d6fda5SVille Syrjälä u32 vtotal = mode->crtc_vtotal; 775*06d6fda5SVille Syrjälä u32 scanline; 776*06d6fda5SVille Syrjälä 777*06d6fda5SVille Syrjälä scanline = intel_crtc_scanlines_since_frame_timestamp(crtc); 778aec0246fSUma Shankar scanline = min(scanline, vtotal - 1); 779aec0246fSUma Shankar scanline = (scanline + vblank_start) % vtotal; 780aec0246fSUma Shankar 781aec0246fSUma Shankar return scanline; 782aec0246fSUma Shankar } 783aec0246fSUma Shankar 7848cbda6b2SJani Nikula /* 7858cbda6b2SJani Nikula * intel_de_read_fw(), only for fast reads of display block, no need for 7868cbda6b2SJani Nikula * forcewake etc. 7878cbda6b2SJani Nikula */ 788a225f079SVille Syrjälä static int __intel_get_crtc_scanline(struct intel_crtc *crtc) 789a225f079SVille Syrjälä { 790a225f079SVille Syrjälä struct drm_device *dev = crtc->base.dev; 791fac5e23eSChris Wilson struct drm_i915_private *dev_priv = to_i915(dev); 7925caa0feaSDaniel Vetter const struct drm_display_mode *mode; 7935caa0feaSDaniel Vetter struct drm_vblank_crtc *vblank; 794a225f079SVille Syrjälä enum pipe pipe = crtc->pipe; 79580715b2fSVille Syrjälä int position, vtotal; 796a225f079SVille Syrjälä 79772259536SVille Syrjälä if (!crtc->active) 79872259536SVille Syrjälä return -1; 79972259536SVille Syrjälä 8005caa0feaSDaniel Vetter vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; 8015caa0feaSDaniel Vetter mode = &vblank->hwmode; 8025caa0feaSDaniel Vetter 803af157b76SVille Syrjälä if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP) 804aec0246fSUma Shankar return __intel_get_crtc_scanline_from_timestamp(crtc); 805aec0246fSUma Shankar 80680715b2fSVille Syrjälä vtotal = mode->crtc_vtotal; 807a225f079SVille Syrjälä if (mode->flags & DRM_MODE_FLAG_INTERLACE) 808a225f079SVille Syrjälä vtotal /= 2; 809a225f079SVille Syrjälä 810cf819effSLucas De Marchi if (IS_GEN(dev_priv, 2)) 8118cbda6b2SJani Nikula position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; 812a225f079SVille Syrjälä else 8138cbda6b2SJani Nikula position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; 814a225f079SVille Syrjälä 815a225f079SVille Syrjälä /* 81641b578fbSJesse Barnes * On HSW, the DSL reg (0x70000) appears to return 0 if we 81741b578fbSJesse Barnes * read it just before the start of vblank. So try it again 81841b578fbSJesse Barnes * so we don't accidentally end up spanning a vblank frame 81941b578fbSJesse Barnes * increment, causing the pipe_update_end() code to squak at us. 82041b578fbSJesse Barnes * 82141b578fbSJesse Barnes * The nature of this problem means we can't simply check the ISR 82241b578fbSJesse Barnes * bit and return the vblank start value; nor can we use the scanline 82341b578fbSJesse Barnes * debug register in the transcoder as it appears to have the same 82441b578fbSJesse Barnes * problem. We may need to extend this to include other platforms, 82541b578fbSJesse Barnes * but so far testing only shows the problem on HSW. 82641b578fbSJesse Barnes */ 82791d14251STvrtko Ursulin if (HAS_DDI(dev_priv) && !position) { 82841b578fbSJesse Barnes int i, temp; 82941b578fbSJesse Barnes 83041b578fbSJesse Barnes for (i = 0; i < 100; i++) { 83141b578fbSJesse Barnes udelay(1); 8328cbda6b2SJani Nikula temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; 83341b578fbSJesse Barnes if (temp != position) { 83441b578fbSJesse Barnes position = temp; 83541b578fbSJesse Barnes break; 83641b578fbSJesse Barnes } 83741b578fbSJesse Barnes } 83841b578fbSJesse Barnes } 83941b578fbSJesse Barnes 84041b578fbSJesse Barnes /* 84180715b2fSVille Syrjälä * See update_scanline_offset() for the details on the 84280715b2fSVille Syrjälä * scanline_offset adjustment. 843a225f079SVille Syrjälä */ 84480715b2fSVille Syrjälä return (position + crtc->scanline_offset) % vtotal; 845a225f079SVille Syrjälä } 846a225f079SVille Syrjälä 8474bbffbf3SThomas Zimmermann static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, 8484bbffbf3SThomas Zimmermann bool in_vblank_irq, 8494bbffbf3SThomas Zimmermann int *vpos, int *hpos, 8503bb403bfSVille Syrjälä ktime_t *stime, ktime_t *etime, 8513bb403bfSVille Syrjälä const struct drm_display_mode *mode) 8520af7e4dfSMario Kleiner { 8534bbffbf3SThomas Zimmermann struct drm_device *dev = _crtc->dev; 854fac5e23eSChris Wilson struct drm_i915_private *dev_priv = to_i915(dev); 8554bbffbf3SThomas Zimmermann struct intel_crtc *crtc = to_intel_crtc(_crtc); 856e8edae54SVille Syrjälä enum pipe pipe = crtc->pipe; 8573aa18df8SVille Syrjälä int position; 85878e8fc6bSVille Syrjälä int vbl_start, vbl_end, hsync_start, htotal, vtotal; 859ad3543edSMario Kleiner unsigned long irqflags; 8608a920e24SVille Syrjälä bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 || 8618a920e24SVille Syrjälä IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) || 862af157b76SVille Syrjälä crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER; 8630af7e4dfSMario Kleiner 86448a1b8d4SPankaj Bharadiya if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) { 86500376ccfSWambui Karuga drm_dbg(&dev_priv->drm, 86600376ccfSWambui Karuga "trying to get scanoutpos for disabled " 8679db4a9c7SJesse Barnes "pipe %c\n", pipe_name(pipe)); 8681bf6ad62SDaniel Vetter return false; 8690af7e4dfSMario Kleiner } 8700af7e4dfSMario Kleiner 871c2baf4b7SVille Syrjälä htotal = mode->crtc_htotal; 87278e8fc6bSVille Syrjälä hsync_start = mode->crtc_hsync_start; 873c2baf4b7SVille Syrjälä vtotal = mode->crtc_vtotal; 874c2baf4b7SVille Syrjälä vbl_start = mode->crtc_vblank_start; 875c2baf4b7SVille Syrjälä vbl_end = mode->crtc_vblank_end; 8760af7e4dfSMario Kleiner 877d31faf65SVille Syrjälä if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 878d31faf65SVille Syrjälä vbl_start = DIV_ROUND_UP(vbl_start, 2); 879d31faf65SVille Syrjälä vbl_end /= 2; 880d31faf65SVille Syrjälä vtotal /= 2; 881d31faf65SVille Syrjälä } 882d31faf65SVille Syrjälä 883ad3543edSMario Kleiner /* 884ad3543edSMario Kleiner * Lock uncore.lock, as we will do multiple timing critical raw 885ad3543edSMario Kleiner * register reads, potentially with preemption disabled, so the 886ad3543edSMario Kleiner * following code must not block on uncore.lock. 887ad3543edSMario Kleiner */ 888ad3543edSMario Kleiner spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 889ad3543edSMario Kleiner 890ad3543edSMario Kleiner /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 891ad3543edSMario Kleiner 892ad3543edSMario Kleiner /* Get optional system timestamp before query. */ 893ad3543edSMario Kleiner if (stime) 894ad3543edSMario Kleiner *stime = ktime_get(); 895ad3543edSMario Kleiner 8968a920e24SVille Syrjälä if (use_scanline_counter) { 8970af7e4dfSMario Kleiner /* No obvious pixelcount register. Only query vertical 8980af7e4dfSMario Kleiner * scanout position from Display scan line register. 8990af7e4dfSMario Kleiner */ 900e8edae54SVille Syrjälä position = __intel_get_crtc_scanline(crtc); 9010af7e4dfSMario Kleiner } else { 9020af7e4dfSMario Kleiner /* Have access to pixelcount since start of frame. 9030af7e4dfSMario Kleiner * We can split this into vertical and horizontal 9040af7e4dfSMario Kleiner * scanout position. 9050af7e4dfSMario Kleiner */ 9068cbda6b2SJani Nikula position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 9070af7e4dfSMario Kleiner 9083aa18df8SVille Syrjälä /* convert to pixel counts */ 9093aa18df8SVille Syrjälä vbl_start *= htotal; 9103aa18df8SVille Syrjälä vbl_end *= htotal; 9113aa18df8SVille Syrjälä vtotal *= htotal; 91278e8fc6bSVille Syrjälä 91378e8fc6bSVille Syrjälä /* 9147e78f1cbSVille Syrjälä * In interlaced modes, the pixel counter counts all pixels, 9157e78f1cbSVille Syrjälä * so one field will have htotal more pixels. In order to avoid 9167e78f1cbSVille Syrjälä * the reported position from jumping backwards when the pixel 9177e78f1cbSVille Syrjälä * counter is beyond the length of the shorter field, just 9187e78f1cbSVille Syrjälä * clamp the position the length of the shorter field. This 9197e78f1cbSVille Syrjälä * matches how the scanline counter based position works since 9207e78f1cbSVille Syrjälä * the scanline counter doesn't count the two half lines. 9217e78f1cbSVille Syrjälä */ 9227e78f1cbSVille Syrjälä if (position >= vtotal) 9237e78f1cbSVille Syrjälä position = vtotal - 1; 9247e78f1cbSVille Syrjälä 9257e78f1cbSVille Syrjälä /* 92678e8fc6bSVille Syrjälä * Start of vblank interrupt is triggered at start of hsync, 92778e8fc6bSVille Syrjälä * just prior to the first active line of vblank. However we 92878e8fc6bSVille Syrjälä * consider lines to start at the leading edge of horizontal 92978e8fc6bSVille Syrjälä * active. So, should we get here before we've crossed into 93078e8fc6bSVille Syrjälä * the horizontal active of the first line in vblank, we would 93178e8fc6bSVille Syrjälä * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, 93278e8fc6bSVille Syrjälä * always add htotal-hsync_start to the current pixel position. 93378e8fc6bSVille Syrjälä */ 93478e8fc6bSVille Syrjälä position = (position + htotal - hsync_start) % vtotal; 9353aa18df8SVille Syrjälä } 9363aa18df8SVille Syrjälä 937ad3543edSMario Kleiner /* Get optional system timestamp after query. */ 938ad3543edSMario Kleiner if (etime) 939ad3543edSMario Kleiner *etime = ktime_get(); 940ad3543edSMario Kleiner 941ad3543edSMario Kleiner /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 942ad3543edSMario Kleiner 943ad3543edSMario Kleiner spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 944ad3543edSMario Kleiner 9453aa18df8SVille Syrjälä /* 9463aa18df8SVille Syrjälä * While in vblank, position will be negative 9473aa18df8SVille Syrjälä * counting up towards 0 at vbl_end. And outside 9483aa18df8SVille Syrjälä * vblank, position will be positive counting 9493aa18df8SVille Syrjälä * up since vbl_end. 9503aa18df8SVille Syrjälä */ 9513aa18df8SVille Syrjälä if (position >= vbl_start) 9523aa18df8SVille Syrjälä position -= vbl_end; 9533aa18df8SVille Syrjälä else 9543aa18df8SVille Syrjälä position += vtotal - vbl_end; 9553aa18df8SVille Syrjälä 9568a920e24SVille Syrjälä if (use_scanline_counter) { 9573aa18df8SVille Syrjälä *vpos = position; 9583aa18df8SVille Syrjälä *hpos = 0; 9593aa18df8SVille Syrjälä } else { 9600af7e4dfSMario Kleiner *vpos = position / htotal; 9610af7e4dfSMario Kleiner *hpos = position - (*vpos * htotal); 9620af7e4dfSMario Kleiner } 9630af7e4dfSMario Kleiner 9641bf6ad62SDaniel Vetter return true; 9650af7e4dfSMario Kleiner } 9660af7e4dfSMario Kleiner 9674bbffbf3SThomas Zimmermann bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error, 9684bbffbf3SThomas Zimmermann ktime_t *vblank_time, bool in_vblank_irq) 9694bbffbf3SThomas Zimmermann { 9704bbffbf3SThomas Zimmermann return drm_crtc_vblank_helper_get_vblank_timestamp_internal( 9714bbffbf3SThomas Zimmermann crtc, max_error, vblank_time, in_vblank_irq, 97248e67807SThomas Zimmermann i915_get_crtc_scanoutpos); 9734bbffbf3SThomas Zimmermann } 9744bbffbf3SThomas Zimmermann 975a225f079SVille Syrjälä int intel_get_crtc_scanline(struct intel_crtc *crtc) 976a225f079SVille Syrjälä { 977fac5e23eSChris Wilson struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 978a225f079SVille Syrjälä unsigned long irqflags; 979a225f079SVille Syrjälä int position; 980a225f079SVille Syrjälä 981a225f079SVille Syrjälä spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 982a225f079SVille Syrjälä position = __intel_get_crtc_scanline(crtc); 983a225f079SVille Syrjälä spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 984a225f079SVille Syrjälä 985a225f079SVille Syrjälä return position; 986a225f079SVille Syrjälä } 987a225f079SVille Syrjälä 988e3689190SBen Widawsky /** 98974bb98baSLucas De Marchi * ivb_parity_work - Workqueue called when a parity error interrupt 990e3689190SBen Widawsky * occurred. 991e3689190SBen Widawsky * @work: workqueue struct 992e3689190SBen Widawsky * 993e3689190SBen Widawsky * Doesn't actually do anything except notify userspace. As a consequence of 994e3689190SBen Widawsky * this event, userspace should try to remap the bad rows since statistically 995e3689190SBen Widawsky * it is likely the same row is more likely to go bad again. 996e3689190SBen Widawsky */ 99774bb98baSLucas De Marchi static void ivb_parity_work(struct work_struct *work) 998e3689190SBen Widawsky { 9992d1013ddSJani Nikula struct drm_i915_private *dev_priv = 1000cefcff8fSJoonas Lahtinen container_of(work, typeof(*dev_priv), l3_parity.error_work); 1001cf1c97dcSAndi Shyti struct intel_gt *gt = &dev_priv->gt; 1002e3689190SBen Widawsky u32 error_status, row, bank, subbank; 100335a85ac6SBen Widawsky char *parity_event[6]; 1004a9c287c9SJani Nikula u32 misccpctl; 1005a9c287c9SJani Nikula u8 slice = 0; 1006e3689190SBen Widawsky 1007e3689190SBen Widawsky /* We must turn off DOP level clock gating to access the L3 registers. 1008e3689190SBen Widawsky * In order to prevent a get/put style interface, acquire struct mutex 1009e3689190SBen Widawsky * any time we access those registers. 1010e3689190SBen Widawsky */ 101191c8a326SChris Wilson mutex_lock(&dev_priv->drm.struct_mutex); 1012e3689190SBen Widawsky 101335a85ac6SBen Widawsky /* If we've screwed up tracking, just let the interrupt fire again */ 101448a1b8d4SPankaj Bharadiya if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) 101535a85ac6SBen Widawsky goto out; 101635a85ac6SBen Widawsky 10172939eb06SJani Nikula misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL); 10182939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 10192939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); 1020e3689190SBen Widawsky 102135a85ac6SBen Widawsky while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { 1022f0f59a00SVille Syrjälä i915_reg_t reg; 102335a85ac6SBen Widawsky 102435a85ac6SBen Widawsky slice--; 102548a1b8d4SPankaj Bharadiya if (drm_WARN_ON_ONCE(&dev_priv->drm, 102648a1b8d4SPankaj Bharadiya slice >= NUM_L3_SLICES(dev_priv))) 102735a85ac6SBen Widawsky break; 102835a85ac6SBen Widawsky 102935a85ac6SBen Widawsky dev_priv->l3_parity.which_slice &= ~(1<<slice); 103035a85ac6SBen Widawsky 10316fa1c5f1SVille Syrjälä reg = GEN7_L3CDERRST1(slice); 103235a85ac6SBen Widawsky 10332939eb06SJani Nikula error_status = intel_uncore_read(&dev_priv->uncore, reg); 1034e3689190SBen Widawsky row = GEN7_PARITY_ERROR_ROW(error_status); 1035e3689190SBen Widawsky bank = GEN7_PARITY_ERROR_BANK(error_status); 1036e3689190SBen Widawsky subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 1037e3689190SBen Widawsky 10382939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); 10392939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, reg); 1040e3689190SBen Widawsky 1041cce723edSBen Widawsky parity_event[0] = I915_L3_PARITY_UEVENT "=1"; 1042e3689190SBen Widawsky parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); 1043e3689190SBen Widawsky parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); 1044e3689190SBen Widawsky parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); 104535a85ac6SBen Widawsky parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); 104635a85ac6SBen Widawsky parity_event[5] = NULL; 1047e3689190SBen Widawsky 104891c8a326SChris Wilson kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, 1049e3689190SBen Widawsky KOBJ_CHANGE, parity_event); 1050e3689190SBen Widawsky 105135a85ac6SBen Widawsky DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", 105235a85ac6SBen Widawsky slice, row, bank, subbank); 1053e3689190SBen Widawsky 105435a85ac6SBen Widawsky kfree(parity_event[4]); 1055e3689190SBen Widawsky kfree(parity_event[3]); 1056e3689190SBen Widawsky kfree(parity_event[2]); 1057e3689190SBen Widawsky kfree(parity_event[1]); 1058e3689190SBen Widawsky } 1059e3689190SBen Widawsky 10602939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); 106135a85ac6SBen Widawsky 106235a85ac6SBen Widawsky out: 106348a1b8d4SPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); 1064cf1c97dcSAndi Shyti spin_lock_irq(>->irq_lock); 1065cf1c97dcSAndi Shyti gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv)); 1066cf1c97dcSAndi Shyti spin_unlock_irq(>->irq_lock); 106735a85ac6SBen Widawsky 106891c8a326SChris Wilson mutex_unlock(&dev_priv->drm.struct_mutex); 106935a85ac6SBen Widawsky } 107035a85ac6SBen Widawsky 1071af92058fSVille Syrjälä static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 1072121e758eSDhinakaran Pandiyan { 1073af92058fSVille Syrjälä switch (pin) { 1074da51e4baSVille Syrjälä case HPD_PORT_TC1: 1075da51e4baSVille Syrjälä case HPD_PORT_TC2: 1076da51e4baSVille Syrjälä case HPD_PORT_TC3: 1077da51e4baSVille Syrjälä case HPD_PORT_TC4: 1078da51e4baSVille Syrjälä case HPD_PORT_TC5: 1079da51e4baSVille Syrjälä case HPD_PORT_TC6: 10804294fa5fSVille Syrjälä return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin); 108148ef15d3SJosé Roberto de Souza default: 108248ef15d3SJosé Roberto de Souza return false; 108348ef15d3SJosé Roberto de Souza } 108448ef15d3SJosé Roberto de Souza } 108548ef15d3SJosé Roberto de Souza 1086af92058fSVille Syrjälä static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 108763c88d22SImre Deak { 1088af92058fSVille Syrjälä switch (pin) { 1089af92058fSVille Syrjälä case HPD_PORT_A: 1090195baa06SVille Syrjälä return val & PORTA_HOTPLUG_LONG_DETECT; 1091af92058fSVille Syrjälä case HPD_PORT_B: 109263c88d22SImre Deak return val & PORTB_HOTPLUG_LONG_DETECT; 1093af92058fSVille Syrjälä case HPD_PORT_C: 109463c88d22SImre Deak return val & PORTC_HOTPLUG_LONG_DETECT; 109563c88d22SImre Deak default: 109663c88d22SImre Deak return false; 109763c88d22SImre Deak } 109863c88d22SImre Deak } 109963c88d22SImre Deak 1100af92058fSVille Syrjälä static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 110131604222SAnusha Srivatsa { 1102af92058fSVille Syrjälä switch (pin) { 1103af92058fSVille Syrjälä case HPD_PORT_A: 1104af92058fSVille Syrjälä case HPD_PORT_B: 11058ef7e340SMatt Roper case HPD_PORT_C: 1106229f31e2SLucas De Marchi case HPD_PORT_D: 11074294fa5fSVille Syrjälä return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin); 110831604222SAnusha Srivatsa default: 110931604222SAnusha Srivatsa return false; 111031604222SAnusha Srivatsa } 111131604222SAnusha Srivatsa } 111231604222SAnusha Srivatsa 1113af92058fSVille Syrjälä static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 111431604222SAnusha Srivatsa { 1115af92058fSVille Syrjälä switch (pin) { 1116da51e4baSVille Syrjälä case HPD_PORT_TC1: 1117da51e4baSVille Syrjälä case HPD_PORT_TC2: 1118da51e4baSVille Syrjälä case HPD_PORT_TC3: 1119da51e4baSVille Syrjälä case HPD_PORT_TC4: 1120da51e4baSVille Syrjälä case HPD_PORT_TC5: 1121da51e4baSVille Syrjälä case HPD_PORT_TC6: 11224294fa5fSVille Syrjälä return val & ICP_TC_HPD_LONG_DETECT(pin); 112352dfdba0SLucas De Marchi default: 112452dfdba0SLucas De Marchi return false; 112552dfdba0SLucas De Marchi } 112652dfdba0SLucas De Marchi } 112752dfdba0SLucas De Marchi 1128af92058fSVille Syrjälä static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) 11296dbf30ceSVille Syrjälä { 1130af92058fSVille Syrjälä switch (pin) { 1131af92058fSVille Syrjälä case HPD_PORT_E: 11326dbf30ceSVille Syrjälä return val & PORTE_HOTPLUG_LONG_DETECT; 11336dbf30ceSVille Syrjälä default: 11346dbf30ceSVille Syrjälä return false; 11356dbf30ceSVille Syrjälä } 11366dbf30ceSVille Syrjälä } 11376dbf30ceSVille Syrjälä 1138af92058fSVille Syrjälä static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 113974c0b395SVille Syrjälä { 1140af92058fSVille Syrjälä switch (pin) { 1141af92058fSVille Syrjälä case HPD_PORT_A: 114274c0b395SVille Syrjälä return val & PORTA_HOTPLUG_LONG_DETECT; 1143af92058fSVille Syrjälä case HPD_PORT_B: 114474c0b395SVille Syrjälä return val & PORTB_HOTPLUG_LONG_DETECT; 1145af92058fSVille Syrjälä case HPD_PORT_C: 114674c0b395SVille Syrjälä return val & PORTC_HOTPLUG_LONG_DETECT; 1147af92058fSVille Syrjälä case HPD_PORT_D: 114874c0b395SVille Syrjälä return val & PORTD_HOTPLUG_LONG_DETECT; 114974c0b395SVille Syrjälä default: 115074c0b395SVille Syrjälä return false; 115174c0b395SVille Syrjälä } 115274c0b395SVille Syrjälä } 115374c0b395SVille Syrjälä 1154af92058fSVille Syrjälä static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 1155e4ce95aaSVille Syrjälä { 1156af92058fSVille Syrjälä switch (pin) { 1157af92058fSVille Syrjälä case HPD_PORT_A: 1158e4ce95aaSVille Syrjälä return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; 1159e4ce95aaSVille Syrjälä default: 1160e4ce95aaSVille Syrjälä return false; 1161e4ce95aaSVille Syrjälä } 1162e4ce95aaSVille Syrjälä } 1163e4ce95aaSVille Syrjälä 1164af92058fSVille Syrjälä static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 116513cf5504SDave Airlie { 1166af92058fSVille Syrjälä switch (pin) { 1167af92058fSVille Syrjälä case HPD_PORT_B: 1168676574dfSJani Nikula return val & PORTB_HOTPLUG_LONG_DETECT; 1169af92058fSVille Syrjälä case HPD_PORT_C: 1170676574dfSJani Nikula return val & PORTC_HOTPLUG_LONG_DETECT; 1171af92058fSVille Syrjälä case HPD_PORT_D: 1172676574dfSJani Nikula return val & PORTD_HOTPLUG_LONG_DETECT; 1173676574dfSJani Nikula default: 1174676574dfSJani Nikula return false; 117513cf5504SDave Airlie } 117613cf5504SDave Airlie } 117713cf5504SDave Airlie 1178af92058fSVille Syrjälä static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 117913cf5504SDave Airlie { 1180af92058fSVille Syrjälä switch (pin) { 1181af92058fSVille Syrjälä case HPD_PORT_B: 1182676574dfSJani Nikula return val & PORTB_HOTPLUG_INT_LONG_PULSE; 1183af92058fSVille Syrjälä case HPD_PORT_C: 1184676574dfSJani Nikula return val & PORTC_HOTPLUG_INT_LONG_PULSE; 1185af92058fSVille Syrjälä case HPD_PORT_D: 1186676574dfSJani Nikula return val & PORTD_HOTPLUG_INT_LONG_PULSE; 1187676574dfSJani Nikula default: 1188676574dfSJani Nikula return false; 118913cf5504SDave Airlie } 119013cf5504SDave Airlie } 119113cf5504SDave Airlie 119242db67d6SVille Syrjälä /* 119342db67d6SVille Syrjälä * Get a bit mask of pins that have triggered, and which ones may be long. 119442db67d6SVille Syrjälä * This can be called multiple times with the same masks to accumulate 119542db67d6SVille Syrjälä * hotplug detection results from several registers. 119642db67d6SVille Syrjälä * 119742db67d6SVille Syrjälä * Note that the caller is expected to zero out the masks initially. 119842db67d6SVille Syrjälä */ 1199cf53902fSRodrigo Vivi static void intel_get_hpd_pins(struct drm_i915_private *dev_priv, 1200cf53902fSRodrigo Vivi u32 *pin_mask, u32 *long_mask, 12018c841e57SJani Nikula u32 hotplug_trigger, u32 dig_hotplug_reg, 1202fd63e2a9SImre Deak const u32 hpd[HPD_NUM_PINS], 1203af92058fSVille Syrjälä bool long_pulse_detect(enum hpd_pin pin, u32 val)) 1204676574dfSJani Nikula { 1205e9be2850SVille Syrjälä enum hpd_pin pin; 1206676574dfSJani Nikula 120752dfdba0SLucas De Marchi BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS); 120852dfdba0SLucas De Marchi 1209e9be2850SVille Syrjälä for_each_hpd_pin(pin) { 1210e9be2850SVille Syrjälä if ((hpd[pin] & hotplug_trigger) == 0) 12118c841e57SJani Nikula continue; 12128c841e57SJani Nikula 1213e9be2850SVille Syrjälä *pin_mask |= BIT(pin); 1214676574dfSJani Nikula 1215af92058fSVille Syrjälä if (long_pulse_detect(pin, dig_hotplug_reg)) 1216e9be2850SVille Syrjälä *long_mask |= BIT(pin); 1217676574dfSJani Nikula } 1218676574dfSJani Nikula 121900376ccfSWambui Karuga drm_dbg(&dev_priv->drm, 122000376ccfSWambui Karuga "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n", 1221f88f0478SVille Syrjälä hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); 1222676574dfSJani Nikula 1223676574dfSJani Nikula } 1224676574dfSJani Nikula 1225a0e066b8SVille Syrjälä static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, 1226a0e066b8SVille Syrjälä const u32 hpd[HPD_NUM_PINS]) 1227a0e066b8SVille Syrjälä { 1228a0e066b8SVille Syrjälä struct intel_encoder *encoder; 1229a0e066b8SVille Syrjälä u32 enabled_irqs = 0; 1230a0e066b8SVille Syrjälä 1231a0e066b8SVille Syrjälä for_each_intel_encoder(&dev_priv->drm, encoder) 1232a0e066b8SVille Syrjälä if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) 1233a0e066b8SVille Syrjälä enabled_irqs |= hpd[encoder->hpd_pin]; 1234a0e066b8SVille Syrjälä 1235a0e066b8SVille Syrjälä return enabled_irqs; 1236a0e066b8SVille Syrjälä } 1237a0e066b8SVille Syrjälä 1238a0e066b8SVille Syrjälä static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv, 1239a0e066b8SVille Syrjälä const u32 hpd[HPD_NUM_PINS]) 1240a0e066b8SVille Syrjälä { 1241a0e066b8SVille Syrjälä struct intel_encoder *encoder; 1242a0e066b8SVille Syrjälä u32 hotplug_irqs = 0; 1243a0e066b8SVille Syrjälä 1244a0e066b8SVille Syrjälä for_each_intel_encoder(&dev_priv->drm, encoder) 1245a0e066b8SVille Syrjälä hotplug_irqs |= hpd[encoder->hpd_pin]; 1246a0e066b8SVille Syrjälä 1247a0e066b8SVille Syrjälä return hotplug_irqs; 1248a0e066b8SVille Syrjälä } 1249a0e066b8SVille Syrjälä 12502ea63927SVille Syrjälä static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915, 12512ea63927SVille Syrjälä hotplug_enables_func hotplug_enables) 12522ea63927SVille Syrjälä { 12532ea63927SVille Syrjälä struct intel_encoder *encoder; 12542ea63927SVille Syrjälä u32 hotplug = 0; 12552ea63927SVille Syrjälä 12562ea63927SVille Syrjälä for_each_intel_encoder(&i915->drm, encoder) 12572ea63927SVille Syrjälä hotplug |= hotplug_enables(i915, encoder->hpd_pin); 12582ea63927SVille Syrjälä 12592ea63927SVille Syrjälä return hotplug; 12602ea63927SVille Syrjälä } 12612ea63927SVille Syrjälä 126291d14251STvrtko Ursulin static void gmbus_irq_handler(struct drm_i915_private *dev_priv) 1263515ac2bbSDaniel Vetter { 126428c70f16SDaniel Vetter wake_up_all(&dev_priv->gmbus_wait_queue); 1265515ac2bbSDaniel Vetter } 1266515ac2bbSDaniel Vetter 126791d14251STvrtko Ursulin static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) 1268ce99c256SDaniel Vetter { 12699ee32feaSDaniel Vetter wake_up_all(&dev_priv->gmbus_wait_queue); 1270ce99c256SDaniel Vetter } 1271ce99c256SDaniel Vetter 12728bf1e9f1SShuang He #if defined(CONFIG_DEBUG_FS) 127391d14251STvrtko Ursulin static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 127491d14251STvrtko Ursulin enum pipe pipe, 1275a9c287c9SJani Nikula u32 crc0, u32 crc1, 1276a9c287c9SJani Nikula u32 crc2, u32 crc3, 1277a9c287c9SJani Nikula u32 crc4) 12788bf1e9f1SShuang He { 12798c6b709dSTomeu Vizoso struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 128000535527SJani Nikula struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 12815cee6c45SVille Syrjälä u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 }; 12825cee6c45SVille Syrjälä 12835cee6c45SVille Syrjälä trace_intel_pipe_crc(crtc, crcs); 1284b2c88f5bSDamien Lespiau 1285d538bbdfSDamien Lespiau spin_lock(&pipe_crc->lock); 12868c6b709dSTomeu Vizoso /* 12878c6b709dSTomeu Vizoso * For some not yet identified reason, the first CRC is 12888c6b709dSTomeu Vizoso * bonkers. So let's just wait for the next vblank and read 12898c6b709dSTomeu Vizoso * out the buggy result. 12908c6b709dSTomeu Vizoso * 1291163e8aecSRodrigo Vivi * On GEN8+ sometimes the second CRC is bonkers as well, so 12928c6b709dSTomeu Vizoso * don't trust that one either. 12938c6b709dSTomeu Vizoso */ 1294033b7a23SMaarten Lankhorst if (pipe_crc->skipped <= 0 || 1295163e8aecSRodrigo Vivi (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) { 12968c6b709dSTomeu Vizoso pipe_crc->skipped++; 12978c6b709dSTomeu Vizoso spin_unlock(&pipe_crc->lock); 12988c6b709dSTomeu Vizoso return; 12998c6b709dSTomeu Vizoso } 13008c6b709dSTomeu Vizoso spin_unlock(&pipe_crc->lock); 13016cc42152SMaarten Lankhorst 1302246ee524STomeu Vizoso drm_crtc_add_crc_entry(&crtc->base, true, 1303ca814b25SDaniel Vetter drm_crtc_accurate_vblank_count(&crtc->base), 1304246ee524STomeu Vizoso crcs); 13058c6b709dSTomeu Vizoso } 1306277de95eSDaniel Vetter #else 1307277de95eSDaniel Vetter static inline void 130891d14251STvrtko Ursulin display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 130991d14251STvrtko Ursulin enum pipe pipe, 1310a9c287c9SJani Nikula u32 crc0, u32 crc1, 1311a9c287c9SJani Nikula u32 crc2, u32 crc3, 1312a9c287c9SJani Nikula u32 crc4) {} 1313277de95eSDaniel Vetter #endif 1314eba94eb9SDaniel Vetter 13151288f9b0SKarthik B S static void flip_done_handler(struct drm_i915_private *i915, 13161288f9b0SKarthik B S enum pipe pipe) 13171288f9b0SKarthik B S { 13181288f9b0SKarthik B S struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, pipe); 13191288f9b0SKarthik B S struct drm_crtc_state *crtc_state = crtc->base.state; 13201288f9b0SKarthik B S struct drm_pending_vblank_event *e = crtc_state->event; 13211288f9b0SKarthik B S struct drm_device *dev = &i915->drm; 13221288f9b0SKarthik B S unsigned long irqflags; 13231288f9b0SKarthik B S 13241288f9b0SKarthik B S spin_lock_irqsave(&dev->event_lock, irqflags); 13251288f9b0SKarthik B S 13261288f9b0SKarthik B S crtc_state->event = NULL; 13271288f9b0SKarthik B S 13281288f9b0SKarthik B S drm_crtc_send_vblank_event(&crtc->base, e); 13291288f9b0SKarthik B S 13301288f9b0SKarthik B S spin_unlock_irqrestore(&dev->event_lock, irqflags); 13311288f9b0SKarthik B S } 1332277de95eSDaniel Vetter 133391d14251STvrtko Ursulin static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 133491d14251STvrtko Ursulin enum pipe pipe) 13355a69b89fSDaniel Vetter { 133691d14251STvrtko Ursulin display_pipe_crc_irq_handler(dev_priv, pipe, 13372939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), 13385a69b89fSDaniel Vetter 0, 0, 0, 0); 13395a69b89fSDaniel Vetter } 13405a69b89fSDaniel Vetter 134191d14251STvrtko Ursulin static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 134291d14251STvrtko Ursulin enum pipe pipe) 1343eba94eb9SDaniel Vetter { 134491d14251STvrtko Ursulin display_pipe_crc_irq_handler(dev_priv, pipe, 13452939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), 13462939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), 13472939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), 13482939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), 13492939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); 1350eba94eb9SDaniel Vetter } 13515b3a856bSDaniel Vetter 135291d14251STvrtko Ursulin static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, 135391d14251STvrtko Ursulin enum pipe pipe) 13545b3a856bSDaniel Vetter { 1355a9c287c9SJani Nikula u32 res1, res2; 13560b5c5ed0SDaniel Vetter 135791d14251STvrtko Ursulin if (INTEL_GEN(dev_priv) >= 3) 13582939eb06SJani Nikula res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe)); 13590b5c5ed0SDaniel Vetter else 13600b5c5ed0SDaniel Vetter res1 = 0; 13610b5c5ed0SDaniel Vetter 136291d14251STvrtko Ursulin if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 13632939eb06SJani Nikula res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe)); 13640b5c5ed0SDaniel Vetter else 13650b5c5ed0SDaniel Vetter res2 = 0; 13665b3a856bSDaniel Vetter 136791d14251STvrtko Ursulin display_pipe_crc_irq_handler(dev_priv, pipe, 13682939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)), 13692939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)), 13702939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)), 13710b5c5ed0SDaniel Vetter res1, res2); 13725b3a856bSDaniel Vetter } 13738bf1e9f1SShuang He 137444d9241eSVille Syrjälä static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) 137544d9241eSVille Syrjälä { 137644d9241eSVille Syrjälä enum pipe pipe; 137744d9241eSVille Syrjälä 137844d9241eSVille Syrjälä for_each_pipe(dev_priv, pipe) { 13792939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe), 138044d9241eSVille Syrjälä PIPESTAT_INT_STATUS_MASK | 138144d9241eSVille Syrjälä PIPE_FIFO_UNDERRUN_STATUS); 138244d9241eSVille Syrjälä 138344d9241eSVille Syrjälä dev_priv->pipestat_irq_mask[pipe] = 0; 138444d9241eSVille Syrjälä } 138544d9241eSVille Syrjälä } 138644d9241eSVille Syrjälä 1387eb64343cSVille Syrjälä static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, 138891d14251STvrtko Ursulin u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 13897e231dbeSJesse Barnes { 1390d048a268SVille Syrjälä enum pipe pipe; 13917e231dbeSJesse Barnes 139258ead0d7SImre Deak spin_lock(&dev_priv->irq_lock); 13931ca993d2SVille Syrjälä 13941ca993d2SVille Syrjälä if (!dev_priv->display_irqs_enabled) { 13951ca993d2SVille Syrjälä spin_unlock(&dev_priv->irq_lock); 13961ca993d2SVille Syrjälä return; 13971ca993d2SVille Syrjälä } 13981ca993d2SVille Syrjälä 1399055e393fSDamien Lespiau for_each_pipe(dev_priv, pipe) { 1400f0f59a00SVille Syrjälä i915_reg_t reg; 14016b12ca56SVille Syrjälä u32 status_mask, enable_mask, iir_bit = 0; 140291d181ddSImre Deak 1403bbb5eebfSDaniel Vetter /* 1404bbb5eebfSDaniel Vetter * PIPESTAT bits get signalled even when the interrupt is 1405bbb5eebfSDaniel Vetter * disabled with the mask bits, and some of the status bits do 1406bbb5eebfSDaniel Vetter * not generate interrupts at all (like the underrun bit). Hence 1407bbb5eebfSDaniel Vetter * we need to be careful that we only handle what we want to 1408bbb5eebfSDaniel Vetter * handle. 1409bbb5eebfSDaniel Vetter */ 14100f239f4cSDaniel Vetter 14110f239f4cSDaniel Vetter /* fifo underruns are filterered in the underrun handler. */ 14126b12ca56SVille Syrjälä status_mask = PIPE_FIFO_UNDERRUN_STATUS; 1413bbb5eebfSDaniel Vetter 1414bbb5eebfSDaniel Vetter switch (pipe) { 1415d048a268SVille Syrjälä default: 1416bbb5eebfSDaniel Vetter case PIPE_A: 1417bbb5eebfSDaniel Vetter iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; 1418bbb5eebfSDaniel Vetter break; 1419bbb5eebfSDaniel Vetter case PIPE_B: 1420bbb5eebfSDaniel Vetter iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; 1421bbb5eebfSDaniel Vetter break; 14223278f67fSVille Syrjälä case PIPE_C: 14233278f67fSVille Syrjälä iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; 14243278f67fSVille Syrjälä break; 1425bbb5eebfSDaniel Vetter } 1426bbb5eebfSDaniel Vetter if (iir & iir_bit) 14276b12ca56SVille Syrjälä status_mask |= dev_priv->pipestat_irq_mask[pipe]; 1428bbb5eebfSDaniel Vetter 14296b12ca56SVille Syrjälä if (!status_mask) 143091d181ddSImre Deak continue; 143191d181ddSImre Deak 143291d181ddSImre Deak reg = PIPESTAT(pipe); 14332939eb06SJani Nikula pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; 14346b12ca56SVille Syrjälä enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); 14357e231dbeSJesse Barnes 14367e231dbeSJesse Barnes /* 14377e231dbeSJesse Barnes * Clear the PIPE*STAT regs before the IIR 1438132c27c9SVille Syrjälä * 1439132c27c9SVille Syrjälä * Toggle the enable bits to make sure we get an 1440132c27c9SVille Syrjälä * edge in the ISR pipe event bit if we don't clear 1441132c27c9SVille Syrjälä * all the enabled status bits. Otherwise the edge 1442132c27c9SVille Syrjälä * triggered IIR on i965/g4x wouldn't notice that 1443132c27c9SVille Syrjälä * an interrupt is still pending. 14447e231dbeSJesse Barnes */ 1445132c27c9SVille Syrjälä if (pipe_stats[pipe]) { 14462939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); 14472939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, reg, enable_mask); 1448132c27c9SVille Syrjälä } 14497e231dbeSJesse Barnes } 145058ead0d7SImre Deak spin_unlock(&dev_priv->irq_lock); 14512ecb8ca4SVille Syrjälä } 14522ecb8ca4SVille Syrjälä 1453eb64343cSVille Syrjälä static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv, 1454eb64343cSVille Syrjälä u16 iir, u32 pipe_stats[I915_MAX_PIPES]) 1455eb64343cSVille Syrjälä { 1456eb64343cSVille Syrjälä enum pipe pipe; 1457eb64343cSVille Syrjälä 1458eb64343cSVille Syrjälä for_each_pipe(dev_priv, pipe) { 1459eb64343cSVille Syrjälä if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 1460aca9310aSAnshuman Gupta intel_handle_vblank(dev_priv, pipe); 1461eb64343cSVille Syrjälä 1462eb64343cSVille Syrjälä if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1463eb64343cSVille Syrjälä i9xx_pipe_crc_irq_handler(dev_priv, pipe); 1464eb64343cSVille Syrjälä 1465eb64343cSVille Syrjälä if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1466eb64343cSVille Syrjälä intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1467eb64343cSVille Syrjälä } 1468eb64343cSVille Syrjälä } 1469eb64343cSVille Syrjälä 1470eb64343cSVille Syrjälä static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, 1471eb64343cSVille Syrjälä u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 1472eb64343cSVille Syrjälä { 1473eb64343cSVille Syrjälä bool blc_event = false; 1474eb64343cSVille Syrjälä enum pipe pipe; 1475eb64343cSVille Syrjälä 1476eb64343cSVille Syrjälä for_each_pipe(dev_priv, pipe) { 1477eb64343cSVille Syrjälä if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 1478aca9310aSAnshuman Gupta intel_handle_vblank(dev_priv, pipe); 1479eb64343cSVille Syrjälä 1480eb64343cSVille Syrjälä if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 1481eb64343cSVille Syrjälä blc_event = true; 1482eb64343cSVille Syrjälä 1483eb64343cSVille Syrjälä if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1484eb64343cSVille Syrjälä i9xx_pipe_crc_irq_handler(dev_priv, pipe); 1485eb64343cSVille Syrjälä 1486eb64343cSVille Syrjälä if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1487eb64343cSVille Syrjälä intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1488eb64343cSVille Syrjälä } 1489eb64343cSVille Syrjälä 1490eb64343cSVille Syrjälä if (blc_event || (iir & I915_ASLE_INTERRUPT)) 1491eb64343cSVille Syrjälä intel_opregion_asle_intr(dev_priv); 1492eb64343cSVille Syrjälä } 1493eb64343cSVille Syrjälä 1494eb64343cSVille Syrjälä static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, 1495eb64343cSVille Syrjälä u32 iir, u32 pipe_stats[I915_MAX_PIPES]) 1496eb64343cSVille Syrjälä { 1497eb64343cSVille Syrjälä bool blc_event = false; 1498eb64343cSVille Syrjälä enum pipe pipe; 1499eb64343cSVille Syrjälä 1500eb64343cSVille Syrjälä for_each_pipe(dev_priv, pipe) { 1501eb64343cSVille Syrjälä if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 1502aca9310aSAnshuman Gupta intel_handle_vblank(dev_priv, pipe); 1503eb64343cSVille Syrjälä 1504eb64343cSVille Syrjälä if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 1505eb64343cSVille Syrjälä blc_event = true; 1506eb64343cSVille Syrjälä 1507eb64343cSVille Syrjälä if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1508eb64343cSVille Syrjälä i9xx_pipe_crc_irq_handler(dev_priv, pipe); 1509eb64343cSVille Syrjälä 1510eb64343cSVille Syrjälä if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1511eb64343cSVille Syrjälä intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 1512eb64343cSVille Syrjälä } 1513eb64343cSVille Syrjälä 1514eb64343cSVille Syrjälä if (blc_event || (iir & I915_ASLE_INTERRUPT)) 1515eb64343cSVille Syrjälä intel_opregion_asle_intr(dev_priv); 1516eb64343cSVille Syrjälä 1517eb64343cSVille Syrjälä if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 1518eb64343cSVille Syrjälä gmbus_irq_handler(dev_priv); 1519eb64343cSVille Syrjälä } 1520eb64343cSVille Syrjälä 152191d14251STvrtko Ursulin static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, 15222ecb8ca4SVille Syrjälä u32 pipe_stats[I915_MAX_PIPES]) 15232ecb8ca4SVille Syrjälä { 15242ecb8ca4SVille Syrjälä enum pipe pipe; 15257e231dbeSJesse Barnes 1526055e393fSDamien Lespiau for_each_pipe(dev_priv, pipe) { 1527fd3a4024SDaniel Vetter if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 1528aca9310aSAnshuman Gupta intel_handle_vblank(dev_priv, pipe); 15294356d586SDaniel Vetter 15304356d586SDaniel Vetter if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 153191d14251STvrtko Ursulin i9xx_pipe_crc_irq_handler(dev_priv, pipe); 15322d9d2b0bSVille Syrjälä 15331f7247c0SDaniel Vetter if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 15341f7247c0SDaniel Vetter intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 153531acc7f5SJesse Barnes } 153631acc7f5SJesse Barnes 1537c1874ed7SImre Deak if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 153891d14251STvrtko Ursulin gmbus_irq_handler(dev_priv); 1539c1874ed7SImre Deak } 1540c1874ed7SImre Deak 15411ae3c34cSVille Syrjälä static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) 154216c6c56bSVille Syrjälä { 15430ba7c51aSVille Syrjälä u32 hotplug_status = 0, hotplug_status_mask; 15440ba7c51aSVille Syrjälä int i; 154516c6c56bSVille Syrjälä 15460ba7c51aSVille Syrjälä if (IS_G4X(dev_priv) || 15470ba7c51aSVille Syrjälä IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 15480ba7c51aSVille Syrjälä hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | 15490ba7c51aSVille Syrjälä DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; 15500ba7c51aSVille Syrjälä else 15510ba7c51aSVille Syrjälä hotplug_status_mask = HOTPLUG_INT_STATUS_I915; 15520ba7c51aSVille Syrjälä 15530ba7c51aSVille Syrjälä /* 15540ba7c51aSVille Syrjälä * We absolutely have to clear all the pending interrupt 15550ba7c51aSVille Syrjälä * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port 15560ba7c51aSVille Syrjälä * interrupt bit won't have an edge, and the i965/g4x 15570ba7c51aSVille Syrjälä * edge triggered IIR will not notice that an interrupt 15580ba7c51aSVille Syrjälä * is still pending. We can't use PORT_HOTPLUG_EN to 15590ba7c51aSVille Syrjälä * guarantee the edge as the act of toggling the enable 15600ba7c51aSVille Syrjälä * bits can itself generate a new hotplug interrupt :( 15610ba7c51aSVille Syrjälä */ 15620ba7c51aSVille Syrjälä for (i = 0; i < 10; i++) { 15632939eb06SJani Nikula u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask; 15640ba7c51aSVille Syrjälä 15650ba7c51aSVille Syrjälä if (tmp == 0) 15660ba7c51aSVille Syrjälä return hotplug_status; 15670ba7c51aSVille Syrjälä 15680ba7c51aSVille Syrjälä hotplug_status |= tmp; 15692939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status); 15700ba7c51aSVille Syrjälä } 15710ba7c51aSVille Syrjälä 157248a1b8d4SPankaj Bharadiya drm_WARN_ONCE(&dev_priv->drm, 1, 15730ba7c51aSVille Syrjälä "PORT_HOTPLUG_STAT did not clear (0x%08x)\n", 15742939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); 15751ae3c34cSVille Syrjälä 15761ae3c34cSVille Syrjälä return hotplug_status; 15771ae3c34cSVille Syrjälä } 15781ae3c34cSVille Syrjälä 157991d14251STvrtko Ursulin static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, 15801ae3c34cSVille Syrjälä u32 hotplug_status) 15811ae3c34cSVille Syrjälä { 15821ae3c34cSVille Syrjälä u32 pin_mask = 0, long_mask = 0; 15830398993bSVille Syrjälä u32 hotplug_trigger; 15843ff60f89SOscar Mateo 15850398993bSVille Syrjälä if (IS_G4X(dev_priv) || 15860398993bSVille Syrjälä IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 15870398993bSVille Syrjälä hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; 15880398993bSVille Syrjälä else 15890398993bSVille Syrjälä hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 159016c6c56bSVille Syrjälä 159158f2cf24SVille Syrjälä if (hotplug_trigger) { 1592cf53902fSRodrigo Vivi intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 1593cf53902fSRodrigo Vivi hotplug_trigger, hotplug_trigger, 15940398993bSVille Syrjälä dev_priv->hotplug.hpd, 1595fd63e2a9SImre Deak i9xx_port_hotplug_long_detect); 159658f2cf24SVille Syrjälä 159791d14251STvrtko Ursulin intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 159858f2cf24SVille Syrjälä } 1599369712e8SJani Nikula 16000398993bSVille Syrjälä if ((IS_G4X(dev_priv) || 16010398993bSVille Syrjälä IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 16020398993bSVille Syrjälä hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) 160391d14251STvrtko Ursulin dp_aux_irq_handler(dev_priv); 160458f2cf24SVille Syrjälä } 160516c6c56bSVille Syrjälä 1606c1874ed7SImre Deak static irqreturn_t valleyview_irq_handler(int irq, void *arg) 1607c1874ed7SImre Deak { 1608b318b824SVille Syrjälä struct drm_i915_private *dev_priv = arg; 1609c1874ed7SImre Deak irqreturn_t ret = IRQ_NONE; 1610c1874ed7SImre Deak 16112dd2a883SImre Deak if (!intel_irqs_enabled(dev_priv)) 16122dd2a883SImre Deak return IRQ_NONE; 16132dd2a883SImre Deak 16141f814dacSImre Deak /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 16159102650fSDaniele Ceraolo Spurio disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 16161f814dacSImre Deak 16171e1cace9SVille Syrjälä do { 16186e814800SVille Syrjälä u32 iir, gt_iir, pm_iir; 16192ecb8ca4SVille Syrjälä u32 pipe_stats[I915_MAX_PIPES] = {}; 16201ae3c34cSVille Syrjälä u32 hotplug_status = 0; 1621a5e485a9SVille Syrjälä u32 ier = 0; 16223ff60f89SOscar Mateo 16232939eb06SJani Nikula gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); 16242939eb06SJani Nikula pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); 16252939eb06SJani Nikula iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 1626c1874ed7SImre Deak 1627c1874ed7SImre Deak if (gt_iir == 0 && pm_iir == 0 && iir == 0) 16281e1cace9SVille Syrjälä break; 1629c1874ed7SImre Deak 1630c1874ed7SImre Deak ret = IRQ_HANDLED; 1631c1874ed7SImre Deak 1632a5e485a9SVille Syrjälä /* 1633a5e485a9SVille Syrjälä * Theory on interrupt generation, based on empirical evidence: 1634a5e485a9SVille Syrjälä * 1635a5e485a9SVille Syrjälä * x = ((VLV_IIR & VLV_IER) || 1636a5e485a9SVille Syrjälä * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && 1637a5e485a9SVille Syrjälä * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); 1638a5e485a9SVille Syrjälä * 1639a5e485a9SVille Syrjälä * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 1640a5e485a9SVille Syrjälä * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to 1641a5e485a9SVille Syrjälä * guarantee the CPU interrupt will be raised again even if we 1642a5e485a9SVille Syrjälä * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR 1643a5e485a9SVille Syrjälä * bits this time around. 1644a5e485a9SVille Syrjälä */ 16452939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 16462939eb06SJani Nikula ier = intel_uncore_read(&dev_priv->uncore, VLV_IER); 16472939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, VLV_IER, 0); 16484a0a0202SVille Syrjälä 16494a0a0202SVille Syrjälä if (gt_iir) 16502939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir); 16514a0a0202SVille Syrjälä if (pm_iir) 16522939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir); 16534a0a0202SVille Syrjälä 16547ce4d1f2SVille Syrjälä if (iir & I915_DISPLAY_PORT_INTERRUPT) 16551ae3c34cSVille Syrjälä hotplug_status = i9xx_hpd_irq_ack(dev_priv); 16567ce4d1f2SVille Syrjälä 16573ff60f89SOscar Mateo /* Call regardless, as some status bits might not be 16583ff60f89SOscar Mateo * signalled in iir */ 1659eb64343cSVille Syrjälä i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 16607ce4d1f2SVille Syrjälä 1661eef57324SJerome Anand if (iir & (I915_LPE_PIPE_A_INTERRUPT | 1662eef57324SJerome Anand I915_LPE_PIPE_B_INTERRUPT)) 1663eef57324SJerome Anand intel_lpe_audio_irq_handler(dev_priv); 1664eef57324SJerome Anand 16657ce4d1f2SVille Syrjälä /* 16667ce4d1f2SVille Syrjälä * VLV_IIR is single buffered, and reflects the level 16677ce4d1f2SVille Syrjälä * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 16687ce4d1f2SVille Syrjälä */ 16697ce4d1f2SVille Syrjälä if (iir) 16702939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 16714a0a0202SVille Syrjälä 16722939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 16732939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 16741ae3c34cSVille Syrjälä 167552894874SVille Syrjälä if (gt_iir) 1676cf1c97dcSAndi Shyti gen6_gt_irq_handler(&dev_priv->gt, gt_iir); 167752894874SVille Syrjälä if (pm_iir) 16783e7abf81SAndi Shyti gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir); 167952894874SVille Syrjälä 16801ae3c34cSVille Syrjälä if (hotplug_status) 168191d14251STvrtko Ursulin i9xx_hpd_irq_handler(dev_priv, hotplug_status); 16822ecb8ca4SVille Syrjälä 168391d14251STvrtko Ursulin valleyview_pipestat_irq_handler(dev_priv, pipe_stats); 16841e1cace9SVille Syrjälä } while (0); 16857e231dbeSJesse Barnes 16869c6508b9SThomas Gleixner pmu_irq_stats(dev_priv, ret); 16879c6508b9SThomas Gleixner 16889102650fSDaniele Ceraolo Spurio enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 16891f814dacSImre Deak 16907e231dbeSJesse Barnes return ret; 16917e231dbeSJesse Barnes } 16927e231dbeSJesse Barnes 169343f328d7SVille Syrjälä static irqreturn_t cherryview_irq_handler(int irq, void *arg) 169443f328d7SVille Syrjälä { 1695b318b824SVille Syrjälä struct drm_i915_private *dev_priv = arg; 169643f328d7SVille Syrjälä irqreturn_t ret = IRQ_NONE; 169743f328d7SVille Syrjälä 16982dd2a883SImre Deak if (!intel_irqs_enabled(dev_priv)) 16992dd2a883SImre Deak return IRQ_NONE; 17002dd2a883SImre Deak 17011f814dacSImre Deak /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 17029102650fSDaniele Ceraolo Spurio disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 17031f814dacSImre Deak 1704579de73bSChris Wilson do { 17056e814800SVille Syrjälä u32 master_ctl, iir; 17062ecb8ca4SVille Syrjälä u32 pipe_stats[I915_MAX_PIPES] = {}; 17071ae3c34cSVille Syrjälä u32 hotplug_status = 0; 1708a5e485a9SVille Syrjälä u32 ier = 0; 1709a5e485a9SVille Syrjälä 17102939eb06SJani Nikula master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; 17112939eb06SJani Nikula iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); 17123278f67fSVille Syrjälä 17133278f67fSVille Syrjälä if (master_ctl == 0 && iir == 0) 17148e5fd599SVille Syrjälä break; 171543f328d7SVille Syrjälä 171627b6c122SOscar Mateo ret = IRQ_HANDLED; 171727b6c122SOscar Mateo 1718a5e485a9SVille Syrjälä /* 1719a5e485a9SVille Syrjälä * Theory on interrupt generation, based on empirical evidence: 1720a5e485a9SVille Syrjälä * 1721a5e485a9SVille Syrjälä * x = ((VLV_IIR & VLV_IER) || 1722a5e485a9SVille Syrjälä * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && 1723a5e485a9SVille Syrjälä * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); 1724a5e485a9SVille Syrjälä * 1725a5e485a9SVille Syrjälä * A CPU interrupt will only be raised when 'x' has a 0->1 edge. 1726a5e485a9SVille Syrjälä * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to 1727a5e485a9SVille Syrjälä * guarantee the CPU interrupt will be raised again even if we 1728a5e485a9SVille Syrjälä * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL 1729a5e485a9SVille Syrjälä * bits this time around. 1730a5e485a9SVille Syrjälä */ 17312939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); 17322939eb06SJani Nikula ier = intel_uncore_read(&dev_priv->uncore, VLV_IER); 17332939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, VLV_IER, 0); 173443f328d7SVille Syrjälä 17356cc32f15SChris Wilson gen8_gt_irq_handler(&dev_priv->gt, master_ctl); 173627b6c122SOscar Mateo 173727b6c122SOscar Mateo if (iir & I915_DISPLAY_PORT_INTERRUPT) 17381ae3c34cSVille Syrjälä hotplug_status = i9xx_hpd_irq_ack(dev_priv); 173943f328d7SVille Syrjälä 174027b6c122SOscar Mateo /* Call regardless, as some status bits might not be 174127b6c122SOscar Mateo * signalled in iir */ 1742eb64343cSVille Syrjälä i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 174343f328d7SVille Syrjälä 1744eef57324SJerome Anand if (iir & (I915_LPE_PIPE_A_INTERRUPT | 1745eef57324SJerome Anand I915_LPE_PIPE_B_INTERRUPT | 1746eef57324SJerome Anand I915_LPE_PIPE_C_INTERRUPT)) 1747eef57324SJerome Anand intel_lpe_audio_irq_handler(dev_priv); 1748eef57324SJerome Anand 17497ce4d1f2SVille Syrjälä /* 17507ce4d1f2SVille Syrjälä * VLV_IIR is single buffered, and reflects the level 17517ce4d1f2SVille Syrjälä * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. 17527ce4d1f2SVille Syrjälä */ 17537ce4d1f2SVille Syrjälä if (iir) 17542939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); 17557ce4d1f2SVille Syrjälä 17562939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); 17572939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 17581ae3c34cSVille Syrjälä 17591ae3c34cSVille Syrjälä if (hotplug_status) 176091d14251STvrtko Ursulin i9xx_hpd_irq_handler(dev_priv, hotplug_status); 17612ecb8ca4SVille Syrjälä 176291d14251STvrtko Ursulin valleyview_pipestat_irq_handler(dev_priv, pipe_stats); 1763579de73bSChris Wilson } while (0); 17643278f67fSVille Syrjälä 17659c6508b9SThomas Gleixner pmu_irq_stats(dev_priv, ret); 17669c6508b9SThomas Gleixner 17679102650fSDaniele Ceraolo Spurio enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 17681f814dacSImre Deak 176943f328d7SVille Syrjälä return ret; 177043f328d7SVille Syrjälä } 177143f328d7SVille Syrjälä 177291d14251STvrtko Ursulin static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, 17730398993bSVille Syrjälä u32 hotplug_trigger) 1774776ad806SJesse Barnes { 177542db67d6SVille Syrjälä u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 1776776ad806SJesse Barnes 17776a39d7c9SJani Nikula /* 17786a39d7c9SJani Nikula * Somehow the PCH doesn't seem to really ack the interrupt to the CPU 17796a39d7c9SJani Nikula * unless we touch the hotplug register, even if hotplug_trigger is 17806a39d7c9SJani Nikula * zero. Not acking leads to "The master control interrupt lied (SDE)!" 17816a39d7c9SJani Nikula * errors. 17826a39d7c9SJani Nikula */ 17832939eb06SJani Nikula dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 17846a39d7c9SJani Nikula if (!hotplug_trigger) { 17856a39d7c9SJani Nikula u32 mask = PORTA_HOTPLUG_STATUS_MASK | 17866a39d7c9SJani Nikula PORTD_HOTPLUG_STATUS_MASK | 17876a39d7c9SJani Nikula PORTC_HOTPLUG_STATUS_MASK | 17886a39d7c9SJani Nikula PORTB_HOTPLUG_STATUS_MASK; 17896a39d7c9SJani Nikula dig_hotplug_reg &= ~mask; 17906a39d7c9SJani Nikula } 17916a39d7c9SJani Nikula 17922939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); 17936a39d7c9SJani Nikula if (!hotplug_trigger) 17946a39d7c9SJani Nikula return; 179513cf5504SDave Airlie 17960398993bSVille Syrjälä intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 17970398993bSVille Syrjälä hotplug_trigger, dig_hotplug_reg, 17980398993bSVille Syrjälä dev_priv->hotplug.pch_hpd, 1799fd63e2a9SImre Deak pch_port_hotplug_long_detect); 180040e56410SVille Syrjälä 180191d14251STvrtko Ursulin intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 1802aaf5ec2eSSonika Jindal } 180391d131d2SDaniel Vetter 180491d14251STvrtko Ursulin static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 180540e56410SVille Syrjälä { 1806d048a268SVille Syrjälä enum pipe pipe; 180740e56410SVille Syrjälä u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 180840e56410SVille Syrjälä 18090398993bSVille Syrjälä ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 181040e56410SVille Syrjälä 1811cfc33bf7SVille Syrjälä if (pch_iir & SDE_AUDIO_POWER_MASK) { 1812cfc33bf7SVille Syrjälä int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> 1813776ad806SJesse Barnes SDE_AUDIO_POWER_SHIFT); 181400376ccfSWambui Karuga drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n", 1815cfc33bf7SVille Syrjälä port_name(port)); 1816cfc33bf7SVille Syrjälä } 1817776ad806SJesse Barnes 1818ce99c256SDaniel Vetter if (pch_iir & SDE_AUX_MASK) 181991d14251STvrtko Ursulin dp_aux_irq_handler(dev_priv); 1820ce99c256SDaniel Vetter 1821776ad806SJesse Barnes if (pch_iir & SDE_GMBUS) 182291d14251STvrtko Ursulin gmbus_irq_handler(dev_priv); 1823776ad806SJesse Barnes 1824776ad806SJesse Barnes if (pch_iir & SDE_AUDIO_HDCP_MASK) 182500376ccfSWambui Karuga drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n"); 1826776ad806SJesse Barnes 1827776ad806SJesse Barnes if (pch_iir & SDE_AUDIO_TRANS_MASK) 182800376ccfSWambui Karuga drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n"); 1829776ad806SJesse Barnes 1830776ad806SJesse Barnes if (pch_iir & SDE_POISON) 183100376ccfSWambui Karuga drm_err(&dev_priv->drm, "PCH poison interrupt\n"); 1832776ad806SJesse Barnes 1833b8b65ccdSAnshuman Gupta if (pch_iir & SDE_FDI_MASK) { 1834055e393fSDamien Lespiau for_each_pipe(dev_priv, pipe) 183500376ccfSWambui Karuga drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", 18369db4a9c7SJesse Barnes pipe_name(pipe), 18372939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); 1838b8b65ccdSAnshuman Gupta } 1839776ad806SJesse Barnes 1840776ad806SJesse Barnes if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 184100376ccfSWambui Karuga drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n"); 1842776ad806SJesse Barnes 1843776ad806SJesse Barnes if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 184400376ccfSWambui Karuga drm_dbg(&dev_priv->drm, 184500376ccfSWambui Karuga "PCH transcoder CRC error interrupt\n"); 1846776ad806SJesse Barnes 1847776ad806SJesse Barnes if (pch_iir & SDE_TRANSA_FIFO_UNDER) 1848a2196033SMatthias Kaehlcke intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); 18498664281bSPaulo Zanoni 18508664281bSPaulo Zanoni if (pch_iir & SDE_TRANSB_FIFO_UNDER) 1851a2196033SMatthias Kaehlcke intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); 18528664281bSPaulo Zanoni } 18538664281bSPaulo Zanoni 185491d14251STvrtko Ursulin static void ivb_err_int_handler(struct drm_i915_private *dev_priv) 18558664281bSPaulo Zanoni { 18562939eb06SJani Nikula u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT); 18575a69b89fSDaniel Vetter enum pipe pipe; 18588664281bSPaulo Zanoni 1859de032bf4SPaulo Zanoni if (err_int & ERR_INT_POISON) 186000376ccfSWambui Karuga drm_err(&dev_priv->drm, "Poison interrupt\n"); 1861de032bf4SPaulo Zanoni 1862055e393fSDamien Lespiau for_each_pipe(dev_priv, pipe) { 18631f7247c0SDaniel Vetter if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) 18641f7247c0SDaniel Vetter intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 18658664281bSPaulo Zanoni 18665a69b89fSDaniel Vetter if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 186791d14251STvrtko Ursulin if (IS_IVYBRIDGE(dev_priv)) 186891d14251STvrtko Ursulin ivb_pipe_crc_irq_handler(dev_priv, pipe); 18695a69b89fSDaniel Vetter else 187091d14251STvrtko Ursulin hsw_pipe_crc_irq_handler(dev_priv, pipe); 18715a69b89fSDaniel Vetter } 18725a69b89fSDaniel Vetter } 18738bf1e9f1SShuang He 18742939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int); 18758664281bSPaulo Zanoni } 18768664281bSPaulo Zanoni 187791d14251STvrtko Ursulin static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) 18788664281bSPaulo Zanoni { 18792939eb06SJani Nikula u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT); 188045c1cd87SMika Kahola enum pipe pipe; 18818664281bSPaulo Zanoni 1882de032bf4SPaulo Zanoni if (serr_int & SERR_INT_POISON) 188300376ccfSWambui Karuga drm_err(&dev_priv->drm, "PCH poison interrupt\n"); 1884de032bf4SPaulo Zanoni 188545c1cd87SMika Kahola for_each_pipe(dev_priv, pipe) 188645c1cd87SMika Kahola if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) 188745c1cd87SMika Kahola intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); 18888664281bSPaulo Zanoni 18892939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int); 1890776ad806SJesse Barnes } 1891776ad806SJesse Barnes 189291d14251STvrtko Ursulin static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 189323e81d69SAdam Jackson { 1894d048a268SVille Syrjälä enum pipe pipe; 18956dbf30ceSVille Syrjälä u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 1896aaf5ec2eSSonika Jindal 18970398993bSVille Syrjälä ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 189891d131d2SDaniel Vetter 1899cfc33bf7SVille Syrjälä if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 1900cfc33bf7SVille Syrjälä int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 190123e81d69SAdam Jackson SDE_AUDIO_POWER_SHIFT_CPT); 190200376ccfSWambui Karuga drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n", 1903cfc33bf7SVille Syrjälä port_name(port)); 1904cfc33bf7SVille Syrjälä } 190523e81d69SAdam Jackson 190623e81d69SAdam Jackson if (pch_iir & SDE_AUX_MASK_CPT) 190791d14251STvrtko Ursulin dp_aux_irq_handler(dev_priv); 190823e81d69SAdam Jackson 190923e81d69SAdam Jackson if (pch_iir & SDE_GMBUS_CPT) 191091d14251STvrtko Ursulin gmbus_irq_handler(dev_priv); 191123e81d69SAdam Jackson 191223e81d69SAdam Jackson if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 191300376ccfSWambui Karuga drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n"); 191423e81d69SAdam Jackson 191523e81d69SAdam Jackson if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 191600376ccfSWambui Karuga drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n"); 191723e81d69SAdam Jackson 1918b8b65ccdSAnshuman Gupta if (pch_iir & SDE_FDI_MASK_CPT) { 1919055e393fSDamien Lespiau for_each_pipe(dev_priv, pipe) 192000376ccfSWambui Karuga drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", 192123e81d69SAdam Jackson pipe_name(pipe), 19222939eb06SJani Nikula intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); 1923b8b65ccdSAnshuman Gupta } 19248664281bSPaulo Zanoni 19258664281bSPaulo Zanoni if (pch_iir & SDE_ERROR_CPT) 192691d14251STvrtko Ursulin cpt_serr_int_handler(dev_priv); 192723e81d69SAdam Jackson } 192823e81d69SAdam Jackson 192958676af6SLucas De Marchi static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 193031604222SAnusha Srivatsa { 1931e76ab2cfSVille Syrjälä u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP; 1932e76ab2cfSVille Syrjälä u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP; 193331604222SAnusha Srivatsa u32 pin_mask = 0, long_mask = 0; 193431604222SAnusha Srivatsa 193531604222SAnusha Srivatsa if (ddi_hotplug_trigger) { 193631604222SAnusha Srivatsa u32 dig_hotplug_reg; 193731604222SAnusha Srivatsa 19382939eb06SJani Nikula dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI); 19392939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg); 194031604222SAnusha Srivatsa 194131604222SAnusha Srivatsa intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 19420398993bSVille Syrjälä ddi_hotplug_trigger, dig_hotplug_reg, 19430398993bSVille Syrjälä dev_priv->hotplug.pch_hpd, 194431604222SAnusha Srivatsa icp_ddi_port_hotplug_long_detect); 194531604222SAnusha Srivatsa } 194631604222SAnusha Srivatsa 194731604222SAnusha Srivatsa if (tc_hotplug_trigger) { 194831604222SAnusha Srivatsa u32 dig_hotplug_reg; 194931604222SAnusha Srivatsa 19502939eb06SJani Nikula dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC); 19512939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg); 195231604222SAnusha Srivatsa 195331604222SAnusha Srivatsa intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 19540398993bSVille Syrjälä tc_hotplug_trigger, dig_hotplug_reg, 19550398993bSVille Syrjälä dev_priv->hotplug.pch_hpd, 1956da51e4baSVille Syrjälä icp_tc_port_hotplug_long_detect); 195752dfdba0SLucas De Marchi } 195852dfdba0SLucas De Marchi 195952dfdba0SLucas De Marchi if (pin_mask) 196052dfdba0SLucas De Marchi intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 196152dfdba0SLucas De Marchi 196252dfdba0SLucas De Marchi if (pch_iir & SDE_GMBUS_ICP) 196352dfdba0SLucas De Marchi gmbus_irq_handler(dev_priv); 196452dfdba0SLucas De Marchi } 196552dfdba0SLucas De Marchi 196691d14251STvrtko Ursulin static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 19676dbf30ceSVille Syrjälä { 19686dbf30ceSVille Syrjälä u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & 19696dbf30ceSVille Syrjälä ~SDE_PORTE_HOTPLUG_SPT; 19706dbf30ceSVille Syrjälä u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; 19716dbf30ceSVille Syrjälä u32 pin_mask = 0, long_mask = 0; 19726dbf30ceSVille Syrjälä 19736dbf30ceSVille Syrjälä if (hotplug_trigger) { 19746dbf30ceSVille Syrjälä u32 dig_hotplug_reg; 19756dbf30ceSVille Syrjälä 19762939eb06SJani Nikula dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 19772939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); 19786dbf30ceSVille Syrjälä 1979cf53902fSRodrigo Vivi intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 19800398993bSVille Syrjälä hotplug_trigger, dig_hotplug_reg, 19810398993bSVille Syrjälä dev_priv->hotplug.pch_hpd, 198274c0b395SVille Syrjälä spt_port_hotplug_long_detect); 19836dbf30ceSVille Syrjälä } 19846dbf30ceSVille Syrjälä 19856dbf30ceSVille Syrjälä if (hotplug2_trigger) { 19866dbf30ceSVille Syrjälä u32 dig_hotplug_reg; 19876dbf30ceSVille Syrjälä 19882939eb06SJani Nikula dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2); 19892939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg); 19906dbf30ceSVille Syrjälä 1991cf53902fSRodrigo Vivi intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 19920398993bSVille Syrjälä hotplug2_trigger, dig_hotplug_reg, 19930398993bSVille Syrjälä dev_priv->hotplug.pch_hpd, 19946dbf30ceSVille Syrjälä spt_port_hotplug2_long_detect); 19956dbf30ceSVille Syrjälä } 19966dbf30ceSVille Syrjälä 19976dbf30ceSVille Syrjälä if (pin_mask) 199891d14251STvrtko Ursulin intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 19996dbf30ceSVille Syrjälä 20006dbf30ceSVille Syrjälä if (pch_iir & SDE_GMBUS_CPT) 200191d14251STvrtko Ursulin gmbus_irq_handler(dev_priv); 20026dbf30ceSVille Syrjälä } 20036dbf30ceSVille Syrjälä 200491d14251STvrtko Ursulin static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, 20050398993bSVille Syrjälä u32 hotplug_trigger) 2006c008bc6eSPaulo Zanoni { 2007e4ce95aaSVille Syrjälä u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 2008e4ce95aaSVille Syrjälä 20092939eb06SJani Nikula dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL); 20102939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); 2011e4ce95aaSVille Syrjälä 20120398993bSVille Syrjälä intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 20130398993bSVille Syrjälä hotplug_trigger, dig_hotplug_reg, 20140398993bSVille Syrjälä dev_priv->hotplug.hpd, 2015e4ce95aaSVille Syrjälä ilk_port_hotplug_long_detect); 201640e56410SVille Syrjälä 201791d14251STvrtko Ursulin intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 2018e4ce95aaSVille Syrjälä } 2019c008bc6eSPaulo Zanoni 202091d14251STvrtko Ursulin static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, 202191d14251STvrtko Ursulin u32 de_iir) 202240e56410SVille Syrjälä { 202340e56410SVille Syrjälä enum pipe pipe; 202440e56410SVille Syrjälä u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; 202540e56410SVille Syrjälä 202640e56410SVille Syrjälä if (hotplug_trigger) 20270398993bSVille Syrjälä ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 202840e56410SVille Syrjälä 2029c008bc6eSPaulo Zanoni if (de_iir & DE_AUX_CHANNEL_A) 203091d14251STvrtko Ursulin dp_aux_irq_handler(dev_priv); 2031c008bc6eSPaulo Zanoni 2032c008bc6eSPaulo Zanoni if (de_iir & DE_GSE) 203391d14251STvrtko Ursulin intel_opregion_asle_intr(dev_priv); 2034c008bc6eSPaulo Zanoni 2035c008bc6eSPaulo Zanoni if (de_iir & DE_POISON) 203600376ccfSWambui Karuga drm_err(&dev_priv->drm, "Poison interrupt\n"); 2037c008bc6eSPaulo Zanoni 2038055e393fSDamien Lespiau for_each_pipe(dev_priv, pipe) { 2039fd3a4024SDaniel Vetter if (de_iir & DE_PIPE_VBLANK(pipe)) 2040aca9310aSAnshuman Gupta intel_handle_vblank(dev_priv, pipe); 2041c008bc6eSPaulo Zanoni 204240da17c2SDaniel Vetter if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 20431f7247c0SDaniel Vetter intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 2044c008bc6eSPaulo Zanoni 204540da17c2SDaniel Vetter if (de_iir & DE_PIPE_CRC_DONE(pipe)) 204691d14251STvrtko Ursulin i9xx_pipe_crc_irq_handler(dev_priv, pipe); 2047c008bc6eSPaulo Zanoni } 2048c008bc6eSPaulo Zanoni 2049c008bc6eSPaulo Zanoni /* check event from PCH */ 2050c008bc6eSPaulo Zanoni if (de_iir & DE_PCH_EVENT) { 20512939eb06SJani Nikula u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 2052c008bc6eSPaulo Zanoni 205391d14251STvrtko Ursulin if (HAS_PCH_CPT(dev_priv)) 205491d14251STvrtko Ursulin cpt_irq_handler(dev_priv, pch_iir); 2055c008bc6eSPaulo Zanoni else 205691d14251STvrtko Ursulin ibx_irq_handler(dev_priv, pch_iir); 2057c008bc6eSPaulo Zanoni 2058c008bc6eSPaulo Zanoni /* should clear PCH hotplug event before clear CPU irq */ 20592939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); 2060c008bc6eSPaulo Zanoni } 2061c008bc6eSPaulo Zanoni 2062cf819effSLucas De Marchi if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT) 20633e7abf81SAndi Shyti gen5_rps_irq_handler(&dev_priv->gt.rps); 2064c008bc6eSPaulo Zanoni } 2065c008bc6eSPaulo Zanoni 206691d14251STvrtko Ursulin static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, 206791d14251STvrtko Ursulin u32 de_iir) 20689719fb98SPaulo Zanoni { 206907d27e20SDamien Lespiau enum pipe pipe; 207023bb4cb5SVille Syrjälä u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; 207123bb4cb5SVille Syrjälä 207240e56410SVille Syrjälä if (hotplug_trigger) 20730398993bSVille Syrjälä ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 20749719fb98SPaulo Zanoni 20759719fb98SPaulo Zanoni if (de_iir & DE_ERR_INT_IVB) 207691d14251STvrtko Ursulin ivb_err_int_handler(dev_priv); 20779719fb98SPaulo Zanoni 207854fd3149SDhinakaran Pandiyan if (de_iir & DE_EDP_PSR_INT_HSW) { 20792939eb06SJani Nikula u32 psr_iir = intel_uncore_read(&dev_priv->uncore, EDP_PSR_IIR); 208054fd3149SDhinakaran Pandiyan 208154fd3149SDhinakaran Pandiyan intel_psr_irq_handler(dev_priv, psr_iir); 20822939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, EDP_PSR_IIR, psr_iir); 208354fd3149SDhinakaran Pandiyan } 2084fc340442SDaniel Vetter 20859719fb98SPaulo Zanoni if (de_iir & DE_AUX_CHANNEL_A_IVB) 208691d14251STvrtko Ursulin dp_aux_irq_handler(dev_priv); 20879719fb98SPaulo Zanoni 20889719fb98SPaulo Zanoni if (de_iir & DE_GSE_IVB) 208991d14251STvrtko Ursulin intel_opregion_asle_intr(dev_priv); 20909719fb98SPaulo Zanoni 2091055e393fSDamien Lespiau for_each_pipe(dev_priv, pipe) { 209233ef04faSVille Syrjälä if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) 2093aca9310aSAnshuman Gupta intel_handle_vblank(dev_priv, pipe); 20949719fb98SPaulo Zanoni } 20959719fb98SPaulo Zanoni 20969719fb98SPaulo Zanoni /* check event from PCH */ 209791d14251STvrtko Ursulin if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { 20982939eb06SJani Nikula u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 20999719fb98SPaulo Zanoni 210091d14251STvrtko Ursulin cpt_irq_handler(dev_priv, pch_iir); 21019719fb98SPaulo Zanoni 21029719fb98SPaulo Zanoni /* clear PCH hotplug event before clear CPU irq */ 21032939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); 21049719fb98SPaulo Zanoni } 21059719fb98SPaulo Zanoni } 21069719fb98SPaulo Zanoni 210772c90f62SOscar Mateo /* 210872c90f62SOscar Mateo * To handle irqs with the minimum potential races with fresh interrupts, we: 210972c90f62SOscar Mateo * 1 - Disable Master Interrupt Control. 211072c90f62SOscar Mateo * 2 - Find the source(s) of the interrupt. 211172c90f62SOscar Mateo * 3 - Clear the Interrupt Identity bits (IIR). 211272c90f62SOscar Mateo * 4 - Process the interrupt(s) that had bits set in the IIRs. 211372c90f62SOscar Mateo * 5 - Re-enable Master Interrupt Control. 211472c90f62SOscar Mateo */ 21159eae5e27SLucas De Marchi static irqreturn_t ilk_irq_handler(int irq, void *arg) 2116b1f14ad0SJesse Barnes { 2117c48a798aSChris Wilson struct drm_i915_private *i915 = arg; 2118c48a798aSChris Wilson void __iomem * const regs = i915->uncore.regs; 2119f1af8fc1SPaulo Zanoni u32 de_iir, gt_iir, de_ier, sde_ier = 0; 21200e43406bSChris Wilson irqreturn_t ret = IRQ_NONE; 2121b1f14ad0SJesse Barnes 2122c48a798aSChris Wilson if (unlikely(!intel_irqs_enabled(i915))) 21232dd2a883SImre Deak return IRQ_NONE; 21242dd2a883SImre Deak 21251f814dacSImre Deak /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 2126c48a798aSChris Wilson disable_rpm_wakeref_asserts(&i915->runtime_pm); 21271f814dacSImre Deak 2128b1f14ad0SJesse Barnes /* disable master interrupt before clearing iir */ 2129c48a798aSChris Wilson de_ier = raw_reg_read(regs, DEIER); 2130c48a798aSChris Wilson raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 21310e43406bSChris Wilson 213244498aeaSPaulo Zanoni /* Disable south interrupts. We'll only write to SDEIIR once, so further 213344498aeaSPaulo Zanoni * interrupts will will be stored on its back queue, and then we'll be 213444498aeaSPaulo Zanoni * able to process them after we restore SDEIER (as soon as we restore 213544498aeaSPaulo Zanoni * it, we'll get an interrupt if SDEIIR still has something to process 213644498aeaSPaulo Zanoni * due to its back queue). */ 2137c48a798aSChris Wilson if (!HAS_PCH_NOP(i915)) { 2138c48a798aSChris Wilson sde_ier = raw_reg_read(regs, SDEIER); 2139c48a798aSChris Wilson raw_reg_write(regs, SDEIER, 0); 2140ab5c608bSBen Widawsky } 214144498aeaSPaulo Zanoni 214272c90f62SOscar Mateo /* Find, clear, then process each source of interrupt */ 214372c90f62SOscar Mateo 2144c48a798aSChris Wilson gt_iir = raw_reg_read(regs, GTIIR); 21450e43406bSChris Wilson if (gt_iir) { 2146c48a798aSChris Wilson raw_reg_write(regs, GTIIR, gt_iir); 2147c48a798aSChris Wilson if (INTEL_GEN(i915) >= 6) 2148c48a798aSChris Wilson gen6_gt_irq_handler(&i915->gt, gt_iir); 2149d8fc8a47SPaulo Zanoni else 2150c48a798aSChris Wilson gen5_gt_irq_handler(&i915->gt, gt_iir); 2151c48a798aSChris Wilson ret = IRQ_HANDLED; 21520e43406bSChris Wilson } 2153b1f14ad0SJesse Barnes 2154c48a798aSChris Wilson de_iir = raw_reg_read(regs, DEIIR); 21550e43406bSChris Wilson if (de_iir) { 2156c48a798aSChris Wilson raw_reg_write(regs, DEIIR, de_iir); 2157c48a798aSChris Wilson if (INTEL_GEN(i915) >= 7) 2158c48a798aSChris Wilson ivb_display_irq_handler(i915, de_iir); 2159f1af8fc1SPaulo Zanoni else 2160c48a798aSChris Wilson ilk_display_irq_handler(i915, de_iir); 21610e43406bSChris Wilson ret = IRQ_HANDLED; 2162c48a798aSChris Wilson } 2163c48a798aSChris Wilson 2164c48a798aSChris Wilson if (INTEL_GEN(i915) >= 6) { 2165c48a798aSChris Wilson u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); 2166c48a798aSChris Wilson if (pm_iir) { 2167c48a798aSChris Wilson raw_reg_write(regs, GEN6_PMIIR, pm_iir); 2168c48a798aSChris Wilson gen6_rps_irq_handler(&i915->gt.rps, pm_iir); 2169c48a798aSChris Wilson ret = IRQ_HANDLED; 21700e43406bSChris Wilson } 2171f1af8fc1SPaulo Zanoni } 2172b1f14ad0SJesse Barnes 2173c48a798aSChris Wilson raw_reg_write(regs, DEIER, de_ier); 2174c48a798aSChris Wilson if (sde_ier) 2175c48a798aSChris Wilson raw_reg_write(regs, SDEIER, sde_ier); 2176b1f14ad0SJesse Barnes 21779c6508b9SThomas Gleixner pmu_irq_stats(i915, ret); 21789c6508b9SThomas Gleixner 21791f814dacSImre Deak /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 2180c48a798aSChris Wilson enable_rpm_wakeref_asserts(&i915->runtime_pm); 21811f814dacSImre Deak 2182b1f14ad0SJesse Barnes return ret; 2183b1f14ad0SJesse Barnes } 2184b1f14ad0SJesse Barnes 218591d14251STvrtko Ursulin static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, 21860398993bSVille Syrjälä u32 hotplug_trigger) 2187d04a492dSShashank Sharma { 2188cebd87a0SVille Syrjälä u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 2189d04a492dSShashank Sharma 21902939eb06SJani Nikula dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 21912939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); 2192d04a492dSShashank Sharma 21930398993bSVille Syrjälä intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 21940398993bSVille Syrjälä hotplug_trigger, dig_hotplug_reg, 21950398993bSVille Syrjälä dev_priv->hotplug.hpd, 2196cebd87a0SVille Syrjälä bxt_port_hotplug_long_detect); 219740e56410SVille Syrjälä 219891d14251STvrtko Ursulin intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 2199d04a492dSShashank Sharma } 2200d04a492dSShashank Sharma 2201121e758eSDhinakaran Pandiyan static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) 2202121e758eSDhinakaran Pandiyan { 2203121e758eSDhinakaran Pandiyan u32 pin_mask = 0, long_mask = 0; 2204b796b971SDhinakaran Pandiyan u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; 2205b796b971SDhinakaran Pandiyan u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; 2206121e758eSDhinakaran Pandiyan 2207121e758eSDhinakaran Pandiyan if (trigger_tc) { 2208b796b971SDhinakaran Pandiyan u32 dig_hotplug_reg; 2209b796b971SDhinakaran Pandiyan 22102939eb06SJani Nikula dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL); 22112939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg); 2212121e758eSDhinakaran Pandiyan 22130398993bSVille Syrjälä intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 22140398993bSVille Syrjälä trigger_tc, dig_hotplug_reg, 22150398993bSVille Syrjälä dev_priv->hotplug.hpd, 2216da51e4baSVille Syrjälä gen11_port_hotplug_long_detect); 2217121e758eSDhinakaran Pandiyan } 2218b796b971SDhinakaran Pandiyan 2219b796b971SDhinakaran Pandiyan if (trigger_tbt) { 2220b796b971SDhinakaran Pandiyan u32 dig_hotplug_reg; 2221b796b971SDhinakaran Pandiyan 22222939eb06SJani Nikula dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL); 22232939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg); 2224b796b971SDhinakaran Pandiyan 22250398993bSVille Syrjälä intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 22260398993bSVille Syrjälä trigger_tbt, dig_hotplug_reg, 22270398993bSVille Syrjälä dev_priv->hotplug.hpd, 2228da51e4baSVille Syrjälä gen11_port_hotplug_long_detect); 2229b796b971SDhinakaran Pandiyan } 2230b796b971SDhinakaran Pandiyan 2231b796b971SDhinakaran Pandiyan if (pin_mask) 2232b796b971SDhinakaran Pandiyan intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); 2233b796b971SDhinakaran Pandiyan else 223400376ccfSWambui Karuga drm_err(&dev_priv->drm, 223500376ccfSWambui Karuga "Unexpected DE HPD interrupt 0x%08x\n", iir); 2236121e758eSDhinakaran Pandiyan } 2237121e758eSDhinakaran Pandiyan 22389d17210fSLucas De Marchi static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) 22399d17210fSLucas De Marchi { 224055523360SLucas De Marchi u32 mask; 22419d17210fSLucas De Marchi 224255523360SLucas De Marchi if (INTEL_GEN(dev_priv) >= 12) 224355523360SLucas De Marchi return TGL_DE_PORT_AUX_DDIA | 224455523360SLucas De Marchi TGL_DE_PORT_AUX_DDIB | 2245e5df52dcSMatt Roper TGL_DE_PORT_AUX_DDIC | 2246e5df52dcSMatt Roper TGL_DE_PORT_AUX_USBC1 | 2247e5df52dcSMatt Roper TGL_DE_PORT_AUX_USBC2 | 2248e5df52dcSMatt Roper TGL_DE_PORT_AUX_USBC3 | 2249e5df52dcSMatt Roper TGL_DE_PORT_AUX_USBC4 | 2250e5df52dcSMatt Roper TGL_DE_PORT_AUX_USBC5 | 2251e5df52dcSMatt Roper TGL_DE_PORT_AUX_USBC6; 2252e5df52dcSMatt Roper 225355523360SLucas De Marchi 225455523360SLucas De Marchi mask = GEN8_AUX_CHANNEL_A; 22559d17210fSLucas De Marchi if (INTEL_GEN(dev_priv) >= 9) 22569d17210fSLucas De Marchi mask |= GEN9_AUX_CHANNEL_B | 22579d17210fSLucas De Marchi GEN9_AUX_CHANNEL_C | 22589d17210fSLucas De Marchi GEN9_AUX_CHANNEL_D; 22599d17210fSLucas De Marchi 226055523360SLucas De Marchi if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11)) 22619d17210fSLucas De Marchi mask |= CNL_AUX_CHANNEL_F; 22629d17210fSLucas De Marchi 226355523360SLucas De Marchi if (IS_GEN(dev_priv, 11)) 226455523360SLucas De Marchi mask |= ICL_AUX_CHANNEL_E; 22659d17210fSLucas De Marchi 22669d17210fSLucas De Marchi return mask; 22679d17210fSLucas De Marchi } 22689d17210fSLucas De Marchi 22695270130dSVille Syrjälä static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) 22705270130dSVille Syrjälä { 227199e2d8bcSMatt Roper if (IS_ROCKETLAKE(dev_priv)) 227299e2d8bcSMatt Roper return RKL_DE_PIPE_IRQ_FAULT_ERRORS; 227399e2d8bcSMatt Roper else if (INTEL_GEN(dev_priv) >= 11) 2274d506a65dSMatt Roper return GEN11_DE_PIPE_IRQ_FAULT_ERRORS; 2275d506a65dSMatt Roper else if (INTEL_GEN(dev_priv) >= 9) 22765270130dSVille Syrjälä return GEN9_DE_PIPE_IRQ_FAULT_ERRORS; 22775270130dSVille Syrjälä else 22785270130dSVille Syrjälä return GEN8_DE_PIPE_IRQ_FAULT_ERRORS; 22795270130dSVille Syrjälä } 22805270130dSVille Syrjälä 228146c63d24SJosé Roberto de Souza static void 228246c63d24SJosé Roberto de Souza gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) 2283abd58f01SBen Widawsky { 2284e04f7eceSVille Syrjälä bool found = false; 2285e04f7eceSVille Syrjälä 2286e04f7eceSVille Syrjälä if (iir & GEN8_DE_MISC_GSE) { 228791d14251STvrtko Ursulin intel_opregion_asle_intr(dev_priv); 2288e04f7eceSVille Syrjälä found = true; 2289e04f7eceSVille Syrjälä } 2290e04f7eceSVille Syrjälä 2291e04f7eceSVille Syrjälä if (iir & GEN8_DE_EDP_PSR) { 22928241cfbeSJosé Roberto de Souza u32 psr_iir; 22938241cfbeSJosé Roberto de Souza i915_reg_t iir_reg; 22948241cfbeSJosé Roberto de Souza 22958241cfbeSJosé Roberto de Souza if (INTEL_GEN(dev_priv) >= 12) 22968241cfbeSJosé Roberto de Souza iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder); 22978241cfbeSJosé Roberto de Souza else 22988241cfbeSJosé Roberto de Souza iir_reg = EDP_PSR_IIR; 22998241cfbeSJosé Roberto de Souza 23002939eb06SJani Nikula psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg); 23012939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir); 23028241cfbeSJosé Roberto de Souza 23038241cfbeSJosé Roberto de Souza if (psr_iir) 23048241cfbeSJosé Roberto de Souza found = true; 230554fd3149SDhinakaran Pandiyan 230654fd3149SDhinakaran Pandiyan intel_psr_irq_handler(dev_priv, psr_iir); 2307e04f7eceSVille Syrjälä } 2308e04f7eceSVille Syrjälä 2309e04f7eceSVille Syrjälä if (!found) 231000376ccfSWambui Karuga drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n"); 2311abd58f01SBen Widawsky } 231246c63d24SJosé Roberto de Souza 231300acb329SVandita Kulkarni static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, 231400acb329SVandita Kulkarni u32 te_trigger) 231500acb329SVandita Kulkarni { 231600acb329SVandita Kulkarni enum pipe pipe = INVALID_PIPE; 231700acb329SVandita Kulkarni enum transcoder dsi_trans; 231800acb329SVandita Kulkarni enum port port; 231900acb329SVandita Kulkarni u32 val, tmp; 232000acb329SVandita Kulkarni 232100acb329SVandita Kulkarni /* 232200acb329SVandita Kulkarni * Incase of dual link, TE comes from DSI_1 232300acb329SVandita Kulkarni * this is to check if dual link is enabled 232400acb329SVandita Kulkarni */ 23252939eb06SJani Nikula val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); 232600acb329SVandita Kulkarni val &= PORT_SYNC_MODE_ENABLE; 232700acb329SVandita Kulkarni 232800acb329SVandita Kulkarni /* 232900acb329SVandita Kulkarni * if dual link is enabled, then read DSI_0 233000acb329SVandita Kulkarni * transcoder registers 233100acb329SVandita Kulkarni */ 233200acb329SVandita Kulkarni port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ? 233300acb329SVandita Kulkarni PORT_A : PORT_B; 233400acb329SVandita Kulkarni dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; 233500acb329SVandita Kulkarni 233600acb329SVandita Kulkarni /* Check if DSI configured in command mode */ 23372939eb06SJani Nikula val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans)); 233800acb329SVandita Kulkarni val = val & OP_MODE_MASK; 233900acb329SVandita Kulkarni 234000acb329SVandita Kulkarni if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) { 234100acb329SVandita Kulkarni drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n"); 234200acb329SVandita Kulkarni return; 234300acb329SVandita Kulkarni } 234400acb329SVandita Kulkarni 234500acb329SVandita Kulkarni /* Get PIPE for handling VBLANK event */ 23462939eb06SJani Nikula val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans)); 234700acb329SVandita Kulkarni switch (val & TRANS_DDI_EDP_INPUT_MASK) { 234800acb329SVandita Kulkarni case TRANS_DDI_EDP_INPUT_A_ON: 234900acb329SVandita Kulkarni pipe = PIPE_A; 235000acb329SVandita Kulkarni break; 235100acb329SVandita Kulkarni case TRANS_DDI_EDP_INPUT_B_ONOFF: 235200acb329SVandita Kulkarni pipe = PIPE_B; 235300acb329SVandita Kulkarni break; 235400acb329SVandita Kulkarni case TRANS_DDI_EDP_INPUT_C_ONOFF: 235500acb329SVandita Kulkarni pipe = PIPE_C; 235600acb329SVandita Kulkarni break; 235700acb329SVandita Kulkarni default: 235800acb329SVandita Kulkarni drm_err(&dev_priv->drm, "Invalid PIPE\n"); 235900acb329SVandita Kulkarni return; 236000acb329SVandita Kulkarni } 236100acb329SVandita Kulkarni 236200acb329SVandita Kulkarni intel_handle_vblank(dev_priv, pipe); 236300acb329SVandita Kulkarni 236400acb329SVandita Kulkarni /* clear TE in dsi IIR */ 236500acb329SVandita Kulkarni port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; 23662939eb06SJani Nikula tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port)); 23672939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp); 236800acb329SVandita Kulkarni } 236900acb329SVandita Kulkarni 237046c63d24SJosé Roberto de Souza static irqreturn_t 237146c63d24SJosé Roberto de Souza gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) 237246c63d24SJosé Roberto de Souza { 237346c63d24SJosé Roberto de Souza irqreturn_t ret = IRQ_NONE; 237446c63d24SJosé Roberto de Souza u32 iir; 237546c63d24SJosé Roberto de Souza enum pipe pipe; 237646c63d24SJosé Roberto de Souza 237746c63d24SJosé Roberto de Souza if (master_ctl & GEN8_DE_MISC_IRQ) { 23782939eb06SJani Nikula iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); 237946c63d24SJosé Roberto de Souza if (iir) { 23802939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir); 238146c63d24SJosé Roberto de Souza ret = IRQ_HANDLED; 238246c63d24SJosé Roberto de Souza gen8_de_misc_irq_handler(dev_priv, iir); 238346c63d24SJosé Roberto de Souza } else { 238400376ccfSWambui Karuga drm_err(&dev_priv->drm, 238500376ccfSWambui Karuga "The master control interrupt lied (DE MISC)!\n"); 2386abd58f01SBen Widawsky } 238746c63d24SJosé Roberto de Souza } 2388abd58f01SBen Widawsky 2389121e758eSDhinakaran Pandiyan if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { 23902939eb06SJani Nikula iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR); 2391121e758eSDhinakaran Pandiyan if (iir) { 23922939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir); 2393121e758eSDhinakaran Pandiyan ret = IRQ_HANDLED; 2394121e758eSDhinakaran Pandiyan gen11_hpd_irq_handler(dev_priv, iir); 2395121e758eSDhinakaran Pandiyan } else { 239600376ccfSWambui Karuga drm_err(&dev_priv->drm, 239700376ccfSWambui Karuga "The master control interrupt lied, (DE HPD)!\n"); 2398121e758eSDhinakaran Pandiyan } 2399121e758eSDhinakaran Pandiyan } 2400121e758eSDhinakaran Pandiyan 24016d766f02SDaniel Vetter if (master_ctl & GEN8_DE_PORT_IRQ) { 24022939eb06SJani Nikula iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR); 2403e32192e1STvrtko Ursulin if (iir) { 2404d04a492dSShashank Sharma bool found = false; 2405cebd87a0SVille Syrjälä 24062939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir); 24076d766f02SDaniel Vetter ret = IRQ_HANDLED; 240888e04703SJesse Barnes 24099d17210fSLucas De Marchi if (iir & gen8_de_port_aux_mask(dev_priv)) { 241091d14251STvrtko Ursulin dp_aux_irq_handler(dev_priv); 2411d04a492dSShashank Sharma found = true; 2412d04a492dSShashank Sharma } 2413d04a492dSShashank Sharma 2414cc3f90f0SAnder Conselvan de Oliveira if (IS_GEN9_LP(dev_priv)) { 24159a55a620SVille Syrjälä u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK; 24169a55a620SVille Syrjälä 24179a55a620SVille Syrjälä if (hotplug_trigger) { 24189a55a620SVille Syrjälä bxt_hpd_irq_handler(dev_priv, hotplug_trigger); 2419d04a492dSShashank Sharma found = true; 2420d04a492dSShashank Sharma } 2421e32192e1STvrtko Ursulin } else if (IS_BROADWELL(dev_priv)) { 24229a55a620SVille Syrjälä u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK; 24239a55a620SVille Syrjälä 24249a55a620SVille Syrjälä if (hotplug_trigger) { 24259a55a620SVille Syrjälä ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 2426e32192e1STvrtko Ursulin found = true; 2427e32192e1STvrtko Ursulin } 2428e32192e1STvrtko Ursulin } 2429d04a492dSShashank Sharma 2430cc3f90f0SAnder Conselvan de Oliveira if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { 243191d14251STvrtko Ursulin gmbus_irq_handler(dev_priv); 24329e63743eSShashank Sharma found = true; 24339e63743eSShashank Sharma } 24349e63743eSShashank Sharma 243500acb329SVandita Kulkarni if (INTEL_GEN(dev_priv) >= 11) { 24369a55a620SVille Syrjälä u32 te_trigger = iir & (DSI0_TE | DSI1_TE); 24379a55a620SVille Syrjälä 24389a55a620SVille Syrjälä if (te_trigger) { 24399a55a620SVille Syrjälä gen11_dsi_te_interrupt_handler(dev_priv, te_trigger); 244000acb329SVandita Kulkarni found = true; 244100acb329SVandita Kulkarni } 244200acb329SVandita Kulkarni } 244300acb329SVandita Kulkarni 2444d04a492dSShashank Sharma if (!found) 244500376ccfSWambui Karuga drm_err(&dev_priv->drm, 244600376ccfSWambui Karuga "Unexpected DE Port interrupt\n"); 24476d766f02SDaniel Vetter } 244838cc46d7SOscar Mateo else 244900376ccfSWambui Karuga drm_err(&dev_priv->drm, 245000376ccfSWambui Karuga "The master control interrupt lied (DE PORT)!\n"); 24516d766f02SDaniel Vetter } 24526d766f02SDaniel Vetter 2453055e393fSDamien Lespiau for_each_pipe(dev_priv, pipe) { 2454fd3a4024SDaniel Vetter u32 fault_errors; 2455abd58f01SBen Widawsky 2456c42664ccSDaniel Vetter if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 2457c42664ccSDaniel Vetter continue; 2458c42664ccSDaniel Vetter 24592939eb06SJani Nikula iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); 2460e32192e1STvrtko Ursulin if (!iir) { 246100376ccfSWambui Karuga drm_err(&dev_priv->drm, 246200376ccfSWambui Karuga "The master control interrupt lied (DE PIPE)!\n"); 2463e32192e1STvrtko Ursulin continue; 2464e32192e1STvrtko Ursulin } 2465770de83dSDamien Lespiau 2466e32192e1STvrtko Ursulin ret = IRQ_HANDLED; 24672939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); 2468e32192e1STvrtko Ursulin 2469fd3a4024SDaniel Vetter if (iir & GEN8_PIPE_VBLANK) 2470aca9310aSAnshuman Gupta intel_handle_vblank(dev_priv, pipe); 2471abd58f01SBen Widawsky 24721288f9b0SKarthik B S if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) 24731288f9b0SKarthik B S flip_done_handler(dev_priv, pipe); 24741288f9b0SKarthik B S 2475e32192e1STvrtko Ursulin if (iir & GEN8_PIPE_CDCLK_CRC_DONE) 247691d14251STvrtko Ursulin hsw_pipe_crc_irq_handler(dev_priv, pipe); 24770fbe7870SDaniel Vetter 2478e32192e1STvrtko Ursulin if (iir & GEN8_PIPE_FIFO_UNDERRUN) 2479e32192e1STvrtko Ursulin intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); 248038d83c96SDaniel Vetter 24815270130dSVille Syrjälä fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); 2482770de83dSDamien Lespiau if (fault_errors) 248300376ccfSWambui Karuga drm_err(&dev_priv->drm, 248400376ccfSWambui Karuga "Fault errors on pipe %c: 0x%08x\n", 248530100f2bSDaniel Vetter pipe_name(pipe), 2486e32192e1STvrtko Ursulin fault_errors); 2487abd58f01SBen Widawsky } 2488abd58f01SBen Widawsky 248991d14251STvrtko Ursulin if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && 2490266ea3d9SShashank Sharma master_ctl & GEN8_DE_PCH_IRQ) { 249192d03a80SDaniel Vetter /* 249292d03a80SDaniel Vetter * FIXME(BDW): Assume for now that the new interrupt handling 249392d03a80SDaniel Vetter * scheme also closed the SDE interrupt handling race we've seen 249492d03a80SDaniel Vetter * on older pch-split platforms. But this needs testing. 249592d03a80SDaniel Vetter */ 24962939eb06SJani Nikula iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); 2497e32192e1STvrtko Ursulin if (iir) { 24982939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SDEIIR, iir); 249992d03a80SDaniel Vetter ret = IRQ_HANDLED; 25006dbf30ceSVille Syrjälä 250158676af6SLucas De Marchi if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 250258676af6SLucas De Marchi icp_irq_handler(dev_priv, iir); 2503c6c30b91SRodrigo Vivi else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) 250491d14251STvrtko Ursulin spt_irq_handler(dev_priv, iir); 25056dbf30ceSVille Syrjälä else 250691d14251STvrtko Ursulin cpt_irq_handler(dev_priv, iir); 25072dfb0b81SJani Nikula } else { 25082dfb0b81SJani Nikula /* 25092dfb0b81SJani Nikula * Like on previous PCH there seems to be something 25102dfb0b81SJani Nikula * fishy going on with forwarding PCH interrupts. 25112dfb0b81SJani Nikula */ 251200376ccfSWambui Karuga drm_dbg(&dev_priv->drm, 251300376ccfSWambui Karuga "The master control interrupt lied (SDE)!\n"); 25142dfb0b81SJani Nikula } 251592d03a80SDaniel Vetter } 251692d03a80SDaniel Vetter 2517f11a0f46STvrtko Ursulin return ret; 2518f11a0f46STvrtko Ursulin } 2519f11a0f46STvrtko Ursulin 25204376b9c9SMika Kuoppala static inline u32 gen8_master_intr_disable(void __iomem * const regs) 25214376b9c9SMika Kuoppala { 25224376b9c9SMika Kuoppala raw_reg_write(regs, GEN8_MASTER_IRQ, 0); 25234376b9c9SMika Kuoppala 25244376b9c9SMika Kuoppala /* 25254376b9c9SMika Kuoppala * Now with master disabled, get a sample of level indications 25264376b9c9SMika Kuoppala * for this interrupt. Indications will be cleared on related acks. 25274376b9c9SMika Kuoppala * New indications can and will light up during processing, 25284376b9c9SMika Kuoppala * and will generate new interrupt after enabling master. 25294376b9c9SMika Kuoppala */ 25304376b9c9SMika Kuoppala return raw_reg_read(regs, GEN8_MASTER_IRQ); 25314376b9c9SMika Kuoppala } 25324376b9c9SMika Kuoppala 25334376b9c9SMika Kuoppala static inline void gen8_master_intr_enable(void __iomem * const regs) 25344376b9c9SMika Kuoppala { 25354376b9c9SMika Kuoppala raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 25364376b9c9SMika Kuoppala } 25374376b9c9SMika Kuoppala 2538f11a0f46STvrtko Ursulin static irqreturn_t gen8_irq_handler(int irq, void *arg) 2539f11a0f46STvrtko Ursulin { 2540b318b824SVille Syrjälä struct drm_i915_private *dev_priv = arg; 254125286aacSDaniele Ceraolo Spurio void __iomem * const regs = dev_priv->uncore.regs; 2542f11a0f46STvrtko Ursulin u32 master_ctl; 2543f11a0f46STvrtko Ursulin 2544f11a0f46STvrtko Ursulin if (!intel_irqs_enabled(dev_priv)) 2545f11a0f46STvrtko Ursulin return IRQ_NONE; 2546f11a0f46STvrtko Ursulin 25474376b9c9SMika Kuoppala master_ctl = gen8_master_intr_disable(regs); 25484376b9c9SMika Kuoppala if (!master_ctl) { 25494376b9c9SMika Kuoppala gen8_master_intr_enable(regs); 2550f11a0f46STvrtko Ursulin return IRQ_NONE; 25514376b9c9SMika Kuoppala } 2552f11a0f46STvrtko Ursulin 25536cc32f15SChris Wilson /* Find, queue (onto bottom-halves), then clear each source */ 25546cc32f15SChris Wilson gen8_gt_irq_handler(&dev_priv->gt, master_ctl); 2555f0fd96f5SChris Wilson 2556f0fd96f5SChris Wilson /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 2557f0fd96f5SChris Wilson if (master_ctl & ~GEN8_GT_IRQS) { 25589102650fSDaniele Ceraolo Spurio disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 255955ef72f2SChris Wilson gen8_de_irq_handler(dev_priv, master_ctl); 25609102650fSDaniele Ceraolo Spurio enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 2561f0fd96f5SChris Wilson } 2562f11a0f46STvrtko Ursulin 25634376b9c9SMika Kuoppala gen8_master_intr_enable(regs); 2564abd58f01SBen Widawsky 25659c6508b9SThomas Gleixner pmu_irq_stats(dev_priv, IRQ_HANDLED); 25669c6508b9SThomas Gleixner 256755ef72f2SChris Wilson return IRQ_HANDLED; 2568abd58f01SBen Widawsky } 2569abd58f01SBen Widawsky 257051951ae7SMika Kuoppala static u32 25719b77011eSTvrtko Ursulin gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl) 2572df0d28c1SDhinakaran Pandiyan { 25739b77011eSTvrtko Ursulin void __iomem * const regs = gt->uncore->regs; 25747a909383SChris Wilson u32 iir; 2575df0d28c1SDhinakaran Pandiyan 2576df0d28c1SDhinakaran Pandiyan if (!(master_ctl & GEN11_GU_MISC_IRQ)) 25777a909383SChris Wilson return 0; 2578df0d28c1SDhinakaran Pandiyan 25797a909383SChris Wilson iir = raw_reg_read(regs, GEN11_GU_MISC_IIR); 25807a909383SChris Wilson if (likely(iir)) 25817a909383SChris Wilson raw_reg_write(regs, GEN11_GU_MISC_IIR, iir); 25827a909383SChris Wilson 25837a909383SChris Wilson return iir; 2584df0d28c1SDhinakaran Pandiyan } 2585df0d28c1SDhinakaran Pandiyan 2586df0d28c1SDhinakaran Pandiyan static void 25879b77011eSTvrtko Ursulin gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir) 2588df0d28c1SDhinakaran Pandiyan { 2589df0d28c1SDhinakaran Pandiyan if (iir & GEN11_GU_MISC_GSE) 25909b77011eSTvrtko Ursulin intel_opregion_asle_intr(gt->i915); 2591df0d28c1SDhinakaran Pandiyan } 2592df0d28c1SDhinakaran Pandiyan 259381067b71SMika Kuoppala static inline u32 gen11_master_intr_disable(void __iomem * const regs) 259481067b71SMika Kuoppala { 259581067b71SMika Kuoppala raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0); 259681067b71SMika Kuoppala 259781067b71SMika Kuoppala /* 259881067b71SMika Kuoppala * Now with master disabled, get a sample of level indications 259981067b71SMika Kuoppala * for this interrupt. Indications will be cleared on related acks. 260081067b71SMika Kuoppala * New indications can and will light up during processing, 260181067b71SMika Kuoppala * and will generate new interrupt after enabling master. 260281067b71SMika Kuoppala */ 260381067b71SMika Kuoppala return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); 260481067b71SMika Kuoppala } 260581067b71SMika Kuoppala 260681067b71SMika Kuoppala static inline void gen11_master_intr_enable(void __iomem * const regs) 260781067b71SMika Kuoppala { 260881067b71SMika Kuoppala raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); 260981067b71SMika Kuoppala } 261081067b71SMika Kuoppala 2611a3265d85SMatt Roper static void 2612a3265d85SMatt Roper gen11_display_irq_handler(struct drm_i915_private *i915) 2613a3265d85SMatt Roper { 2614a3265d85SMatt Roper void __iomem * const regs = i915->uncore.regs; 2615a3265d85SMatt Roper const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL); 2616a3265d85SMatt Roper 2617a3265d85SMatt Roper disable_rpm_wakeref_asserts(&i915->runtime_pm); 2618a3265d85SMatt Roper /* 2619a3265d85SMatt Roper * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ 2620a3265d85SMatt Roper * for the display related bits. 2621a3265d85SMatt Roper */ 2622a3265d85SMatt Roper raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0); 2623a3265d85SMatt Roper gen8_de_irq_handler(i915, disp_ctl); 2624a3265d85SMatt Roper raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 2625a3265d85SMatt Roper GEN11_DISPLAY_IRQ_ENABLE); 2626a3265d85SMatt Roper 2627a3265d85SMatt Roper enable_rpm_wakeref_asserts(&i915->runtime_pm); 2628a3265d85SMatt Roper } 2629a3265d85SMatt Roper 26307be8782aSLucas De Marchi static __always_inline irqreturn_t 26317be8782aSLucas De Marchi __gen11_irq_handler(struct drm_i915_private * const i915, 26327be8782aSLucas De Marchi u32 (*intr_disable)(void __iomem * const regs), 26337be8782aSLucas De Marchi void (*intr_enable)(void __iomem * const regs)) 263451951ae7SMika Kuoppala { 263525286aacSDaniele Ceraolo Spurio void __iomem * const regs = i915->uncore.regs; 26369b77011eSTvrtko Ursulin struct intel_gt *gt = &i915->gt; 263751951ae7SMika Kuoppala u32 master_ctl; 2638df0d28c1SDhinakaran Pandiyan u32 gu_misc_iir; 263951951ae7SMika Kuoppala 264051951ae7SMika Kuoppala if (!intel_irqs_enabled(i915)) 264151951ae7SMika Kuoppala return IRQ_NONE; 264251951ae7SMika Kuoppala 26437be8782aSLucas De Marchi master_ctl = intr_disable(regs); 264481067b71SMika Kuoppala if (!master_ctl) { 26457be8782aSLucas De Marchi intr_enable(regs); 264651951ae7SMika Kuoppala return IRQ_NONE; 264781067b71SMika Kuoppala } 264851951ae7SMika Kuoppala 26496cc32f15SChris Wilson /* Find, queue (onto bottom-halves), then clear each source */ 26509b77011eSTvrtko Ursulin gen11_gt_irq_handler(gt, master_ctl); 265151951ae7SMika Kuoppala 265251951ae7SMika Kuoppala /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 2653a3265d85SMatt Roper if (master_ctl & GEN11_DISPLAY_IRQ) 2654a3265d85SMatt Roper gen11_display_irq_handler(i915); 265551951ae7SMika Kuoppala 26569b77011eSTvrtko Ursulin gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); 2657df0d28c1SDhinakaran Pandiyan 26587be8782aSLucas De Marchi intr_enable(regs); 265951951ae7SMika Kuoppala 26609b77011eSTvrtko Ursulin gen11_gu_misc_irq_handler(gt, gu_misc_iir); 2661df0d28c1SDhinakaran Pandiyan 26629c6508b9SThomas Gleixner pmu_irq_stats(i915, IRQ_HANDLED); 26639c6508b9SThomas Gleixner 266451951ae7SMika Kuoppala return IRQ_HANDLED; 266551951ae7SMika Kuoppala } 266651951ae7SMika Kuoppala 26677be8782aSLucas De Marchi static irqreturn_t gen11_irq_handler(int irq, void *arg) 26687be8782aSLucas De Marchi { 26697be8782aSLucas De Marchi return __gen11_irq_handler(arg, 26707be8782aSLucas De Marchi gen11_master_intr_disable, 26717be8782aSLucas De Marchi gen11_master_intr_enable); 26727be8782aSLucas De Marchi } 26737be8782aSLucas De Marchi 267497b492f5SLucas De Marchi static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs) 267597b492f5SLucas De Marchi { 267697b492f5SLucas De Marchi u32 val; 267797b492f5SLucas De Marchi 267897b492f5SLucas De Marchi /* First disable interrupts */ 267997b492f5SLucas De Marchi raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0); 268097b492f5SLucas De Marchi 268197b492f5SLucas De Marchi /* Get the indication levels and ack the master unit */ 268297b492f5SLucas De Marchi val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR); 268397b492f5SLucas De Marchi if (unlikely(!val)) 268497b492f5SLucas De Marchi return 0; 268597b492f5SLucas De Marchi 268697b492f5SLucas De Marchi raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val); 268797b492f5SLucas De Marchi 268897b492f5SLucas De Marchi /* 268997b492f5SLucas De Marchi * Now with master disabled, get a sample of level indications 269097b492f5SLucas De Marchi * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ 269197b492f5SLucas De Marchi * out as this bit doesn't exist anymore for DG1 269297b492f5SLucas De Marchi */ 269397b492f5SLucas De Marchi val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ; 269497b492f5SLucas De Marchi if (unlikely(!val)) 269597b492f5SLucas De Marchi return 0; 269697b492f5SLucas De Marchi 269797b492f5SLucas De Marchi raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val); 269897b492f5SLucas De Marchi 269997b492f5SLucas De Marchi return val; 270097b492f5SLucas De Marchi } 270197b492f5SLucas De Marchi 270297b492f5SLucas De Marchi static inline void dg1_master_intr_enable(void __iomem * const regs) 270397b492f5SLucas De Marchi { 270497b492f5SLucas De Marchi raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ); 270597b492f5SLucas De Marchi } 270697b492f5SLucas De Marchi 270797b492f5SLucas De Marchi static irqreturn_t dg1_irq_handler(int irq, void *arg) 270897b492f5SLucas De Marchi { 270997b492f5SLucas De Marchi return __gen11_irq_handler(arg, 271097b492f5SLucas De Marchi dg1_master_intr_disable_and_ack, 271197b492f5SLucas De Marchi dg1_master_intr_enable); 271297b492f5SLucas De Marchi } 271397b492f5SLucas De Marchi 271442f52ef8SKeith Packard /* Called from drm generic code, passed 'crtc' which 271542f52ef8SKeith Packard * we use as a pipe index 271642f52ef8SKeith Packard */ 271708fa8fd0SVille Syrjälä int i8xx_enable_vblank(struct drm_crtc *crtc) 27180a3e67a4SJesse Barnes { 271908fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 272008fa8fd0SVille Syrjälä enum pipe pipe = to_intel_crtc(crtc)->pipe; 2721e9d21d7fSKeith Packard unsigned long irqflags; 272271e0ffa5SJesse Barnes 27231ec14ad3SChris Wilson spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 272486e83e35SChris Wilson i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 272586e83e35SChris Wilson spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 272686e83e35SChris Wilson 272786e83e35SChris Wilson return 0; 272886e83e35SChris Wilson } 272986e83e35SChris Wilson 27307d423af9SVille Syrjälä int i915gm_enable_vblank(struct drm_crtc *crtc) 2731d938da6bSVille Syrjälä { 273208fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2733d938da6bSVille Syrjälä 27347d423af9SVille Syrjälä /* 27357d423af9SVille Syrjälä * Vblank interrupts fail to wake the device up from C2+. 27367d423af9SVille Syrjälä * Disabling render clock gating during C-states avoids 27377d423af9SVille Syrjälä * the problem. There is a small power cost so we do this 27387d423af9SVille Syrjälä * only when vblank interrupts are actually enabled. 27397d423af9SVille Syrjälä */ 27407d423af9SVille Syrjälä if (dev_priv->vblank_enabled++ == 0) 27412939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 2742d938da6bSVille Syrjälä 274308fa8fd0SVille Syrjälä return i8xx_enable_vblank(crtc); 2744d938da6bSVille Syrjälä } 2745d938da6bSVille Syrjälä 274608fa8fd0SVille Syrjälä int i965_enable_vblank(struct drm_crtc *crtc) 274786e83e35SChris Wilson { 274808fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 274908fa8fd0SVille Syrjälä enum pipe pipe = to_intel_crtc(crtc)->pipe; 275086e83e35SChris Wilson unsigned long irqflags; 275186e83e35SChris Wilson 275286e83e35SChris Wilson spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 27537c463586SKeith Packard i915_enable_pipestat(dev_priv, pipe, 2754755e9019SImre Deak PIPE_START_VBLANK_INTERRUPT_STATUS); 27551ec14ad3SChris Wilson spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 27568692d00eSChris Wilson 27570a3e67a4SJesse Barnes return 0; 27580a3e67a4SJesse Barnes } 27590a3e67a4SJesse Barnes 276008fa8fd0SVille Syrjälä int ilk_enable_vblank(struct drm_crtc *crtc) 2761f796cf8fSJesse Barnes { 276208fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 276308fa8fd0SVille Syrjälä enum pipe pipe = to_intel_crtc(crtc)->pipe; 2764f796cf8fSJesse Barnes unsigned long irqflags; 2765a9c287c9SJani Nikula u32 bit = INTEL_GEN(dev_priv) >= 7 ? 276686e83e35SChris Wilson DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 2767f796cf8fSJesse Barnes 2768f796cf8fSJesse Barnes spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2769fbdedaeaSVille Syrjälä ilk_enable_display_irq(dev_priv, bit); 2770b1f14ad0SJesse Barnes spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2771b1f14ad0SJesse Barnes 27722e8bf223SDhinakaran Pandiyan /* Even though there is no DMC, frame counter can get stuck when 27732e8bf223SDhinakaran Pandiyan * PSR is active as no frames are generated. 27742e8bf223SDhinakaran Pandiyan */ 27752e8bf223SDhinakaran Pandiyan if (HAS_PSR(dev_priv)) 277608fa8fd0SVille Syrjälä drm_crtc_vblank_restore(crtc); 27772e8bf223SDhinakaran Pandiyan 2778b1f14ad0SJesse Barnes return 0; 2779b1f14ad0SJesse Barnes } 2780b1f14ad0SJesse Barnes 27819c9e97c4SVandita Kulkarni static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, 27829c9e97c4SVandita Kulkarni bool enable) 27839c9e97c4SVandita Kulkarni { 27849c9e97c4SVandita Kulkarni struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 27859c9e97c4SVandita Kulkarni enum port port; 27869c9e97c4SVandita Kulkarni u32 tmp; 27879c9e97c4SVandita Kulkarni 27889c9e97c4SVandita Kulkarni if (!(intel_crtc->mode_flags & 27899c9e97c4SVandita Kulkarni (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0))) 27909c9e97c4SVandita Kulkarni return false; 27919c9e97c4SVandita Kulkarni 27929c9e97c4SVandita Kulkarni /* for dual link cases we consider TE from slave */ 27939c9e97c4SVandita Kulkarni if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 27949c9e97c4SVandita Kulkarni port = PORT_B; 27959c9e97c4SVandita Kulkarni else 27969c9e97c4SVandita Kulkarni port = PORT_A; 27979c9e97c4SVandita Kulkarni 27982939eb06SJani Nikula tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port)); 27999c9e97c4SVandita Kulkarni if (enable) 28009c9e97c4SVandita Kulkarni tmp &= ~DSI_TE_EVENT; 28019c9e97c4SVandita Kulkarni else 28029c9e97c4SVandita Kulkarni tmp |= DSI_TE_EVENT; 28039c9e97c4SVandita Kulkarni 28042939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp); 28059c9e97c4SVandita Kulkarni 28062939eb06SJani Nikula tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port)); 28072939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp); 28089c9e97c4SVandita Kulkarni 28099c9e97c4SVandita Kulkarni return true; 28109c9e97c4SVandita Kulkarni } 28119c9e97c4SVandita Kulkarni 281208fa8fd0SVille Syrjälä int bdw_enable_vblank(struct drm_crtc *crtc) 2813abd58f01SBen Widawsky { 281408fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 28159c9e97c4SVandita Kulkarni struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 28169c9e97c4SVandita Kulkarni enum pipe pipe = intel_crtc->pipe; 2817abd58f01SBen Widawsky unsigned long irqflags; 2818abd58f01SBen Widawsky 28199c9e97c4SVandita Kulkarni if (gen11_dsi_configure_te(intel_crtc, true)) 28209c9e97c4SVandita Kulkarni return 0; 28219c9e97c4SVandita Kulkarni 2822abd58f01SBen Widawsky spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2823013d3752SVille Syrjälä bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); 2824abd58f01SBen Widawsky spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2825013d3752SVille Syrjälä 28262e8bf223SDhinakaran Pandiyan /* Even if there is no DMC, frame counter can get stuck when 28272e8bf223SDhinakaran Pandiyan * PSR is active as no frames are generated, so check only for PSR. 28282e8bf223SDhinakaran Pandiyan */ 28292e8bf223SDhinakaran Pandiyan if (HAS_PSR(dev_priv)) 283008fa8fd0SVille Syrjälä drm_crtc_vblank_restore(crtc); 28312e8bf223SDhinakaran Pandiyan 2832abd58f01SBen Widawsky return 0; 2833abd58f01SBen Widawsky } 2834abd58f01SBen Widawsky 283542f52ef8SKeith Packard /* Called from drm generic code, passed 'crtc' which 283642f52ef8SKeith Packard * we use as a pipe index 283742f52ef8SKeith Packard */ 283808fa8fd0SVille Syrjälä void i8xx_disable_vblank(struct drm_crtc *crtc) 283986e83e35SChris Wilson { 284008fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 284108fa8fd0SVille Syrjälä enum pipe pipe = to_intel_crtc(crtc)->pipe; 284286e83e35SChris Wilson unsigned long irqflags; 284386e83e35SChris Wilson 284486e83e35SChris Wilson spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 284586e83e35SChris Wilson i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); 284686e83e35SChris Wilson spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 284786e83e35SChris Wilson } 284886e83e35SChris Wilson 28497d423af9SVille Syrjälä void i915gm_disable_vblank(struct drm_crtc *crtc) 2850d938da6bSVille Syrjälä { 285108fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 2852d938da6bSVille Syrjälä 285308fa8fd0SVille Syrjälä i8xx_disable_vblank(crtc); 2854d938da6bSVille Syrjälä 28557d423af9SVille Syrjälä if (--dev_priv->vblank_enabled == 0) 28562939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); 2857d938da6bSVille Syrjälä } 2858d938da6bSVille Syrjälä 285908fa8fd0SVille Syrjälä void i965_disable_vblank(struct drm_crtc *crtc) 28600a3e67a4SJesse Barnes { 286108fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 286208fa8fd0SVille Syrjälä enum pipe pipe = to_intel_crtc(crtc)->pipe; 2863e9d21d7fSKeith Packard unsigned long irqflags; 28640a3e67a4SJesse Barnes 28651ec14ad3SChris Wilson spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 28667c463586SKeith Packard i915_disable_pipestat(dev_priv, pipe, 2867755e9019SImre Deak PIPE_START_VBLANK_INTERRUPT_STATUS); 28681ec14ad3SChris Wilson spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 28690a3e67a4SJesse Barnes } 28700a3e67a4SJesse Barnes 287108fa8fd0SVille Syrjälä void ilk_disable_vblank(struct drm_crtc *crtc) 2872f796cf8fSJesse Barnes { 287308fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 287408fa8fd0SVille Syrjälä enum pipe pipe = to_intel_crtc(crtc)->pipe; 2875f796cf8fSJesse Barnes unsigned long irqflags; 2876a9c287c9SJani Nikula u32 bit = INTEL_GEN(dev_priv) >= 7 ? 287786e83e35SChris Wilson DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); 2878f796cf8fSJesse Barnes 2879f796cf8fSJesse Barnes spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2880fbdedaeaSVille Syrjälä ilk_disable_display_irq(dev_priv, bit); 2881b1f14ad0SJesse Barnes spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2882b1f14ad0SJesse Barnes } 2883b1f14ad0SJesse Barnes 288408fa8fd0SVille Syrjälä void bdw_disable_vblank(struct drm_crtc *crtc) 2885abd58f01SBen Widawsky { 288608fa8fd0SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->dev); 28879c9e97c4SVandita Kulkarni struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 28889c9e97c4SVandita Kulkarni enum pipe pipe = intel_crtc->pipe; 2889abd58f01SBen Widawsky unsigned long irqflags; 2890abd58f01SBen Widawsky 28919c9e97c4SVandita Kulkarni if (gen11_dsi_configure_te(intel_crtc, false)) 28929c9e97c4SVandita Kulkarni return; 28939c9e97c4SVandita Kulkarni 2894abd58f01SBen Widawsky spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2895013d3752SVille Syrjälä bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); 2896abd58f01SBen Widawsky spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2897abd58f01SBen Widawsky } 2898abd58f01SBen Widawsky 2899b243f530STvrtko Ursulin static void ibx_irq_reset(struct drm_i915_private *dev_priv) 290091738a95SPaulo Zanoni { 2901b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 2902b16b2a2fSPaulo Zanoni 29036e266956STvrtko Ursulin if (HAS_PCH_NOP(dev_priv)) 290491738a95SPaulo Zanoni return; 290591738a95SPaulo Zanoni 2906b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, SDE); 2907105b122eSPaulo Zanoni 29086e266956STvrtko Ursulin if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) 29092939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff); 2910622364b6SPaulo Zanoni } 2911105b122eSPaulo Zanoni 291270591a41SVille Syrjälä static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) 291370591a41SVille Syrjälä { 2914b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 2915b16b2a2fSPaulo Zanoni 291671b8b41dSVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) 2917f0818984STvrtko Ursulin intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); 291871b8b41dSVille Syrjälä else 2919f0818984STvrtko Ursulin intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK); 292071b8b41dSVille Syrjälä 2921ad22d106SVille Syrjälä i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); 29222939eb06SJani Nikula intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); 292370591a41SVille Syrjälä 292444d9241eSVille Syrjälä i9xx_pipestat_irq_reset(dev_priv); 292570591a41SVille Syrjälä 2926b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, VLV_); 29278bd099a7SChris Wilson dev_priv->irq_mask = ~0u; 292870591a41SVille Syrjälä } 292970591a41SVille Syrjälä 29308bb61306SVille Syrjälä static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) 29318bb61306SVille Syrjälä { 2932b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 2933b16b2a2fSPaulo Zanoni 29348bb61306SVille Syrjälä u32 pipestat_mask; 29359ab981f2SVille Syrjälä u32 enable_mask; 29368bb61306SVille Syrjälä enum pipe pipe; 29378bb61306SVille Syrjälä 2938842ebf7aSVille Syrjälä pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; 29398bb61306SVille Syrjälä 29408bb61306SVille Syrjälä i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 29418bb61306SVille Syrjälä for_each_pipe(dev_priv, pipe) 29428bb61306SVille Syrjälä i915_enable_pipestat(dev_priv, pipe, pipestat_mask); 29438bb61306SVille Syrjälä 29449ab981f2SVille Syrjälä enable_mask = I915_DISPLAY_PORT_INTERRUPT | 29458bb61306SVille Syrjälä I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2946ebf5f921SVille Syrjälä I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2947ebf5f921SVille Syrjälä I915_LPE_PIPE_A_INTERRUPT | 2948ebf5f921SVille Syrjälä I915_LPE_PIPE_B_INTERRUPT; 2949ebf5f921SVille Syrjälä 29508bb61306SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) 2951ebf5f921SVille Syrjälä enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | 2952ebf5f921SVille Syrjälä I915_LPE_PIPE_C_INTERRUPT; 29536b7eafc1SVille Syrjälä 295448a1b8d4SPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u); 29556b7eafc1SVille Syrjälä 29569ab981f2SVille Syrjälä dev_priv->irq_mask = ~enable_mask; 29578bb61306SVille Syrjälä 2958b16b2a2fSPaulo Zanoni GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); 29598bb61306SVille Syrjälä } 29608bb61306SVille Syrjälä 29618bb61306SVille Syrjälä /* drm_dma.h hooks 29628bb61306SVille Syrjälä */ 29639eae5e27SLucas De Marchi static void ilk_irq_reset(struct drm_i915_private *dev_priv) 29648bb61306SVille Syrjälä { 2965b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 29668bb61306SVille Syrjälä 2967b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, DE); 2968e44adb5dSChris Wilson dev_priv->irq_mask = ~0u; 2969e44adb5dSChris Wilson 2970cf819effSLucas De Marchi if (IS_GEN(dev_priv, 7)) 2971f0818984STvrtko Ursulin intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff); 29728bb61306SVille Syrjälä 2973fc340442SDaniel Vetter if (IS_HASWELL(dev_priv)) { 2974f0818984STvrtko Ursulin intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 2975f0818984STvrtko Ursulin intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 2976fc340442SDaniel Vetter } 2977fc340442SDaniel Vetter 2978cf1c97dcSAndi Shyti gen5_gt_irq_reset(&dev_priv->gt); 29798bb61306SVille Syrjälä 2980b243f530STvrtko Ursulin ibx_irq_reset(dev_priv); 29818bb61306SVille Syrjälä } 29828bb61306SVille Syrjälä 2983b318b824SVille Syrjälä static void valleyview_irq_reset(struct drm_i915_private *dev_priv) 29847e231dbeSJesse Barnes { 29852939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); 29862939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 298734c7b8a7SVille Syrjälä 2988cf1c97dcSAndi Shyti gen5_gt_irq_reset(&dev_priv->gt); 29897e231dbeSJesse Barnes 2990ad22d106SVille Syrjälä spin_lock_irq(&dev_priv->irq_lock); 29919918271eSVille Syrjälä if (dev_priv->display_irqs_enabled) 299270591a41SVille Syrjälä vlv_display_irq_reset(dev_priv); 2993ad22d106SVille Syrjälä spin_unlock_irq(&dev_priv->irq_lock); 29947e231dbeSJesse Barnes } 29957e231dbeSJesse Barnes 2996b318b824SVille Syrjälä static void gen8_irq_reset(struct drm_i915_private *dev_priv) 2997abd58f01SBen Widawsky { 2998b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 2999d048a268SVille Syrjälä enum pipe pipe; 3000abd58f01SBen Widawsky 300125286aacSDaniele Ceraolo Spurio gen8_master_intr_disable(dev_priv->uncore.regs); 3002abd58f01SBen Widawsky 3003cf1c97dcSAndi Shyti gen8_gt_irq_reset(&dev_priv->gt); 3004abd58f01SBen Widawsky 3005f0818984STvrtko Ursulin intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 3006f0818984STvrtko Ursulin intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 3007e04f7eceSVille Syrjälä 3008055e393fSDamien Lespiau for_each_pipe(dev_priv, pipe) 3009f458ebbcSDaniel Vetter if (intel_display_power_is_enabled(dev_priv, 3010813bde43SPaulo Zanoni POWER_DOMAIN_PIPE(pipe))) 3011b16b2a2fSPaulo Zanoni GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 3012abd58f01SBen Widawsky 3013b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); 3014b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); 3015b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, GEN8_PCU_); 3016abd58f01SBen Widawsky 30176e266956STvrtko Ursulin if (HAS_PCH_SPLIT(dev_priv)) 3018b243f530STvrtko Ursulin ibx_irq_reset(dev_priv); 3019abd58f01SBen Widawsky } 3020abd58f01SBen Widawsky 3021a3265d85SMatt Roper static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) 302251951ae7SMika Kuoppala { 3023b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 3024d048a268SVille Syrjälä enum pipe pipe; 3025562ddcb7SMatt Roper u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3026562ddcb7SMatt Roper BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 302751951ae7SMika Kuoppala 3028f0818984STvrtko Ursulin intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0); 302951951ae7SMika Kuoppala 30308241cfbeSJosé Roberto de Souza if (INTEL_GEN(dev_priv) >= 12) { 30318241cfbeSJosé Roberto de Souza enum transcoder trans; 30328241cfbeSJosé Roberto de Souza 3033562ddcb7SMatt Roper for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { 30348241cfbeSJosé Roberto de Souza enum intel_display_power_domain domain; 30358241cfbeSJosé Roberto de Souza 30368241cfbeSJosé Roberto de Souza domain = POWER_DOMAIN_TRANSCODER(trans); 30378241cfbeSJosé Roberto de Souza if (!intel_display_power_is_enabled(dev_priv, domain)) 30388241cfbeSJosé Roberto de Souza continue; 30398241cfbeSJosé Roberto de Souza 30408241cfbeSJosé Roberto de Souza intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff); 30418241cfbeSJosé Roberto de Souza intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff); 30428241cfbeSJosé Roberto de Souza } 30438241cfbeSJosé Roberto de Souza } else { 3044f0818984STvrtko Ursulin intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); 3045f0818984STvrtko Ursulin intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); 30468241cfbeSJosé Roberto de Souza } 304762819dfdSJosé Roberto de Souza 304851951ae7SMika Kuoppala for_each_pipe(dev_priv, pipe) 304951951ae7SMika Kuoppala if (intel_display_power_is_enabled(dev_priv, 305051951ae7SMika Kuoppala POWER_DOMAIN_PIPE(pipe))) 3051b16b2a2fSPaulo Zanoni GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 305251951ae7SMika Kuoppala 3053b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_); 3054b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_); 3055b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_); 305631604222SAnusha Srivatsa 305729b43ae2SRodrigo Vivi if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3058b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, SDE); 30599b2383a7SMatt Roper 3060b896898cSBob Paauwe /* Wa_14010685332:cnp/cmp,tgp,adp */ 3061b896898cSBob Paauwe if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP || 3062b896898cSBob Paauwe (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && 3063b896898cSBob Paauwe INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) { 30649b2383a7SMatt Roper intel_uncore_rmw(uncore, SOUTH_CHICKEN1, 30659b2383a7SMatt Roper SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); 30669b2383a7SMatt Roper intel_uncore_rmw(uncore, SOUTH_CHICKEN1, 30679b2383a7SMatt Roper SBCLK_RUN_REFCLK_DIS, 0); 30689b2383a7SMatt Roper } 306951951ae7SMika Kuoppala } 307051951ae7SMika Kuoppala 3071a3265d85SMatt Roper static void gen11_irq_reset(struct drm_i915_private *dev_priv) 3072a3265d85SMatt Roper { 3073a3265d85SMatt Roper struct intel_uncore *uncore = &dev_priv->uncore; 3074a3265d85SMatt Roper 307597b492f5SLucas De Marchi if (HAS_MASTER_UNIT_IRQ(dev_priv)) 307697b492f5SLucas De Marchi dg1_master_intr_disable_and_ack(dev_priv->uncore.regs); 307797b492f5SLucas De Marchi else 3078a3265d85SMatt Roper gen11_master_intr_disable(dev_priv->uncore.regs); 3079a3265d85SMatt Roper 3080a3265d85SMatt Roper gen11_gt_irq_reset(&dev_priv->gt); 3081a3265d85SMatt Roper gen11_display_irq_reset(dev_priv); 3082a3265d85SMatt Roper 3083a3265d85SMatt Roper GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); 3084a3265d85SMatt Roper GEN3_IRQ_RESET(uncore, GEN8_PCU_); 3085a3265d85SMatt Roper } 3086a3265d85SMatt Roper 30874c6c03beSDamien Lespiau void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, 3088001bd2cbSImre Deak u8 pipe_mask) 3089d49bdb0eSPaulo Zanoni { 3090b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 3091b16b2a2fSPaulo Zanoni 3092a9c287c9SJani Nikula u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; 30936831f3e3SVille Syrjälä enum pipe pipe; 3094d49bdb0eSPaulo Zanoni 30951288f9b0SKarthik B S if (INTEL_GEN(dev_priv) >= 9) 30961288f9b0SKarthik B S extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; 30971288f9b0SKarthik B S 309813321786SDaniel Vetter spin_lock_irq(&dev_priv->irq_lock); 30999dfe2e3aSImre Deak 31009dfe2e3aSImre Deak if (!intel_irqs_enabled(dev_priv)) { 31019dfe2e3aSImre Deak spin_unlock_irq(&dev_priv->irq_lock); 31029dfe2e3aSImre Deak return; 31039dfe2e3aSImre Deak } 31049dfe2e3aSImre Deak 31056831f3e3SVille Syrjälä for_each_pipe_masked(dev_priv, pipe, pipe_mask) 3106b16b2a2fSPaulo Zanoni GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, 31076831f3e3SVille Syrjälä dev_priv->de_irq_mask[pipe], 31086831f3e3SVille Syrjälä ~dev_priv->de_irq_mask[pipe] | extra_ier); 31099dfe2e3aSImre Deak 311013321786SDaniel Vetter spin_unlock_irq(&dev_priv->irq_lock); 3111d49bdb0eSPaulo Zanoni } 3112d49bdb0eSPaulo Zanoni 3113aae8ba84SVille Syrjälä void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, 3114001bd2cbSImre Deak u8 pipe_mask) 3115aae8ba84SVille Syrjälä { 3116b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 31176831f3e3SVille Syrjälä enum pipe pipe; 31186831f3e3SVille Syrjälä 3119aae8ba84SVille Syrjälä spin_lock_irq(&dev_priv->irq_lock); 31209dfe2e3aSImre Deak 31219dfe2e3aSImre Deak if (!intel_irqs_enabled(dev_priv)) { 31229dfe2e3aSImre Deak spin_unlock_irq(&dev_priv->irq_lock); 31239dfe2e3aSImre Deak return; 31249dfe2e3aSImre Deak } 31259dfe2e3aSImre Deak 31266831f3e3SVille Syrjälä for_each_pipe_masked(dev_priv, pipe, pipe_mask) 3127b16b2a2fSPaulo Zanoni GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); 31289dfe2e3aSImre Deak 3129aae8ba84SVille Syrjälä spin_unlock_irq(&dev_priv->irq_lock); 3130aae8ba84SVille Syrjälä 3131aae8ba84SVille Syrjälä /* make sure we're done processing display irqs */ 3132315ca4c4SVille Syrjälä intel_synchronize_irq(dev_priv); 3133aae8ba84SVille Syrjälä } 3134aae8ba84SVille Syrjälä 3135b318b824SVille Syrjälä static void cherryview_irq_reset(struct drm_i915_private *dev_priv) 313643f328d7SVille Syrjälä { 3137b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 313843f328d7SVille Syrjälä 31392939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); 31402939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 314143f328d7SVille Syrjälä 3142cf1c97dcSAndi Shyti gen8_gt_irq_reset(&dev_priv->gt); 314343f328d7SVille Syrjälä 3144b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, GEN8_PCU_); 314543f328d7SVille Syrjälä 3146ad22d106SVille Syrjälä spin_lock_irq(&dev_priv->irq_lock); 31479918271eSVille Syrjälä if (dev_priv->display_irqs_enabled) 314870591a41SVille Syrjälä vlv_display_irq_reset(dev_priv); 3149ad22d106SVille Syrjälä spin_unlock_irq(&dev_priv->irq_lock); 315043f328d7SVille Syrjälä } 315143f328d7SVille Syrjälä 31522ea63927SVille Syrjälä static u32 ibx_hotplug_enables(struct drm_i915_private *i915, 31532ea63927SVille Syrjälä enum hpd_pin pin) 31542ea63927SVille Syrjälä { 31552ea63927SVille Syrjälä switch (pin) { 31562ea63927SVille Syrjälä case HPD_PORT_A: 31572ea63927SVille Syrjälä /* 31582ea63927SVille Syrjälä * When CPU and PCH are on the same package, port A 31592ea63927SVille Syrjälä * HPD must be enabled in both north and south. 31602ea63927SVille Syrjälä */ 31612ea63927SVille Syrjälä return HAS_PCH_LPT_LP(i915) ? 31622ea63927SVille Syrjälä PORTA_HOTPLUG_ENABLE : 0; 31632ea63927SVille Syrjälä case HPD_PORT_B: 31642ea63927SVille Syrjälä return PORTB_HOTPLUG_ENABLE | 31652ea63927SVille Syrjälä PORTB_PULSE_DURATION_2ms; 31662ea63927SVille Syrjälä case HPD_PORT_C: 31672ea63927SVille Syrjälä return PORTC_HOTPLUG_ENABLE | 31682ea63927SVille Syrjälä PORTC_PULSE_DURATION_2ms; 31692ea63927SVille Syrjälä case HPD_PORT_D: 31702ea63927SVille Syrjälä return PORTD_HOTPLUG_ENABLE | 31712ea63927SVille Syrjälä PORTD_PULSE_DURATION_2ms; 31722ea63927SVille Syrjälä default: 31732ea63927SVille Syrjälä return 0; 31742ea63927SVille Syrjälä } 31752ea63927SVille Syrjälä } 31762ea63927SVille Syrjälä 31771a56b1a2SImre Deak static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) 31781a56b1a2SImre Deak { 31791a56b1a2SImre Deak u32 hotplug; 31801a56b1a2SImre Deak 31811a56b1a2SImre Deak /* 31821a56b1a2SImre Deak * Enable digital hotplug on the PCH, and configure the DP short pulse 31831a56b1a2SImre Deak * duration to 2ms (which is the minimum in the Display Port spec). 31841a56b1a2SImre Deak * The pulse duration bits are reserved on LPT+. 31851a56b1a2SImre Deak */ 31862939eb06SJani Nikula hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 31872ea63927SVille Syrjälä hotplug &= ~(PORTA_HOTPLUG_ENABLE | 31882ea63927SVille Syrjälä PORTB_HOTPLUG_ENABLE | 31892ea63927SVille Syrjälä PORTC_HOTPLUG_ENABLE | 31902ea63927SVille Syrjälä PORTD_HOTPLUG_ENABLE | 31912ea63927SVille Syrjälä PORTB_PULSE_DURATION_MASK | 31921a56b1a2SImre Deak PORTC_PULSE_DURATION_MASK | 31931a56b1a2SImre Deak PORTD_PULSE_DURATION_MASK); 31942ea63927SVille Syrjälä hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables); 31952939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); 31961a56b1a2SImre Deak } 31971a56b1a2SImre Deak 319891d14251STvrtko Ursulin static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) 319982a28bcfSDaniel Vetter { 32001a56b1a2SImre Deak u32 hotplug_irqs, enabled_irqs; 320182a28bcfSDaniel Vetter 32020398993bSVille Syrjälä enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 32036d3144ebSVille Syrjälä hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 320482a28bcfSDaniel Vetter 3205fee884edSDaniel Vetter ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 320682a28bcfSDaniel Vetter 32071a56b1a2SImre Deak ibx_hpd_detection_setup(dev_priv); 32086dbf30ceSVille Syrjälä } 320926951cafSXiong Zhang 32102ea63927SVille Syrjälä static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915, 32112ea63927SVille Syrjälä enum hpd_pin pin) 32122ea63927SVille Syrjälä { 32132ea63927SVille Syrjälä switch (pin) { 32142ea63927SVille Syrjälä case HPD_PORT_A: 32152ea63927SVille Syrjälä case HPD_PORT_B: 32162ea63927SVille Syrjälä case HPD_PORT_C: 32172ea63927SVille Syrjälä case HPD_PORT_D: 32182ea63927SVille Syrjälä return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin); 32192ea63927SVille Syrjälä default: 32202ea63927SVille Syrjälä return 0; 32212ea63927SVille Syrjälä } 32222ea63927SVille Syrjälä } 32232ea63927SVille Syrjälä 32242ea63927SVille Syrjälä static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915, 32252ea63927SVille Syrjälä enum hpd_pin pin) 32262ea63927SVille Syrjälä { 32272ea63927SVille Syrjälä switch (pin) { 32282ea63927SVille Syrjälä case HPD_PORT_TC1: 32292ea63927SVille Syrjälä case HPD_PORT_TC2: 32302ea63927SVille Syrjälä case HPD_PORT_TC3: 32312ea63927SVille Syrjälä case HPD_PORT_TC4: 32322ea63927SVille Syrjälä case HPD_PORT_TC5: 32332ea63927SVille Syrjälä case HPD_PORT_TC6: 32342ea63927SVille Syrjälä return ICP_TC_HPD_ENABLE(pin); 32352ea63927SVille Syrjälä default: 32362ea63927SVille Syrjälä return 0; 32372ea63927SVille Syrjälä } 32382ea63927SVille Syrjälä } 32392ea63927SVille Syrjälä 32402ea63927SVille Syrjälä static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv) 324131604222SAnusha Srivatsa { 324231604222SAnusha Srivatsa u32 hotplug; 324331604222SAnusha Srivatsa 32442939eb06SJani Nikula hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI); 32452ea63927SVille Syrjälä hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) | 32462ea63927SVille Syrjälä SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | 32472ea63927SVille Syrjälä SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | 32482ea63927SVille Syrjälä SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D)); 32492ea63927SVille Syrjälä hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables); 32502939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug); 325131604222SAnusha Srivatsa } 3252815f4ef2SVille Syrjälä 32532ea63927SVille Syrjälä static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) 3254815f4ef2SVille Syrjälä { 3255815f4ef2SVille Syrjälä u32 hotplug; 3256815f4ef2SVille Syrjälä 32572939eb06SJani Nikula hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC); 32582ea63927SVille Syrjälä hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) | 32592ea63927SVille Syrjälä ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | 32602ea63927SVille Syrjälä ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | 32612ea63927SVille Syrjälä ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | 32622ea63927SVille Syrjälä ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | 32632ea63927SVille Syrjälä ICP_TC_HPD_ENABLE(HPD_PORT_TC6)); 32642ea63927SVille Syrjälä hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables); 32652939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug); 32668ef7e340SMatt Roper } 326731604222SAnusha Srivatsa 32682ea63927SVille Syrjälä static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv) 326931604222SAnusha Srivatsa { 327031604222SAnusha Srivatsa u32 hotplug_irqs, enabled_irqs; 327131604222SAnusha Srivatsa 32720398993bSVille Syrjälä enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 32736d3144ebSVille Syrjälä hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 327431604222SAnusha Srivatsa 3275f619e516SAnusha Srivatsa if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP) 32762939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); 3277f49108d0SMatt Roper 327831604222SAnusha Srivatsa ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 327931604222SAnusha Srivatsa 32802ea63927SVille Syrjälä icp_ddi_hpd_detection_setup(dev_priv); 32812ea63927SVille Syrjälä icp_tc_hpd_detection_setup(dev_priv); 328252dfdba0SLucas De Marchi } 328352dfdba0SLucas De Marchi 32842ea63927SVille Syrjälä static u32 gen11_hotplug_enables(struct drm_i915_private *i915, 32852ea63927SVille Syrjälä enum hpd_pin pin) 32868ef7e340SMatt Roper { 32872ea63927SVille Syrjälä switch (pin) { 32882ea63927SVille Syrjälä case HPD_PORT_TC1: 32892ea63927SVille Syrjälä case HPD_PORT_TC2: 32902ea63927SVille Syrjälä case HPD_PORT_TC3: 32912ea63927SVille Syrjälä case HPD_PORT_TC4: 32922ea63927SVille Syrjälä case HPD_PORT_TC5: 32932ea63927SVille Syrjälä case HPD_PORT_TC6: 32942ea63927SVille Syrjälä return GEN11_HOTPLUG_CTL_ENABLE(pin); 32952ea63927SVille Syrjälä default: 32962ea63927SVille Syrjälä return 0; 329731604222SAnusha Srivatsa } 3298943682e3SMatt Roper } 3299943682e3SMatt Roper 3300229f31e2SLucas De Marchi static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) 3301229f31e2SLucas De Marchi { 3302b18c1eb9SClinton A Taylor u32 val; 3303b18c1eb9SClinton A Taylor 33042939eb06SJani Nikula val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1); 3305b18c1eb9SClinton A Taylor val |= (INVERT_DDIA_HPD | 3306b18c1eb9SClinton A Taylor INVERT_DDIB_HPD | 3307b18c1eb9SClinton A Taylor INVERT_DDIC_HPD | 3308b18c1eb9SClinton A Taylor INVERT_DDID_HPD); 33092939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val); 3310b18c1eb9SClinton A Taylor 33112ea63927SVille Syrjälä icp_hpd_irq_setup(dev_priv); 3312229f31e2SLucas De Marchi } 3313229f31e2SLucas De Marchi 331452c7f5f1SVille Syrjälä static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) 3315121e758eSDhinakaran Pandiyan { 3316121e758eSDhinakaran Pandiyan u32 hotplug; 3317121e758eSDhinakaran Pandiyan 33182939eb06SJani Nikula hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL); 33192ea63927SVille Syrjälä hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) | 33205b76e860SVille Syrjälä GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) | 33215b76e860SVille Syrjälä GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) | 33225b76e860SVille Syrjälä GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) | 33235b76e860SVille Syrjälä GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) | 33242ea63927SVille Syrjälä GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6)); 33252ea63927SVille Syrjälä hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables); 33262939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug); 332752c7f5f1SVille Syrjälä } 332852c7f5f1SVille Syrjälä 332952c7f5f1SVille Syrjälä static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv) 333052c7f5f1SVille Syrjälä { 333152c7f5f1SVille Syrjälä u32 hotplug; 3332b796b971SDhinakaran Pandiyan 33332939eb06SJani Nikula hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL); 33342ea63927SVille Syrjälä hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) | 33355b76e860SVille Syrjälä GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) | 33365b76e860SVille Syrjälä GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) | 33375b76e860SVille Syrjälä GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) | 33385b76e860SVille Syrjälä GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) | 33392ea63927SVille Syrjälä GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6)); 33402ea63927SVille Syrjälä hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables); 33412939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug); 3342121e758eSDhinakaran Pandiyan } 3343121e758eSDhinakaran Pandiyan 3344121e758eSDhinakaran Pandiyan static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) 3345121e758eSDhinakaran Pandiyan { 3346121e758eSDhinakaran Pandiyan u32 hotplug_irqs, enabled_irqs; 3347121e758eSDhinakaran Pandiyan u32 val; 3348121e758eSDhinakaran Pandiyan 33490398993bSVille Syrjälä enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); 33506d3144ebSVille Syrjälä hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); 3351121e758eSDhinakaran Pandiyan 33522939eb06SJani Nikula val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); 3353121e758eSDhinakaran Pandiyan val &= ~hotplug_irqs; 3354587a87b9SImre Deak val |= ~enabled_irqs & hotplug_irqs; 33552939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val); 33562939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); 3357121e758eSDhinakaran Pandiyan 335852c7f5f1SVille Syrjälä gen11_tc_hpd_detection_setup(dev_priv); 335952c7f5f1SVille Syrjälä gen11_tbt_hpd_detection_setup(dev_priv); 336031604222SAnusha Srivatsa 33612ea63927SVille Syrjälä if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 33622ea63927SVille Syrjälä icp_hpd_irq_setup(dev_priv); 33632ea63927SVille Syrjälä } 33642ea63927SVille Syrjälä 33652ea63927SVille Syrjälä static u32 spt_hotplug_enables(struct drm_i915_private *i915, 33662ea63927SVille Syrjälä enum hpd_pin pin) 33672ea63927SVille Syrjälä { 33682ea63927SVille Syrjälä switch (pin) { 33692ea63927SVille Syrjälä case HPD_PORT_A: 33702ea63927SVille Syrjälä return PORTA_HOTPLUG_ENABLE; 33712ea63927SVille Syrjälä case HPD_PORT_B: 33722ea63927SVille Syrjälä return PORTB_HOTPLUG_ENABLE; 33732ea63927SVille Syrjälä case HPD_PORT_C: 33742ea63927SVille Syrjälä return PORTC_HOTPLUG_ENABLE; 33752ea63927SVille Syrjälä case HPD_PORT_D: 33762ea63927SVille Syrjälä return PORTD_HOTPLUG_ENABLE; 33772ea63927SVille Syrjälä default: 33782ea63927SVille Syrjälä return 0; 33792ea63927SVille Syrjälä } 33802ea63927SVille Syrjälä } 33812ea63927SVille Syrjälä 33822ea63927SVille Syrjälä static u32 spt_hotplug2_enables(struct drm_i915_private *i915, 33832ea63927SVille Syrjälä enum hpd_pin pin) 33842ea63927SVille Syrjälä { 33852ea63927SVille Syrjälä switch (pin) { 33862ea63927SVille Syrjälä case HPD_PORT_E: 33872ea63927SVille Syrjälä return PORTE_HOTPLUG_ENABLE; 33882ea63927SVille Syrjälä default: 33892ea63927SVille Syrjälä return 0; 33902ea63927SVille Syrjälä } 3391121e758eSDhinakaran Pandiyan } 3392121e758eSDhinakaran Pandiyan 33932a57d9ccSImre Deak static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) 33942a57d9ccSImre Deak { 33953b92e263SRodrigo Vivi u32 val, hotplug; 33963b92e263SRodrigo Vivi 33973b92e263SRodrigo Vivi /* Display WA #1179 WaHardHangonHotPlug: cnp */ 33983b92e263SRodrigo Vivi if (HAS_PCH_CNP(dev_priv)) { 33992939eb06SJani Nikula val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1); 34003b92e263SRodrigo Vivi val &= ~CHASSIS_CLK_REQ_DURATION_MASK; 34013b92e263SRodrigo Vivi val |= CHASSIS_CLK_REQ_DURATION(0xf); 34022939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val); 34033b92e263SRodrigo Vivi } 34042a57d9ccSImre Deak 34052a57d9ccSImre Deak /* Enable digital hotplug on the PCH */ 34062939eb06SJani Nikula hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 34072ea63927SVille Syrjälä hotplug &= ~(PORTA_HOTPLUG_ENABLE | 34082a57d9ccSImre Deak PORTB_HOTPLUG_ENABLE | 34092a57d9ccSImre Deak PORTC_HOTPLUG_ENABLE | 34102ea63927SVille Syrjälä PORTD_HOTPLUG_ENABLE); 34112ea63927SVille Syrjälä hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables); 34122939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); 34132a57d9ccSImre Deak 34142939eb06SJani Nikula hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2); 34152ea63927SVille Syrjälä hotplug &= ~PORTE_HOTPLUG_ENABLE; 34162ea63927SVille Syrjälä hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables); 34172939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug); 34182a57d9ccSImre Deak } 34192a57d9ccSImre Deak 342091d14251STvrtko Ursulin static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) 34216dbf30ceSVille Syrjälä { 34222a57d9ccSImre Deak u32 hotplug_irqs, enabled_irqs; 34236dbf30ceSVille Syrjälä 3424f49108d0SMatt Roper if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 34252939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); 3426f49108d0SMatt Roper 34270398993bSVille Syrjälä enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 34286d3144ebSVille Syrjälä hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); 34296dbf30ceSVille Syrjälä 34306dbf30ceSVille Syrjälä ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 34316dbf30ceSVille Syrjälä 34322a57d9ccSImre Deak spt_hpd_detection_setup(dev_priv); 343326951cafSXiong Zhang } 34347fe0b973SKeith Packard 34352ea63927SVille Syrjälä static u32 ilk_hotplug_enables(struct drm_i915_private *i915, 34362ea63927SVille Syrjälä enum hpd_pin pin) 34372ea63927SVille Syrjälä { 34382ea63927SVille Syrjälä switch (pin) { 34392ea63927SVille Syrjälä case HPD_PORT_A: 34402ea63927SVille Syrjälä return DIGITAL_PORTA_HOTPLUG_ENABLE | 34412ea63927SVille Syrjälä DIGITAL_PORTA_PULSE_DURATION_2ms; 34422ea63927SVille Syrjälä default: 34432ea63927SVille Syrjälä return 0; 34442ea63927SVille Syrjälä } 34452ea63927SVille Syrjälä } 34462ea63927SVille Syrjälä 34471a56b1a2SImre Deak static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) 34481a56b1a2SImre Deak { 34491a56b1a2SImre Deak u32 hotplug; 34501a56b1a2SImre Deak 34511a56b1a2SImre Deak /* 34521a56b1a2SImre Deak * Enable digital hotplug on the CPU, and configure the DP short pulse 34531a56b1a2SImre Deak * duration to 2ms (which is the minimum in the Display Port spec) 34541a56b1a2SImre Deak * The pulse duration bits are reserved on HSW+. 34551a56b1a2SImre Deak */ 34562939eb06SJani Nikula hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL); 34572ea63927SVille Syrjälä hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE | 34582ea63927SVille Syrjälä DIGITAL_PORTA_PULSE_DURATION_MASK); 34592ea63927SVille Syrjälä hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables); 34602939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); 34611a56b1a2SImre Deak } 34621a56b1a2SImre Deak 346391d14251STvrtko Ursulin static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) 3464e4ce95aaSVille Syrjälä { 34651a56b1a2SImre Deak u32 hotplug_irqs, enabled_irqs; 3466e4ce95aaSVille Syrjälä 34670398993bSVille Syrjälä enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); 34686d3144ebSVille Syrjälä hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); 34693a3b3c7dSVille Syrjälä 34706d3144ebSVille Syrjälä if (INTEL_GEN(dev_priv) >= 8) 34713a3b3c7dSVille Syrjälä bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); 34726d3144ebSVille Syrjälä else 34733a3b3c7dSVille Syrjälä ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); 3474e4ce95aaSVille Syrjälä 34751a56b1a2SImre Deak ilk_hpd_detection_setup(dev_priv); 3476e4ce95aaSVille Syrjälä 347791d14251STvrtko Ursulin ibx_hpd_irq_setup(dev_priv); 3478e4ce95aaSVille Syrjälä } 3479e4ce95aaSVille Syrjälä 34802ea63927SVille Syrjälä static u32 bxt_hotplug_enables(struct drm_i915_private *i915, 34812ea63927SVille Syrjälä enum hpd_pin pin) 34822ea63927SVille Syrjälä { 34832ea63927SVille Syrjälä u32 hotplug; 34842ea63927SVille Syrjälä 34852ea63927SVille Syrjälä switch (pin) { 34862ea63927SVille Syrjälä case HPD_PORT_A: 34872ea63927SVille Syrjälä hotplug = PORTA_HOTPLUG_ENABLE; 34882ea63927SVille Syrjälä if (intel_bios_is_port_hpd_inverted(i915, PORT_A)) 34892ea63927SVille Syrjälä hotplug |= BXT_DDIA_HPD_INVERT; 34902ea63927SVille Syrjälä return hotplug; 34912ea63927SVille Syrjälä case HPD_PORT_B: 34922ea63927SVille Syrjälä hotplug = PORTB_HOTPLUG_ENABLE; 34932ea63927SVille Syrjälä if (intel_bios_is_port_hpd_inverted(i915, PORT_B)) 34942ea63927SVille Syrjälä hotplug |= BXT_DDIB_HPD_INVERT; 34952ea63927SVille Syrjälä return hotplug; 34962ea63927SVille Syrjälä case HPD_PORT_C: 34972ea63927SVille Syrjälä hotplug = PORTC_HOTPLUG_ENABLE; 34982ea63927SVille Syrjälä if (intel_bios_is_port_hpd_inverted(i915, PORT_C)) 34992ea63927SVille Syrjälä hotplug |= BXT_DDIC_HPD_INVERT; 35002ea63927SVille Syrjälä return hotplug; 35012ea63927SVille Syrjälä default: 35022ea63927SVille Syrjälä return 0; 35032ea63927SVille Syrjälä } 35042ea63927SVille Syrjälä } 35052ea63927SVille Syrjälä 35062ea63927SVille Syrjälä static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) 3507e0a20ad7SShashank Sharma { 35082a57d9ccSImre Deak u32 hotplug; 3509e0a20ad7SShashank Sharma 35102939eb06SJani Nikula hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); 35112ea63927SVille Syrjälä hotplug &= ~(PORTA_HOTPLUG_ENABLE | 35122a57d9ccSImre Deak PORTB_HOTPLUG_ENABLE | 35132ea63927SVille Syrjälä PORTC_HOTPLUG_ENABLE | 35142ea63927SVille Syrjälä BXT_DDIA_HPD_INVERT | 35152ea63927SVille Syrjälä BXT_DDIB_HPD_INVERT | 35162ea63927SVille Syrjälä BXT_DDIC_HPD_INVERT); 35172ea63927SVille Syrjälä hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables); 35182939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); 3519e0a20ad7SShashank Sharma } 3520e0a20ad7SShashank Sharma 35212a57d9ccSImre Deak static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) 35222a57d9ccSImre Deak { 35232a57d9ccSImre Deak u32 hotplug_irqs, enabled_irqs; 35242a57d9ccSImre Deak 35250398993bSVille Syrjälä enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); 35266d3144ebSVille Syrjälä hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); 35272a57d9ccSImre Deak 35282a57d9ccSImre Deak bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); 35292a57d9ccSImre Deak 35302ea63927SVille Syrjälä bxt_hpd_detection_setup(dev_priv); 35312a57d9ccSImre Deak } 35322a57d9ccSImre Deak 3533a0a6d8cbSVille Syrjälä /* 3534a0a6d8cbSVille Syrjälä * SDEIER is also touched by the interrupt handler to work around missed PCH 3535a0a6d8cbSVille Syrjälä * interrupts. Hence we can't update it after the interrupt handler is enabled - 3536a0a6d8cbSVille Syrjälä * instead we unconditionally enable all PCH interrupt sources here, but then 3537a0a6d8cbSVille Syrjälä * only unmask them as needed with SDEIMR. 3538a0a6d8cbSVille Syrjälä * 3539a0a6d8cbSVille Syrjälä * Note that we currently do this after installing the interrupt handler, 3540a0a6d8cbSVille Syrjälä * but before we enable the master interrupt. That should be sufficient 3541a0a6d8cbSVille Syrjälä * to avoid races with the irq handler, assuming we have MSI. Shared legacy 3542a0a6d8cbSVille Syrjälä * interrupts could still race. 3543a0a6d8cbSVille Syrjälä */ 3544b318b824SVille Syrjälä static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) 3545d46da437SPaulo Zanoni { 3546a0a6d8cbSVille Syrjälä struct intel_uncore *uncore = &dev_priv->uncore; 354782a28bcfSDaniel Vetter u32 mask; 3548d46da437SPaulo Zanoni 35496e266956STvrtko Ursulin if (HAS_PCH_NOP(dev_priv)) 3550692a04cfSDaniel Vetter return; 3551692a04cfSDaniel Vetter 35526e266956STvrtko Ursulin if (HAS_PCH_IBX(dev_priv)) 35535c673b60SDaniel Vetter mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; 35544ebc6509SDhinakaran Pandiyan else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) 35555c673b60SDaniel Vetter mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; 35564ebc6509SDhinakaran Pandiyan else 35574ebc6509SDhinakaran Pandiyan mask = SDE_GMBUS_CPT; 35588664281bSPaulo Zanoni 3559a0a6d8cbSVille Syrjälä GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); 3560d46da437SPaulo Zanoni } 3561d46da437SPaulo Zanoni 35629eae5e27SLucas De Marchi static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) 3563036a4a7dSZhenyu Wang { 3564b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 35658e76f8dcSPaulo Zanoni u32 display_mask, extra_mask; 35668e76f8dcSPaulo Zanoni 3567b243f530STvrtko Ursulin if (INTEL_GEN(dev_priv) >= 7) { 35688e76f8dcSPaulo Zanoni display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 3569842ebf7aSVille Syrjälä DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB); 35708e76f8dcSPaulo Zanoni extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | 357123bb4cb5SVille Syrjälä DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | 357223bb4cb5SVille Syrjälä DE_DP_A_HOTPLUG_IVB); 35738e76f8dcSPaulo Zanoni } else { 35748e76f8dcSPaulo Zanoni display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 3575842ebf7aSVille Syrjälä DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE | 3576842ebf7aSVille Syrjälä DE_PIPEA_CRC_DONE | DE_POISON); 3577c6073d4cSVille Syrjälä extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | 3578e4ce95aaSVille Syrjälä DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | 3579e4ce95aaSVille Syrjälä DE_DP_A_HOTPLUG); 35808e76f8dcSPaulo Zanoni } 3581036a4a7dSZhenyu Wang 3582fc340442SDaniel Vetter if (IS_HASWELL(dev_priv)) { 3583b16b2a2fSPaulo Zanoni gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); 3584fc340442SDaniel Vetter display_mask |= DE_EDP_PSR_INT_HSW; 3585fc340442SDaniel Vetter } 3586fc340442SDaniel Vetter 3587c6073d4cSVille Syrjälä if (IS_IRONLAKE_M(dev_priv)) 3588c6073d4cSVille Syrjälä extra_mask |= DE_PCU_EVENT; 3589c6073d4cSVille Syrjälä 35901ec14ad3SChris Wilson dev_priv->irq_mask = ~display_mask; 3591036a4a7dSZhenyu Wang 3592a0a6d8cbSVille Syrjälä ibx_irq_postinstall(dev_priv); 3593622364b6SPaulo Zanoni 3594a9922912SVille Syrjälä gen5_gt_irq_postinstall(&dev_priv->gt); 3595a9922912SVille Syrjälä 3596b16b2a2fSPaulo Zanoni GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, 3597b16b2a2fSPaulo Zanoni display_mask | extra_mask); 3598036a4a7dSZhenyu Wang } 3599036a4a7dSZhenyu Wang 3600f8b79e58SImre Deak void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) 3601f8b79e58SImre Deak { 360267520415SChris Wilson lockdep_assert_held(&dev_priv->irq_lock); 3603f8b79e58SImre Deak 3604f8b79e58SImre Deak if (dev_priv->display_irqs_enabled) 3605f8b79e58SImre Deak return; 3606f8b79e58SImre Deak 3607f8b79e58SImre Deak dev_priv->display_irqs_enabled = true; 3608f8b79e58SImre Deak 3609d6c69803SVille Syrjälä if (intel_irqs_enabled(dev_priv)) { 3610d6c69803SVille Syrjälä vlv_display_irq_reset(dev_priv); 3611ad22d106SVille Syrjälä vlv_display_irq_postinstall(dev_priv); 3612f8b79e58SImre Deak } 3613d6c69803SVille Syrjälä } 3614f8b79e58SImre Deak 3615f8b79e58SImre Deak void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) 3616f8b79e58SImre Deak { 361767520415SChris Wilson lockdep_assert_held(&dev_priv->irq_lock); 3618f8b79e58SImre Deak 3619f8b79e58SImre Deak if (!dev_priv->display_irqs_enabled) 3620f8b79e58SImre Deak return; 3621f8b79e58SImre Deak 3622f8b79e58SImre Deak dev_priv->display_irqs_enabled = false; 3623f8b79e58SImre Deak 3624950eabafSImre Deak if (intel_irqs_enabled(dev_priv)) 3625ad22d106SVille Syrjälä vlv_display_irq_reset(dev_priv); 3626f8b79e58SImre Deak } 3627f8b79e58SImre Deak 36280e6c9a9eSVille Syrjälä 3629b318b824SVille Syrjälä static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) 36300e6c9a9eSVille Syrjälä { 3631cf1c97dcSAndi Shyti gen5_gt_irq_postinstall(&dev_priv->gt); 36327e231dbeSJesse Barnes 3633ad22d106SVille Syrjälä spin_lock_irq(&dev_priv->irq_lock); 36349918271eSVille Syrjälä if (dev_priv->display_irqs_enabled) 3635ad22d106SVille Syrjälä vlv_display_irq_postinstall(dev_priv); 3636ad22d106SVille Syrjälä spin_unlock_irq(&dev_priv->irq_lock); 3637ad22d106SVille Syrjälä 36382939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 36392939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); 364020afbda2SDaniel Vetter } 364120afbda2SDaniel Vetter 3642abd58f01SBen Widawsky static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 3643abd58f01SBen Widawsky { 3644b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 3645b16b2a2fSPaulo Zanoni 3646869129eeSMatt Roper u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | 3647869129eeSMatt Roper GEN8_PIPE_CDCLK_CRC_DONE; 3648a9c287c9SJani Nikula u32 de_pipe_enables; 3649054318c7SImre Deak u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); 36503a3b3c7dSVille Syrjälä u32 de_port_enables; 3651df0d28c1SDhinakaran Pandiyan u32 de_misc_masked = GEN8_DE_EDP_PSR; 3652562ddcb7SMatt Roper u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3653562ddcb7SMatt Roper BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 36543a3b3c7dSVille Syrjälä enum pipe pipe; 3655770de83dSDamien Lespiau 3656df0d28c1SDhinakaran Pandiyan if (INTEL_GEN(dev_priv) <= 10) 3657df0d28c1SDhinakaran Pandiyan de_misc_masked |= GEN8_DE_MISC_GSE; 3658df0d28c1SDhinakaran Pandiyan 3659cc3f90f0SAnder Conselvan de Oliveira if (IS_GEN9_LP(dev_priv)) 36603a3b3c7dSVille Syrjälä de_port_masked |= BXT_DE_PORT_GMBUS; 3661a324fcacSRodrigo Vivi 36629c9e97c4SVandita Kulkarni if (INTEL_GEN(dev_priv) >= 11) { 36639c9e97c4SVandita Kulkarni enum port port; 36649c9e97c4SVandita Kulkarni 36659c9e97c4SVandita Kulkarni if (intel_bios_is_dsi_present(dev_priv, &port)) 36669c9e97c4SVandita Kulkarni de_port_masked |= DSI0_TE | DSI1_TE; 36679c9e97c4SVandita Kulkarni } 36689c9e97c4SVandita Kulkarni 3669770de83dSDamien Lespiau de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | 3670770de83dSDamien Lespiau GEN8_PIPE_FIFO_UNDERRUN; 3671770de83dSDamien Lespiau 36721288f9b0SKarthik B S if (INTEL_GEN(dev_priv) >= 9) 36731288f9b0SKarthik B S de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; 36741288f9b0SKarthik B S 36753a3b3c7dSVille Syrjälä de_port_enables = de_port_masked; 3676cc3f90f0SAnder Conselvan de Oliveira if (IS_GEN9_LP(dev_priv)) 3677a52bb15bSVille Syrjälä de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; 3678a52bb15bSVille Syrjälä else if (IS_BROADWELL(dev_priv)) 3679e5abaab3SVille Syrjälä de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK; 36803a3b3c7dSVille Syrjälä 36818241cfbeSJosé Roberto de Souza if (INTEL_GEN(dev_priv) >= 12) { 36828241cfbeSJosé Roberto de Souza enum transcoder trans; 36838241cfbeSJosé Roberto de Souza 3684562ddcb7SMatt Roper for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { 36858241cfbeSJosé Roberto de Souza enum intel_display_power_domain domain; 36868241cfbeSJosé Roberto de Souza 36878241cfbeSJosé Roberto de Souza domain = POWER_DOMAIN_TRANSCODER(trans); 36888241cfbeSJosé Roberto de Souza if (!intel_display_power_is_enabled(dev_priv, domain)) 36898241cfbeSJosé Roberto de Souza continue; 36908241cfbeSJosé Roberto de Souza 36918241cfbeSJosé Roberto de Souza gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans)); 36928241cfbeSJosé Roberto de Souza } 36938241cfbeSJosé Roberto de Souza } else { 3694b16b2a2fSPaulo Zanoni gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); 36958241cfbeSJosé Roberto de Souza } 3696e04f7eceSVille Syrjälä 36970a195c02SMika Kahola for_each_pipe(dev_priv, pipe) { 36980a195c02SMika Kahola dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; 3699abd58f01SBen Widawsky 3700f458ebbcSDaniel Vetter if (intel_display_power_is_enabled(dev_priv, 3701813bde43SPaulo Zanoni POWER_DOMAIN_PIPE(pipe))) 3702b16b2a2fSPaulo Zanoni GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, 3703813bde43SPaulo Zanoni dev_priv->de_irq_mask[pipe], 370435079899SPaulo Zanoni de_pipe_enables); 37050a195c02SMika Kahola } 3706abd58f01SBen Widawsky 3707b16b2a2fSPaulo Zanoni GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables); 3708b16b2a2fSPaulo Zanoni GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); 37092a57d9ccSImre Deak 3710121e758eSDhinakaran Pandiyan if (INTEL_GEN(dev_priv) >= 11) { 3711121e758eSDhinakaran Pandiyan u32 de_hpd_masked = 0; 3712b796b971SDhinakaran Pandiyan u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | 3713b796b971SDhinakaran Pandiyan GEN11_DE_TBT_HOTPLUG_MASK; 3714121e758eSDhinakaran Pandiyan 3715b16b2a2fSPaulo Zanoni GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, 3716b16b2a2fSPaulo Zanoni de_hpd_enables); 3717abd58f01SBen Widawsky } 3718121e758eSDhinakaran Pandiyan } 3719abd58f01SBen Widawsky 3720b318b824SVille Syrjälä static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) 3721abd58f01SBen Widawsky { 37226e266956STvrtko Ursulin if (HAS_PCH_SPLIT(dev_priv)) 3723a0a6d8cbSVille Syrjälä ibx_irq_postinstall(dev_priv); 3724622364b6SPaulo Zanoni 3725cf1c97dcSAndi Shyti gen8_gt_irq_postinstall(&dev_priv->gt); 3726abd58f01SBen Widawsky gen8_de_irq_postinstall(dev_priv); 3727abd58f01SBen Widawsky 372825286aacSDaniele Ceraolo Spurio gen8_master_intr_enable(dev_priv->uncore.regs); 3729abd58f01SBen Widawsky } 3730abd58f01SBen Widawsky 3731b318b824SVille Syrjälä static void icp_irq_postinstall(struct drm_i915_private *dev_priv) 373231604222SAnusha Srivatsa { 37339696f041SVille Syrjälä struct intel_uncore *uncore = &dev_priv->uncore; 373431604222SAnusha Srivatsa u32 mask = SDE_GMBUS_ICP; 373531604222SAnusha Srivatsa 37369696f041SVille Syrjälä GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); 373731604222SAnusha Srivatsa } 373831604222SAnusha Srivatsa 3739b318b824SVille Syrjälä static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) 374051951ae7SMika Kuoppala { 3741b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 3742df0d28c1SDhinakaran Pandiyan u32 gu_misc_masked = GEN11_GU_MISC_GSE; 374351951ae7SMika Kuoppala 374429b43ae2SRodrigo Vivi if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3745b318b824SVille Syrjälä icp_irq_postinstall(dev_priv); 374631604222SAnusha Srivatsa 37479b77011eSTvrtko Ursulin gen11_gt_irq_postinstall(&dev_priv->gt); 374851951ae7SMika Kuoppala gen8_de_irq_postinstall(dev_priv); 374951951ae7SMika Kuoppala 3750b16b2a2fSPaulo Zanoni GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); 3751df0d28c1SDhinakaran Pandiyan 37522939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); 375351951ae7SMika Kuoppala 375497b492f5SLucas De Marchi if (HAS_MASTER_UNIT_IRQ(dev_priv)) { 375597b492f5SLucas De Marchi dg1_master_intr_enable(uncore->regs); 37562939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR); 375797b492f5SLucas De Marchi } else { 37589b77011eSTvrtko Ursulin gen11_master_intr_enable(uncore->regs); 37592939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ); 376051951ae7SMika Kuoppala } 376197b492f5SLucas De Marchi } 376251951ae7SMika Kuoppala 3763b318b824SVille Syrjälä static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) 376443f328d7SVille Syrjälä { 3765cf1c97dcSAndi Shyti gen8_gt_irq_postinstall(&dev_priv->gt); 376643f328d7SVille Syrjälä 3767ad22d106SVille Syrjälä spin_lock_irq(&dev_priv->irq_lock); 37689918271eSVille Syrjälä if (dev_priv->display_irqs_enabled) 3769ad22d106SVille Syrjälä vlv_display_irq_postinstall(dev_priv); 3770ad22d106SVille Syrjälä spin_unlock_irq(&dev_priv->irq_lock); 3771ad22d106SVille Syrjälä 37722939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 37732939eb06SJani Nikula intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); 377443f328d7SVille Syrjälä } 377543f328d7SVille Syrjälä 3776b318b824SVille Syrjälä static void i8xx_irq_reset(struct drm_i915_private *dev_priv) 3777c2798b19SChris Wilson { 3778b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 3779c2798b19SChris Wilson 378044d9241eSVille Syrjälä i9xx_pipestat_irq_reset(dev_priv); 378144d9241eSVille Syrjälä 3782b16b2a2fSPaulo Zanoni GEN2_IRQ_RESET(uncore); 3783e44adb5dSChris Wilson dev_priv->irq_mask = ~0u; 3784c2798b19SChris Wilson } 3785c2798b19SChris Wilson 3786b318b824SVille Syrjälä static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv) 3787c2798b19SChris Wilson { 3788b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 3789e9e9848aSVille Syrjälä u16 enable_mask; 3790c2798b19SChris Wilson 37914f5fd91fSTvrtko Ursulin intel_uncore_write16(uncore, 37924f5fd91fSTvrtko Ursulin EMR, 37934f5fd91fSTvrtko Ursulin ~(I915_ERROR_PAGE_TABLE | 3794045cebd2SVille Syrjälä I915_ERROR_MEMORY_REFRESH)); 3795c2798b19SChris Wilson 3796c2798b19SChris Wilson /* Unmask the interrupts that we always want on. */ 3797c2798b19SChris Wilson dev_priv->irq_mask = 3798c2798b19SChris Wilson ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 379916659bc5SVille Syrjälä I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 380016659bc5SVille Syrjälä I915_MASTER_ERROR_INTERRUPT); 3801c2798b19SChris Wilson 3802e9e9848aSVille Syrjälä enable_mask = 3803c2798b19SChris Wilson I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3804c2798b19SChris Wilson I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 380516659bc5SVille Syrjälä I915_MASTER_ERROR_INTERRUPT | 3806e9e9848aSVille Syrjälä I915_USER_INTERRUPT; 3807e9e9848aSVille Syrjälä 3808b16b2a2fSPaulo Zanoni GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask); 3809c2798b19SChris Wilson 3810379ef82dSDaniel Vetter /* Interrupt setup is already guaranteed to be single-threaded, this is 3811379ef82dSDaniel Vetter * just to make the assert_spin_locked check happy. */ 3812d6207435SDaniel Vetter spin_lock_irq(&dev_priv->irq_lock); 3813755e9019SImre Deak i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 3814755e9019SImre Deak i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 3815d6207435SDaniel Vetter spin_unlock_irq(&dev_priv->irq_lock); 3816c2798b19SChris Wilson } 3817c2798b19SChris Wilson 38184f5fd91fSTvrtko Ursulin static void i8xx_error_irq_ack(struct drm_i915_private *i915, 381978c357ddSVille Syrjälä u16 *eir, u16 *eir_stuck) 382078c357ddSVille Syrjälä { 38214f5fd91fSTvrtko Ursulin struct intel_uncore *uncore = &i915->uncore; 382278c357ddSVille Syrjälä u16 emr; 382378c357ddSVille Syrjälä 38244f5fd91fSTvrtko Ursulin *eir = intel_uncore_read16(uncore, EIR); 382578c357ddSVille Syrjälä 382678c357ddSVille Syrjälä if (*eir) 38274f5fd91fSTvrtko Ursulin intel_uncore_write16(uncore, EIR, *eir); 382878c357ddSVille Syrjälä 38294f5fd91fSTvrtko Ursulin *eir_stuck = intel_uncore_read16(uncore, EIR); 383078c357ddSVille Syrjälä if (*eir_stuck == 0) 383178c357ddSVille Syrjälä return; 383278c357ddSVille Syrjälä 383378c357ddSVille Syrjälä /* 383478c357ddSVille Syrjälä * Toggle all EMR bits to make sure we get an edge 383578c357ddSVille Syrjälä * in the ISR master error bit if we don't clear 383678c357ddSVille Syrjälä * all the EIR bits. Otherwise the edge triggered 383778c357ddSVille Syrjälä * IIR on i965/g4x wouldn't notice that an interrupt 383878c357ddSVille Syrjälä * is still pending. Also some EIR bits can't be 383978c357ddSVille Syrjälä * cleared except by handling the underlying error 384078c357ddSVille Syrjälä * (or by a GPU reset) so we mask any bit that 384178c357ddSVille Syrjälä * remains set. 384278c357ddSVille Syrjälä */ 38434f5fd91fSTvrtko Ursulin emr = intel_uncore_read16(uncore, EMR); 38444f5fd91fSTvrtko Ursulin intel_uncore_write16(uncore, EMR, 0xffff); 38454f5fd91fSTvrtko Ursulin intel_uncore_write16(uncore, EMR, emr | *eir_stuck); 384678c357ddSVille Syrjälä } 384778c357ddSVille Syrjälä 384878c357ddSVille Syrjälä static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv, 384978c357ddSVille Syrjälä u16 eir, u16 eir_stuck) 385078c357ddSVille Syrjälä { 385178c357ddSVille Syrjälä DRM_DEBUG("Master Error: EIR 0x%04x\n", eir); 385278c357ddSVille Syrjälä 385378c357ddSVille Syrjälä if (eir_stuck) 385400376ccfSWambui Karuga drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n", 385500376ccfSWambui Karuga eir_stuck); 385678c357ddSVille Syrjälä } 385778c357ddSVille Syrjälä 385878c357ddSVille Syrjälä static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, 385978c357ddSVille Syrjälä u32 *eir, u32 *eir_stuck) 386078c357ddSVille Syrjälä { 386178c357ddSVille Syrjälä u32 emr; 386278c357ddSVille Syrjälä 38632939eb06SJani Nikula *eir = intel_uncore_read(&dev_priv->uncore, EIR); 386478c357ddSVille Syrjälä 38652939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, EIR, *eir); 386678c357ddSVille Syrjälä 38672939eb06SJani Nikula *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); 386878c357ddSVille Syrjälä if (*eir_stuck == 0) 386978c357ddSVille Syrjälä return; 387078c357ddSVille Syrjälä 387178c357ddSVille Syrjälä /* 387278c357ddSVille Syrjälä * Toggle all EMR bits to make sure we get an edge 387378c357ddSVille Syrjälä * in the ISR master error bit if we don't clear 387478c357ddSVille Syrjälä * all the EIR bits. Otherwise the edge triggered 387578c357ddSVille Syrjälä * IIR on i965/g4x wouldn't notice that an interrupt 387678c357ddSVille Syrjälä * is still pending. Also some EIR bits can't be 387778c357ddSVille Syrjälä * cleared except by handling the underlying error 387878c357ddSVille Syrjälä * (or by a GPU reset) so we mask any bit that 387978c357ddSVille Syrjälä * remains set. 388078c357ddSVille Syrjälä */ 38812939eb06SJani Nikula emr = intel_uncore_read(&dev_priv->uncore, EMR); 38822939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff); 38832939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck); 388478c357ddSVille Syrjälä } 388578c357ddSVille Syrjälä 388678c357ddSVille Syrjälä static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, 388778c357ddSVille Syrjälä u32 eir, u32 eir_stuck) 388878c357ddSVille Syrjälä { 388978c357ddSVille Syrjälä DRM_DEBUG("Master Error, EIR 0x%08x\n", eir); 389078c357ddSVille Syrjälä 389178c357ddSVille Syrjälä if (eir_stuck) 389200376ccfSWambui Karuga drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n", 389300376ccfSWambui Karuga eir_stuck); 389478c357ddSVille Syrjälä } 389578c357ddSVille Syrjälä 3896ff1f525eSDaniel Vetter static irqreturn_t i8xx_irq_handler(int irq, void *arg) 3897c2798b19SChris Wilson { 3898b318b824SVille Syrjälä struct drm_i915_private *dev_priv = arg; 3899af722d28SVille Syrjälä irqreturn_t ret = IRQ_NONE; 3900c2798b19SChris Wilson 39012dd2a883SImre Deak if (!intel_irqs_enabled(dev_priv)) 39022dd2a883SImre Deak return IRQ_NONE; 39032dd2a883SImre Deak 39041f814dacSImre Deak /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 39059102650fSDaniele Ceraolo Spurio disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 39061f814dacSImre Deak 3907af722d28SVille Syrjälä do { 3908af722d28SVille Syrjälä u32 pipe_stats[I915_MAX_PIPES] = {}; 390978c357ddSVille Syrjälä u16 eir = 0, eir_stuck = 0; 3910af722d28SVille Syrjälä u16 iir; 3911af722d28SVille Syrjälä 39124f5fd91fSTvrtko Ursulin iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR); 3913c2798b19SChris Wilson if (iir == 0) 3914af722d28SVille Syrjälä break; 3915c2798b19SChris Wilson 3916af722d28SVille Syrjälä ret = IRQ_HANDLED; 3917c2798b19SChris Wilson 3918eb64343cSVille Syrjälä /* Call regardless, as some status bits might not be 3919eb64343cSVille Syrjälä * signalled in iir */ 3920eb64343cSVille Syrjälä i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 3921c2798b19SChris Wilson 392278c357ddSVille Syrjälä if (iir & I915_MASTER_ERROR_INTERRUPT) 392378c357ddSVille Syrjälä i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 392478c357ddSVille Syrjälä 39254f5fd91fSTvrtko Ursulin intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); 3926c2798b19SChris Wilson 3927c2798b19SChris Wilson if (iir & I915_USER_INTERRUPT) 392873c8bfb7SChris Wilson intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); 3929c2798b19SChris Wilson 393078c357ddSVille Syrjälä if (iir & I915_MASTER_ERROR_INTERRUPT) 393178c357ddSVille Syrjälä i8xx_error_irq_handler(dev_priv, eir, eir_stuck); 3932af722d28SVille Syrjälä 3933eb64343cSVille Syrjälä i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); 3934af722d28SVille Syrjälä } while (0); 3935c2798b19SChris Wilson 39369c6508b9SThomas Gleixner pmu_irq_stats(dev_priv, ret); 39379c6508b9SThomas Gleixner 39389102650fSDaniele Ceraolo Spurio enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 39391f814dacSImre Deak 39401f814dacSImre Deak return ret; 3941c2798b19SChris Wilson } 3942c2798b19SChris Wilson 3943b318b824SVille Syrjälä static void i915_irq_reset(struct drm_i915_private *dev_priv) 3944a266c7d5SChris Wilson { 3945b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 3946a266c7d5SChris Wilson 394756b857a5STvrtko Ursulin if (I915_HAS_HOTPLUG(dev_priv)) { 39480706f17cSEgbert Eich i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); 39492939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); 3950a266c7d5SChris Wilson } 3951a266c7d5SChris Wilson 395244d9241eSVille Syrjälä i9xx_pipestat_irq_reset(dev_priv); 395344d9241eSVille Syrjälä 3954b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, GEN2_); 3955e44adb5dSChris Wilson dev_priv->irq_mask = ~0u; 3956a266c7d5SChris Wilson } 3957a266c7d5SChris Wilson 3958b318b824SVille Syrjälä static void i915_irq_postinstall(struct drm_i915_private *dev_priv) 3959a266c7d5SChris Wilson { 3960b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 396138bde180SChris Wilson u32 enable_mask; 3962a266c7d5SChris Wilson 39632939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE | 3964045cebd2SVille Syrjälä I915_ERROR_MEMORY_REFRESH)); 396538bde180SChris Wilson 396638bde180SChris Wilson /* Unmask the interrupts that we always want on. */ 396738bde180SChris Wilson dev_priv->irq_mask = 396838bde180SChris Wilson ~(I915_ASLE_INTERRUPT | 396938bde180SChris Wilson I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 397016659bc5SVille Syrjälä I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 397116659bc5SVille Syrjälä I915_MASTER_ERROR_INTERRUPT); 397238bde180SChris Wilson 397338bde180SChris Wilson enable_mask = 397438bde180SChris Wilson I915_ASLE_INTERRUPT | 397538bde180SChris Wilson I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 397638bde180SChris Wilson I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 397716659bc5SVille Syrjälä I915_MASTER_ERROR_INTERRUPT | 397838bde180SChris Wilson I915_USER_INTERRUPT; 397938bde180SChris Wilson 398056b857a5STvrtko Ursulin if (I915_HAS_HOTPLUG(dev_priv)) { 3981a266c7d5SChris Wilson /* Enable in IER... */ 3982a266c7d5SChris Wilson enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 3983a266c7d5SChris Wilson /* and unmask in IMR */ 3984a266c7d5SChris Wilson dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 3985a266c7d5SChris Wilson } 3986a266c7d5SChris Wilson 3987b16b2a2fSPaulo Zanoni GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); 3988a266c7d5SChris Wilson 3989379ef82dSDaniel Vetter /* Interrupt setup is already guaranteed to be single-threaded, this is 3990379ef82dSDaniel Vetter * just to make the assert_spin_locked check happy. */ 3991d6207435SDaniel Vetter spin_lock_irq(&dev_priv->irq_lock); 3992755e9019SImre Deak i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 3993755e9019SImre Deak i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 3994d6207435SDaniel Vetter spin_unlock_irq(&dev_priv->irq_lock); 3995379ef82dSDaniel Vetter 3996c30bb1fdSVille Syrjälä i915_enable_asle_pipestat(dev_priv); 399720afbda2SDaniel Vetter } 399820afbda2SDaniel Vetter 3999ff1f525eSDaniel Vetter static irqreturn_t i915_irq_handler(int irq, void *arg) 4000a266c7d5SChris Wilson { 4001b318b824SVille Syrjälä struct drm_i915_private *dev_priv = arg; 4002af722d28SVille Syrjälä irqreturn_t ret = IRQ_NONE; 4003a266c7d5SChris Wilson 40042dd2a883SImre Deak if (!intel_irqs_enabled(dev_priv)) 40052dd2a883SImre Deak return IRQ_NONE; 40062dd2a883SImre Deak 40071f814dacSImre Deak /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 40089102650fSDaniele Ceraolo Spurio disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 40091f814dacSImre Deak 401038bde180SChris Wilson do { 4011eb64343cSVille Syrjälä u32 pipe_stats[I915_MAX_PIPES] = {}; 401278c357ddSVille Syrjälä u32 eir = 0, eir_stuck = 0; 4013af722d28SVille Syrjälä u32 hotplug_status = 0; 4014af722d28SVille Syrjälä u32 iir; 4015a266c7d5SChris Wilson 40162939eb06SJani Nikula iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 4017af722d28SVille Syrjälä if (iir == 0) 4018af722d28SVille Syrjälä break; 4019af722d28SVille Syrjälä 4020af722d28SVille Syrjälä ret = IRQ_HANDLED; 4021af722d28SVille Syrjälä 4022af722d28SVille Syrjälä if (I915_HAS_HOTPLUG(dev_priv) && 4023af722d28SVille Syrjälä iir & I915_DISPLAY_PORT_INTERRUPT) 4024af722d28SVille Syrjälä hotplug_status = i9xx_hpd_irq_ack(dev_priv); 4025a266c7d5SChris Wilson 4026eb64343cSVille Syrjälä /* Call regardless, as some status bits might not be 4027eb64343cSVille Syrjälä * signalled in iir */ 4028eb64343cSVille Syrjälä i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 4029a266c7d5SChris Wilson 403078c357ddSVille Syrjälä if (iir & I915_MASTER_ERROR_INTERRUPT) 403178c357ddSVille Syrjälä i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 403278c357ddSVille Syrjälä 40332939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 4034a266c7d5SChris Wilson 4035a266c7d5SChris Wilson if (iir & I915_USER_INTERRUPT) 403673c8bfb7SChris Wilson intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); 4037a266c7d5SChris Wilson 403878c357ddSVille Syrjälä if (iir & I915_MASTER_ERROR_INTERRUPT) 403978c357ddSVille Syrjälä i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 4040a266c7d5SChris Wilson 4041af722d28SVille Syrjälä if (hotplug_status) 4042af722d28SVille Syrjälä i9xx_hpd_irq_handler(dev_priv, hotplug_status); 4043af722d28SVille Syrjälä 4044af722d28SVille Syrjälä i915_pipestat_irq_handler(dev_priv, iir, pipe_stats); 4045af722d28SVille Syrjälä } while (0); 4046a266c7d5SChris Wilson 40479c6508b9SThomas Gleixner pmu_irq_stats(dev_priv, ret); 40489c6508b9SThomas Gleixner 40499102650fSDaniele Ceraolo Spurio enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 40501f814dacSImre Deak 4051a266c7d5SChris Wilson return ret; 4052a266c7d5SChris Wilson } 4053a266c7d5SChris Wilson 4054b318b824SVille Syrjälä static void i965_irq_reset(struct drm_i915_private *dev_priv) 4055a266c7d5SChris Wilson { 4056b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 4057a266c7d5SChris Wilson 40580706f17cSEgbert Eich i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); 40592939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); 4060a266c7d5SChris Wilson 406144d9241eSVille Syrjälä i9xx_pipestat_irq_reset(dev_priv); 406244d9241eSVille Syrjälä 4063b16b2a2fSPaulo Zanoni GEN3_IRQ_RESET(uncore, GEN2_); 4064e44adb5dSChris Wilson dev_priv->irq_mask = ~0u; 4065a266c7d5SChris Wilson } 4066a266c7d5SChris Wilson 4067b318b824SVille Syrjälä static void i965_irq_postinstall(struct drm_i915_private *dev_priv) 4068a266c7d5SChris Wilson { 4069b16b2a2fSPaulo Zanoni struct intel_uncore *uncore = &dev_priv->uncore; 4070bbba0a97SChris Wilson u32 enable_mask; 4071a266c7d5SChris Wilson u32 error_mask; 4072a266c7d5SChris Wilson 4073045cebd2SVille Syrjälä /* 4074045cebd2SVille Syrjälä * Enable some error detection, note the instruction error mask 4075045cebd2SVille Syrjälä * bit is reserved, so we leave it masked. 4076045cebd2SVille Syrjälä */ 4077045cebd2SVille Syrjälä if (IS_G4X(dev_priv)) { 4078045cebd2SVille Syrjälä error_mask = ~(GM45_ERROR_PAGE_TABLE | 4079045cebd2SVille Syrjälä GM45_ERROR_MEM_PRIV | 4080045cebd2SVille Syrjälä GM45_ERROR_CP_PRIV | 4081045cebd2SVille Syrjälä I915_ERROR_MEMORY_REFRESH); 4082045cebd2SVille Syrjälä } else { 4083045cebd2SVille Syrjälä error_mask = ~(I915_ERROR_PAGE_TABLE | 4084045cebd2SVille Syrjälä I915_ERROR_MEMORY_REFRESH); 4085045cebd2SVille Syrjälä } 40862939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, EMR, error_mask); 4087045cebd2SVille Syrjälä 4088a266c7d5SChris Wilson /* Unmask the interrupts that we always want on. */ 4089c30bb1fdSVille Syrjälä dev_priv->irq_mask = 4090c30bb1fdSVille Syrjälä ~(I915_ASLE_INTERRUPT | 4091adca4730SChris Wilson I915_DISPLAY_PORT_INTERRUPT | 4092bbba0a97SChris Wilson I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 4093bbba0a97SChris Wilson I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 409478c357ddSVille Syrjälä I915_MASTER_ERROR_INTERRUPT); 4095bbba0a97SChris Wilson 4096c30bb1fdSVille Syrjälä enable_mask = 4097c30bb1fdSVille Syrjälä I915_ASLE_INTERRUPT | 4098c30bb1fdSVille Syrjälä I915_DISPLAY_PORT_INTERRUPT | 4099c30bb1fdSVille Syrjälä I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 4100c30bb1fdSVille Syrjälä I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 410178c357ddSVille Syrjälä I915_MASTER_ERROR_INTERRUPT | 4102c30bb1fdSVille Syrjälä I915_USER_INTERRUPT; 4103bbba0a97SChris Wilson 410491d14251STvrtko Ursulin if (IS_G4X(dev_priv)) 4105bbba0a97SChris Wilson enable_mask |= I915_BSD_USER_INTERRUPT; 4106a266c7d5SChris Wilson 4107b16b2a2fSPaulo Zanoni GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); 4108c30bb1fdSVille Syrjälä 4109b79480baSDaniel Vetter /* Interrupt setup is already guaranteed to be single-threaded, this is 4110b79480baSDaniel Vetter * just to make the assert_spin_locked check happy. */ 4111d6207435SDaniel Vetter spin_lock_irq(&dev_priv->irq_lock); 4112755e9019SImre Deak i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 4113755e9019SImre Deak i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); 4114755e9019SImre Deak i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); 4115d6207435SDaniel Vetter spin_unlock_irq(&dev_priv->irq_lock); 4116a266c7d5SChris Wilson 411791d14251STvrtko Ursulin i915_enable_asle_pipestat(dev_priv); 411820afbda2SDaniel Vetter } 411920afbda2SDaniel Vetter 412091d14251STvrtko Ursulin static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) 412120afbda2SDaniel Vetter { 412220afbda2SDaniel Vetter u32 hotplug_en; 412320afbda2SDaniel Vetter 412467520415SChris Wilson lockdep_assert_held(&dev_priv->irq_lock); 4125b5ea2d56SDaniel Vetter 4126adca4730SChris Wilson /* Note HDMI and DP share hotplug bits */ 4127e5868a31SEgbert Eich /* enable bits are the same for all generations */ 412891d14251STvrtko Ursulin hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); 4129a266c7d5SChris Wilson /* Programming the CRT detection parameters tends 4130a266c7d5SChris Wilson to generate a spurious hotplug event about three 4131a266c7d5SChris Wilson seconds later. So just do it once. 4132a266c7d5SChris Wilson */ 413391d14251STvrtko Ursulin if (IS_G4X(dev_priv)) 4134a266c7d5SChris Wilson hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 4135a266c7d5SChris Wilson hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 4136a266c7d5SChris Wilson 4137a266c7d5SChris Wilson /* Ignore TV since it's buggy */ 41380706f17cSEgbert Eich i915_hotplug_interrupt_update_locked(dev_priv, 4139f9e3dc78SJani Nikula HOTPLUG_INT_EN_MASK | 4140f9e3dc78SJani Nikula CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | 4141f9e3dc78SJani Nikula CRT_HOTPLUG_ACTIVATION_PERIOD_64, 41420706f17cSEgbert Eich hotplug_en); 4143a266c7d5SChris Wilson } 4144a266c7d5SChris Wilson 4145ff1f525eSDaniel Vetter static irqreturn_t i965_irq_handler(int irq, void *arg) 4146a266c7d5SChris Wilson { 4147b318b824SVille Syrjälä struct drm_i915_private *dev_priv = arg; 4148af722d28SVille Syrjälä irqreturn_t ret = IRQ_NONE; 4149a266c7d5SChris Wilson 41502dd2a883SImre Deak if (!intel_irqs_enabled(dev_priv)) 41512dd2a883SImre Deak return IRQ_NONE; 41522dd2a883SImre Deak 41531f814dacSImre Deak /* IRQs are synced during runtime_suspend, we don't require a wakeref */ 41549102650fSDaniele Ceraolo Spurio disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 41551f814dacSImre Deak 4156af722d28SVille Syrjälä do { 4157eb64343cSVille Syrjälä u32 pipe_stats[I915_MAX_PIPES] = {}; 415878c357ddSVille Syrjälä u32 eir = 0, eir_stuck = 0; 4159af722d28SVille Syrjälä u32 hotplug_status = 0; 4160af722d28SVille Syrjälä u32 iir; 41612c8ba29fSChris Wilson 41622939eb06SJani Nikula iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); 4163af722d28SVille Syrjälä if (iir == 0) 4164af722d28SVille Syrjälä break; 4165af722d28SVille Syrjälä 4166af722d28SVille Syrjälä ret = IRQ_HANDLED; 4167af722d28SVille Syrjälä 4168af722d28SVille Syrjälä if (iir & I915_DISPLAY_PORT_INTERRUPT) 4169af722d28SVille Syrjälä hotplug_status = i9xx_hpd_irq_ack(dev_priv); 4170a266c7d5SChris Wilson 4171eb64343cSVille Syrjälä /* Call regardless, as some status bits might not be 4172eb64343cSVille Syrjälä * signalled in iir */ 4173eb64343cSVille Syrjälä i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); 4174a266c7d5SChris Wilson 417578c357ddSVille Syrjälä if (iir & I915_MASTER_ERROR_INTERRUPT) 417678c357ddSVille Syrjälä i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); 417778c357ddSVille Syrjälä 41782939eb06SJani Nikula intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); 4179a266c7d5SChris Wilson 4180a266c7d5SChris Wilson if (iir & I915_USER_INTERRUPT) 418173c8bfb7SChris Wilson intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); 4182af722d28SVille Syrjälä 4183a266c7d5SChris Wilson if (iir & I915_BSD_USER_INTERRUPT) 418473c8bfb7SChris Wilson intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]); 4185a266c7d5SChris Wilson 418678c357ddSVille Syrjälä if (iir & I915_MASTER_ERROR_INTERRUPT) 418778c357ddSVille Syrjälä i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 4188515ac2bbSDaniel Vetter 4189af722d28SVille Syrjälä if (hotplug_status) 4190af722d28SVille Syrjälä i9xx_hpd_irq_handler(dev_priv, hotplug_status); 4191af722d28SVille Syrjälä 4192af722d28SVille Syrjälä i965_pipestat_irq_handler(dev_priv, iir, pipe_stats); 4193af722d28SVille Syrjälä } while (0); 4194a266c7d5SChris Wilson 41959c6508b9SThomas Gleixner pmu_irq_stats(dev_priv, IRQ_HANDLED); 41969c6508b9SThomas Gleixner 41979102650fSDaniele Ceraolo Spurio enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 41981f814dacSImre Deak 4199a266c7d5SChris Wilson return ret; 4200a266c7d5SChris Wilson } 4201a266c7d5SChris Wilson 4202fca52a55SDaniel Vetter /** 4203fca52a55SDaniel Vetter * intel_irq_init - initializes irq support 4204fca52a55SDaniel Vetter * @dev_priv: i915 device instance 4205fca52a55SDaniel Vetter * 4206fca52a55SDaniel Vetter * This function initializes all the irq support including work items, timers 4207fca52a55SDaniel Vetter * and all the vtables. It does not setup the interrupt itself though. 4208fca52a55SDaniel Vetter */ 4209b963291cSDaniel Vetter void intel_irq_init(struct drm_i915_private *dev_priv) 4210f71d4af4SJesse Barnes { 421191c8a326SChris Wilson struct drm_device *dev = &dev_priv->drm; 4212cefcff8fSJoonas Lahtinen int i; 42138b2e326dSChris Wilson 421474bb98baSLucas De Marchi INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work); 4215cefcff8fSJoonas Lahtinen for (i = 0; i < MAX_L3_SLICES; ++i) 4216cefcff8fSJoonas Lahtinen dev_priv->l3_parity.remap_info[i] = NULL; 42178b2e326dSChris Wilson 4218633023a4SDaniele Ceraolo Spurio /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */ 4219702668e6SDaniele Ceraolo Spurio if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11) 42202239e6dfSDaniele Ceraolo Spurio dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16; 422126705e20SSagar Arun Kamble 42229a450b68SLucas De Marchi if (!HAS_DISPLAY(dev_priv)) 42239a450b68SLucas De Marchi return; 42249a450b68SLucas De Marchi 422596bd87b7SLucas De Marchi intel_hpd_init_pins(dev_priv); 422696bd87b7SLucas De Marchi 422796bd87b7SLucas De Marchi intel_hpd_init_work(dev_priv); 422896bd87b7SLucas De Marchi 422921da2700SVille Syrjälä dev->vblank_disable_immediate = true; 423021da2700SVille Syrjälä 4231262fd485SChris Wilson /* Most platforms treat the display irq block as an always-on 4232262fd485SChris Wilson * power domain. vlv/chv can disable it at runtime and need 4233262fd485SChris Wilson * special care to avoid writing any of the display block registers 4234262fd485SChris Wilson * outside of the power domain. We defer setting up the display irqs 4235262fd485SChris Wilson * in this case to the runtime pm. 4236262fd485SChris Wilson */ 4237262fd485SChris Wilson dev_priv->display_irqs_enabled = true; 4238262fd485SChris Wilson if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4239262fd485SChris Wilson dev_priv->display_irqs_enabled = false; 4240262fd485SChris Wilson 4241317eaa95SLyude dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD; 42429a64c650SLyude Paul /* If we have MST support, we want to avoid doing short HPD IRQ storm 42439a64c650SLyude Paul * detection, as short HPD storms will occur as a natural part of 42449a64c650SLyude Paul * sideband messaging with MST. 42459a64c650SLyude Paul * On older platforms however, IRQ storms can occur with both long and 42469a64c650SLyude Paul * short pulses, as seen on some G4x systems. 42479a64c650SLyude Paul */ 42489a64c650SLyude Paul dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv); 4249317eaa95SLyude 42502ccf2e03SChris Wilson if (HAS_GMCH(dev_priv)) { 42512ccf2e03SChris Wilson if (I915_HAS_HOTPLUG(dev_priv)) 42522ccf2e03SChris Wilson dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 42532ccf2e03SChris Wilson } else { 4254229f31e2SLucas De Marchi if (HAS_PCH_DG1(dev_priv)) 4255229f31e2SLucas De Marchi dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup; 42568ef7e340SMatt Roper else if (INTEL_GEN(dev_priv) >= 11) 4257121e758eSDhinakaran Pandiyan dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup; 4258b318b824SVille Syrjälä else if (IS_GEN9_LP(dev_priv)) 4259e0a20ad7SShashank Sharma dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; 4260c6c30b91SRodrigo Vivi else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) 42616dbf30ceSVille Syrjälä dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; 42626dbf30ceSVille Syrjälä else 42633a3b3c7dSVille Syrjälä dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; 4264f71d4af4SJesse Barnes } 42652ccf2e03SChris Wilson } 426620afbda2SDaniel Vetter 4267fca52a55SDaniel Vetter /** 4268cefcff8fSJoonas Lahtinen * intel_irq_fini - deinitializes IRQ support 4269cefcff8fSJoonas Lahtinen * @i915: i915 device instance 4270cefcff8fSJoonas Lahtinen * 4271cefcff8fSJoonas Lahtinen * This function deinitializes all the IRQ support. 4272cefcff8fSJoonas Lahtinen */ 4273cefcff8fSJoonas Lahtinen void intel_irq_fini(struct drm_i915_private *i915) 4274cefcff8fSJoonas Lahtinen { 4275cefcff8fSJoonas Lahtinen int i; 4276cefcff8fSJoonas Lahtinen 4277cefcff8fSJoonas Lahtinen for (i = 0; i < MAX_L3_SLICES; ++i) 4278cefcff8fSJoonas Lahtinen kfree(i915->l3_parity.remap_info[i]); 4279cefcff8fSJoonas Lahtinen } 4280cefcff8fSJoonas Lahtinen 4281b318b824SVille Syrjälä static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) 4282b318b824SVille Syrjälä { 4283b318b824SVille Syrjälä if (HAS_GMCH(dev_priv)) { 4284b318b824SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) 4285b318b824SVille Syrjälä return cherryview_irq_handler; 4286b318b824SVille Syrjälä else if (IS_VALLEYVIEW(dev_priv)) 4287b318b824SVille Syrjälä return valleyview_irq_handler; 4288b318b824SVille Syrjälä else if (IS_GEN(dev_priv, 4)) 4289b318b824SVille Syrjälä return i965_irq_handler; 4290b318b824SVille Syrjälä else if (IS_GEN(dev_priv, 3)) 4291b318b824SVille Syrjälä return i915_irq_handler; 4292b318b824SVille Syrjälä else 4293b318b824SVille Syrjälä return i8xx_irq_handler; 4294b318b824SVille Syrjälä } else { 429597b492f5SLucas De Marchi if (HAS_MASTER_UNIT_IRQ(dev_priv)) 429697b492f5SLucas De Marchi return dg1_irq_handler; 4297b318b824SVille Syrjälä if (INTEL_GEN(dev_priv) >= 11) 4298b318b824SVille Syrjälä return gen11_irq_handler; 4299b318b824SVille Syrjälä else if (INTEL_GEN(dev_priv) >= 8) 4300b318b824SVille Syrjälä return gen8_irq_handler; 4301b318b824SVille Syrjälä else 43029eae5e27SLucas De Marchi return ilk_irq_handler; 4303b318b824SVille Syrjälä } 4304b318b824SVille Syrjälä } 4305b318b824SVille Syrjälä 4306b318b824SVille Syrjälä static void intel_irq_reset(struct drm_i915_private *dev_priv) 4307b318b824SVille Syrjälä { 4308b318b824SVille Syrjälä if (HAS_GMCH(dev_priv)) { 4309b318b824SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) 4310b318b824SVille Syrjälä cherryview_irq_reset(dev_priv); 4311b318b824SVille Syrjälä else if (IS_VALLEYVIEW(dev_priv)) 4312b318b824SVille Syrjälä valleyview_irq_reset(dev_priv); 4313b318b824SVille Syrjälä else if (IS_GEN(dev_priv, 4)) 4314b318b824SVille Syrjälä i965_irq_reset(dev_priv); 4315b318b824SVille Syrjälä else if (IS_GEN(dev_priv, 3)) 4316b318b824SVille Syrjälä i915_irq_reset(dev_priv); 4317b318b824SVille Syrjälä else 4318b318b824SVille Syrjälä i8xx_irq_reset(dev_priv); 4319b318b824SVille Syrjälä } else { 4320b318b824SVille Syrjälä if (INTEL_GEN(dev_priv) >= 11) 4321b318b824SVille Syrjälä gen11_irq_reset(dev_priv); 4322b318b824SVille Syrjälä else if (INTEL_GEN(dev_priv) >= 8) 4323b318b824SVille Syrjälä gen8_irq_reset(dev_priv); 4324b318b824SVille Syrjälä else 43259eae5e27SLucas De Marchi ilk_irq_reset(dev_priv); 4326b318b824SVille Syrjälä } 4327b318b824SVille Syrjälä } 4328b318b824SVille Syrjälä 4329b318b824SVille Syrjälä static void intel_irq_postinstall(struct drm_i915_private *dev_priv) 4330b318b824SVille Syrjälä { 4331b318b824SVille Syrjälä if (HAS_GMCH(dev_priv)) { 4332b318b824SVille Syrjälä if (IS_CHERRYVIEW(dev_priv)) 4333b318b824SVille Syrjälä cherryview_irq_postinstall(dev_priv); 4334b318b824SVille Syrjälä else if (IS_VALLEYVIEW(dev_priv)) 4335b318b824SVille Syrjälä valleyview_irq_postinstall(dev_priv); 4336b318b824SVille Syrjälä else if (IS_GEN(dev_priv, 4)) 4337b318b824SVille Syrjälä i965_irq_postinstall(dev_priv); 4338b318b824SVille Syrjälä else if (IS_GEN(dev_priv, 3)) 4339b318b824SVille Syrjälä i915_irq_postinstall(dev_priv); 4340b318b824SVille Syrjälä else 4341b318b824SVille Syrjälä i8xx_irq_postinstall(dev_priv); 4342b318b824SVille Syrjälä } else { 4343b318b824SVille Syrjälä if (INTEL_GEN(dev_priv) >= 11) 4344b318b824SVille Syrjälä gen11_irq_postinstall(dev_priv); 4345b318b824SVille Syrjälä else if (INTEL_GEN(dev_priv) >= 8) 4346b318b824SVille Syrjälä gen8_irq_postinstall(dev_priv); 4347b318b824SVille Syrjälä else 43489eae5e27SLucas De Marchi ilk_irq_postinstall(dev_priv); 4349b318b824SVille Syrjälä } 4350b318b824SVille Syrjälä } 4351b318b824SVille Syrjälä 4352cefcff8fSJoonas Lahtinen /** 4353fca52a55SDaniel Vetter * intel_irq_install - enables the hardware interrupt 4354fca52a55SDaniel Vetter * @dev_priv: i915 device instance 4355fca52a55SDaniel Vetter * 4356fca52a55SDaniel Vetter * This function enables the hardware interrupt handling, but leaves the hotplug 4357fca52a55SDaniel Vetter * handling still disabled. It is called after intel_irq_init(). 4358fca52a55SDaniel Vetter * 4359fca52a55SDaniel Vetter * In the driver load and resume code we need working interrupts in a few places 4360fca52a55SDaniel Vetter * but don't want to deal with the hassle of concurrent probe and hotplug 4361fca52a55SDaniel Vetter * workers. Hence the split into this two-stage approach. 4362fca52a55SDaniel Vetter */ 43632aeb7d3aSDaniel Vetter int intel_irq_install(struct drm_i915_private *dev_priv) 43642aeb7d3aSDaniel Vetter { 4365b318b824SVille Syrjälä int irq = dev_priv->drm.pdev->irq; 4366b318b824SVille Syrjälä int ret; 4367b318b824SVille Syrjälä 43682aeb7d3aSDaniel Vetter /* 43692aeb7d3aSDaniel Vetter * We enable some interrupt sources in our postinstall hooks, so mark 43702aeb7d3aSDaniel Vetter * interrupts as enabled _before_ actually enabling them to avoid 43712aeb7d3aSDaniel Vetter * special cases in our ordering checks. 43722aeb7d3aSDaniel Vetter */ 4373ad1443f0SSagar Arun Kamble dev_priv->runtime_pm.irqs_enabled = true; 43742aeb7d3aSDaniel Vetter 4375b318b824SVille Syrjälä dev_priv->drm.irq_enabled = true; 4376b318b824SVille Syrjälä 4377b318b824SVille Syrjälä intel_irq_reset(dev_priv); 4378b318b824SVille Syrjälä 4379b318b824SVille Syrjälä ret = request_irq(irq, intel_irq_handler(dev_priv), 4380b318b824SVille Syrjälä IRQF_SHARED, DRIVER_NAME, dev_priv); 4381b318b824SVille Syrjälä if (ret < 0) { 4382b318b824SVille Syrjälä dev_priv->drm.irq_enabled = false; 4383b318b824SVille Syrjälä return ret; 4384b318b824SVille Syrjälä } 4385b318b824SVille Syrjälä 4386b318b824SVille Syrjälä intel_irq_postinstall(dev_priv); 4387b318b824SVille Syrjälä 4388b318b824SVille Syrjälä return ret; 43892aeb7d3aSDaniel Vetter } 43902aeb7d3aSDaniel Vetter 4391fca52a55SDaniel Vetter /** 4392fca52a55SDaniel Vetter * intel_irq_uninstall - finilizes all irq handling 4393fca52a55SDaniel Vetter * @dev_priv: i915 device instance 4394fca52a55SDaniel Vetter * 4395fca52a55SDaniel Vetter * This stops interrupt and hotplug handling and unregisters and frees all 4396fca52a55SDaniel Vetter * resources acquired in the init functions. 4397fca52a55SDaniel Vetter */ 43982aeb7d3aSDaniel Vetter void intel_irq_uninstall(struct drm_i915_private *dev_priv) 43992aeb7d3aSDaniel Vetter { 4400b318b824SVille Syrjälä int irq = dev_priv->drm.pdev->irq; 4401b318b824SVille Syrjälä 4402b318b824SVille Syrjälä /* 4403789fa874SJanusz Krzysztofik * FIXME we can get called twice during driver probe 4404789fa874SJanusz Krzysztofik * error handling as well as during driver remove due to 4405789fa874SJanusz Krzysztofik * intel_modeset_driver_remove() calling us out of sequence. 4406789fa874SJanusz Krzysztofik * Would be nice if it didn't do that... 4407b318b824SVille Syrjälä */ 4408b318b824SVille Syrjälä if (!dev_priv->drm.irq_enabled) 4409b318b824SVille Syrjälä return; 4410b318b824SVille Syrjälä 4411b318b824SVille Syrjälä dev_priv->drm.irq_enabled = false; 4412b318b824SVille Syrjälä 4413b318b824SVille Syrjälä intel_irq_reset(dev_priv); 4414b318b824SVille Syrjälä 4415b318b824SVille Syrjälä free_irq(irq, dev_priv); 4416b318b824SVille Syrjälä 44172aeb7d3aSDaniel Vetter intel_hpd_cancel_work(dev_priv); 4418ad1443f0SSagar Arun Kamble dev_priv->runtime_pm.irqs_enabled = false; 44192aeb7d3aSDaniel Vetter } 44202aeb7d3aSDaniel Vetter 4421fca52a55SDaniel Vetter /** 4422fca52a55SDaniel Vetter * intel_runtime_pm_disable_interrupts - runtime interrupt disabling 4423fca52a55SDaniel Vetter * @dev_priv: i915 device instance 4424fca52a55SDaniel Vetter * 4425fca52a55SDaniel Vetter * This function is used to disable interrupts at runtime, both in the runtime 4426fca52a55SDaniel Vetter * pm and the system suspend/resume code. 4427fca52a55SDaniel Vetter */ 4428b963291cSDaniel Vetter void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) 4429c67a470bSPaulo Zanoni { 4430b318b824SVille Syrjälä intel_irq_reset(dev_priv); 4431ad1443f0SSagar Arun Kamble dev_priv->runtime_pm.irqs_enabled = false; 4432315ca4c4SVille Syrjälä intel_synchronize_irq(dev_priv); 4433c67a470bSPaulo Zanoni } 4434c67a470bSPaulo Zanoni 4435fca52a55SDaniel Vetter /** 4436fca52a55SDaniel Vetter * intel_runtime_pm_enable_interrupts - runtime interrupt enabling 4437fca52a55SDaniel Vetter * @dev_priv: i915 device instance 4438fca52a55SDaniel Vetter * 4439fca52a55SDaniel Vetter * This function is used to enable interrupts at runtime, both in the runtime 4440fca52a55SDaniel Vetter * pm and the system suspend/resume code. 4441fca52a55SDaniel Vetter */ 4442b963291cSDaniel Vetter void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) 4443c67a470bSPaulo Zanoni { 4444ad1443f0SSagar Arun Kamble dev_priv->runtime_pm.irqs_enabled = true; 4445b318b824SVille Syrjälä intel_irq_reset(dev_priv); 4446b318b824SVille Syrjälä intel_irq_postinstall(dev_priv); 4447c67a470bSPaulo Zanoni } 4448d64575eeSJani Nikula 4449d64575eeSJani Nikula bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 4450d64575eeSJani Nikula { 4451d64575eeSJani Nikula /* 4452d64575eeSJani Nikula * We only use drm_irq_uninstall() at unload and VT switch, so 4453d64575eeSJani Nikula * this is the only thing we need to check. 4454d64575eeSJani Nikula */ 4455d64575eeSJani Nikula return dev_priv->runtime_pm.irqs_enabled; 4456d64575eeSJani Nikula } 4457d64575eeSJani Nikula 4458d64575eeSJani Nikula void intel_synchronize_irq(struct drm_i915_private *i915) 4459d64575eeSJani Nikula { 4460d64575eeSJani Nikula synchronize_irq(i915->drm.pdev->irq); 4461d64575eeSJani Nikula } 4462