1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/pnp.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_aperture.h> 44 #include <drm/drm_atomic_helper.h> 45 #include <drm/drm_ioctl.h> 46 #include <drm/drm_managed.h> 47 #include <drm/drm_probe_helper.h> 48 49 #include "display/intel_acpi.h" 50 #include "display/intel_bw.h" 51 #include "display/intel_cdclk.h" 52 #include "display/intel_display_types.h" 53 #include "display/intel_dmc.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dpt.h" 56 #include "display/intel_fbdev.h" 57 #include "display/intel_hotplug.h" 58 #include "display/intel_overlay.h" 59 #include "display/intel_pch_refclk.h" 60 #include "display/intel_pipe_crc.h" 61 #include "display/intel_pps.h" 62 #include "display/intel_sprite.h" 63 #include "display/intel_vga.h" 64 #include "display/skl_watermark.h" 65 66 #include "gem/i915_gem_context.h" 67 #include "gem/i915_gem_create.h" 68 #include "gem/i915_gem_dmabuf.h" 69 #include "gem/i915_gem_ioctls.h" 70 #include "gem/i915_gem_mman.h" 71 #include "gem/i915_gem_pm.h" 72 #include "gt/intel_gt.h" 73 #include "gt/intel_gt_pm.h" 74 #include "gt/intel_rc6.h" 75 76 #include "pxp/intel_pxp_pm.h" 77 78 #include "i915_file_private.h" 79 #include "i915_debugfs.h" 80 #include "i915_driver.h" 81 #include "i915_drm_client.h" 82 #include "i915_drv.h" 83 #include "i915_getparam.h" 84 #include "i915_ioc32.h" 85 #include "i915_ioctl.h" 86 #include "i915_irq.h" 87 #include "i915_memcpy.h" 88 #include "i915_perf.h" 89 #include "i915_query.h" 90 #include "i915_suspend.h" 91 #include "i915_switcheroo.h" 92 #include "i915_sysfs.h" 93 #include "i915_utils.h" 94 #include "i915_vgpu.h" 95 #include "intel_dram.h" 96 #include "intel_gvt.h" 97 #include "intel_memory_region.h" 98 #include "intel_pci_config.h" 99 #include "intel_pcode.h" 100 #include "intel_pm.h" 101 #include "intel_region_ttm.h" 102 #include "vlv_suspend.h" 103 104 /* Intel Rapid Start Technology ACPI device name */ 105 static const char irst_name[] = "INT3392"; 106 107 static const struct drm_driver i915_drm_driver; 108 109 static void i915_release_bridge_dev(struct drm_device *dev, 110 void *bridge) 111 { 112 pci_dev_put(bridge); 113 } 114 115 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) 116 { 117 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); 118 119 dev_priv->bridge_dev = 120 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 121 if (!dev_priv->bridge_dev) { 122 drm_err(&dev_priv->drm, "bridge device not found\n"); 123 return -EIO; 124 } 125 126 return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev, 127 dev_priv->bridge_dev); 128 } 129 130 /* Allocate space for the MCH regs if needed, return nonzero on error */ 131 static int 132 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) 133 { 134 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 135 u32 temp_lo, temp_hi = 0; 136 u64 mchbar_addr; 137 int ret; 138 139 if (GRAPHICS_VER(dev_priv) >= 4) 140 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 141 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); 142 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 143 144 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 145 #ifdef CONFIG_PNP 146 if (mchbar_addr && 147 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 148 return 0; 149 #endif 150 151 /* Get some space for it */ 152 dev_priv->mch_res.name = "i915 MCHBAR"; 153 dev_priv->mch_res.flags = IORESOURCE_MEM; 154 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, 155 &dev_priv->mch_res, 156 MCHBAR_SIZE, MCHBAR_SIZE, 157 PCIBIOS_MIN_MEM, 158 0, pcibios_align_resource, 159 dev_priv->bridge_dev); 160 if (ret) { 161 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret); 162 dev_priv->mch_res.start = 0; 163 return ret; 164 } 165 166 if (GRAPHICS_VER(dev_priv) >= 4) 167 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, 168 upper_32_bits(dev_priv->mch_res.start)); 169 170 pci_write_config_dword(dev_priv->bridge_dev, reg, 171 lower_32_bits(dev_priv->mch_res.start)); 172 return 0; 173 } 174 175 /* Setup MCHBAR if possible, return true if we should disable it again */ 176 static void 177 intel_setup_mchbar(struct drm_i915_private *dev_priv) 178 { 179 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 180 u32 temp; 181 bool enabled; 182 183 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 184 return; 185 186 dev_priv->mchbar_need_disable = false; 187 188 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 189 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); 190 enabled = !!(temp & DEVEN_MCHBAR_EN); 191 } else { 192 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 193 enabled = temp & 1; 194 } 195 196 /* If it's already enabled, don't have to do anything */ 197 if (enabled) 198 return; 199 200 if (intel_alloc_mchbar_resource(dev_priv)) 201 return; 202 203 dev_priv->mchbar_need_disable = true; 204 205 /* Space is allocated or reserved, so enable it. */ 206 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 207 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 208 temp | DEVEN_MCHBAR_EN); 209 } else { 210 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 211 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); 212 } 213 } 214 215 static void 216 intel_teardown_mchbar(struct drm_i915_private *dev_priv) 217 { 218 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 219 220 if (dev_priv->mchbar_need_disable) { 221 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 222 u32 deven_val; 223 224 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, 225 &deven_val); 226 deven_val &= ~DEVEN_MCHBAR_EN; 227 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 228 deven_val); 229 } else { 230 u32 mchbar_val; 231 232 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, 233 &mchbar_val); 234 mchbar_val &= ~1; 235 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, 236 mchbar_val); 237 } 238 } 239 240 if (dev_priv->mch_res.start) 241 release_resource(&dev_priv->mch_res); 242 } 243 244 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 245 { 246 /* 247 * The i915 workqueue is primarily used for batched retirement of 248 * requests (and thus managing bo) once the task has been completed 249 * by the GPU. i915_retire_requests() is called directly when we 250 * need high-priority retirement, such as waiting for an explicit 251 * bo. 252 * 253 * It is also used for periodic low-priority events, such as 254 * idle-timers and recording error state. 255 * 256 * All tasks on the workqueue are expected to acquire the dev mutex 257 * so there is no point in running more than one instance of the 258 * workqueue at any time. Use an ordered one. 259 */ 260 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 261 if (dev_priv->wq == NULL) 262 goto out_err; 263 264 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 265 if (dev_priv->display.hotplug.dp_wq == NULL) 266 goto out_free_wq; 267 268 return 0; 269 270 out_free_wq: 271 destroy_workqueue(dev_priv->wq); 272 out_err: 273 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 274 275 return -ENOMEM; 276 } 277 278 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 279 { 280 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 281 destroy_workqueue(dev_priv->wq); 282 } 283 284 /* 285 * We don't keep the workarounds for pre-production hardware, so we expect our 286 * driver to fail on these machines in one way or another. A little warning on 287 * dmesg may help both the user and the bug triagers. 288 * 289 * Our policy for removing pre-production workarounds is to keep the 290 * current gen workarounds as a guide to the bring-up of the next gen 291 * (workarounds have a habit of persisting!). Anything older than that 292 * should be removed along with the complications they introduce. 293 */ 294 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 295 { 296 bool pre = false; 297 298 pre |= IS_HSW_EARLY_SDV(dev_priv); 299 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 300 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 301 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 302 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 303 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 304 305 if (pre) { 306 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 307 "It may not be fully functional.\n"); 308 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 309 } 310 } 311 312 static void sanitize_gpu(struct drm_i915_private *i915) 313 { 314 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { 315 struct intel_gt *gt; 316 unsigned int i; 317 318 for_each_gt(gt, i915, i) 319 __intel_gt_reset(gt, ALL_ENGINES); 320 } 321 } 322 323 /** 324 * i915_driver_early_probe - setup state not requiring device access 325 * @dev_priv: device private 326 * 327 * Initialize everything that is a "SW-only" state, that is state not 328 * requiring accessing the device or exposing the driver via kernel internal 329 * or userspace interfaces. Example steps belonging here: lock initialization, 330 * system memory allocation, setting up device specific attributes and 331 * function hooks not requiring accessing the device. 332 */ 333 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 334 { 335 int ret = 0; 336 337 if (i915_inject_probe_failure(dev_priv)) 338 return -ENODEV; 339 340 intel_device_info_subplatform_init(dev_priv); 341 intel_step_init(dev_priv); 342 343 intel_uncore_mmio_debug_init_early(dev_priv); 344 345 spin_lock_init(&dev_priv->irq_lock); 346 spin_lock_init(&dev_priv->gpu_error.lock); 347 mutex_init(&dev_priv->display.backlight.lock); 348 349 mutex_init(&dev_priv->sb_lock); 350 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 351 352 mutex_init(&dev_priv->display.audio.mutex); 353 mutex_init(&dev_priv->display.wm.wm_mutex); 354 mutex_init(&dev_priv->display.pps.mutex); 355 mutex_init(&dev_priv->display.hdcp.comp_mutex); 356 357 i915_memcpy_init_early(dev_priv); 358 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 359 360 ret = i915_workqueues_init(dev_priv); 361 if (ret < 0) 362 return ret; 363 364 ret = vlv_suspend_init(dev_priv); 365 if (ret < 0) 366 goto err_workqueues; 367 368 ret = intel_region_ttm_device_init(dev_priv); 369 if (ret) 370 goto err_ttm; 371 372 intel_wopcm_init_early(&dev_priv->wopcm); 373 374 ret = intel_root_gt_init_early(dev_priv); 375 if (ret < 0) 376 goto err_rootgt; 377 378 i915_drm_clients_init(&dev_priv->clients, dev_priv); 379 380 i915_gem_init_early(dev_priv); 381 382 /* This must be called before any calls to HAS_PCH_* */ 383 intel_detect_pch(dev_priv); 384 385 intel_pm_setup(dev_priv); 386 ret = intel_power_domains_init(dev_priv); 387 if (ret < 0) 388 goto err_gem; 389 intel_irq_init(dev_priv); 390 intel_init_display_hooks(dev_priv); 391 intel_init_clock_gating_hooks(dev_priv); 392 393 intel_detect_preproduction_hw(dev_priv); 394 395 return 0; 396 397 err_gem: 398 i915_gem_cleanup_early(dev_priv); 399 intel_gt_driver_late_release_all(dev_priv); 400 i915_drm_clients_fini(&dev_priv->clients); 401 err_rootgt: 402 intel_region_ttm_device_fini(dev_priv); 403 err_ttm: 404 vlv_suspend_cleanup(dev_priv); 405 err_workqueues: 406 i915_workqueues_cleanup(dev_priv); 407 return ret; 408 } 409 410 /** 411 * i915_driver_late_release - cleanup the setup done in 412 * i915_driver_early_probe() 413 * @dev_priv: device private 414 */ 415 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 416 { 417 intel_irq_fini(dev_priv); 418 intel_power_domains_cleanup(dev_priv); 419 i915_gem_cleanup_early(dev_priv); 420 intel_gt_driver_late_release_all(dev_priv); 421 i915_drm_clients_fini(&dev_priv->clients); 422 intel_region_ttm_device_fini(dev_priv); 423 vlv_suspend_cleanup(dev_priv); 424 i915_workqueues_cleanup(dev_priv); 425 426 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 427 mutex_destroy(&dev_priv->sb_lock); 428 429 i915_params_free(&dev_priv->params); 430 } 431 432 /** 433 * i915_driver_mmio_probe - setup device MMIO 434 * @dev_priv: device private 435 * 436 * Setup minimal device state necessary for MMIO accesses later in the 437 * initialization sequence. The setup here should avoid any other device-wide 438 * side effects or exposing the driver via kernel internal or user space 439 * interfaces. 440 */ 441 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 442 { 443 struct intel_gt *gt; 444 int ret, i; 445 446 if (i915_inject_probe_failure(dev_priv)) 447 return -ENODEV; 448 449 ret = i915_get_bridge_dev(dev_priv); 450 if (ret < 0) 451 return ret; 452 453 for_each_gt(gt, dev_priv, i) { 454 ret = intel_uncore_init_mmio(gt->uncore); 455 if (ret) 456 return ret; 457 458 ret = drmm_add_action_or_reset(&dev_priv->drm, 459 intel_uncore_fini_mmio, 460 gt->uncore); 461 if (ret) 462 return ret; 463 } 464 465 /* Try to make sure MCHBAR is enabled before poking at it */ 466 intel_setup_mchbar(dev_priv); 467 intel_device_info_runtime_init(dev_priv); 468 469 for_each_gt(gt, dev_priv, i) { 470 ret = intel_gt_init_mmio(gt); 471 if (ret) 472 goto err_uncore; 473 } 474 475 /* As early as possible, scrub existing GPU state before clobbering */ 476 sanitize_gpu(dev_priv); 477 478 return 0; 479 480 err_uncore: 481 intel_teardown_mchbar(dev_priv); 482 483 return ret; 484 } 485 486 /** 487 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 488 * @dev_priv: device private 489 */ 490 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 491 { 492 intel_teardown_mchbar(dev_priv); 493 } 494 495 /** 496 * i915_set_dma_info - set all relevant PCI dma info as configured for the 497 * platform 498 * @i915: valid i915 instance 499 * 500 * Set the dma max segment size, device and coherent masks. The dma mask set 501 * needs to occur before i915_ggtt_probe_hw. 502 * 503 * A couple of platforms have special needs. Address them as well. 504 * 505 */ 506 static int i915_set_dma_info(struct drm_i915_private *i915) 507 { 508 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 509 int ret; 510 511 GEM_BUG_ON(!mask_size); 512 513 /* 514 * We don't have a max segment size, so set it to the max so sg's 515 * debugging layer doesn't complain 516 */ 517 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 518 519 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 520 if (ret) 521 goto mask_err; 522 523 /* overlay on gen2 is broken and can't address above 1G */ 524 if (GRAPHICS_VER(i915) == 2) 525 mask_size = 30; 526 527 /* 528 * 965GM sometimes incorrectly writes to hardware status page (HWS) 529 * using 32bit addressing, overwriting memory if HWS is located 530 * above 4GB. 531 * 532 * The documentation also mentions an issue with undefined 533 * behaviour if any general state is accessed within a page above 4GB, 534 * which also needs to be handled carefully. 535 */ 536 if (IS_I965G(i915) || IS_I965GM(i915)) 537 mask_size = 32; 538 539 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 540 if (ret) 541 goto mask_err; 542 543 return 0; 544 545 mask_err: 546 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 547 return ret; 548 } 549 550 static int i915_pcode_init(struct drm_i915_private *i915) 551 { 552 struct intel_gt *gt; 553 int id, ret; 554 555 for_each_gt(gt, i915, id) { 556 ret = intel_pcode_init(gt->uncore); 557 if (ret) { 558 drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret); 559 return ret; 560 } 561 } 562 563 return 0; 564 } 565 566 /** 567 * i915_driver_hw_probe - setup state requiring device access 568 * @dev_priv: device private 569 * 570 * Setup state that requires accessing the device, but doesn't require 571 * exposing the driver via kernel internal or userspace interfaces. 572 */ 573 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 574 { 575 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 576 struct pci_dev *root_pdev; 577 int ret; 578 579 if (i915_inject_probe_failure(dev_priv)) 580 return -ENODEV; 581 582 if (HAS_PPGTT(dev_priv)) { 583 if (intel_vgpu_active(dev_priv) && 584 !intel_vgpu_has_full_ppgtt(dev_priv)) { 585 i915_report_error(dev_priv, 586 "incompatible vGPU found, support for isolated ppGTT required\n"); 587 return -ENXIO; 588 } 589 } 590 591 if (HAS_EXECLISTS(dev_priv)) { 592 /* 593 * Older GVT emulation depends upon intercepting CSB mmio, 594 * which we no longer use, preferring to use the HWSP cache 595 * instead. 596 */ 597 if (intel_vgpu_active(dev_priv) && 598 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 599 i915_report_error(dev_priv, 600 "old vGPU host found, support for HWSP emulation required\n"); 601 return -ENXIO; 602 } 603 } 604 605 /* needs to be done before ggtt probe */ 606 intel_dram_edram_detect(dev_priv); 607 608 ret = i915_set_dma_info(dev_priv); 609 if (ret) 610 return ret; 611 612 i915_perf_init(dev_priv); 613 614 ret = intel_gt_assign_ggtt(to_gt(dev_priv)); 615 if (ret) 616 goto err_perf; 617 618 ret = i915_ggtt_probe_hw(dev_priv); 619 if (ret) 620 goto err_perf; 621 622 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 623 if (ret) 624 goto err_ggtt; 625 626 ret = i915_ggtt_init_hw(dev_priv); 627 if (ret) 628 goto err_ggtt; 629 630 ret = intel_memory_regions_hw_probe(dev_priv); 631 if (ret) 632 goto err_ggtt; 633 634 ret = intel_gt_tiles_init(dev_priv); 635 if (ret) 636 goto err_mem_regions; 637 638 ret = i915_ggtt_enable_hw(dev_priv); 639 if (ret) { 640 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 641 goto err_mem_regions; 642 } 643 644 pci_set_master(pdev); 645 646 /* On the 945G/GM, the chipset reports the MSI capability on the 647 * integrated graphics even though the support isn't actually there 648 * according to the published specs. It doesn't appear to function 649 * correctly in testing on 945G. 650 * This may be a side effect of MSI having been made available for PEG 651 * and the registers being closely associated. 652 * 653 * According to chipset errata, on the 965GM, MSI interrupts may 654 * be lost or delayed, and was defeatured. MSI interrupts seem to 655 * get lost on g4x as well, and interrupt delivery seems to stay 656 * properly dead afterwards. So we'll just disable them for all 657 * pre-gen5 chipsets. 658 * 659 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 660 * interrupts even when in MSI mode. This results in spurious 661 * interrupt warnings if the legacy irq no. is shared with another 662 * device. The kernel then disables that interrupt source and so 663 * prevents the other device from working properly. 664 */ 665 if (GRAPHICS_VER(dev_priv) >= 5) { 666 if (pci_enable_msi(pdev) < 0) 667 drm_dbg(&dev_priv->drm, "can't enable MSI"); 668 } 669 670 ret = intel_gvt_init(dev_priv); 671 if (ret) 672 goto err_msi; 673 674 intel_opregion_setup(dev_priv); 675 676 ret = i915_pcode_init(dev_priv); 677 if (ret) 678 goto err_msi; 679 680 /* 681 * Fill the dram structure to get the system dram info. This will be 682 * used for memory latency calculation. 683 */ 684 intel_dram_detect(dev_priv); 685 686 intel_bw_init_hw(dev_priv); 687 688 /* 689 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 690 * This should be totally removed when we handle the pci states properly 691 * on runtime PM and on s2idle cases. 692 */ 693 root_pdev = pcie_find_root_port(pdev); 694 if (root_pdev) 695 pci_d3cold_disable(root_pdev); 696 697 return 0; 698 699 err_msi: 700 if (pdev->msi_enabled) 701 pci_disable_msi(pdev); 702 err_mem_regions: 703 intel_memory_regions_driver_release(dev_priv); 704 err_ggtt: 705 i915_ggtt_driver_release(dev_priv); 706 i915_gem_drain_freed_objects(dev_priv); 707 i915_ggtt_driver_late_release(dev_priv); 708 err_perf: 709 i915_perf_fini(dev_priv); 710 return ret; 711 } 712 713 /** 714 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 715 * @dev_priv: device private 716 */ 717 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 718 { 719 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 720 struct pci_dev *root_pdev; 721 722 i915_perf_fini(dev_priv); 723 724 if (pdev->msi_enabled) 725 pci_disable_msi(pdev); 726 727 root_pdev = pcie_find_root_port(pdev); 728 if (root_pdev) 729 pci_d3cold_enable(root_pdev); 730 } 731 732 /** 733 * i915_driver_register - register the driver with the rest of the system 734 * @dev_priv: device private 735 * 736 * Perform any steps necessary to make the driver available via kernel 737 * internal or userspace interfaces. 738 */ 739 static void i915_driver_register(struct drm_i915_private *dev_priv) 740 { 741 struct drm_device *dev = &dev_priv->drm; 742 struct intel_gt *gt; 743 unsigned int i; 744 745 i915_gem_driver_register(dev_priv); 746 i915_pmu_register(dev_priv); 747 748 intel_vgpu_register(dev_priv); 749 750 /* Reveal our presence to userspace */ 751 if (drm_dev_register(dev, 0)) { 752 drm_err(&dev_priv->drm, 753 "Failed to register driver for userspace access!\n"); 754 return; 755 } 756 757 i915_debugfs_register(dev_priv); 758 i915_setup_sysfs(dev_priv); 759 760 /* Depends on sysfs having been initialized */ 761 i915_perf_register(dev_priv); 762 763 for_each_gt(gt, dev_priv, i) 764 intel_gt_driver_register(gt); 765 766 intel_display_driver_register(dev_priv); 767 768 intel_power_domains_enable(dev_priv); 769 intel_runtime_pm_enable(&dev_priv->runtime_pm); 770 771 intel_register_dsm_handler(); 772 773 if (i915_switcheroo_register(dev_priv)) 774 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 775 } 776 777 /** 778 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 779 * @dev_priv: device private 780 */ 781 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 782 { 783 struct intel_gt *gt; 784 unsigned int i; 785 786 i915_switcheroo_unregister(dev_priv); 787 788 intel_unregister_dsm_handler(); 789 790 intel_runtime_pm_disable(&dev_priv->runtime_pm); 791 intel_power_domains_disable(dev_priv); 792 793 intel_display_driver_unregister(dev_priv); 794 795 for_each_gt(gt, dev_priv, i) 796 intel_gt_driver_unregister(gt); 797 798 i915_perf_unregister(dev_priv); 799 i915_pmu_unregister(dev_priv); 800 801 i915_teardown_sysfs(dev_priv); 802 drm_dev_unplug(&dev_priv->drm); 803 804 i915_gem_driver_unregister(dev_priv); 805 } 806 807 void 808 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 809 { 810 drm_printf(p, "iommu: %s\n", 811 str_enabled_disabled(i915_vtd_active(i915))); 812 } 813 814 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 815 { 816 if (drm_debug_enabled(DRM_UT_DRIVER)) { 817 struct drm_printer p = drm_debug_printer("i915 device info:"); 818 struct intel_gt *gt; 819 unsigned int i; 820 821 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 822 INTEL_DEVID(dev_priv), 823 INTEL_REVID(dev_priv), 824 intel_platform_name(INTEL_INFO(dev_priv)->platform), 825 intel_subplatform(RUNTIME_INFO(dev_priv), 826 INTEL_INFO(dev_priv)->platform), 827 GRAPHICS_VER(dev_priv)); 828 829 intel_device_info_print(INTEL_INFO(dev_priv), 830 RUNTIME_INFO(dev_priv), &p); 831 i915_print_iommu_status(dev_priv, &p); 832 for_each_gt(gt, dev_priv, i) 833 intel_gt_info_print(>->info, &p); 834 } 835 836 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 837 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 838 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 839 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 840 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 841 drm_info(&dev_priv->drm, 842 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 843 } 844 845 static struct drm_i915_private * 846 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 847 { 848 const struct intel_device_info *match_info = 849 (struct intel_device_info *)ent->driver_data; 850 struct intel_device_info *device_info; 851 struct intel_runtime_info *runtime; 852 struct drm_i915_private *i915; 853 854 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 855 struct drm_i915_private, drm); 856 if (IS_ERR(i915)) 857 return i915; 858 859 pci_set_drvdata(pdev, i915); 860 861 /* Device parameters start as a copy of module parameters. */ 862 i915_params_copy(&i915->params, &i915_modparams); 863 864 /* Setup the write-once "constant" device info */ 865 device_info = mkwrite_device_info(i915); 866 memcpy(device_info, match_info, sizeof(*device_info)); 867 868 /* Initialize initial runtime info from static const data and pdev. */ 869 runtime = RUNTIME_INFO(i915); 870 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime)); 871 runtime->device_id = pdev->device; 872 873 return i915; 874 } 875 876 /** 877 * i915_driver_probe - setup chip and create an initial config 878 * @pdev: PCI device 879 * @ent: matching PCI ID entry 880 * 881 * The driver probe routine has to do several things: 882 * - drive output discovery via intel_modeset_init() 883 * - initialize the memory manager 884 * - allocate initial config memory 885 * - setup the DRM framebuffer with the allocated memory 886 */ 887 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 888 { 889 struct drm_i915_private *i915; 890 int ret; 891 892 i915 = i915_driver_create(pdev, ent); 893 if (IS_ERR(i915)) 894 return PTR_ERR(i915); 895 896 /* Disable nuclear pageflip by default on pre-ILK */ 897 if (!i915->params.nuclear_pageflip && DISPLAY_VER(i915) < 5) 898 i915->drm.driver_features &= ~DRIVER_ATOMIC; 899 900 ret = pci_enable_device(pdev); 901 if (ret) 902 goto out_fini; 903 904 ret = i915_driver_early_probe(i915); 905 if (ret < 0) 906 goto out_pci_disable; 907 908 disable_rpm_wakeref_asserts(&i915->runtime_pm); 909 910 intel_vgpu_detect(i915); 911 912 ret = intel_gt_probe_all(i915); 913 if (ret < 0) 914 goto out_runtime_pm_put; 915 916 ret = i915_driver_mmio_probe(i915); 917 if (ret < 0) 918 goto out_tiles_cleanup; 919 920 ret = i915_driver_hw_probe(i915); 921 if (ret < 0) 922 goto out_cleanup_mmio; 923 924 ret = intel_modeset_init_noirq(i915); 925 if (ret < 0) 926 goto out_cleanup_hw; 927 928 ret = intel_irq_install(i915); 929 if (ret) 930 goto out_cleanup_modeset; 931 932 ret = intel_modeset_init_nogem(i915); 933 if (ret) 934 goto out_cleanup_irq; 935 936 ret = i915_gem_init(i915); 937 if (ret) 938 goto out_cleanup_modeset2; 939 940 ret = intel_modeset_init(i915); 941 if (ret) 942 goto out_cleanup_gem; 943 944 i915_driver_register(i915); 945 946 enable_rpm_wakeref_asserts(&i915->runtime_pm); 947 948 i915_welcome_messages(i915); 949 950 i915->do_release = true; 951 952 return 0; 953 954 out_cleanup_gem: 955 i915_gem_suspend(i915); 956 i915_gem_driver_remove(i915); 957 i915_gem_driver_release(i915); 958 out_cleanup_modeset2: 959 /* FIXME clean up the error path */ 960 intel_modeset_driver_remove(i915); 961 intel_irq_uninstall(i915); 962 intel_modeset_driver_remove_noirq(i915); 963 goto out_cleanup_modeset; 964 out_cleanup_irq: 965 intel_irq_uninstall(i915); 966 out_cleanup_modeset: 967 intel_modeset_driver_remove_nogem(i915); 968 out_cleanup_hw: 969 i915_driver_hw_remove(i915); 970 intel_memory_regions_driver_release(i915); 971 i915_ggtt_driver_release(i915); 972 i915_gem_drain_freed_objects(i915); 973 i915_ggtt_driver_late_release(i915); 974 out_cleanup_mmio: 975 i915_driver_mmio_release(i915); 976 out_tiles_cleanup: 977 intel_gt_release_all(i915); 978 out_runtime_pm_put: 979 enable_rpm_wakeref_asserts(&i915->runtime_pm); 980 i915_driver_late_release(i915); 981 out_pci_disable: 982 pci_disable_device(pdev); 983 out_fini: 984 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 985 return ret; 986 } 987 988 void i915_driver_remove(struct drm_i915_private *i915) 989 { 990 intel_wakeref_t wakeref; 991 992 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 993 994 i915_driver_unregister(i915); 995 996 /* Flush any external code that still may be under the RCU lock */ 997 synchronize_rcu(); 998 999 i915_gem_suspend(i915); 1000 1001 intel_gvt_driver_remove(i915); 1002 1003 intel_modeset_driver_remove(i915); 1004 1005 intel_irq_uninstall(i915); 1006 1007 intel_modeset_driver_remove_noirq(i915); 1008 1009 i915_reset_error_state(i915); 1010 i915_gem_driver_remove(i915); 1011 1012 intel_modeset_driver_remove_nogem(i915); 1013 1014 i915_driver_hw_remove(i915); 1015 1016 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1017 } 1018 1019 static void i915_driver_release(struct drm_device *dev) 1020 { 1021 struct drm_i915_private *dev_priv = to_i915(dev); 1022 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1023 intel_wakeref_t wakeref; 1024 1025 if (!dev_priv->do_release) 1026 return; 1027 1028 wakeref = intel_runtime_pm_get(rpm); 1029 1030 i915_gem_driver_release(dev_priv); 1031 1032 intel_memory_regions_driver_release(dev_priv); 1033 i915_ggtt_driver_release(dev_priv); 1034 i915_gem_drain_freed_objects(dev_priv); 1035 i915_ggtt_driver_late_release(dev_priv); 1036 1037 i915_driver_mmio_release(dev_priv); 1038 1039 intel_runtime_pm_put(rpm, wakeref); 1040 1041 intel_runtime_pm_driver_release(rpm); 1042 1043 i915_driver_late_release(dev_priv); 1044 } 1045 1046 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 1047 { 1048 struct drm_i915_private *i915 = to_i915(dev); 1049 int ret; 1050 1051 ret = i915_gem_open(i915, file); 1052 if (ret) 1053 return ret; 1054 1055 return 0; 1056 } 1057 1058 /** 1059 * i915_driver_lastclose - clean up after all DRM clients have exited 1060 * @dev: DRM device 1061 * 1062 * Take care of cleaning up after all DRM clients have exited. In the 1063 * mode setting case, we want to restore the kernel's initial mode (just 1064 * in case the last client left us in a bad state). 1065 * 1066 * Additionally, in the non-mode setting case, we'll tear down the GTT 1067 * and DMA structures, since the kernel won't be using them, and clea 1068 * up any GEM state. 1069 */ 1070 static void i915_driver_lastclose(struct drm_device *dev) 1071 { 1072 struct drm_i915_private *i915 = to_i915(dev); 1073 1074 intel_fbdev_restore_mode(dev); 1075 1076 if (HAS_DISPLAY(i915)) 1077 vga_switcheroo_process_delayed_switch(); 1078 } 1079 1080 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1081 { 1082 struct drm_i915_file_private *file_priv = file->driver_priv; 1083 1084 i915_gem_context_close(file); 1085 i915_drm_client_put(file_priv->client); 1086 1087 kfree_rcu(file_priv, rcu); 1088 1089 /* Catch up with all the deferred frees from "this" client */ 1090 i915_gem_flush_free_objects(to_i915(dev)); 1091 } 1092 1093 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 1094 { 1095 struct drm_device *dev = &dev_priv->drm; 1096 struct intel_encoder *encoder; 1097 1098 if (!HAS_DISPLAY(dev_priv)) 1099 return; 1100 1101 drm_modeset_lock_all(dev); 1102 for_each_intel_encoder(dev, encoder) 1103 if (encoder->suspend) 1104 encoder->suspend(encoder); 1105 drm_modeset_unlock_all(dev); 1106 } 1107 1108 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 1109 { 1110 struct drm_device *dev = &dev_priv->drm; 1111 struct intel_encoder *encoder; 1112 1113 if (!HAS_DISPLAY(dev_priv)) 1114 return; 1115 1116 drm_modeset_lock_all(dev); 1117 for_each_intel_encoder(dev, encoder) 1118 if (encoder->shutdown) 1119 encoder->shutdown(encoder); 1120 drm_modeset_unlock_all(dev); 1121 } 1122 1123 void i915_driver_shutdown(struct drm_i915_private *i915) 1124 { 1125 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1126 intel_runtime_pm_disable(&i915->runtime_pm); 1127 intel_power_domains_disable(i915); 1128 1129 if (HAS_DISPLAY(i915)) { 1130 drm_kms_helper_poll_disable(&i915->drm); 1131 1132 drm_atomic_helper_shutdown(&i915->drm); 1133 } 1134 1135 intel_dp_mst_suspend(i915); 1136 1137 intel_runtime_pm_disable_interrupts(i915); 1138 intel_hpd_cancel_work(i915); 1139 1140 intel_suspend_encoders(i915); 1141 intel_shutdown_encoders(i915); 1142 1143 intel_dmc_ucode_suspend(i915); 1144 1145 i915_gem_suspend(i915); 1146 1147 /* 1148 * The only requirement is to reboot with display DC states disabled, 1149 * for now leaving all display power wells in the INIT power domain 1150 * enabled. 1151 * 1152 * TODO: 1153 * - unify the pci_driver::shutdown sequence here with the 1154 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1155 * - unify the driver remove and system/runtime suspend sequences with 1156 * the above unified shutdown/poweroff sequence. 1157 */ 1158 intel_power_domains_driver_remove(i915); 1159 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1160 1161 intel_runtime_pm_driver_release(&i915->runtime_pm); 1162 } 1163 1164 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1165 { 1166 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1167 if (acpi_target_system_state() < ACPI_STATE_S3) 1168 return true; 1169 #endif 1170 return false; 1171 } 1172 1173 static int i915_drm_prepare(struct drm_device *dev) 1174 { 1175 struct drm_i915_private *i915 = to_i915(dev); 1176 1177 /* 1178 * NB intel_display_suspend() may issue new requests after we've 1179 * ostensibly marked the GPU as ready-to-sleep here. We need to 1180 * split out that work and pull it forward so that after point, 1181 * the GPU is not woken again. 1182 */ 1183 return i915_gem_backup_suspend(i915); 1184 } 1185 1186 static int i915_drm_suspend(struct drm_device *dev) 1187 { 1188 struct drm_i915_private *dev_priv = to_i915(dev); 1189 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1190 pci_power_t opregion_target_state; 1191 1192 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1193 1194 /* We do a lot of poking in a lot of registers, make sure they work 1195 * properly. */ 1196 intel_power_domains_disable(dev_priv); 1197 if (HAS_DISPLAY(dev_priv)) 1198 drm_kms_helper_poll_disable(dev); 1199 1200 pci_save_state(pdev); 1201 1202 intel_display_suspend(dev); 1203 1204 intel_dp_mst_suspend(dev_priv); 1205 1206 intel_runtime_pm_disable_interrupts(dev_priv); 1207 intel_hpd_cancel_work(dev_priv); 1208 1209 intel_suspend_encoders(dev_priv); 1210 1211 intel_suspend_hw(dev_priv); 1212 1213 /* Must be called before GGTT is suspended. */ 1214 intel_dpt_suspend(dev_priv); 1215 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1216 1217 i915_save_display(dev_priv); 1218 1219 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1220 intel_opregion_suspend(dev_priv, opregion_target_state); 1221 1222 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1223 1224 dev_priv->suspend_count++; 1225 1226 intel_dmc_ucode_suspend(dev_priv); 1227 1228 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1229 1230 i915_gem_drain_freed_objects(dev_priv); 1231 1232 return 0; 1233 } 1234 1235 static enum i915_drm_suspend_mode 1236 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) 1237 { 1238 if (hibernate) 1239 return I915_DRM_SUSPEND_HIBERNATE; 1240 1241 if (suspend_to_idle(dev_priv)) 1242 return I915_DRM_SUSPEND_IDLE; 1243 1244 return I915_DRM_SUSPEND_MEM; 1245 } 1246 1247 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1248 { 1249 struct drm_i915_private *dev_priv = to_i915(dev); 1250 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1251 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1252 struct intel_gt *gt; 1253 int ret, i; 1254 1255 disable_rpm_wakeref_asserts(rpm); 1256 1257 i915_gem_suspend_late(dev_priv); 1258 1259 for_each_gt(gt, dev_priv, i) 1260 intel_uncore_suspend(gt->uncore); 1261 1262 intel_power_domains_suspend(dev_priv, 1263 get_suspend_mode(dev_priv, hibernation)); 1264 1265 intel_display_power_suspend_late(dev_priv); 1266 1267 ret = vlv_suspend_complete(dev_priv); 1268 if (ret) { 1269 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1270 intel_power_domains_resume(dev_priv); 1271 1272 goto out; 1273 } 1274 1275 pci_disable_device(pdev); 1276 /* 1277 * During hibernation on some platforms the BIOS may try to access 1278 * the device even though it's already in D3 and hang the machine. So 1279 * leave the device in D0 on those platforms and hope the BIOS will 1280 * power down the device properly. The issue was seen on multiple old 1281 * GENs with different BIOS vendors, so having an explicit blacklist 1282 * is inpractical; apply the workaround on everything pre GEN6. The 1283 * platforms where the issue was seen: 1284 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1285 * Fujitsu FSC S7110 1286 * Acer Aspire 1830T 1287 */ 1288 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1289 pci_set_power_state(pdev, PCI_D3hot); 1290 1291 out: 1292 enable_rpm_wakeref_asserts(rpm); 1293 if (!dev_priv->uncore.user_forcewake_count) 1294 intel_runtime_pm_driver_release(rpm); 1295 1296 return ret; 1297 } 1298 1299 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1300 pm_message_t state) 1301 { 1302 int error; 1303 1304 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1305 state.event != PM_EVENT_FREEZE)) 1306 return -EINVAL; 1307 1308 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1309 return 0; 1310 1311 error = i915_drm_suspend(&i915->drm); 1312 if (error) 1313 return error; 1314 1315 return i915_drm_suspend_late(&i915->drm, false); 1316 } 1317 1318 static int i915_drm_resume(struct drm_device *dev) 1319 { 1320 struct drm_i915_private *dev_priv = to_i915(dev); 1321 int ret; 1322 1323 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1324 1325 ret = i915_pcode_init(dev_priv); 1326 if (ret) 1327 return ret; 1328 1329 sanitize_gpu(dev_priv); 1330 1331 ret = i915_ggtt_enable_hw(dev_priv); 1332 if (ret) 1333 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1334 1335 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1336 /* Must be called after GGTT is resumed. */ 1337 intel_dpt_resume(dev_priv); 1338 1339 intel_dmc_ucode_resume(dev_priv); 1340 1341 i915_restore_display(dev_priv); 1342 intel_pps_unlock_regs_wa(dev_priv); 1343 1344 intel_init_pch_refclk(dev_priv); 1345 1346 /* 1347 * Interrupts have to be enabled before any batches are run. If not the 1348 * GPU will hang. i915_gem_init_hw() will initiate batches to 1349 * update/restore the context. 1350 * 1351 * drm_mode_config_reset() needs AUX interrupts. 1352 * 1353 * Modeset enabling in intel_modeset_init_hw() also needs working 1354 * interrupts. 1355 */ 1356 intel_runtime_pm_enable_interrupts(dev_priv); 1357 1358 if (HAS_DISPLAY(dev_priv)) 1359 drm_mode_config_reset(dev); 1360 1361 i915_gem_resume(dev_priv); 1362 1363 intel_modeset_init_hw(dev_priv); 1364 intel_init_clock_gating(dev_priv); 1365 intel_hpd_init(dev_priv); 1366 1367 /* MST sideband requires HPD interrupts enabled */ 1368 intel_dp_mst_resume(dev_priv); 1369 intel_display_resume(dev); 1370 1371 intel_hpd_poll_disable(dev_priv); 1372 if (HAS_DISPLAY(dev_priv)) 1373 drm_kms_helper_poll_enable(dev); 1374 1375 intel_opregion_resume(dev_priv); 1376 1377 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1378 1379 intel_power_domains_enable(dev_priv); 1380 1381 intel_gvt_resume(dev_priv); 1382 1383 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1384 1385 return 0; 1386 } 1387 1388 static int i915_drm_resume_early(struct drm_device *dev) 1389 { 1390 struct drm_i915_private *dev_priv = to_i915(dev); 1391 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1392 struct intel_gt *gt; 1393 int ret, i; 1394 1395 /* 1396 * We have a resume ordering issue with the snd-hda driver also 1397 * requiring our device to be power up. Due to the lack of a 1398 * parent/child relationship we currently solve this with an early 1399 * resume hook. 1400 * 1401 * FIXME: This should be solved with a special hdmi sink device or 1402 * similar so that power domains can be employed. 1403 */ 1404 1405 /* 1406 * Note that we need to set the power state explicitly, since we 1407 * powered off the device during freeze and the PCI core won't power 1408 * it back up for us during thaw. Powering off the device during 1409 * freeze is not a hard requirement though, and during the 1410 * suspend/resume phases the PCI core makes sure we get here with the 1411 * device powered on. So in case we change our freeze logic and keep 1412 * the device powered we can also remove the following set power state 1413 * call. 1414 */ 1415 ret = pci_set_power_state(pdev, PCI_D0); 1416 if (ret) { 1417 drm_err(&dev_priv->drm, 1418 "failed to set PCI D0 power state (%d)\n", ret); 1419 return ret; 1420 } 1421 1422 /* 1423 * Note that pci_enable_device() first enables any parent bridge 1424 * device and only then sets the power state for this device. The 1425 * bridge enabling is a nop though, since bridge devices are resumed 1426 * first. The order of enabling power and enabling the device is 1427 * imposed by the PCI core as described above, so here we preserve the 1428 * same order for the freeze/thaw phases. 1429 * 1430 * TODO: eventually we should remove pci_disable_device() / 1431 * pci_enable_enable_device() from suspend/resume. Due to how they 1432 * depend on the device enable refcount we can't anyway depend on them 1433 * disabling/enabling the device. 1434 */ 1435 if (pci_enable_device(pdev)) 1436 return -EIO; 1437 1438 pci_set_master(pdev); 1439 1440 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1441 1442 ret = vlv_resume_prepare(dev_priv, false); 1443 if (ret) 1444 drm_err(&dev_priv->drm, 1445 "Resume prepare failed: %d, continuing anyway\n", ret); 1446 1447 for_each_gt(gt, dev_priv, i) { 1448 intel_uncore_resume_early(gt->uncore); 1449 intel_gt_check_and_clear_faults(gt); 1450 } 1451 1452 intel_display_power_resume_early(dev_priv); 1453 1454 intel_power_domains_resume(dev_priv); 1455 1456 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1457 1458 return ret; 1459 } 1460 1461 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1462 { 1463 int ret; 1464 1465 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1466 return 0; 1467 1468 ret = i915_drm_resume_early(&i915->drm); 1469 if (ret) 1470 return ret; 1471 1472 return i915_drm_resume(&i915->drm); 1473 } 1474 1475 static int i915_pm_prepare(struct device *kdev) 1476 { 1477 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1478 1479 if (!i915) { 1480 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1481 return -ENODEV; 1482 } 1483 1484 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1485 return 0; 1486 1487 return i915_drm_prepare(&i915->drm); 1488 } 1489 1490 static int i915_pm_suspend(struct device *kdev) 1491 { 1492 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1493 1494 if (!i915) { 1495 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1496 return -ENODEV; 1497 } 1498 1499 i915_ggtt_mark_pte_lost(i915, false); 1500 1501 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1502 return 0; 1503 1504 return i915_drm_suspend(&i915->drm); 1505 } 1506 1507 static int i915_pm_suspend_late(struct device *kdev) 1508 { 1509 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1510 1511 /* 1512 * We have a suspend ordering issue with the snd-hda driver also 1513 * requiring our device to be power up. Due to the lack of a 1514 * parent/child relationship we currently solve this with an late 1515 * suspend hook. 1516 * 1517 * FIXME: This should be solved with a special hdmi sink device or 1518 * similar so that power domains can be employed. 1519 */ 1520 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1521 return 0; 1522 1523 return i915_drm_suspend_late(&i915->drm, false); 1524 } 1525 1526 static int i915_pm_poweroff_late(struct device *kdev) 1527 { 1528 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1529 1530 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1531 return 0; 1532 1533 return i915_drm_suspend_late(&i915->drm, true); 1534 } 1535 1536 static int i915_pm_resume_early(struct device *kdev) 1537 { 1538 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1539 1540 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1541 return 0; 1542 1543 return i915_drm_resume_early(&i915->drm); 1544 } 1545 1546 static int i915_pm_resume(struct device *kdev) 1547 { 1548 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1549 1550 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1551 return 0; 1552 1553 /* 1554 * If IRST is enabled, or if we can't detect whether it's enabled, 1555 * then we must assume we lost the GGTT page table entries, since 1556 * they are not retained if IRST decided to enter S4. 1557 */ 1558 if (!IS_ENABLED(CONFIG_ACPI) || acpi_dev_present(irst_name, NULL, -1)) 1559 i915_ggtt_mark_pte_lost(i915, true); 1560 1561 return i915_drm_resume(&i915->drm); 1562 } 1563 1564 /* freeze: before creating the hibernation_image */ 1565 static int i915_pm_freeze(struct device *kdev) 1566 { 1567 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1568 int ret; 1569 1570 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1571 ret = i915_drm_suspend(&i915->drm); 1572 if (ret) 1573 return ret; 1574 } 1575 1576 ret = i915_gem_freeze(i915); 1577 if (ret) 1578 return ret; 1579 1580 return 0; 1581 } 1582 1583 static int i915_pm_freeze_late(struct device *kdev) 1584 { 1585 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1586 int ret; 1587 1588 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1589 ret = i915_drm_suspend_late(&i915->drm, true); 1590 if (ret) 1591 return ret; 1592 } 1593 1594 ret = i915_gem_freeze_late(i915); 1595 if (ret) 1596 return ret; 1597 1598 return 0; 1599 } 1600 1601 /* thaw: called after creating the hibernation image, but before turning off. */ 1602 static int i915_pm_thaw_early(struct device *kdev) 1603 { 1604 return i915_pm_resume_early(kdev); 1605 } 1606 1607 static int i915_pm_thaw(struct device *kdev) 1608 { 1609 return i915_pm_resume(kdev); 1610 } 1611 1612 /* restore: called after loading the hibernation image. */ 1613 static int i915_pm_restore_early(struct device *kdev) 1614 { 1615 return i915_pm_resume_early(kdev); 1616 } 1617 1618 static int i915_pm_restore(struct device *kdev) 1619 { 1620 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1621 1622 i915_ggtt_mark_pte_lost(i915, true); 1623 return i915_pm_resume(kdev); 1624 } 1625 1626 static int intel_runtime_suspend(struct device *kdev) 1627 { 1628 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1629 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1630 struct intel_gt *gt; 1631 int ret, i; 1632 1633 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1634 return -ENODEV; 1635 1636 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1637 1638 disable_rpm_wakeref_asserts(rpm); 1639 1640 /* 1641 * We are safe here against re-faults, since the fault handler takes 1642 * an RPM reference. 1643 */ 1644 i915_gem_runtime_suspend(dev_priv); 1645 1646 for_each_gt(gt, dev_priv, i) 1647 intel_gt_runtime_suspend(gt); 1648 1649 intel_runtime_pm_disable_interrupts(dev_priv); 1650 1651 for_each_gt(gt, dev_priv, i) 1652 intel_uncore_suspend(gt->uncore); 1653 1654 intel_display_power_suspend(dev_priv); 1655 1656 ret = vlv_suspend_complete(dev_priv); 1657 if (ret) { 1658 drm_err(&dev_priv->drm, 1659 "Runtime suspend failed, disabling it (%d)\n", ret); 1660 intel_uncore_runtime_resume(&dev_priv->uncore); 1661 1662 intel_runtime_pm_enable_interrupts(dev_priv); 1663 1664 intel_gt_runtime_resume(to_gt(dev_priv)); 1665 1666 enable_rpm_wakeref_asserts(rpm); 1667 1668 return ret; 1669 } 1670 1671 enable_rpm_wakeref_asserts(rpm); 1672 intel_runtime_pm_driver_release(rpm); 1673 1674 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1675 drm_err(&dev_priv->drm, 1676 "Unclaimed access detected prior to suspending\n"); 1677 1678 rpm->suspended = true; 1679 1680 /* 1681 * FIXME: We really should find a document that references the arguments 1682 * used below! 1683 */ 1684 if (IS_BROADWELL(dev_priv)) { 1685 /* 1686 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1687 * being detected, and the call we do at intel_runtime_resume() 1688 * won't be able to restore them. Since PCI_D3hot matches the 1689 * actual specification and appears to be working, use it. 1690 */ 1691 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1692 } else { 1693 /* 1694 * current versions of firmware which depend on this opregion 1695 * notification have repurposed the D1 definition to mean 1696 * "runtime suspended" vs. what you would normally expect (D3) 1697 * to distinguish it from notifications that might be sent via 1698 * the suspend path. 1699 */ 1700 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1701 } 1702 1703 assert_forcewakes_inactive(&dev_priv->uncore); 1704 1705 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1706 intel_hpd_poll_enable(dev_priv); 1707 1708 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1709 return 0; 1710 } 1711 1712 static int intel_runtime_resume(struct device *kdev) 1713 { 1714 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1715 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1716 struct intel_gt *gt; 1717 int ret, i; 1718 1719 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1720 return -ENODEV; 1721 1722 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1723 1724 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1725 disable_rpm_wakeref_asserts(rpm); 1726 1727 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1728 rpm->suspended = false; 1729 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1730 drm_dbg(&dev_priv->drm, 1731 "Unclaimed access during suspend, bios?\n"); 1732 1733 intel_display_power_resume(dev_priv); 1734 1735 ret = vlv_resume_prepare(dev_priv, true); 1736 1737 for_each_gt(gt, dev_priv, i) 1738 intel_uncore_runtime_resume(gt->uncore); 1739 1740 intel_runtime_pm_enable_interrupts(dev_priv); 1741 1742 /* 1743 * No point of rolling back things in case of an error, as the best 1744 * we can do is to hope that things will still work (and disable RPM). 1745 */ 1746 for_each_gt(gt, dev_priv, i) 1747 intel_gt_runtime_resume(gt); 1748 1749 /* 1750 * On VLV/CHV display interrupts are part of the display 1751 * power well, so hpd is reinitialized from there. For 1752 * everyone else do it here. 1753 */ 1754 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1755 intel_hpd_init(dev_priv); 1756 intel_hpd_poll_disable(dev_priv); 1757 } 1758 1759 skl_watermark_ipc_update(dev_priv); 1760 1761 enable_rpm_wakeref_asserts(rpm); 1762 1763 if (ret) 1764 drm_err(&dev_priv->drm, 1765 "Runtime resume failed, disabling it (%d)\n", ret); 1766 else 1767 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1768 1769 return ret; 1770 } 1771 1772 const struct dev_pm_ops i915_pm_ops = { 1773 /* 1774 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1775 * PMSG_RESUME] 1776 */ 1777 .prepare = i915_pm_prepare, 1778 .suspend = i915_pm_suspend, 1779 .suspend_late = i915_pm_suspend_late, 1780 .resume_early = i915_pm_resume_early, 1781 .resume = i915_pm_resume, 1782 1783 /* 1784 * S4 event handlers 1785 * @freeze, @freeze_late : called (1) before creating the 1786 * hibernation image [PMSG_FREEZE] and 1787 * (2) after rebooting, before restoring 1788 * the image [PMSG_QUIESCE] 1789 * @thaw, @thaw_early : called (1) after creating the hibernation 1790 * image, before writing it [PMSG_THAW] 1791 * and (2) after failing to create or 1792 * restore the image [PMSG_RECOVER] 1793 * @poweroff, @poweroff_late: called after writing the hibernation 1794 * image, before rebooting [PMSG_HIBERNATE] 1795 * @restore, @restore_early : called after rebooting and restoring the 1796 * hibernation image [PMSG_RESTORE] 1797 */ 1798 .freeze = i915_pm_freeze, 1799 .freeze_late = i915_pm_freeze_late, 1800 .thaw_early = i915_pm_thaw_early, 1801 .thaw = i915_pm_thaw, 1802 .poweroff = i915_pm_suspend, 1803 .poweroff_late = i915_pm_poweroff_late, 1804 .restore_early = i915_pm_restore_early, 1805 .restore = i915_pm_restore, 1806 1807 /* S0ix (via runtime suspend) event handlers */ 1808 .runtime_suspend = intel_runtime_suspend, 1809 .runtime_resume = intel_runtime_resume, 1810 }; 1811 1812 static const struct file_operations i915_driver_fops = { 1813 .owner = THIS_MODULE, 1814 .open = drm_open, 1815 .release = drm_release_noglobal, 1816 .unlocked_ioctl = drm_ioctl, 1817 .mmap = i915_gem_mmap, 1818 .poll = drm_poll, 1819 .read = drm_read, 1820 .compat_ioctl = i915_ioc32_compat_ioctl, 1821 .llseek = noop_llseek, 1822 #ifdef CONFIG_PROC_FS 1823 .show_fdinfo = i915_drm_client_fdinfo, 1824 #endif 1825 }; 1826 1827 static int 1828 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1829 struct drm_file *file) 1830 { 1831 return -ENODEV; 1832 } 1833 1834 static const struct drm_ioctl_desc i915_ioctls[] = { 1835 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1836 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1837 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1838 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1839 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1840 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1841 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1842 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1843 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1844 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1845 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1846 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1847 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1848 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1849 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1850 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1851 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1852 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1853 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1854 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1855 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1856 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1857 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1858 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1859 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1860 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1861 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1862 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1863 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1864 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1865 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1866 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1867 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1868 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1869 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1870 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1871 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1872 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1873 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1874 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1875 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1876 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1877 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1878 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1879 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1880 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1881 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1882 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1883 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1884 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1885 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1886 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1887 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1888 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1889 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1890 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1891 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1892 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1893 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1894 }; 1895 1896 /* 1897 * Interface history: 1898 * 1899 * 1.1: Original. 1900 * 1.2: Add Power Management 1901 * 1.3: Add vblank support 1902 * 1.4: Fix cmdbuffer path, add heap destroy 1903 * 1.5: Add vblank pipe configuration 1904 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1905 * - Support vertical blank on secondary display pipe 1906 */ 1907 #define DRIVER_MAJOR 1 1908 #define DRIVER_MINOR 6 1909 #define DRIVER_PATCHLEVEL 0 1910 1911 static const struct drm_driver i915_drm_driver = { 1912 /* Don't use MTRRs here; the Xserver or userspace app should 1913 * deal with them for Intel hardware. 1914 */ 1915 .driver_features = 1916 DRIVER_GEM | 1917 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1918 DRIVER_SYNCOBJ_TIMELINE, 1919 .release = i915_driver_release, 1920 .open = i915_driver_open, 1921 .lastclose = i915_driver_lastclose, 1922 .postclose = i915_driver_postclose, 1923 1924 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1925 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1926 .gem_prime_import = i915_gem_prime_import, 1927 1928 .dumb_create = i915_gem_dumb_create, 1929 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1930 1931 .ioctls = i915_ioctls, 1932 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1933 .fops = &i915_driver_fops, 1934 .name = DRIVER_NAME, 1935 .desc = DRIVER_DESC, 1936 .date = DRIVER_DATE, 1937 .major = DRIVER_MAJOR, 1938 .minor = DRIVER_MINOR, 1939 .patchlevel = DRIVER_PATCHLEVEL, 1940 }; 1941