1*04d348aeSZhi Wang /* 2*04d348aeSZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3*04d348aeSZhi Wang * 4*04d348aeSZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 5*04d348aeSZhi Wang * copy of this software and associated documentation files (the "Software"), 6*04d348aeSZhi Wang * to deal in the Software without restriction, including without limitation 7*04d348aeSZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*04d348aeSZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 9*04d348aeSZhi Wang * Software is furnished to do so, subject to the following conditions: 10*04d348aeSZhi Wang * 11*04d348aeSZhi Wang * The above copyright notice and this permission notice (including the next 12*04d348aeSZhi Wang * paragraph) shall be included in all copies or substantial portions of the 13*04d348aeSZhi Wang * Software. 14*04d348aeSZhi Wang * 15*04d348aeSZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*04d348aeSZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*04d348aeSZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*04d348aeSZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19*04d348aeSZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20*04d348aeSZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21*04d348aeSZhi Wang * SOFTWARE. 22*04d348aeSZhi Wang * 23*04d348aeSZhi Wang * Authors: 24*04d348aeSZhi Wang * Ke Yu 25*04d348aeSZhi Wang * Zhiyuan Lv <zhiyuan.lv@intel.com> 26*04d348aeSZhi Wang * 27*04d348aeSZhi Wang * Contributors: 28*04d348aeSZhi Wang * Terrence Xu <terrence.xu@intel.com> 29*04d348aeSZhi Wang * Changbin Du <changbin.du@intel.com> 30*04d348aeSZhi Wang * Bing Niu <bing.niu@intel.com> 31*04d348aeSZhi Wang * Zhi Wang <zhi.a.wang@intel.com> 32*04d348aeSZhi Wang * 33*04d348aeSZhi Wang */ 34*04d348aeSZhi Wang 35*04d348aeSZhi Wang #ifndef _GVT_EDID_H_ 36*04d348aeSZhi Wang #define _GVT_EDID_H_ 37*04d348aeSZhi Wang 38*04d348aeSZhi Wang #define EDID_SIZE 128 39*04d348aeSZhi Wang #define EDID_ADDR 0x50 /* Linux hvm EDID addr */ 40*04d348aeSZhi Wang 41*04d348aeSZhi Wang #define GVT_AUX_NATIVE_WRITE 0x8 42*04d348aeSZhi Wang #define GVT_AUX_NATIVE_READ 0x9 43*04d348aeSZhi Wang #define GVT_AUX_I2C_WRITE 0x0 44*04d348aeSZhi Wang #define GVT_AUX_I2C_READ 0x1 45*04d348aeSZhi Wang #define GVT_AUX_I2C_STATUS 0x2 46*04d348aeSZhi Wang #define GVT_AUX_I2C_MOT 0x4 47*04d348aeSZhi Wang #define GVT_AUX_I2C_REPLY_ACK (0x0 << 6) 48*04d348aeSZhi Wang 49*04d348aeSZhi Wang struct intel_vgpu_edid_data { 50*04d348aeSZhi Wang bool data_valid; 51*04d348aeSZhi Wang unsigned char edid_block[EDID_SIZE]; 52*04d348aeSZhi Wang }; 53*04d348aeSZhi Wang 54*04d348aeSZhi Wang enum gmbus_cycle_type { 55*04d348aeSZhi Wang GMBUS_NOCYCLE = 0x0, 56*04d348aeSZhi Wang NIDX_NS_W = 0x1, 57*04d348aeSZhi Wang IDX_NS_W = 0x3, 58*04d348aeSZhi Wang GMBUS_STOP = 0x4, 59*04d348aeSZhi Wang NIDX_STOP = 0x5, 60*04d348aeSZhi Wang IDX_STOP = 0x7 61*04d348aeSZhi Wang }; 62*04d348aeSZhi Wang 63*04d348aeSZhi Wang /* 64*04d348aeSZhi Wang * States of GMBUS 65*04d348aeSZhi Wang * 66*04d348aeSZhi Wang * GMBUS0-3 could be related to the EDID virtualization. Another two GMBUS 67*04d348aeSZhi Wang * registers, GMBUS4 (interrupt mask) and GMBUS5 (2 byte indes register), are 68*04d348aeSZhi Wang * not considered here. Below describes the usage of GMBUS registers that are 69*04d348aeSZhi Wang * cared by the EDID virtualization 70*04d348aeSZhi Wang * 71*04d348aeSZhi Wang * GMBUS0: 72*04d348aeSZhi Wang * R/W 73*04d348aeSZhi Wang * port selection. value of bit0 - bit2 corresponds to the GPIO registers. 74*04d348aeSZhi Wang * 75*04d348aeSZhi Wang * GMBUS1: 76*04d348aeSZhi Wang * R/W Protect 77*04d348aeSZhi Wang * Command and Status. 78*04d348aeSZhi Wang * bit0 is the direction bit: 1 is read; 0 is write. 79*04d348aeSZhi Wang * bit1 - bit7 is slave 7-bit address. 80*04d348aeSZhi Wang * bit16 - bit24 total byte count (ignore?) 81*04d348aeSZhi Wang * 82*04d348aeSZhi Wang * GMBUS2: 83*04d348aeSZhi Wang * Most of bits are read only except bit 15 (IN_USE) 84*04d348aeSZhi Wang * Status register 85*04d348aeSZhi Wang * bit0 - bit8 current byte count 86*04d348aeSZhi Wang * bit 11: hardware ready; 87*04d348aeSZhi Wang * 88*04d348aeSZhi Wang * GMBUS3: 89*04d348aeSZhi Wang * Read/Write 90*04d348aeSZhi Wang * Data for transfer 91*04d348aeSZhi Wang */ 92*04d348aeSZhi Wang 93*04d348aeSZhi Wang /* From hw specs, Other phases like START, ADDRESS, INDEX 94*04d348aeSZhi Wang * are invisible to GMBUS MMIO interface. So no definitions 95*04d348aeSZhi Wang * in below enum types 96*04d348aeSZhi Wang */ 97*04d348aeSZhi Wang enum gvt_gmbus_phase { 98*04d348aeSZhi Wang GMBUS_IDLE_PHASE = 0, 99*04d348aeSZhi Wang GMBUS_DATA_PHASE, 100*04d348aeSZhi Wang GMBUS_WAIT_PHASE, 101*04d348aeSZhi Wang //GMBUS_STOP_PHASE, 102*04d348aeSZhi Wang GMBUS_MAX_PHASE 103*04d348aeSZhi Wang }; 104*04d348aeSZhi Wang 105*04d348aeSZhi Wang struct intel_vgpu_i2c_gmbus { 106*04d348aeSZhi Wang unsigned int total_byte_count; /* from GMBUS1 */ 107*04d348aeSZhi Wang enum gmbus_cycle_type cycle_type; 108*04d348aeSZhi Wang enum gvt_gmbus_phase phase; 109*04d348aeSZhi Wang }; 110*04d348aeSZhi Wang 111*04d348aeSZhi Wang struct intel_vgpu_i2c_aux_ch { 112*04d348aeSZhi Wang bool i2c_over_aux_ch; 113*04d348aeSZhi Wang bool aux_ch_mot; 114*04d348aeSZhi Wang }; 115*04d348aeSZhi Wang 116*04d348aeSZhi Wang enum i2c_state { 117*04d348aeSZhi Wang I2C_NOT_SPECIFIED = 0, 118*04d348aeSZhi Wang I2C_GMBUS = 1, 119*04d348aeSZhi Wang I2C_AUX_CH = 2 120*04d348aeSZhi Wang }; 121*04d348aeSZhi Wang 122*04d348aeSZhi Wang /* I2C sequences cannot interleave. 123*04d348aeSZhi Wang * GMBUS and AUX_CH sequences cannot interleave. 124*04d348aeSZhi Wang */ 125*04d348aeSZhi Wang struct intel_vgpu_i2c_edid { 126*04d348aeSZhi Wang enum i2c_state state; 127*04d348aeSZhi Wang 128*04d348aeSZhi Wang unsigned int port; 129*04d348aeSZhi Wang bool slave_selected; 130*04d348aeSZhi Wang bool edid_available; 131*04d348aeSZhi Wang unsigned int current_edid_read; 132*04d348aeSZhi Wang 133*04d348aeSZhi Wang struct intel_vgpu_i2c_gmbus gmbus; 134*04d348aeSZhi Wang struct intel_vgpu_i2c_aux_ch aux_ch; 135*04d348aeSZhi Wang }; 136*04d348aeSZhi Wang 137*04d348aeSZhi Wang void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu); 138*04d348aeSZhi Wang 139*04d348aeSZhi Wang int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu, 140*04d348aeSZhi Wang unsigned int offset, void *p_data, unsigned int bytes); 141*04d348aeSZhi Wang 142*04d348aeSZhi Wang int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu, 143*04d348aeSZhi Wang unsigned int offset, void *p_data, unsigned int bytes); 144*04d348aeSZhi Wang 145*04d348aeSZhi Wang void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu, 146*04d348aeSZhi Wang int port_idx, 147*04d348aeSZhi Wang unsigned int offset, 148*04d348aeSZhi Wang void *p_data); 149*04d348aeSZhi Wang 150*04d348aeSZhi Wang #endif /*_GVT_EDID_H_*/ 151