xref: /openbmc/linux/drivers/gpu/drm/i915/gt/gen2_engine_cs.h (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
1*c1f85878SChris Wilson /* SPDX-License-Identifier: MIT */
2*c1f85878SChris Wilson /*
3*c1f85878SChris Wilson  * Copyright © 2020 Intel Corporation
4*c1f85878SChris Wilson  */
5*c1f85878SChris Wilson 
6*c1f85878SChris Wilson #ifndef __GEN2_ENGINE_CS_H__
7*c1f85878SChris Wilson #define __GEN2_ENGINE_CS_H__
8*c1f85878SChris Wilson 
9*c1f85878SChris Wilson #include <linux/types.h>
10*c1f85878SChris Wilson 
11*c1f85878SChris Wilson struct i915_request;
12*c1f85878SChris Wilson struct intel_engine_cs;
13*c1f85878SChris Wilson 
14*c1f85878SChris Wilson int gen2_emit_flush(struct i915_request *rq, u32 mode);
15*c1f85878SChris Wilson int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode);
16*c1f85878SChris Wilson int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode);
17*c1f85878SChris Wilson 
18*c1f85878SChris Wilson u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs);
19*c1f85878SChris Wilson u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs);
20*c1f85878SChris Wilson 
21*c1f85878SChris Wilson int i830_emit_bb_start(struct i915_request *rq,
22*c1f85878SChris Wilson 		       u64 offset, u32 len,
23*c1f85878SChris Wilson 		       unsigned int dispatch_flags);
24*c1f85878SChris Wilson int gen3_emit_bb_start(struct i915_request *rq,
25*c1f85878SChris Wilson 		       u64 offset, u32 len,
26*c1f85878SChris Wilson 		       unsigned int dispatch_flags);
27*c1f85878SChris Wilson int gen4_emit_bb_start(struct i915_request *rq,
28*c1f85878SChris Wilson 		       u64 offset, u32 length,
29*c1f85878SChris Wilson 		       unsigned int dispatch_flags);
30*c1f85878SChris Wilson 
31*c1f85878SChris Wilson void gen2_irq_enable(struct intel_engine_cs *engine);
32*c1f85878SChris Wilson void gen2_irq_disable(struct intel_engine_cs *engine);
33*c1f85878SChris Wilson void gen3_irq_enable(struct intel_engine_cs *engine);
34*c1f85878SChris Wilson void gen3_irq_disable(struct intel_engine_cs *engine);
35*c1f85878SChris Wilson void gen5_irq_enable(struct intel_engine_cs *engine);
36*c1f85878SChris Wilson void gen5_irq_disable(struct intel_engine_cs *engine);
37*c1f85878SChris Wilson 
38*c1f85878SChris Wilson #endif /* __GEN2_ENGINE_CS_H__ */
39