1*065695b3SJani Nikula /* SPDX-License-Identifier: MIT */ 2*065695b3SJani Nikula /* 3*065695b3SJani Nikula * Copyright © 2023 Intel Corporation 4*065695b3SJani Nikula */ 5*065695b3SJani Nikula 6*065695b3SJani Nikula #ifndef __INTEL_PPS_REGS_H__ 7*065695b3SJani Nikula #define __INTEL_PPS_REGS_H__ 8*065695b3SJani Nikula 9*065695b3SJani Nikula #include "intel_display_reg_defs.h" 10*065695b3SJani Nikula 11*065695b3SJani Nikula /* Panel power sequencing */ 12*065695b3SJani Nikula #define PPS_BASE 0x61200 13*065695b3SJani Nikula #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 14*065695b3SJani Nikula #define PCH_PPS_BASE 0xC7200 15*065695b3SJani Nikula 16*065695b3SJani Nikula #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \ 17*065695b3SJani Nikula PPS_BASE + (reg) + \ 18*065695b3SJani Nikula (pps_idx) * 0x100) 19*065695b3SJani Nikula 20*065695b3SJani Nikula #define _PP_STATUS 0x61200 21*065695b3SJani Nikula #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 22*065695b3SJani Nikula #define PP_ON REG_BIT(31) 23*065695b3SJani Nikula /* 24*065695b3SJani Nikula * Indicates that all dependencies of the panel are on: 25*065695b3SJani Nikula * 26*065695b3SJani Nikula * - PLL enabled 27*065695b3SJani Nikula * - pipe enabled 28*065695b3SJani Nikula * - LVDS/DVOB/DVOC on 29*065695b3SJani Nikula */ 30*065695b3SJani Nikula #define PP_READY REG_BIT(30) 31*065695b3SJani Nikula #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 32*065695b3SJani Nikula #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 33*065695b3SJani Nikula #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 34*065695b3SJani Nikula #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 35*065695b3SJani Nikula #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 36*065695b3SJani Nikula #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 37*065695b3SJani Nikula #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 38*065695b3SJani Nikula #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 39*065695b3SJani Nikula #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 40*065695b3SJani Nikula #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 41*065695b3SJani Nikula #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 42*065695b3SJani Nikula #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 43*065695b3SJani Nikula #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 44*065695b3SJani Nikula #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 45*065695b3SJani Nikula #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 46*065695b3SJani Nikula 47*065695b3SJani Nikula #define _PP_CONTROL 0x61204 48*065695b3SJani Nikula #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 49*065695b3SJani Nikula #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 50*065695b3SJani Nikula #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 51*065695b3SJani Nikula #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 52*065695b3SJani Nikula #define EDP_FORCE_VDD REG_BIT(3) 53*065695b3SJani Nikula #define EDP_BLC_ENABLE REG_BIT(2) 54*065695b3SJani Nikula #define PANEL_POWER_RESET REG_BIT(1) 55*065695b3SJani Nikula #define PANEL_POWER_ON REG_BIT(0) 56*065695b3SJani Nikula 57*065695b3SJani Nikula #define _PP_ON_DELAYS 0x61208 58*065695b3SJani Nikula #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 59*065695b3SJani Nikula #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 60*065695b3SJani Nikula #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 61*065695b3SJani Nikula #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 62*065695b3SJani Nikula #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 63*065695b3SJani Nikula #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 64*065695b3SJani Nikula #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 65*065695b3SJani Nikula #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 66*065695b3SJani Nikula #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 67*065695b3SJani Nikula 68*065695b3SJani Nikula #define _PP_OFF_DELAYS 0x6120C 69*065695b3SJani Nikula #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 70*065695b3SJani Nikula #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 71*065695b3SJani Nikula #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 72*065695b3SJani Nikula 73*065695b3SJani Nikula #define _PP_DIVISOR 0x61210 74*065695b3SJani Nikula #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 75*065695b3SJani Nikula #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 76*065695b3SJani Nikula #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 77*065695b3SJani Nikula 78*065695b3SJani Nikula #endif /* __INTEL_PPS_REGS_H__ */ 79