12b874a02SJani Nikula /* SPDX-License-Identifier: MIT */ 22b874a02SJani Nikula /* 32b874a02SJani Nikula * Copyright © 2023 Intel Corporation 42b874a02SJani Nikula */ 52b874a02SJani Nikula 62b874a02SJani Nikula #ifndef __INTEL_DISPLAY_IRQ_H__ 72b874a02SJani Nikula #define __INTEL_DISPLAY_IRQ_H__ 82b874a02SJani Nikula 92b874a02SJani Nikula #include <linux/types.h> 102b874a02SJani Nikula 112b874a02SJani Nikula #include "intel_display_limits.h" 122b874a02SJani Nikula 132b874a02SJani Nikula enum pipe; 142b874a02SJani Nikula struct drm_i915_private; 152b874a02SJani Nikula struct drm_crtc; 162b874a02SJani Nikula 172b874a02SJani Nikula void valleyview_enable_display_irqs(struct drm_i915_private *i915); 182b874a02SJani Nikula void valleyview_disable_display_irqs(struct drm_i915_private *i915); 192b874a02SJani Nikula 202b874a02SJani Nikula void ilk_update_display_irq(struct drm_i915_private *i915, 212b874a02SJani Nikula u32 interrupt_mask, u32 enabled_irq_mask); 222b874a02SJani Nikula void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits); 232b874a02SJani Nikula void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits); 242b874a02SJani Nikula 252b874a02SJani Nikula void bdw_update_port_irq(struct drm_i915_private *i915, u32 interrupt_mask, u32 enabled_irq_mask); 262b874a02SJani Nikula void bdw_enable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits); 272b874a02SJani Nikula void bdw_disable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits); 282b874a02SJani Nikula 292b874a02SJani Nikula void ibx_display_interrupt_update(struct drm_i915_private *i915, 302b874a02SJani Nikula u32 interrupt_mask, u32 enabled_irq_mask); 312b874a02SJani Nikula void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits); 322b874a02SJani Nikula void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits); 332b874a02SJani Nikula 342b874a02SJani Nikula void gen8_irq_power_well_post_enable(struct drm_i915_private *i915, u8 pipe_mask); 352b874a02SJani Nikula void gen8_irq_power_well_pre_disable(struct drm_i915_private *i915, u8 pipe_mask); 362b874a02SJani Nikula u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *i915); 372b874a02SJani Nikula 382b874a02SJani Nikula int i8xx_enable_vblank(struct drm_crtc *crtc); 392b874a02SJani Nikula int i915gm_enable_vblank(struct drm_crtc *crtc); 402b874a02SJani Nikula int i965_enable_vblank(struct drm_crtc *crtc); 412b874a02SJani Nikula int ilk_enable_vblank(struct drm_crtc *crtc); 422b874a02SJani Nikula int bdw_enable_vblank(struct drm_crtc *crtc); 432b874a02SJani Nikula void i8xx_disable_vblank(struct drm_crtc *crtc); 442b874a02SJani Nikula void i915gm_disable_vblank(struct drm_crtc *crtc); 452b874a02SJani Nikula void i965_disable_vblank(struct drm_crtc *crtc); 462b874a02SJani Nikula void ilk_disable_vblank(struct drm_crtc *crtc); 472b874a02SJani Nikula void bdw_disable_vblank(struct drm_crtc *crtc); 482b874a02SJani Nikula 492b874a02SJani Nikula void ivb_display_irq_handler(struct drm_i915_private *i915, u32 de_iir); 502b874a02SJani Nikula void ilk_display_irq_handler(struct drm_i915_private *i915, u32 de_iir); 512b874a02SJani Nikula void gen8_de_irq_handler(struct drm_i915_private *i915, u32 master_ctl); 522b874a02SJani Nikula void gen11_display_irq_handler(struct drm_i915_private *i915); 532b874a02SJani Nikula 542b874a02SJani Nikula u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl); 552b874a02SJani Nikula void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir); 562b874a02SJani Nikula 572b874a02SJani Nikula void vlv_display_irq_reset(struct drm_i915_private *i915); 582b874a02SJani Nikula void gen8_display_irq_reset(struct drm_i915_private *i915); 592b874a02SJani Nikula void gen11_display_irq_reset(struct drm_i915_private *i915); 602b874a02SJani Nikula 612b874a02SJani Nikula void vlv_display_irq_postinstall(struct drm_i915_private *i915); 62*fcc02c75SJani Nikula void ilk_de_irq_postinstall(struct drm_i915_private *i915); 632b874a02SJani Nikula void gen8_de_irq_postinstall(struct drm_i915_private *i915); 642b874a02SJani Nikula void gen11_de_irq_postinstall(struct drm_i915_private *i915); 651007337fSJani Nikula void dg1_de_irq_postinstall(struct drm_i915_private *i915); 662b874a02SJani Nikula 672b874a02SJani Nikula u32 i915_pipestat_enable_mask(struct drm_i915_private *i915, enum pipe pipe); 682b874a02SJani Nikula void i915_enable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask); 692b874a02SJani Nikula void i915_disable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask); 702b874a02SJani Nikula void i915_enable_asle_pipestat(struct drm_i915_private *i915); 712b874a02SJani Nikula void i9xx_pipestat_irq_reset(struct drm_i915_private *i915); 722b874a02SJani Nikula 732b874a02SJani Nikula void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 742b874a02SJani Nikula 752b874a02SJani Nikula void i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 762b874a02SJani Nikula void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 772b874a02SJani Nikula void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_stats[I915_MAX_PIPES]); 782b874a02SJani Nikula void i8xx_pipestat_irq_handler(struct drm_i915_private *i915, u16 iir, u32 pipe_stats[I915_MAX_PIPES]); 792b874a02SJani Nikula 801486d040SJani Nikula void intel_display_irq_init(struct drm_i915_private *i915); 811486d040SJani Nikula 822b874a02SJani Nikula #endif /* __INTEL_DISPLAY_IRQ_H__ */ 83