1df0566a6SJani Nikula /* SPDX-License-Identifier: MIT */ 2df0566a6SJani Nikula /* 3df0566a6SJani Nikula * Copyright © 2019 Intel Corporation 4df0566a6SJani Nikula */ 5df0566a6SJani Nikula 6df0566a6SJani Nikula #ifndef __INTEL_BW_H__ 7df0566a6SJani Nikula #define __INTEL_BW_H__ 8df0566a6SJani Nikula 9df0566a6SJani Nikula #include <drm/drm_atomic.h> 10df0566a6SJani Nikula 11acc855d3SJani Nikula #include "intel_display_limits.h" 12cd191546SStanislav Lisovskiy #include "intel_display_power.h" 13cac91e67SStanislav Lisovskiy #include "intel_global_state.h" 14df0566a6SJani Nikula 15df0566a6SJani Nikula struct drm_i915_private; 16df0566a6SJani Nikula struct intel_atomic_state; 17df0566a6SJani Nikula struct intel_crtc_state; 18df0566a6SJani Nikula 19cd191546SStanislav Lisovskiy struct intel_dbuf_bw { 205ac860ccSVille Syrjälä unsigned int max_bw[I915_MAX_DBUF_SLICES]; 215ac860ccSVille Syrjälä u8 active_planes[I915_MAX_DBUF_SLICES]; 22cd191546SStanislav Lisovskiy }; 23cd191546SStanislav Lisovskiy 24df0566a6SJani Nikula struct intel_bw_state { 25fd1a9bbaSVille Syrjälä struct intel_global_state base; 26cd191546SStanislav Lisovskiy struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES]; 27df0566a6SJani Nikula 289728889fSStanislav Lisovskiy /* 299728889fSStanislav Lisovskiy * Contains a bit mask, used to determine, whether correspondent 309728889fSStanislav Lisovskiy * pipe allows SAGV or not. 319728889fSStanislav Lisovskiy */ 329728889fSStanislav Lisovskiy u8 pipe_sagv_reject; 339728889fSStanislav Lisovskiy 34c0299cc9SVille Syrjälä /* bitmask of active pipes */ 35c0299cc9SVille Syrjälä u8 active_pipes; 36c0299cc9SVille Syrjälä 3720f505f2SStanislav Lisovskiy /* 38*a5819e51SVinod Govindapillai * From MTL onwards, to lock a QGV point, punit expects the peak BW of 39*a5819e51SVinod Govindapillai * the selected QGV point as the parameter in multiples of 100MB/s 40*a5819e51SVinod Govindapillai */ 41*a5819e51SVinod Govindapillai u16 qgv_point_peakbw; 42*a5819e51SVinod Govindapillai 43*a5819e51SVinod Govindapillai /* 4420f505f2SStanislav Lisovskiy * Current QGV points mask, which restricts 4520f505f2SStanislav Lisovskiy * some particular SAGV states, not to confuse 4620f505f2SStanislav Lisovskiy * with pipe_sagv_mask. 4720f505f2SStanislav Lisovskiy */ 48c0299cc9SVille Syrjälä u16 qgv_points_mask; 4920f505f2SStanislav Lisovskiy 50ea083969SVille Syrjälä int min_cdclk[I915_MAX_PIPES]; 51df0566a6SJani Nikula unsigned int data_rate[I915_MAX_PIPES]; 52df0566a6SJani Nikula u8 num_active_planes[I915_MAX_PIPES]; 53df0566a6SJani Nikula }; 54df0566a6SJani Nikula 55df0566a6SJani Nikula #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base) 56df0566a6SJani Nikula 57442e7ee8SStanislav Lisovskiy struct intel_bw_state * 58442e7ee8SStanislav Lisovskiy intel_atomic_get_old_bw_state(struct intel_atomic_state *state); 59442e7ee8SStanislav Lisovskiy 60442e7ee8SStanislav Lisovskiy struct intel_bw_state * 61442e7ee8SStanislav Lisovskiy intel_atomic_get_new_bw_state(struct intel_atomic_state *state); 62442e7ee8SStanislav Lisovskiy 63442e7ee8SStanislav Lisovskiy struct intel_bw_state * 64442e7ee8SStanislav Lisovskiy intel_atomic_get_bw_state(struct intel_atomic_state *state); 65442e7ee8SStanislav Lisovskiy 66df0566a6SJani Nikula void intel_bw_init_hw(struct drm_i915_private *dev_priv); 67df0566a6SJani Nikula int intel_bw_init(struct drm_i915_private *dev_priv); 68df0566a6SJani Nikula int intel_bw_atomic_check(struct intel_atomic_state *state); 69df0566a6SJani Nikula void intel_bw_crtc_update(struct intel_bw_state *bw_state, 70df0566a6SJani Nikula const struct intel_crtc_state *crtc_state); 7120f505f2SStanislav Lisovskiy int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, 7220f505f2SStanislav Lisovskiy u32 points_mask); 735ac860ccSVille Syrjälä int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, 745ac860ccSVille Syrjälä bool *need_cdclk_calc); 755ac860ccSVille Syrjälä int intel_bw_min_cdclk(struct drm_i915_private *i915, 765ac860ccSVille Syrjälä const struct intel_bw_state *bw_state); 77df0566a6SJani Nikula 78df0566a6SJani Nikula #endif /* __INTEL_BW_H__ */ 79