xref: /openbmc/linux/drivers/gpu/drm/i915/display/hsw_ips.h (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1f3b603deSVille Syrjälä /* SPDX-License-Identifier: MIT */
2f3b603deSVille Syrjälä /*
3f3b603deSVille Syrjälä  * Copyright © 2022 Intel Corporation
4f3b603deSVille Syrjälä  */
5f3b603deSVille Syrjälä 
6f3b603deSVille Syrjälä #ifndef __HSW_IPS_H__
7f3b603deSVille Syrjälä #define __HSW_IPS_H__
8f3b603deSVille Syrjälä 
9f3b603deSVille Syrjälä #include <linux/types.h>
10f3b603deSVille Syrjälä 
11f3b603deSVille Syrjälä struct intel_atomic_state;
12f3b603deSVille Syrjälä struct intel_crtc;
13f3b603deSVille Syrjälä struct intel_crtc_state;
14f3b603deSVille Syrjälä 
15f3b603deSVille Syrjälä bool hsw_ips_disable(const struct intel_crtc_state *crtc_state);
16f3b603deSVille Syrjälä bool hsw_ips_pre_update(struct intel_atomic_state *state,
17f3b603deSVille Syrjälä 			struct intel_crtc *crtc);
18f3b603deSVille Syrjälä void hsw_ips_post_update(struct intel_atomic_state *state,
19f3b603deSVille Syrjälä 			 struct intel_crtc *crtc);
20f3b603deSVille Syrjälä bool hsw_crtc_supports_ips(struct intel_crtc *crtc);
21f3b603deSVille Syrjälä bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
22f3b603deSVille Syrjälä int hsw_ips_compute_config(struct intel_atomic_state *state,
23f3b603deSVille Syrjälä 			   struct intel_crtc *crtc);
2428f5f888SVille Syrjälä void hsw_ips_get_config(struct intel_crtc_state *crtc_state);
25*1fb4da5fSVille Syrjälä void hsw_ips_crtc_debugfs_add(struct intel_crtc *crtc);
26f3b603deSVille Syrjälä 
27f3b603deSVille Syrjälä #endif /* __HSW_IPS_H__ */
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