1b27e35aeSChris Wilsonconfig DRM_I915_USERFAULT_AUTOSUSPEND 2b27e35aeSChris Wilson int "Runtime autosuspend delay for userspace GGTT mmaps (ms)" 3b27e35aeSChris Wilson default 250 # milliseconds 4b27e35aeSChris Wilson help 5b27e35aeSChris Wilson On runtime suspend, as we suspend the device, we have to revoke 6b27e35aeSChris Wilson userspace GGTT mmaps and force userspace to take a pagefault on 7b27e35aeSChris Wilson their next access. The revocation and subsequent recreation of 8b27e35aeSChris Wilson the GGTT mmap can be very slow and so we impose a small hysteris 9b27e35aeSChris Wilson that complements the runtime-pm autosuspend and provides a lower 10b27e35aeSChris Wilson floor on the autosuspend delay. 11b27e35aeSChris Wilson 12b27e35aeSChris Wilson May be 0 to disable the extra delay and solely use the device level 13b27e35aeSChris Wilson runtime pm autosuspend delay tunable. 14b27e35aeSChris Wilson 15058179e7SChris Wilsonconfig DRM_I915_HEARTBEAT_INTERVAL 16058179e7SChris Wilson int "Interval between heartbeat pulses (ms)" 17058179e7SChris Wilson default 2500 # milliseconds 18058179e7SChris Wilson help 19058179e7SChris Wilson The driver sends a periodic heartbeat down all active engines to 20058179e7SChris Wilson check the health of the GPU and undertake regular house-keeping of 21058179e7SChris Wilson internal driver state. 22058179e7SChris Wilson 23058179e7SChris Wilson May be 0 to disable heartbeats and therefore disable automatic GPU 24058179e7SChris Wilson hang detection. 25058179e7SChris Wilson 263a7a92abSChris Wilsonconfig DRM_I915_PREEMPT_TIMEOUT 273a7a92abSChris Wilson int "Preempt timeout (ms, jiffy granularity)" 285766a5ffSChris Wilson default 640 # milliseconds 293a7a92abSChris Wilson help 303a7a92abSChris Wilson How long to wait (in milliseconds) for a preemption event to occur 313a7a92abSChris Wilson when submitting a new context via execlists. If the current context 323a7a92abSChris Wilson does not hit an arbitration point and yield to HW before the timer 333a7a92abSChris Wilson expires, the HW will be reset to allow the more important context 343a7a92abSChris Wilson to execute. 353a7a92abSChris Wilson 363a7a92abSChris Wilson May be 0 to disable the timeout. 373a7a92abSChris Wilson 38*062444bbSChris Wilsonconfig DRM_I915_MAX_REQUEST_BUSYWAIT 39*062444bbSChris Wilson int "Busywait for request completion limit (ns)" 40*062444bbSChris Wilson default 8000 # nanoseconds 417ce99d24SChris Wilson help 427ce99d24SChris Wilson Before sleeping waiting for a request (GPU operation) to complete, 437ce99d24SChris Wilson we may spend some time polling for its completion. As the IRQ may 447ce99d24SChris Wilson take a non-negligible time to setup, we do a short spin first to 457ce99d24SChris Wilson check if the request will complete in the time it would have taken 467ce99d24SChris Wilson us to enable the interrupt. 477ce99d24SChris Wilson 48*062444bbSChris Wilson This is adjustable via 49*062444bbSChris Wilson /sys/class/drm/card?/engine/*/max_busywait_duration_ns 50*062444bbSChris Wilson 517ce99d24SChris Wilson May be 0 to disable the initial spin. In practice, we estimate 527ce99d24SChris Wilson the cost of enabling the interrupt (if currently disabled) to be 537ce99d24SChris Wilson a few microseconds. 54a8c51ed2SChris Wilson 55a8c51ed2SChris Wilsonconfig DRM_I915_STOP_TIMEOUT 56a8c51ed2SChris Wilson int "How long to wait for an engine to quiesce gracefully before reset (ms)" 57a8c51ed2SChris Wilson default 100 # milliseconds 58a8c51ed2SChris Wilson help 59a8c51ed2SChris Wilson By stopping submission and sleeping for a short time before resetting 60a8c51ed2SChris Wilson the GPU, we allow the innocent contexts also on the system to quiesce. 61a8c51ed2SChris Wilson It is then less likely for a hanging context to cause collateral 62a8c51ed2SChris Wilson damage as the system is reset in order to recover. The corollary is 63a8c51ed2SChris Wilson that the reset itself may take longer and so be more disruptive to 64a8c51ed2SChris Wilson interactive or low latency workloads. 65b79029b2SChris Wilson 66b79029b2SChris Wilsonconfig DRM_I915_TIMESLICE_DURATION 67b79029b2SChris Wilson int "Scheduling quantum for userspace batches (ms, jiffy granularity)" 68b79029b2SChris Wilson default 1 # milliseconds 69b79029b2SChris Wilson help 70b79029b2SChris Wilson When two user batches of equal priority are executing, we will 71b79029b2SChris Wilson alternate execution of each batch to ensure forward progress of 72b79029b2SChris Wilson all users. This is necessary in some cases where there may be 73b79029b2SChris Wilson an implicit dependency between those batches that requires 74b79029b2SChris Wilson concurrent execution in order for them to proceed, e.g. they 75b79029b2SChris Wilson interact with each other via userspace semaphores. Each context 76b79029b2SChris Wilson is scheduled for execution for the timeslice duration, before 77b79029b2SChris Wilson switching to the next context. 78b79029b2SChris Wilson 791a2695a7SChris Wilson This is adjustable via 801a2695a7SChris Wilson /sys/class/drm/card?/engine/*/timeslice_duration_ms 811a2695a7SChris Wilson 82b79029b2SChris Wilson May be 0 to disable timeslicing. 83