xref: /openbmc/linux/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h (revision 762f99f4f3cb41a775b5157dd761217beba65873)
1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2f819b0d4SXinliang Liu /*
3f819b0d4SXinliang Liu  * Copyright (c) 2016 Linaro Limited.
4*6616125bSHao Fang  * Copyright (c) 2014-2016 HiSilicon Limited.
5f819b0d4SXinliang Liu  */
6f819b0d4SXinliang Liu 
7f819b0d4SXinliang Liu #ifndef __DW_DSI_REG_H__
8f819b0d4SXinliang Liu #define __DW_DSI_REG_H__
9f819b0d4SXinliang Liu 
10f819b0d4SXinliang Liu #define MASK(x)				(BIT(x) - 1)
11f819b0d4SXinliang Liu 
12f819b0d4SXinliang Liu /*
13f819b0d4SXinliang Liu  * regs
14f819b0d4SXinliang Liu  */
15f819b0d4SXinliang Liu #define PWR_UP                  0x04  /* Core power-up */
16f819b0d4SXinliang Liu #define RESET                   0
17f819b0d4SXinliang Liu #define POWERUP                 BIT(0)
18f819b0d4SXinliang Liu #define PHY_IF_CFG              0xA4  /* D-PHY interface configuration */
19f819b0d4SXinliang Liu #define CLKMGR_CFG              0x08  /* the internal clock dividers */
20f819b0d4SXinliang Liu #define PHY_RSTZ                0xA0  /* D-PHY reset control */
21f819b0d4SXinliang Liu #define PHY_ENABLECLK           BIT(2)
22f819b0d4SXinliang Liu #define PHY_UNRSTZ              BIT(1)
23f819b0d4SXinliang Liu #define PHY_UNSHUTDOWNZ         BIT(0)
24f819b0d4SXinliang Liu #define PHY_TST_CTRL0           0xB4  /* D-PHY test interface control 0 */
25f819b0d4SXinliang Liu #define PHY_TST_CTRL1           0xB8  /* D-PHY test interface control 1 */
26f819b0d4SXinliang Liu #define CLK_TLPX                0x10
27f819b0d4SXinliang Liu #define CLK_THS_PREPARE         0x11
28f819b0d4SXinliang Liu #define CLK_THS_ZERO            0x12
29f819b0d4SXinliang Liu #define CLK_THS_TRAIL           0x13
30f819b0d4SXinliang Liu #define CLK_TWAKEUP             0x14
31f819b0d4SXinliang Liu #define DATA_TLPX(x)            (0x20 + ((x) << 4))
32f819b0d4SXinliang Liu #define DATA_THS_PREPARE(x)     (0x21 + ((x) << 4))
33f819b0d4SXinliang Liu #define DATA_THS_ZERO(x)        (0x22 + ((x) << 4))
34f819b0d4SXinliang Liu #define DATA_THS_TRAIL(x)       (0x23 + ((x) << 4))
35f819b0d4SXinliang Liu #define DATA_TTA_GO(x)          (0x24 + ((x) << 4))
36f819b0d4SXinliang Liu #define DATA_TTA_GET(x)         (0x25 + ((x) << 4))
37f819b0d4SXinliang Liu #define DATA_TWAKEUP(x)         (0x26 + ((x) << 4))
38f819b0d4SXinliang Liu #define PHY_CFG_I               0x60
39f819b0d4SXinliang Liu #define PHY_CFG_PLL_I           0x63
40f819b0d4SXinliang Liu #define PHY_CFG_PLL_II          0x64
41f819b0d4SXinliang Liu #define PHY_CFG_PLL_III         0x65
42f819b0d4SXinliang Liu #define PHY_CFG_PLL_IV          0x66
43f819b0d4SXinliang Liu #define PHY_CFG_PLL_V           0x67
44f819b0d4SXinliang Liu #define DPI_COLOR_CODING        0x10  /* DPI color coding */
45f819b0d4SXinliang Liu #define DPI_CFG_POL             0x14  /* DPI polarity configuration */
46f819b0d4SXinliang Liu #define VID_HSA_TIME            0x48  /* Horizontal Sync Active time */
47f819b0d4SXinliang Liu #define VID_HBP_TIME            0x4C  /* Horizontal Back Porch time */
48f819b0d4SXinliang Liu #define VID_HLINE_TIME          0x50  /* Line time */
49f819b0d4SXinliang Liu #define VID_VSA_LINES           0x54  /* Vertical Sync Active period */
50f819b0d4SXinliang Liu #define VID_VBP_LINES           0x58  /* Vertical Back Porch period */
51f819b0d4SXinliang Liu #define VID_VFP_LINES           0x5C  /* Vertical Front Porch period */
52f819b0d4SXinliang Liu #define VID_VACTIVE_LINES       0x60  /* Vertical resolution */
53f819b0d4SXinliang Liu #define VID_PKT_SIZE            0x3C  /* Video packet size */
54f819b0d4SXinliang Liu #define VID_MODE_CFG            0x38  /* Video mode configuration */
55f819b0d4SXinliang Liu #define PHY_TMR_CFG             0x9C  /* Data lanes timing configuration */
56f819b0d4SXinliang Liu #define BTA_TO_CNT              0x8C  /* Response timeout definition */
57f819b0d4SXinliang Liu #define PHY_TMR_LPCLK_CFG       0x98  /* clock lane timing configuration */
58f819b0d4SXinliang Liu #define CLK_DATA_TMR_CFG        0xCC
59f819b0d4SXinliang Liu #define LPCLK_CTRL              0x94  /* Low-power in clock lane */
60f819b0d4SXinliang Liu #define PHY_TXREQUESTCLKHS      BIT(0)
61f819b0d4SXinliang Liu #define MODE_CFG                0x34  /* Video or Command mode selection */
62f819b0d4SXinliang Liu #define PHY_STATUS              0xB0  /* D-PHY PPI status interface */
63f819b0d4SXinliang Liu 
64f819b0d4SXinliang Liu #define	PHY_STOP_WAIT_TIME      0x30
65f819b0d4SXinliang Liu 
66f819b0d4SXinliang Liu /*
67f819b0d4SXinliang Liu  * regs relevant enum
68f819b0d4SXinliang Liu  */
69f819b0d4SXinliang Liu enum dpi_color_coding {
70f819b0d4SXinliang Liu 	DSI_24BITS_1 = 5,
71f819b0d4SXinliang Liu };
72f819b0d4SXinliang Liu 
73f819b0d4SXinliang Liu enum dsi_video_mode_type {
74f819b0d4SXinliang Liu 	DSI_NON_BURST_SYNC_PULSES = 0,
75f819b0d4SXinliang Liu 	DSI_NON_BURST_SYNC_EVENTS,
76f819b0d4SXinliang Liu 	DSI_BURST_SYNC_PULSES_1,
77f819b0d4SXinliang Liu 	DSI_BURST_SYNC_PULSES_2
78f819b0d4SXinliang Liu };
79f819b0d4SXinliang Liu 
80f819b0d4SXinliang Liu enum dsi_work_mode {
81f819b0d4SXinliang Liu 	DSI_VIDEO_MODE = 0,
82f819b0d4SXinliang Liu 	DSI_COMMAND_MODE
83f819b0d4SXinliang Liu };
84f819b0d4SXinliang Liu 
85f819b0d4SXinliang Liu /*
86f819b0d4SXinliang Liu  * Register Write/Read Helper functions
87f819b0d4SXinliang Liu  */
dw_update_bits(void __iomem * addr,u32 bit_start,u32 mask,u32 val)88f819b0d4SXinliang Liu static inline void dw_update_bits(void __iomem *addr, u32 bit_start,
89f819b0d4SXinliang Liu 				  u32 mask, u32 val)
90f819b0d4SXinliang Liu {
91f819b0d4SXinliang Liu 	u32 tmp, orig;
92f819b0d4SXinliang Liu 
93f819b0d4SXinliang Liu 	orig = readl(addr);
94f819b0d4SXinliang Liu 	tmp = orig & ~(mask << bit_start);
95f819b0d4SXinliang Liu 	tmp |= (val & mask) << bit_start;
96f819b0d4SXinliang Liu 	writel(tmp, addr);
97f819b0d4SXinliang Liu }
98f819b0d4SXinliang Liu 
99f819b0d4SXinliang Liu #endif /* __DW_DRM_DSI_H__ */
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