1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/kernel.h> 12 #include <linux/media-bus-format.h> 13 #include <linux/minmax.h> 14 #include <linux/module.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/slab.h> 18 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_drv.h> 21 #include <drm/drm_mipi_dsi.h> 22 #include <drm/drm_of.h> 23 #include <drm/drm_panel.h> 24 #include <video/mipi_display.h> 25 #include <video/videomode.h> 26 27 /* Global (16-bit addressable) */ 28 #define TC358768_CHIPID 0x0000 29 #define TC358768_SYSCTL 0x0002 30 #define TC358768_CONFCTL 0x0004 31 #define TC358768_VSDLY 0x0006 32 #define TC358768_DATAFMT 0x0008 33 #define TC358768_GPIOEN 0x000E 34 #define TC358768_GPIODIR 0x0010 35 #define TC358768_GPIOIN 0x0012 36 #define TC358768_GPIOOUT 0x0014 37 #define TC358768_PLLCTL0 0x0016 38 #define TC358768_PLLCTL1 0x0018 39 #define TC358768_CMDBYTE 0x0022 40 #define TC358768_PP_MISC 0x0032 41 #define TC358768_DSITX_DT 0x0050 42 #define TC358768_FIFOSTATUS 0x00F8 43 44 /* Debug (16-bit addressable) */ 45 #define TC358768_VBUFCTRL 0x00E0 46 #define TC358768_DBG_WIDTH 0x00E2 47 #define TC358768_DBG_VBLANK 0x00E4 48 #define TC358768_DBG_DATA 0x00E8 49 50 /* TX PHY (32-bit addressable) */ 51 #define TC358768_CLW_DPHYCONTTX 0x0100 52 #define TC358768_D0W_DPHYCONTTX 0x0104 53 #define TC358768_D1W_DPHYCONTTX 0x0108 54 #define TC358768_D2W_DPHYCONTTX 0x010C 55 #define TC358768_D3W_DPHYCONTTX 0x0110 56 #define TC358768_CLW_CNTRL 0x0140 57 #define TC358768_D0W_CNTRL 0x0144 58 #define TC358768_D1W_CNTRL 0x0148 59 #define TC358768_D2W_CNTRL 0x014C 60 #define TC358768_D3W_CNTRL 0x0150 61 62 /* TX PPI (32-bit addressable) */ 63 #define TC358768_STARTCNTRL 0x0204 64 #define TC358768_DSITXSTATUS 0x0208 65 #define TC358768_LINEINITCNT 0x0210 66 #define TC358768_LPTXTIMECNT 0x0214 67 #define TC358768_TCLK_HEADERCNT 0x0218 68 #define TC358768_TCLK_TRAILCNT 0x021C 69 #define TC358768_THS_HEADERCNT 0x0220 70 #define TC358768_TWAKEUP 0x0224 71 #define TC358768_TCLK_POSTCNT 0x0228 72 #define TC358768_THS_TRAILCNT 0x022C 73 #define TC358768_HSTXVREGCNT 0x0230 74 #define TC358768_HSTXVREGEN 0x0234 75 #define TC358768_TXOPTIONCNTRL 0x0238 76 #define TC358768_BTACNTRL1 0x023C 77 78 /* TX CTRL (32-bit addressable) */ 79 #define TC358768_DSI_CONTROL 0x040C 80 #define TC358768_DSI_STATUS 0x0410 81 #define TC358768_DSI_INT 0x0414 82 #define TC358768_DSI_INT_ENA 0x0418 83 #define TC358768_DSICMD_RDFIFO 0x0430 84 #define TC358768_DSI_ACKERR 0x0434 85 #define TC358768_DSI_ACKERR_INTENA 0x0438 86 #define TC358768_DSI_ACKERR_HALT 0x043c 87 #define TC358768_DSI_RXERR 0x0440 88 #define TC358768_DSI_RXERR_INTENA 0x0444 89 #define TC358768_DSI_RXERR_HALT 0x0448 90 #define TC358768_DSI_ERR 0x044C 91 #define TC358768_DSI_ERR_INTENA 0x0450 92 #define TC358768_DSI_ERR_HALT 0x0454 93 #define TC358768_DSI_CONFW 0x0500 94 #define TC358768_DSI_LPCMD 0x0500 95 #define TC358768_DSI_RESET 0x0504 96 #define TC358768_DSI_INT_CLR 0x050C 97 #define TC358768_DSI_START 0x0518 98 99 /* DSITX CTRL (16-bit addressable) */ 100 #define TC358768_DSICMD_TX 0x0600 101 #define TC358768_DSICMD_TYPE 0x0602 102 #define TC358768_DSICMD_WC 0x0604 103 #define TC358768_DSICMD_WD0 0x0610 104 #define TC358768_DSICMD_WD1 0x0612 105 #define TC358768_DSICMD_WD2 0x0614 106 #define TC358768_DSICMD_WD3 0x0616 107 #define TC358768_DSI_EVENT 0x0620 108 #define TC358768_DSI_VSW 0x0622 109 #define TC358768_DSI_VBPR 0x0624 110 #define TC358768_DSI_VACT 0x0626 111 #define TC358768_DSI_HSW 0x0628 112 #define TC358768_DSI_HBPR 0x062A 113 #define TC358768_DSI_HACT 0x062C 114 115 /* TC358768_DSI_CONTROL (0x040C) register */ 116 #define TC358768_DSI_CONTROL_DIS_MODE BIT(15) 117 #define TC358768_DSI_CONTROL_TXMD BIT(7) 118 #define TC358768_DSI_CONTROL_HSCKMD BIT(5) 119 #define TC358768_DSI_CONTROL_EOTDIS BIT(0) 120 121 /* TC358768_DSI_CONFW (0x0500) register */ 122 #define TC358768_DSI_CONFW_MODE_SET (5 << 29) 123 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) 124 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24) 125 126 static const char * const tc358768_supplies[] = { 127 "vddc", "vddmipi", "vddio" 128 }; 129 130 struct tc358768_dsi_output { 131 struct mipi_dsi_device *dev; 132 struct drm_panel *panel; 133 struct drm_bridge *bridge; 134 }; 135 136 struct tc358768_priv { 137 struct device *dev; 138 struct regmap *regmap; 139 struct gpio_desc *reset_gpio; 140 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)]; 141 struct clk *refclk; 142 int enabled; 143 int error; 144 145 struct mipi_dsi_host dsi_host; 146 struct drm_bridge bridge; 147 struct tc358768_dsi_output output; 148 149 u32 pd_lines; /* number of Parallel Port Input Data Lines */ 150 u32 dsi_lanes; /* number of DSI Lanes */ 151 u32 dsi_bpp; /* number of Bits Per Pixel over DSI */ 152 153 /* Parameters for PLL programming */ 154 u32 fbd; /* PLL feedback divider */ 155 u32 prd; /* PLL input divider */ 156 u32 frs; /* PLL Freqency range for HSCK (post divider) */ 157 158 u32 dsiclk; /* pll_clk / 2 */ 159 }; 160 161 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host 162 *host) 163 { 164 return container_of(host, struct tc358768_priv, dsi_host); 165 } 166 167 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge 168 *bridge) 169 { 170 return container_of(bridge, struct tc358768_priv, bridge); 171 } 172 173 static int tc358768_clear_error(struct tc358768_priv *priv) 174 { 175 int ret = priv->error; 176 177 priv->error = 0; 178 return ret; 179 } 180 181 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val) 182 { 183 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 184 int tmpval = val; 185 size_t count = 2; 186 187 if (priv->error) 188 return; 189 190 /* 16-bit register? */ 191 if (reg < 0x100 || reg >= 0x600) 192 count = 1; 193 194 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count); 195 } 196 197 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val) 198 { 199 size_t count = 2; 200 201 if (priv->error) 202 return; 203 204 /* 16-bit register? */ 205 if (reg < 0x100 || reg >= 0x600) { 206 *val = 0; 207 count = 1; 208 } 209 210 priv->error = regmap_bulk_read(priv->regmap, reg, val, count); 211 } 212 213 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask, 214 u32 val) 215 { 216 u32 tmp, orig; 217 218 tc358768_read(priv, reg, &orig); 219 220 if (priv->error) 221 return; 222 223 tmp = orig & ~mask; 224 tmp |= val & mask; 225 if (tmp != orig) 226 tc358768_write(priv, reg, tmp); 227 } 228 229 static int tc358768_sw_reset(struct tc358768_priv *priv) 230 { 231 /* Assert Reset */ 232 tc358768_write(priv, TC358768_SYSCTL, 1); 233 /* Release Reset, Exit Sleep */ 234 tc358768_write(priv, TC358768_SYSCTL, 0); 235 236 return tc358768_clear_error(priv); 237 } 238 239 static void tc358768_hw_enable(struct tc358768_priv *priv) 240 { 241 int ret; 242 243 if (priv->enabled) 244 return; 245 246 ret = clk_prepare_enable(priv->refclk); 247 if (ret < 0) 248 dev_err(priv->dev, "error enabling refclk (%d)\n", ret); 249 250 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 251 if (ret < 0) 252 dev_err(priv->dev, "error enabling regulators (%d)\n", ret); 253 254 if (priv->reset_gpio) 255 usleep_range(200, 300); 256 257 /* 258 * The RESX is active low (GPIO_ACTIVE_LOW). 259 * DEASSERT (value = 0) the reset_gpio to enable the chip 260 */ 261 gpiod_set_value_cansleep(priv->reset_gpio, 0); 262 263 /* wait for encoder clocks to stabilize */ 264 usleep_range(1000, 2000); 265 266 priv->enabled = true; 267 } 268 269 static void tc358768_hw_disable(struct tc358768_priv *priv) 270 { 271 int ret; 272 273 if (!priv->enabled) 274 return; 275 276 /* 277 * The RESX is active low (GPIO_ACTIVE_LOW). 278 * ASSERT (value = 1) the reset_gpio to disable the chip 279 */ 280 gpiod_set_value_cansleep(priv->reset_gpio, 1); 281 282 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 283 priv->supplies); 284 if (ret < 0) 285 dev_err(priv->dev, "error disabling regulators (%d)\n", ret); 286 287 clk_disable_unprepare(priv->refclk); 288 289 priv->enabled = false; 290 } 291 292 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk) 293 { 294 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp); 295 } 296 297 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) 298 { 299 return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes); 300 } 301 302 static int tc358768_calc_pll(struct tc358768_priv *priv, 303 const struct drm_display_mode *mode, 304 bool verify_only) 305 { 306 static const u32 frs_limits[] = { 307 1000000000, 308 500000000, 309 250000000, 310 125000000, 311 62500000 312 }; 313 unsigned long refclk; 314 u32 prd, target_pll, i, max_pll, min_pll; 315 u32 frs, best_diff, best_pll, best_prd, best_fbd; 316 317 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000); 318 319 /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */ 320 321 for (i = 0; i < ARRAY_SIZE(frs_limits); i++) 322 if (target_pll >= frs_limits[i]) 323 break; 324 325 if (i == ARRAY_SIZE(frs_limits) || i == 0) 326 return -EINVAL; 327 328 frs = i - 1; 329 max_pll = frs_limits[i - 1]; 330 min_pll = frs_limits[i]; 331 332 refclk = clk_get_rate(priv->refclk); 333 334 best_diff = UINT_MAX; 335 best_pll = 0; 336 best_prd = 0; 337 best_fbd = 0; 338 339 for (prd = 0; prd < 16; ++prd) { 340 u32 divisor = (prd + 1) * (1 << frs); 341 u32 fbd; 342 343 for (fbd = 0; fbd < 512; ++fbd) { 344 u32 pll, diff, pll_in; 345 346 pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor); 347 348 if (pll >= max_pll || pll < min_pll) 349 continue; 350 351 pll_in = (u32)div_u64((u64)refclk, prd + 1); 352 if (pll_in < 4000000) 353 continue; 354 355 diff = max(pll, target_pll) - min(pll, target_pll); 356 357 if (diff < best_diff) { 358 best_diff = diff; 359 best_pll = pll; 360 best_prd = prd; 361 best_fbd = fbd; 362 363 if (best_diff == 0) 364 goto found; 365 } 366 } 367 } 368 369 if (best_diff == UINT_MAX) { 370 dev_err(priv->dev, "could not find suitable PLL setup\n"); 371 return -EINVAL; 372 } 373 374 found: 375 if (verify_only) 376 return 0; 377 378 priv->fbd = best_fbd; 379 priv->prd = best_prd; 380 priv->frs = frs; 381 priv->dsiclk = best_pll / 2; 382 383 return 0; 384 } 385 386 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, 387 struct mipi_dsi_device *dev) 388 { 389 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 390 struct drm_bridge *bridge; 391 struct drm_panel *panel; 392 struct device_node *ep; 393 int ret; 394 395 if (dev->lanes > 4) { 396 dev_err(priv->dev, "unsupported number of data lanes(%u)\n", 397 dev->lanes); 398 return -EINVAL; 399 } 400 401 /* 402 * tc358768 supports both Video and Pulse mode, but the driver only 403 * implements Video (event) mode currently 404 */ 405 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) { 406 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n"); 407 return -ENOTSUPP; 408 } 409 410 /* 411 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only 412 * RGB888 is verified. 413 */ 414 if (dev->format != MIPI_DSI_FMT_RGB888) { 415 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n"); 416 return -ENOTSUPP; 417 } 418 419 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel, 420 &bridge); 421 if (ret) 422 return ret; 423 424 if (panel) { 425 bridge = drm_panel_bridge_add_typed(panel, 426 DRM_MODE_CONNECTOR_DSI); 427 if (IS_ERR(bridge)) 428 return PTR_ERR(bridge); 429 } 430 431 priv->output.dev = dev; 432 priv->output.bridge = bridge; 433 priv->output.panel = panel; 434 435 priv->dsi_lanes = dev->lanes; 436 priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format); 437 438 /* get input ep (port0/endpoint0) */ 439 ret = -EINVAL; 440 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0); 441 if (ep) { 442 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines); 443 444 of_node_put(ep); 445 } 446 447 if (ret) 448 priv->pd_lines = priv->dsi_bpp; 449 450 drm_bridge_add(&priv->bridge); 451 452 return 0; 453 } 454 455 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host, 456 struct mipi_dsi_device *dev) 457 { 458 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 459 460 drm_bridge_remove(&priv->bridge); 461 if (priv->output.panel) 462 drm_panel_bridge_remove(priv->output.bridge); 463 464 return 0; 465 } 466 467 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, 468 const struct mipi_dsi_msg *msg) 469 { 470 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 471 struct mipi_dsi_packet packet; 472 int ret; 473 474 if (!priv->enabled) { 475 dev_err(priv->dev, "Bridge is not enabled\n"); 476 return -ENODEV; 477 } 478 479 if (msg->rx_len) { 480 dev_warn(priv->dev, "MIPI rx is not supported\n"); 481 return -ENOTSUPP; 482 } 483 484 if (msg->tx_len > 8) { 485 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n"); 486 return -ENOTSUPP; 487 } 488 489 ret = mipi_dsi_create_packet(&packet, msg); 490 if (ret) 491 return ret; 492 493 if (mipi_dsi_packet_format_is_short(msg->type)) { 494 tc358768_write(priv, TC358768_DSICMD_TYPE, 495 (0x10 << 8) | (packet.header[0] & 0x3f)); 496 tc358768_write(priv, TC358768_DSICMD_WC, 0); 497 tc358768_write(priv, TC358768_DSICMD_WD0, 498 (packet.header[2] << 8) | packet.header[1]); 499 } else { 500 int i; 501 502 tc358768_write(priv, TC358768_DSICMD_TYPE, 503 (0x40 << 8) | (packet.header[0] & 0x3f)); 504 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length); 505 for (i = 0; i < packet.payload_length; i += 2) { 506 u16 val = packet.payload[i]; 507 508 if (i + 1 < packet.payload_length) 509 val |= packet.payload[i + 1] << 8; 510 511 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val); 512 } 513 } 514 515 /* start transfer */ 516 tc358768_write(priv, TC358768_DSICMD_TX, 1); 517 518 ret = tc358768_clear_error(priv); 519 if (ret) 520 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 521 else 522 ret = packet.size; 523 524 return ret; 525 } 526 527 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = { 528 .attach = tc358768_dsi_host_attach, 529 .detach = tc358768_dsi_host_detach, 530 .transfer = tc358768_dsi_host_transfer, 531 }; 532 533 static int tc358768_bridge_attach(struct drm_bridge *bridge, 534 enum drm_bridge_attach_flags flags) 535 { 536 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 537 538 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) { 539 dev_err(priv->dev, "needs atomic updates support\n"); 540 return -ENOTSUPP; 541 } 542 543 return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge, 544 flags); 545 } 546 547 static enum drm_mode_status 548 tc358768_bridge_mode_valid(struct drm_bridge *bridge, 549 const struct drm_display_info *info, 550 const struct drm_display_mode *mode) 551 { 552 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 553 554 if (tc358768_calc_pll(priv, mode, true)) 555 return MODE_CLOCK_RANGE; 556 557 return MODE_OK; 558 } 559 560 static void tc358768_bridge_disable(struct drm_bridge *bridge) 561 { 562 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 563 int ret; 564 565 /* set FrmStop */ 566 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15)); 567 568 /* wait at least for one frame */ 569 msleep(50); 570 571 /* clear PP_en */ 572 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0); 573 574 /* set RstPtr */ 575 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14)); 576 577 ret = tc358768_clear_error(priv); 578 if (ret) 579 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 580 } 581 582 static void tc358768_bridge_post_disable(struct drm_bridge *bridge) 583 { 584 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 585 586 tc358768_hw_disable(priv); 587 } 588 589 static int tc358768_setup_pll(struct tc358768_priv *priv, 590 const struct drm_display_mode *mode) 591 { 592 u32 fbd, prd, frs; 593 int ret; 594 595 ret = tc358768_calc_pll(priv, mode, false); 596 if (ret) { 597 dev_err(priv->dev, "PLL calculation failed: %d\n", ret); 598 return ret; 599 } 600 601 fbd = priv->fbd; 602 prd = priv->prd; 603 frs = priv->frs; 604 605 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n", 606 clk_get_rate(priv->refclk), fbd, prd, frs); 607 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n", 608 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); 609 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n", 610 tc358768_pll_to_pclk(priv, priv->dsiclk * 2), 611 mode->clock * 1000); 612 613 /* PRD[15:12] FBD[8:0] */ 614 tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd); 615 616 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ 617 tc358768_write(priv, TC358768_PLLCTL1, 618 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0)); 619 620 /* wait for lock */ 621 usleep_range(1000, 2000); 622 623 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */ 624 tc358768_write(priv, TC358768_PLLCTL1, 625 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0)); 626 627 return tc358768_clear_error(priv); 628 } 629 630 #define TC358768_PRECISION 1000 631 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk) 632 { 633 return (ns * TC358768_PRECISION + period_nsk) / period_nsk; 634 } 635 636 static u32 tc358768_to_ns(u32 nsk) 637 { 638 return (nsk / TC358768_PRECISION); 639 } 640 641 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) 642 { 643 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 644 struct mipi_dsi_device *dsi_dev = priv->output.dev; 645 unsigned long mode_flags = dsi_dev->mode_flags; 646 u32 val, val2, lptxcnt, hact, data_type; 647 s32 raw_val; 648 const struct drm_display_mode *mode; 649 u32 dsibclk_nsk, dsiclk_nsk, ui_nsk; 650 u32 dsiclk, dsibclk, video_start; 651 const u32 internal_delay = 40; 652 int ret, i; 653 struct videomode vm; 654 655 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 656 dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n"); 657 mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS; 658 } 659 660 tc358768_hw_enable(priv); 661 662 ret = tc358768_sw_reset(priv); 663 if (ret) { 664 dev_err(priv->dev, "Software reset failed: %d\n", ret); 665 tc358768_hw_disable(priv); 666 return; 667 } 668 669 mode = &bridge->encoder->crtc->state->adjusted_mode; 670 ret = tc358768_setup_pll(priv, mode); 671 if (ret) { 672 dev_err(priv->dev, "PLL setup failed: %d\n", ret); 673 tc358768_hw_disable(priv); 674 return; 675 } 676 677 drm_display_mode_to_videomode(mode, &vm); 678 679 dsiclk = priv->dsiclk; 680 dsibclk = dsiclk / 4; 681 682 /* Data Format Control Register */ 683 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ 684 switch (dsi_dev->format) { 685 case MIPI_DSI_FMT_RGB888: 686 val |= (0x3 << 4); 687 hact = vm.hactive * 3; 688 video_start = (vm.hsync_len + vm.hback_porch) * 3; 689 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 690 break; 691 case MIPI_DSI_FMT_RGB666: 692 val |= (0x4 << 4); 693 hact = vm.hactive * 3; 694 video_start = (vm.hsync_len + vm.hback_porch) * 3; 695 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 696 break; 697 698 case MIPI_DSI_FMT_RGB666_PACKED: 699 val |= (0x4 << 4) | BIT(3); 700 hact = vm.hactive * 18 / 8; 701 video_start = (vm.hsync_len + vm.hback_porch) * 18 / 8; 702 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 703 break; 704 705 case MIPI_DSI_FMT_RGB565: 706 val |= (0x5 << 4); 707 hact = vm.hactive * 2; 708 video_start = (vm.hsync_len + vm.hback_porch) * 2; 709 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 710 break; 711 default: 712 dev_err(priv->dev, "Invalid data format (%u)\n", 713 dsi_dev->format); 714 tc358768_hw_disable(priv); 715 return; 716 } 717 718 /* VSDly[9:0] */ 719 video_start = max(video_start, internal_delay + 1) - internal_delay; 720 tc358768_write(priv, TC358768_VSDLY, video_start); 721 722 tc358768_write(priv, TC358768_DATAFMT, val); 723 tc358768_write(priv, TC358768_DSITX_DT, data_type); 724 725 /* Enable D-PHY (HiZ->LP11) */ 726 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); 727 /* Enable lanes */ 728 for (i = 0; i < dsi_dev->lanes; i++) 729 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); 730 731 /* DSI Timings */ 732 dsibclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, 733 dsibclk); 734 dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); 735 ui_nsk = dsiclk_nsk / 2; 736 dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk); 737 dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk); 738 dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk); 739 740 /* LP11 > 100us for D-PHY Rx Init */ 741 val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1; 742 dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val); 743 tc358768_write(priv, TC358768_LINEINITCNT, val); 744 745 /* LPTimeCnt > 50ns */ 746 val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1; 747 lptxcnt = val; 748 dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val); 749 tc358768_write(priv, TC358768_LPTXTIMECNT, val); 750 751 /* 38ns < TCLK_PREPARE < 95ns */ 752 val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; 753 /* TCLK_PREPARE + TCLK_ZERO > 300ns */ 754 val2 = tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), 755 dsibclk_nsk) - 2; 756 val |= val2 << 8; 757 dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val); 758 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); 759 760 /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */ 761 raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 5; 762 val = clamp(raw_val, 0, 127); 763 dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val); 764 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); 765 766 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ 767 val = 50 + tc358768_to_ns(4 * ui_nsk); 768 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; 769 /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ 770 raw_val = tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_nsk) - 10; 771 val2 = clamp(raw_val, 0, 127); 772 val |= val2 << 8; 773 dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val); 774 tc358768_write(priv, TC358768_THS_HEADERCNT, val); 775 776 /* TWAKEUP > 1ms in lptxcnt steps */ 777 val = tc358768_ns_to_cnt(1020000, dsibclk_nsk); 778 val = val / (lptxcnt + 1) - 1; 779 dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val); 780 tc358768_write(priv, TC358768_TWAKEUP, val); 781 782 /* TCLK_POSTCNT > 60ns + 52*UI */ 783 val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), 784 dsibclk_nsk) - 3; 785 dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val); 786 tc358768_write(priv, TC358768_TCLK_POSTCNT, val); 787 788 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ 789 raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk), 790 dsibclk_nsk) - 4; 791 val = clamp(raw_val, 0, 15); 792 dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val); 793 tc358768_write(priv, TC358768_THS_TRAILCNT, val); 794 795 val = BIT(0); 796 for (i = 0; i < dsi_dev->lanes; i++) 797 val |= BIT(i + 1); 798 tc358768_write(priv, TC358768_HSTXVREGEN, val); 799 800 tc358768_write(priv, TC358768_TXOPTIONCNTRL, 801 (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); 802 803 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ 804 val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); 805 val = tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1; 806 val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), 807 dsibclk_nsk) - 2; 808 val = val << 16 | val2; 809 dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val); 810 tc358768_write(priv, TC358768_BTACNTRL1, val); 811 812 /* START[0] */ 813 tc358768_write(priv, TC358768_STARTCNTRL, 1); 814 815 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 816 /* Set pulse mode */ 817 tc358768_write(priv, TC358768_DSI_EVENT, 0); 818 819 /* vact */ 820 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); 821 822 /* vsw */ 823 tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len); 824 825 /* vbp */ 826 tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch); 827 828 /* hsw * byteclk * ndl / pclk */ 829 val = (u32)div_u64(vm.hsync_len * 830 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, 831 vm.pixelclock); 832 tc358768_write(priv, TC358768_DSI_HSW, val); 833 834 /* hbp * byteclk * ndl / pclk */ 835 val = (u32)div_u64(vm.hback_porch * 836 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, 837 vm.pixelclock); 838 tc358768_write(priv, TC358768_DSI_HBPR, val); 839 } else { 840 /* Set event mode */ 841 tc358768_write(priv, TC358768_DSI_EVENT, 1); 842 843 /* vact */ 844 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); 845 846 /* vsw (+ vbp) */ 847 tc358768_write(priv, TC358768_DSI_VSW, 848 vm.vsync_len + vm.vback_porch); 849 850 /* vbp (not used in event mode) */ 851 tc358768_write(priv, TC358768_DSI_VBPR, 0); 852 853 /* (hsw + hbp) * byteclk * ndl / pclk */ 854 val = (u32)div_u64((vm.hsync_len + vm.hback_porch) * 855 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, 856 vm.pixelclock); 857 tc358768_write(priv, TC358768_DSI_HSW, val); 858 859 /* hbp (not used in event mode) */ 860 tc358768_write(priv, TC358768_DSI_HBPR, 0); 861 } 862 863 /* hact (bytes) */ 864 tc358768_write(priv, TC358768_DSI_HACT, hact); 865 866 /* VSYNC polarity */ 867 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), 868 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0); 869 870 /* HSYNC polarity */ 871 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), 872 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0); 873 874 /* Start DSI Tx */ 875 tc358768_write(priv, TC358768_DSI_START, 0x1); 876 877 /* Configure DSI_Control register */ 878 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 879 val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | 880 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; 881 tc358768_write(priv, TC358768_DSI_CONFW, val); 882 883 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 884 val |= (dsi_dev->lanes - 1) << 1; 885 886 val |= TC358768_DSI_CONTROL_TXMD; 887 888 if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 889 val |= TC358768_DSI_CONTROL_HSCKMD; 890 891 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 892 val |= TC358768_DSI_CONTROL_EOTDIS; 893 894 tc358768_write(priv, TC358768_DSI_CONFW, val); 895 896 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 897 val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */ 898 tc358768_write(priv, TC358768_DSI_CONFW, val); 899 900 ret = tc358768_clear_error(priv); 901 if (ret) { 902 dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret); 903 tc358768_bridge_disable(bridge); 904 tc358768_bridge_post_disable(bridge); 905 } 906 } 907 908 static void tc358768_bridge_enable(struct drm_bridge *bridge) 909 { 910 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 911 int ret; 912 913 if (!priv->enabled) { 914 dev_err(priv->dev, "Bridge is not enabled\n"); 915 return; 916 } 917 918 /* clear FrmStop and RstPtr */ 919 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0); 920 921 /* set PP_en */ 922 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6)); 923 924 ret = tc358768_clear_error(priv); 925 if (ret) { 926 dev_err(priv->dev, "Bridge enable failed: %d\n", ret); 927 tc358768_bridge_disable(bridge); 928 tc358768_bridge_post_disable(bridge); 929 } 930 } 931 932 #define MAX_INPUT_SEL_FORMATS 1 933 934 static u32 * 935 tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 936 struct drm_bridge_state *bridge_state, 937 struct drm_crtc_state *crtc_state, 938 struct drm_connector_state *conn_state, 939 u32 output_fmt, 940 unsigned int *num_input_fmts) 941 { 942 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 943 u32 *input_fmts; 944 945 *num_input_fmts = 0; 946 947 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 948 GFP_KERNEL); 949 if (!input_fmts) 950 return NULL; 951 952 switch (priv->pd_lines) { 953 case 16: 954 input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16; 955 break; 956 case 18: 957 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18; 958 break; 959 default: 960 case 24: 961 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 962 break; 963 } 964 965 *num_input_fmts = MAX_INPUT_SEL_FORMATS; 966 967 return input_fmts; 968 } 969 970 static const struct drm_bridge_funcs tc358768_bridge_funcs = { 971 .attach = tc358768_bridge_attach, 972 .mode_valid = tc358768_bridge_mode_valid, 973 .pre_enable = tc358768_bridge_pre_enable, 974 .enable = tc358768_bridge_enable, 975 .disable = tc358768_bridge_disable, 976 .post_disable = tc358768_bridge_post_disable, 977 978 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 979 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 980 .atomic_reset = drm_atomic_helper_bridge_reset, 981 .atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts, 982 }; 983 984 static const struct drm_bridge_timings default_tc358768_timings = { 985 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 986 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE 987 | DRM_BUS_FLAG_DE_HIGH, 988 }; 989 990 static bool tc358768_is_reserved_reg(unsigned int reg) 991 { 992 switch (reg) { 993 case 0x114 ... 0x13f: 994 case 0x200: 995 case 0x20c: 996 case 0x400 ... 0x408: 997 case 0x41c ... 0x42f: 998 return true; 999 default: 1000 return false; 1001 } 1002 } 1003 1004 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg) 1005 { 1006 if (tc358768_is_reserved_reg(reg)) 1007 return false; 1008 1009 switch (reg) { 1010 case TC358768_CHIPID: 1011 case TC358768_FIFOSTATUS: 1012 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2): 1013 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2): 1014 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2): 1015 return false; 1016 default: 1017 return true; 1018 } 1019 } 1020 1021 static bool tc358768_readable_reg(struct device *dev, unsigned int reg) 1022 { 1023 if (tc358768_is_reserved_reg(reg)) 1024 return false; 1025 1026 switch (reg) { 1027 case TC358768_STARTCNTRL: 1028 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2): 1029 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2): 1030 case TC358768_DSI_START ... (TC358768_DSI_START + 2): 1031 case TC358768_DBG_DATA: 1032 return false; 1033 default: 1034 return true; 1035 } 1036 } 1037 1038 static const struct regmap_config tc358768_regmap_config = { 1039 .name = "tc358768", 1040 .reg_bits = 16, 1041 .val_bits = 16, 1042 .max_register = TC358768_DSI_HACT, 1043 .cache_type = REGCACHE_NONE, 1044 .writeable_reg = tc358768_writeable_reg, 1045 .readable_reg = tc358768_readable_reg, 1046 .reg_format_endian = REGMAP_ENDIAN_BIG, 1047 .val_format_endian = REGMAP_ENDIAN_BIG, 1048 }; 1049 1050 static const struct i2c_device_id tc358768_i2c_ids[] = { 1051 { "tc358768", 0 }, 1052 { "tc358778", 0 }, 1053 { } 1054 }; 1055 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids); 1056 1057 static const struct of_device_id tc358768_of_ids[] = { 1058 { .compatible = "toshiba,tc358768", }, 1059 { .compatible = "toshiba,tc358778", }, 1060 { } 1061 }; 1062 MODULE_DEVICE_TABLE(of, tc358768_of_ids); 1063 1064 static int tc358768_get_regulators(struct tc358768_priv *priv) 1065 { 1066 int i, ret; 1067 1068 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i) 1069 priv->supplies[i].supply = tc358768_supplies[i]; 1070 1071 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies), 1072 priv->supplies); 1073 if (ret < 0) 1074 dev_err(priv->dev, "failed to get regulators: %d\n", ret); 1075 1076 return ret; 1077 } 1078 1079 static int tc358768_i2c_probe(struct i2c_client *client) 1080 { 1081 struct tc358768_priv *priv; 1082 struct device *dev = &client->dev; 1083 struct device_node *np = dev->of_node; 1084 int ret; 1085 1086 if (!np) 1087 return -ENODEV; 1088 1089 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1090 if (!priv) 1091 return -ENOMEM; 1092 1093 dev_set_drvdata(dev, priv); 1094 priv->dev = dev; 1095 1096 ret = tc358768_get_regulators(priv); 1097 if (ret) 1098 return ret; 1099 1100 priv->refclk = devm_clk_get(dev, "refclk"); 1101 if (IS_ERR(priv->refclk)) 1102 return PTR_ERR(priv->refclk); 1103 1104 /* 1105 * RESX is low active, to disable tc358768 initially (keep in reset) 1106 * the gpio line must be LOW. This is the ASSERTED state of 1107 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED). 1108 */ 1109 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1110 GPIOD_OUT_HIGH); 1111 if (IS_ERR(priv->reset_gpio)) 1112 return PTR_ERR(priv->reset_gpio); 1113 1114 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config); 1115 if (IS_ERR(priv->regmap)) { 1116 dev_err(dev, "Failed to init regmap\n"); 1117 return PTR_ERR(priv->regmap); 1118 } 1119 1120 priv->dsi_host.dev = dev; 1121 priv->dsi_host.ops = &tc358768_dsi_host_ops; 1122 1123 priv->bridge.funcs = &tc358768_bridge_funcs; 1124 priv->bridge.timings = &default_tc358768_timings; 1125 priv->bridge.of_node = np; 1126 1127 i2c_set_clientdata(client, priv); 1128 1129 return mipi_dsi_host_register(&priv->dsi_host); 1130 } 1131 1132 static void tc358768_i2c_remove(struct i2c_client *client) 1133 { 1134 struct tc358768_priv *priv = i2c_get_clientdata(client); 1135 1136 mipi_dsi_host_unregister(&priv->dsi_host); 1137 } 1138 1139 static struct i2c_driver tc358768_driver = { 1140 .driver = { 1141 .name = "tc358768", 1142 .of_match_table = tc358768_of_ids, 1143 }, 1144 .id_table = tc358768_i2c_ids, 1145 .probe = tc358768_i2c_probe, 1146 .remove = tc358768_i2c_remove, 1147 }; 1148 module_i2c_driver(tc358768_driver); 1149 1150 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1151 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge"); 1152 MODULE_LICENSE("GPL v2"); 1153