1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/kernel.h> 12 #include <linux/media-bus-format.h> 13 #include <linux/minmax.h> 14 #include <linux/module.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/slab.h> 18 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_drv.h> 21 #include <drm/drm_mipi_dsi.h> 22 #include <drm/drm_of.h> 23 #include <drm/drm_panel.h> 24 #include <video/mipi_display.h> 25 #include <video/videomode.h> 26 27 /* Global (16-bit addressable) */ 28 #define TC358768_CHIPID 0x0000 29 #define TC358768_SYSCTL 0x0002 30 #define TC358768_CONFCTL 0x0004 31 #define TC358768_VSDLY 0x0006 32 #define TC358768_DATAFMT 0x0008 33 #define TC358768_GPIOEN 0x000E 34 #define TC358768_GPIODIR 0x0010 35 #define TC358768_GPIOIN 0x0012 36 #define TC358768_GPIOOUT 0x0014 37 #define TC358768_PLLCTL0 0x0016 38 #define TC358768_PLLCTL1 0x0018 39 #define TC358768_CMDBYTE 0x0022 40 #define TC358768_PP_MISC 0x0032 41 #define TC358768_DSITX_DT 0x0050 42 #define TC358768_FIFOSTATUS 0x00F8 43 44 /* Debug (16-bit addressable) */ 45 #define TC358768_VBUFCTRL 0x00E0 46 #define TC358768_DBG_WIDTH 0x00E2 47 #define TC358768_DBG_VBLANK 0x00E4 48 #define TC358768_DBG_DATA 0x00E8 49 50 /* TX PHY (32-bit addressable) */ 51 #define TC358768_CLW_DPHYCONTTX 0x0100 52 #define TC358768_D0W_DPHYCONTTX 0x0104 53 #define TC358768_D1W_DPHYCONTTX 0x0108 54 #define TC358768_D2W_DPHYCONTTX 0x010C 55 #define TC358768_D3W_DPHYCONTTX 0x0110 56 #define TC358768_CLW_CNTRL 0x0140 57 #define TC358768_D0W_CNTRL 0x0144 58 #define TC358768_D1W_CNTRL 0x0148 59 #define TC358768_D2W_CNTRL 0x014C 60 #define TC358768_D3W_CNTRL 0x0150 61 62 /* TX PPI (32-bit addressable) */ 63 #define TC358768_STARTCNTRL 0x0204 64 #define TC358768_DSITXSTATUS 0x0208 65 #define TC358768_LINEINITCNT 0x0210 66 #define TC358768_LPTXTIMECNT 0x0214 67 #define TC358768_TCLK_HEADERCNT 0x0218 68 #define TC358768_TCLK_TRAILCNT 0x021C 69 #define TC358768_THS_HEADERCNT 0x0220 70 #define TC358768_TWAKEUP 0x0224 71 #define TC358768_TCLK_POSTCNT 0x0228 72 #define TC358768_THS_TRAILCNT 0x022C 73 #define TC358768_HSTXVREGCNT 0x0230 74 #define TC358768_HSTXVREGEN 0x0234 75 #define TC358768_TXOPTIONCNTRL 0x0238 76 #define TC358768_BTACNTRL1 0x023C 77 78 /* TX CTRL (32-bit addressable) */ 79 #define TC358768_DSI_CONTROL 0x040C 80 #define TC358768_DSI_STATUS 0x0410 81 #define TC358768_DSI_INT 0x0414 82 #define TC358768_DSI_INT_ENA 0x0418 83 #define TC358768_DSICMD_RDFIFO 0x0430 84 #define TC358768_DSI_ACKERR 0x0434 85 #define TC358768_DSI_ACKERR_INTENA 0x0438 86 #define TC358768_DSI_ACKERR_HALT 0x043c 87 #define TC358768_DSI_RXERR 0x0440 88 #define TC358768_DSI_RXERR_INTENA 0x0444 89 #define TC358768_DSI_RXERR_HALT 0x0448 90 #define TC358768_DSI_ERR 0x044C 91 #define TC358768_DSI_ERR_INTENA 0x0450 92 #define TC358768_DSI_ERR_HALT 0x0454 93 #define TC358768_DSI_CONFW 0x0500 94 #define TC358768_DSI_LPCMD 0x0500 95 #define TC358768_DSI_RESET 0x0504 96 #define TC358768_DSI_INT_CLR 0x050C 97 #define TC358768_DSI_START 0x0518 98 99 /* DSITX CTRL (16-bit addressable) */ 100 #define TC358768_DSICMD_TX 0x0600 101 #define TC358768_DSICMD_TYPE 0x0602 102 #define TC358768_DSICMD_WC 0x0604 103 #define TC358768_DSICMD_WD0 0x0610 104 #define TC358768_DSICMD_WD1 0x0612 105 #define TC358768_DSICMD_WD2 0x0614 106 #define TC358768_DSICMD_WD3 0x0616 107 #define TC358768_DSI_EVENT 0x0620 108 #define TC358768_DSI_VSW 0x0622 109 #define TC358768_DSI_VBPR 0x0624 110 #define TC358768_DSI_VACT 0x0626 111 #define TC358768_DSI_HSW 0x0628 112 #define TC358768_DSI_HBPR 0x062A 113 #define TC358768_DSI_HACT 0x062C 114 115 /* TC358768_DSI_CONTROL (0x040C) register */ 116 #define TC358768_DSI_CONTROL_DIS_MODE BIT(15) 117 #define TC358768_DSI_CONTROL_TXMD BIT(7) 118 #define TC358768_DSI_CONTROL_HSCKMD BIT(5) 119 #define TC358768_DSI_CONTROL_EOTDIS BIT(0) 120 121 /* TC358768_DSI_CONFW (0x0500) register */ 122 #define TC358768_DSI_CONFW_MODE_SET (5 << 29) 123 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) 124 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24) 125 126 static const char * const tc358768_supplies[] = { 127 "vddc", "vddmipi", "vddio" 128 }; 129 130 struct tc358768_dsi_output { 131 struct mipi_dsi_device *dev; 132 struct drm_panel *panel; 133 struct drm_bridge *bridge; 134 }; 135 136 struct tc358768_priv { 137 struct device *dev; 138 struct regmap *regmap; 139 struct gpio_desc *reset_gpio; 140 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)]; 141 struct clk *refclk; 142 int enabled; 143 int error; 144 145 struct mipi_dsi_host dsi_host; 146 struct drm_bridge bridge; 147 struct tc358768_dsi_output output; 148 149 u32 pd_lines; /* number of Parallel Port Input Data Lines */ 150 u32 dsi_lanes; /* number of DSI Lanes */ 151 u32 dsi_bpp; /* number of Bits Per Pixel over DSI */ 152 153 /* Parameters for PLL programming */ 154 u32 fbd; /* PLL feedback divider */ 155 u32 prd; /* PLL input divider */ 156 u32 frs; /* PLL Freqency range for HSCK (post divider) */ 157 158 u32 dsiclk; /* pll_clk / 2 */ 159 }; 160 161 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host 162 *host) 163 { 164 return container_of(host, struct tc358768_priv, dsi_host); 165 } 166 167 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge 168 *bridge) 169 { 170 return container_of(bridge, struct tc358768_priv, bridge); 171 } 172 173 static int tc358768_clear_error(struct tc358768_priv *priv) 174 { 175 int ret = priv->error; 176 177 priv->error = 0; 178 return ret; 179 } 180 181 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val) 182 { 183 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 184 int tmpval = val; 185 size_t count = 2; 186 187 if (priv->error) 188 return; 189 190 /* 16-bit register? */ 191 if (reg < 0x100 || reg >= 0x600) 192 count = 1; 193 194 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count); 195 } 196 197 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val) 198 { 199 size_t count = 2; 200 201 if (priv->error) 202 return; 203 204 /* 16-bit register? */ 205 if (reg < 0x100 || reg >= 0x600) { 206 *val = 0; 207 count = 1; 208 } 209 210 priv->error = regmap_bulk_read(priv->regmap, reg, val, count); 211 } 212 213 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask, 214 u32 val) 215 { 216 u32 tmp, orig; 217 218 tc358768_read(priv, reg, &orig); 219 220 if (priv->error) 221 return; 222 223 tmp = orig & ~mask; 224 tmp |= val & mask; 225 if (tmp != orig) 226 tc358768_write(priv, reg, tmp); 227 } 228 229 static int tc358768_sw_reset(struct tc358768_priv *priv) 230 { 231 /* Assert Reset */ 232 tc358768_write(priv, TC358768_SYSCTL, 1); 233 /* Release Reset, Exit Sleep */ 234 tc358768_write(priv, TC358768_SYSCTL, 0); 235 236 return tc358768_clear_error(priv); 237 } 238 239 static void tc358768_hw_enable(struct tc358768_priv *priv) 240 { 241 int ret; 242 243 if (priv->enabled) 244 return; 245 246 ret = clk_prepare_enable(priv->refclk); 247 if (ret < 0) 248 dev_err(priv->dev, "error enabling refclk (%d)\n", ret); 249 250 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 251 if (ret < 0) 252 dev_err(priv->dev, "error enabling regulators (%d)\n", ret); 253 254 if (priv->reset_gpio) 255 usleep_range(200, 300); 256 257 /* 258 * The RESX is active low (GPIO_ACTIVE_LOW). 259 * DEASSERT (value = 0) the reset_gpio to enable the chip 260 */ 261 gpiod_set_value_cansleep(priv->reset_gpio, 0); 262 263 /* wait for encoder clocks to stabilize */ 264 usleep_range(1000, 2000); 265 266 priv->enabled = true; 267 } 268 269 static void tc358768_hw_disable(struct tc358768_priv *priv) 270 { 271 int ret; 272 273 if (!priv->enabled) 274 return; 275 276 /* 277 * The RESX is active low (GPIO_ACTIVE_LOW). 278 * ASSERT (value = 1) the reset_gpio to disable the chip 279 */ 280 gpiod_set_value_cansleep(priv->reset_gpio, 1); 281 282 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 283 priv->supplies); 284 if (ret < 0) 285 dev_err(priv->dev, "error disabling regulators (%d)\n", ret); 286 287 clk_disable_unprepare(priv->refclk); 288 289 priv->enabled = false; 290 } 291 292 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk) 293 { 294 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp); 295 } 296 297 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) 298 { 299 return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes); 300 } 301 302 static int tc358768_calc_pll(struct tc358768_priv *priv, 303 const struct drm_display_mode *mode, 304 bool verify_only) 305 { 306 static const u32 frs_limits[] = { 307 1000000000, 308 500000000, 309 250000000, 310 125000000, 311 62500000 312 }; 313 unsigned long refclk; 314 u32 prd, target_pll, i, max_pll, min_pll; 315 u32 frs, best_diff, best_pll, best_prd, best_fbd; 316 317 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000); 318 319 /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */ 320 321 for (i = 0; i < ARRAY_SIZE(frs_limits); i++) 322 if (target_pll >= frs_limits[i]) 323 break; 324 325 if (i == ARRAY_SIZE(frs_limits) || i == 0) 326 return -EINVAL; 327 328 frs = i - 1; 329 max_pll = frs_limits[i - 1]; 330 min_pll = frs_limits[i]; 331 332 refclk = clk_get_rate(priv->refclk); 333 334 best_diff = UINT_MAX; 335 best_pll = 0; 336 best_prd = 0; 337 best_fbd = 0; 338 339 for (prd = 0; prd < 16; ++prd) { 340 u32 divisor = (prd + 1) * (1 << frs); 341 u32 fbd; 342 343 for (fbd = 0; fbd < 512; ++fbd) { 344 u32 pll, diff, pll_in; 345 346 pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor); 347 348 if (pll >= max_pll || pll < min_pll) 349 continue; 350 351 pll_in = (u32)div_u64((u64)refclk, prd + 1); 352 if (pll_in < 4000000) 353 continue; 354 355 diff = max(pll, target_pll) - min(pll, target_pll); 356 357 if (diff < best_diff) { 358 best_diff = diff; 359 best_pll = pll; 360 best_prd = prd; 361 best_fbd = fbd; 362 363 if (best_diff == 0) 364 goto found; 365 } 366 } 367 } 368 369 if (best_diff == UINT_MAX) { 370 dev_err(priv->dev, "could not find suitable PLL setup\n"); 371 return -EINVAL; 372 } 373 374 found: 375 if (verify_only) 376 return 0; 377 378 priv->fbd = best_fbd; 379 priv->prd = best_prd; 380 priv->frs = frs; 381 priv->dsiclk = best_pll / 2; 382 383 return 0; 384 } 385 386 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, 387 struct mipi_dsi_device *dev) 388 { 389 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 390 struct drm_bridge *bridge; 391 struct drm_panel *panel; 392 struct device_node *ep; 393 int ret; 394 395 if (dev->lanes > 4) { 396 dev_err(priv->dev, "unsupported number of data lanes(%u)\n", 397 dev->lanes); 398 return -EINVAL; 399 } 400 401 /* 402 * tc358768 supports both Video and Pulse mode, but the driver only 403 * implements Video (event) mode currently 404 */ 405 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) { 406 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n"); 407 return -ENOTSUPP; 408 } 409 410 /* 411 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only 412 * RGB888 is verified. 413 */ 414 if (dev->format != MIPI_DSI_FMT_RGB888) { 415 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n"); 416 return -ENOTSUPP; 417 } 418 419 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel, 420 &bridge); 421 if (ret) 422 return ret; 423 424 if (panel) { 425 bridge = drm_panel_bridge_add_typed(panel, 426 DRM_MODE_CONNECTOR_DSI); 427 if (IS_ERR(bridge)) 428 return PTR_ERR(bridge); 429 } 430 431 priv->output.dev = dev; 432 priv->output.bridge = bridge; 433 priv->output.panel = panel; 434 435 priv->dsi_lanes = dev->lanes; 436 priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format); 437 438 /* get input ep (port0/endpoint0) */ 439 ret = -EINVAL; 440 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0); 441 if (ep) { 442 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines); 443 444 of_node_put(ep); 445 } 446 447 if (ret) 448 priv->pd_lines = priv->dsi_bpp; 449 450 drm_bridge_add(&priv->bridge); 451 452 return 0; 453 } 454 455 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host, 456 struct mipi_dsi_device *dev) 457 { 458 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 459 460 drm_bridge_remove(&priv->bridge); 461 if (priv->output.panel) 462 drm_panel_bridge_remove(priv->output.bridge); 463 464 return 0; 465 } 466 467 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, 468 const struct mipi_dsi_msg *msg) 469 { 470 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 471 struct mipi_dsi_packet packet; 472 int ret; 473 474 if (!priv->enabled) { 475 dev_err(priv->dev, "Bridge is not enabled\n"); 476 return -ENODEV; 477 } 478 479 if (msg->rx_len) { 480 dev_warn(priv->dev, "MIPI rx is not supported\n"); 481 return -ENOTSUPP; 482 } 483 484 if (msg->tx_len > 8) { 485 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n"); 486 return -ENOTSUPP; 487 } 488 489 ret = mipi_dsi_create_packet(&packet, msg); 490 if (ret) 491 return ret; 492 493 if (mipi_dsi_packet_format_is_short(msg->type)) { 494 tc358768_write(priv, TC358768_DSICMD_TYPE, 495 (0x10 << 8) | (packet.header[0] & 0x3f)); 496 tc358768_write(priv, TC358768_DSICMD_WC, 0); 497 tc358768_write(priv, TC358768_DSICMD_WD0, 498 (packet.header[2] << 8) | packet.header[1]); 499 } else { 500 int i; 501 502 tc358768_write(priv, TC358768_DSICMD_TYPE, 503 (0x40 << 8) | (packet.header[0] & 0x3f)); 504 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length); 505 for (i = 0; i < packet.payload_length; i += 2) { 506 u16 val = packet.payload[i]; 507 508 if (i + 1 < packet.payload_length) 509 val |= packet.payload[i + 1] << 8; 510 511 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val); 512 } 513 } 514 515 /* start transfer */ 516 tc358768_write(priv, TC358768_DSICMD_TX, 1); 517 518 ret = tc358768_clear_error(priv); 519 if (ret) 520 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 521 else 522 ret = packet.size; 523 524 return ret; 525 } 526 527 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = { 528 .attach = tc358768_dsi_host_attach, 529 .detach = tc358768_dsi_host_detach, 530 .transfer = tc358768_dsi_host_transfer, 531 }; 532 533 static int tc358768_bridge_attach(struct drm_bridge *bridge, 534 enum drm_bridge_attach_flags flags) 535 { 536 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 537 538 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) { 539 dev_err(priv->dev, "needs atomic updates support\n"); 540 return -ENOTSUPP; 541 } 542 543 return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge, 544 flags); 545 } 546 547 static enum drm_mode_status 548 tc358768_bridge_mode_valid(struct drm_bridge *bridge, 549 const struct drm_display_info *info, 550 const struct drm_display_mode *mode) 551 { 552 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 553 554 if (tc358768_calc_pll(priv, mode, true)) 555 return MODE_CLOCK_RANGE; 556 557 return MODE_OK; 558 } 559 560 static void tc358768_bridge_disable(struct drm_bridge *bridge) 561 { 562 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 563 int ret; 564 565 /* set FrmStop */ 566 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15)); 567 568 /* wait at least for one frame */ 569 msleep(50); 570 571 /* clear PP_en */ 572 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0); 573 574 /* set RstPtr */ 575 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14)); 576 577 ret = tc358768_clear_error(priv); 578 if (ret) 579 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 580 } 581 582 static void tc358768_bridge_post_disable(struct drm_bridge *bridge) 583 { 584 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 585 586 tc358768_hw_disable(priv); 587 } 588 589 static int tc358768_setup_pll(struct tc358768_priv *priv, 590 const struct drm_display_mode *mode) 591 { 592 u32 fbd, prd, frs; 593 int ret; 594 595 ret = tc358768_calc_pll(priv, mode, false); 596 if (ret) { 597 dev_err(priv->dev, "PLL calculation failed: %d\n", ret); 598 return ret; 599 } 600 601 fbd = priv->fbd; 602 prd = priv->prd; 603 frs = priv->frs; 604 605 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n", 606 clk_get_rate(priv->refclk), fbd, prd, frs); 607 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n", 608 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); 609 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n", 610 tc358768_pll_to_pclk(priv, priv->dsiclk * 2), 611 mode->clock * 1000); 612 613 /* PRD[15:12] FBD[8:0] */ 614 tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd); 615 616 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ 617 tc358768_write(priv, TC358768_PLLCTL1, 618 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0)); 619 620 /* wait for lock */ 621 usleep_range(1000, 2000); 622 623 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */ 624 tc358768_write(priv, TC358768_PLLCTL1, 625 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0)); 626 627 return tc358768_clear_error(priv); 628 } 629 630 #define TC358768_PRECISION 1000 631 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk) 632 { 633 return (ns * TC358768_PRECISION + period_nsk) / period_nsk; 634 } 635 636 static u32 tc358768_to_ns(u32 nsk) 637 { 638 return (nsk / TC358768_PRECISION); 639 } 640 641 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) 642 { 643 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 644 struct mipi_dsi_device *dsi_dev = priv->output.dev; 645 unsigned long mode_flags = dsi_dev->mode_flags; 646 u32 val, val2, lptxcnt, hact, data_type; 647 s32 raw_val; 648 const struct drm_display_mode *mode; 649 u32 dsibclk_nsk, dsiclk_nsk, ui_nsk; 650 u32 dsiclk, dsibclk, video_start; 651 const u32 internal_delay = 40; 652 int ret, i; 653 654 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 655 dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n"); 656 mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS; 657 } 658 659 tc358768_hw_enable(priv); 660 661 ret = tc358768_sw_reset(priv); 662 if (ret) { 663 dev_err(priv->dev, "Software reset failed: %d\n", ret); 664 tc358768_hw_disable(priv); 665 return; 666 } 667 668 mode = &bridge->encoder->crtc->state->adjusted_mode; 669 ret = tc358768_setup_pll(priv, mode); 670 if (ret) { 671 dev_err(priv->dev, "PLL setup failed: %d\n", ret); 672 tc358768_hw_disable(priv); 673 return; 674 } 675 676 dsiclk = priv->dsiclk; 677 dsibclk = dsiclk / 4; 678 679 /* Data Format Control Register */ 680 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ 681 switch (dsi_dev->format) { 682 case MIPI_DSI_FMT_RGB888: 683 val |= (0x3 << 4); 684 hact = mode->hdisplay * 3; 685 video_start = (mode->htotal - mode->hsync_start) * 3; 686 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 687 break; 688 case MIPI_DSI_FMT_RGB666: 689 val |= (0x4 << 4); 690 hact = mode->hdisplay * 3; 691 video_start = (mode->htotal - mode->hsync_start) * 3; 692 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 693 break; 694 695 case MIPI_DSI_FMT_RGB666_PACKED: 696 val |= (0x4 << 4) | BIT(3); 697 hact = mode->hdisplay * 18 / 8; 698 video_start = (mode->htotal - mode->hsync_start) * 18 / 8; 699 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 700 break; 701 702 case MIPI_DSI_FMT_RGB565: 703 val |= (0x5 << 4); 704 hact = mode->hdisplay * 2; 705 video_start = (mode->htotal - mode->hsync_start) * 2; 706 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 707 break; 708 default: 709 dev_err(priv->dev, "Invalid data format (%u)\n", 710 dsi_dev->format); 711 tc358768_hw_disable(priv); 712 return; 713 } 714 715 /* VSDly[9:0] */ 716 video_start = max(video_start, internal_delay + 1) - internal_delay; 717 tc358768_write(priv, TC358768_VSDLY, video_start); 718 719 tc358768_write(priv, TC358768_DATAFMT, val); 720 tc358768_write(priv, TC358768_DSITX_DT, data_type); 721 722 /* Enable D-PHY (HiZ->LP11) */ 723 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); 724 /* Enable lanes */ 725 for (i = 0; i < dsi_dev->lanes; i++) 726 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); 727 728 /* DSI Timings */ 729 dsibclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, 730 dsibclk); 731 dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); 732 ui_nsk = dsiclk_nsk / 2; 733 dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk); 734 dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk); 735 dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk); 736 737 /* LP11 > 100us for D-PHY Rx Init */ 738 val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1; 739 dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val); 740 tc358768_write(priv, TC358768_LINEINITCNT, val); 741 742 /* LPTimeCnt > 50ns */ 743 val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1; 744 lptxcnt = val; 745 dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val); 746 tc358768_write(priv, TC358768_LPTXTIMECNT, val); 747 748 /* 38ns < TCLK_PREPARE < 95ns */ 749 val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; 750 /* TCLK_PREPARE + TCLK_ZERO > 300ns */ 751 val2 = tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), 752 dsibclk_nsk) - 2; 753 val |= val2 << 8; 754 dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val); 755 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); 756 757 /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */ 758 raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 5; 759 val = clamp(raw_val, 0, 127); 760 dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val); 761 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); 762 763 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ 764 val = 50 + tc358768_to_ns(4 * ui_nsk); 765 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; 766 /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ 767 raw_val = tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_nsk) - 10; 768 val2 = clamp(raw_val, 0, 127); 769 val |= val2 << 8; 770 dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val); 771 tc358768_write(priv, TC358768_THS_HEADERCNT, val); 772 773 /* TWAKEUP > 1ms in lptxcnt steps */ 774 val = tc358768_ns_to_cnt(1020000, dsibclk_nsk); 775 val = val / (lptxcnt + 1) - 1; 776 dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val); 777 tc358768_write(priv, TC358768_TWAKEUP, val); 778 779 /* TCLK_POSTCNT > 60ns + 52*UI */ 780 val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), 781 dsibclk_nsk) - 3; 782 dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val); 783 tc358768_write(priv, TC358768_TCLK_POSTCNT, val); 784 785 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ 786 raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk), 787 dsibclk_nsk) - 4; 788 val = clamp(raw_val, 0, 15); 789 dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val); 790 tc358768_write(priv, TC358768_THS_TRAILCNT, val); 791 792 val = BIT(0); 793 for (i = 0; i < dsi_dev->lanes; i++) 794 val |= BIT(i + 1); 795 tc358768_write(priv, TC358768_HSTXVREGEN, val); 796 797 if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 798 tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); 799 800 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ 801 val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); 802 val = tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1; 803 val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), 804 dsibclk_nsk) - 2; 805 val = val << 16 | val2; 806 dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val); 807 tc358768_write(priv, TC358768_BTACNTRL1, val); 808 809 /* START[0] */ 810 tc358768_write(priv, TC358768_STARTCNTRL, 1); 811 812 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 813 /* Set pulse mode */ 814 tc358768_write(priv, TC358768_DSI_EVENT, 0); 815 816 /* vact */ 817 tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); 818 819 /* vsw */ 820 tc358768_write(priv, TC358768_DSI_VSW, 821 mode->vsync_end - mode->vsync_start); 822 /* vbp */ 823 tc358768_write(priv, TC358768_DSI_VBPR, 824 mode->vtotal - mode->vsync_end); 825 826 /* hsw * byteclk * ndl / pclk */ 827 val = (u32)div_u64((mode->hsync_end - mode->hsync_start) * 828 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, 829 mode->clock * 1000); 830 tc358768_write(priv, TC358768_DSI_HSW, val); 831 832 /* hbp * byteclk * ndl / pclk */ 833 val = (u32)div_u64((mode->htotal - mode->hsync_end) * 834 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, 835 mode->clock * 1000); 836 tc358768_write(priv, TC358768_DSI_HBPR, val); 837 } else { 838 /* Set event mode */ 839 tc358768_write(priv, TC358768_DSI_EVENT, 1); 840 841 /* vact */ 842 tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); 843 844 /* vsw (+ vbp) */ 845 tc358768_write(priv, TC358768_DSI_VSW, 846 mode->vtotal - mode->vsync_start); 847 /* vbp (not used in event mode) */ 848 tc358768_write(priv, TC358768_DSI_VBPR, 0); 849 850 /* (hsw + hbp) * byteclk * ndl / pclk */ 851 val = (u32)div_u64((mode->htotal - mode->hsync_start) * 852 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, 853 mode->clock * 1000); 854 tc358768_write(priv, TC358768_DSI_HSW, val); 855 856 /* hbp (not used in event mode) */ 857 tc358768_write(priv, TC358768_DSI_HBPR, 0); 858 } 859 860 /* hact (bytes) */ 861 tc358768_write(priv, TC358768_DSI_HACT, hact); 862 863 /* VSYNC polarity */ 864 if (!(mode->flags & DRM_MODE_FLAG_NVSYNC)) 865 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5)); 866 /* HSYNC polarity */ 867 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 868 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0)); 869 870 /* Start DSI Tx */ 871 tc358768_write(priv, TC358768_DSI_START, 0x1); 872 873 /* Configure DSI_Control register */ 874 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 875 val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | 876 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; 877 tc358768_write(priv, TC358768_DSI_CONFW, val); 878 879 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 880 val |= (dsi_dev->lanes - 1) << 1; 881 882 val |= TC358768_DSI_CONTROL_TXMD; 883 884 if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 885 val |= TC358768_DSI_CONTROL_HSCKMD; 886 887 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 888 val |= TC358768_DSI_CONTROL_EOTDIS; 889 890 tc358768_write(priv, TC358768_DSI_CONFW, val); 891 892 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 893 val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */ 894 tc358768_write(priv, TC358768_DSI_CONFW, val); 895 896 ret = tc358768_clear_error(priv); 897 if (ret) { 898 dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret); 899 tc358768_bridge_disable(bridge); 900 tc358768_bridge_post_disable(bridge); 901 } 902 } 903 904 static void tc358768_bridge_enable(struct drm_bridge *bridge) 905 { 906 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 907 int ret; 908 909 if (!priv->enabled) { 910 dev_err(priv->dev, "Bridge is not enabled\n"); 911 return; 912 } 913 914 /* clear FrmStop and RstPtr */ 915 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0); 916 917 /* set PP_en */ 918 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6)); 919 920 ret = tc358768_clear_error(priv); 921 if (ret) { 922 dev_err(priv->dev, "Bridge enable failed: %d\n", ret); 923 tc358768_bridge_disable(bridge); 924 tc358768_bridge_post_disable(bridge); 925 } 926 } 927 928 #define MAX_INPUT_SEL_FORMATS 1 929 930 static u32 * 931 tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 932 struct drm_bridge_state *bridge_state, 933 struct drm_crtc_state *crtc_state, 934 struct drm_connector_state *conn_state, 935 u32 output_fmt, 936 unsigned int *num_input_fmts) 937 { 938 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 939 u32 *input_fmts; 940 941 *num_input_fmts = 0; 942 943 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 944 GFP_KERNEL); 945 if (!input_fmts) 946 return NULL; 947 948 switch (priv->pd_lines) { 949 case 16: 950 input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16; 951 break; 952 case 18: 953 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18; 954 break; 955 default: 956 case 24: 957 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 958 break; 959 } 960 961 *num_input_fmts = MAX_INPUT_SEL_FORMATS; 962 963 return input_fmts; 964 } 965 966 static const struct drm_bridge_funcs tc358768_bridge_funcs = { 967 .attach = tc358768_bridge_attach, 968 .mode_valid = tc358768_bridge_mode_valid, 969 .pre_enable = tc358768_bridge_pre_enable, 970 .enable = tc358768_bridge_enable, 971 .disable = tc358768_bridge_disable, 972 .post_disable = tc358768_bridge_post_disable, 973 974 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 975 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 976 .atomic_reset = drm_atomic_helper_bridge_reset, 977 .atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts, 978 }; 979 980 static const struct drm_bridge_timings default_tc358768_timings = { 981 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 982 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE 983 | DRM_BUS_FLAG_DE_HIGH, 984 }; 985 986 static bool tc358768_is_reserved_reg(unsigned int reg) 987 { 988 switch (reg) { 989 case 0x114 ... 0x13f: 990 case 0x200: 991 case 0x20c: 992 case 0x400 ... 0x408: 993 case 0x41c ... 0x42f: 994 return true; 995 default: 996 return false; 997 } 998 } 999 1000 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg) 1001 { 1002 if (tc358768_is_reserved_reg(reg)) 1003 return false; 1004 1005 switch (reg) { 1006 case TC358768_CHIPID: 1007 case TC358768_FIFOSTATUS: 1008 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2): 1009 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2): 1010 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2): 1011 return false; 1012 default: 1013 return true; 1014 } 1015 } 1016 1017 static bool tc358768_readable_reg(struct device *dev, unsigned int reg) 1018 { 1019 if (tc358768_is_reserved_reg(reg)) 1020 return false; 1021 1022 switch (reg) { 1023 case TC358768_STARTCNTRL: 1024 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2): 1025 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2): 1026 case TC358768_DSI_START ... (TC358768_DSI_START + 2): 1027 case TC358768_DBG_DATA: 1028 return false; 1029 default: 1030 return true; 1031 } 1032 } 1033 1034 static const struct regmap_config tc358768_regmap_config = { 1035 .name = "tc358768", 1036 .reg_bits = 16, 1037 .val_bits = 16, 1038 .max_register = TC358768_DSI_HACT, 1039 .cache_type = REGCACHE_NONE, 1040 .writeable_reg = tc358768_writeable_reg, 1041 .readable_reg = tc358768_readable_reg, 1042 .reg_format_endian = REGMAP_ENDIAN_BIG, 1043 .val_format_endian = REGMAP_ENDIAN_BIG, 1044 }; 1045 1046 static const struct i2c_device_id tc358768_i2c_ids[] = { 1047 { "tc358768", 0 }, 1048 { "tc358778", 0 }, 1049 { } 1050 }; 1051 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids); 1052 1053 static const struct of_device_id tc358768_of_ids[] = { 1054 { .compatible = "toshiba,tc358768", }, 1055 { .compatible = "toshiba,tc358778", }, 1056 { } 1057 }; 1058 MODULE_DEVICE_TABLE(of, tc358768_of_ids); 1059 1060 static int tc358768_get_regulators(struct tc358768_priv *priv) 1061 { 1062 int i, ret; 1063 1064 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i) 1065 priv->supplies[i].supply = tc358768_supplies[i]; 1066 1067 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies), 1068 priv->supplies); 1069 if (ret < 0) 1070 dev_err(priv->dev, "failed to get regulators: %d\n", ret); 1071 1072 return ret; 1073 } 1074 1075 static int tc358768_i2c_probe(struct i2c_client *client) 1076 { 1077 struct tc358768_priv *priv; 1078 struct device *dev = &client->dev; 1079 struct device_node *np = dev->of_node; 1080 int ret; 1081 1082 if (!np) 1083 return -ENODEV; 1084 1085 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1086 if (!priv) 1087 return -ENOMEM; 1088 1089 dev_set_drvdata(dev, priv); 1090 priv->dev = dev; 1091 1092 ret = tc358768_get_regulators(priv); 1093 if (ret) 1094 return ret; 1095 1096 priv->refclk = devm_clk_get(dev, "refclk"); 1097 if (IS_ERR(priv->refclk)) 1098 return PTR_ERR(priv->refclk); 1099 1100 /* 1101 * RESX is low active, to disable tc358768 initially (keep in reset) 1102 * the gpio line must be LOW. This is the ASSERTED state of 1103 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED). 1104 */ 1105 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1106 GPIOD_OUT_HIGH); 1107 if (IS_ERR(priv->reset_gpio)) 1108 return PTR_ERR(priv->reset_gpio); 1109 1110 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config); 1111 if (IS_ERR(priv->regmap)) { 1112 dev_err(dev, "Failed to init regmap\n"); 1113 return PTR_ERR(priv->regmap); 1114 } 1115 1116 priv->dsi_host.dev = dev; 1117 priv->dsi_host.ops = &tc358768_dsi_host_ops; 1118 1119 priv->bridge.funcs = &tc358768_bridge_funcs; 1120 priv->bridge.timings = &default_tc358768_timings; 1121 priv->bridge.of_node = np; 1122 1123 i2c_set_clientdata(client, priv); 1124 1125 return mipi_dsi_host_register(&priv->dsi_host); 1126 } 1127 1128 static void tc358768_i2c_remove(struct i2c_client *client) 1129 { 1130 struct tc358768_priv *priv = i2c_get_clientdata(client); 1131 1132 mipi_dsi_host_unregister(&priv->dsi_host); 1133 } 1134 1135 static struct i2c_driver tc358768_driver = { 1136 .driver = { 1137 .name = "tc358768", 1138 .of_match_table = tc358768_of_ids, 1139 }, 1140 .id_table = tc358768_i2c_ids, 1141 .probe = tc358768_i2c_probe, 1142 .remove = tc358768_i2c_remove, 1143 }; 1144 module_i2c_driver(tc358768_driver); 1145 1146 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1147 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge"); 1148 MODULE_LICENSE("GPL v2"); 1149