xref: /openbmc/linux/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c (revision c900529f3d9161bfde5cca0754f83b4d3c3e0220)
1afba7e6cSSwapnil Jakhade // SPDX-License-Identifier: GPL-2.0
2afba7e6cSSwapnil Jakhade /*
3afba7e6cSSwapnil Jakhade  * TI j721e Cadence MHDP8546 DP wrapper
4afba7e6cSSwapnil Jakhade  *
5afba7e6cSSwapnil Jakhade  * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
6afba7e6cSSwapnil Jakhade  * Author: Jyri Sarha <jsarha@ti.com>
7afba7e6cSSwapnil Jakhade  */
8afba7e6cSSwapnil Jakhade 
9afba7e6cSSwapnil Jakhade #include <linux/io.h>
10afba7e6cSSwapnil Jakhade #include <linux/platform_device.h>
11afba7e6cSSwapnil Jakhade 
12afba7e6cSSwapnil Jakhade #include "cdns-mhdp8546-j721e.h"
13afba7e6cSSwapnil Jakhade 
14afba7e6cSSwapnil Jakhade #define	REVISION			0x00
15afba7e6cSSwapnil Jakhade #define	DPTX_IPCFG			0x04
16afba7e6cSSwapnil Jakhade #define	ECC_MEM_CFG			0x08
17afba7e6cSSwapnil Jakhade #define	DPTX_DSC_CFG			0x0c
18afba7e6cSSwapnil Jakhade #define	DPTX_SRC_CFG			0x10
19afba7e6cSSwapnil Jakhade #define	DPTX_VIF_SECURE_MODE_CFG	0x14
20afba7e6cSSwapnil Jakhade #define	DPTX_VIF_CONN_STATUS		0x18
21afba7e6cSSwapnil Jakhade #define	PHY_CLK_STATUS			0x1c
22afba7e6cSSwapnil Jakhade 
23afba7e6cSSwapnil Jakhade #define DPTX_SRC_AIF_EN			BIT(16)
24afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_3_IN30B		BIT(11)
25afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_2_IN30B		BIT(10)
26afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_1_IN30B		BIT(9)
27afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_0_IN30B		BIT(8)
28afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_3_SEL_DPI5		BIT(7)
29afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_3_SEL_DPI3		0
30afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_2_SEL_DPI4		BIT(6)
31afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_2_SEL_DPI2		0
32afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_1_SEL_DPI3		BIT(5)
33afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_1_SEL_DPI1		0
34afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_0_SEL_DPI2		BIT(4)
35afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_0_SEL_DPI0		0
36afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_3_EN		BIT(3)
37afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_2_EN		BIT(2)
38afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_1_EN		BIT(1)
39afba7e6cSSwapnil Jakhade #define DPTX_SRC_VIF_0_EN		BIT(0)
40afba7e6cSSwapnil Jakhade 
41afba7e6cSSwapnil Jakhade /* TODO turn DPTX_IPCFG fw_mem_clk_en at pm_runtime_suspend. */
42afba7e6cSSwapnil Jakhade 
cdns_mhdp_j721e_init(struct cdns_mhdp_device * mhdp)43afba7e6cSSwapnil Jakhade static int cdns_mhdp_j721e_init(struct cdns_mhdp_device *mhdp)
44afba7e6cSSwapnil Jakhade {
45afba7e6cSSwapnil Jakhade 	struct platform_device *pdev = to_platform_device(mhdp->dev);
46afba7e6cSSwapnil Jakhade 
47afba7e6cSSwapnil Jakhade 	mhdp->j721e_regs = devm_platform_ioremap_resource(pdev, 1);
48afba7e6cSSwapnil Jakhade 	return PTR_ERR_OR_ZERO(mhdp->j721e_regs);
49afba7e6cSSwapnil Jakhade }
50afba7e6cSSwapnil Jakhade 
cdns_mhdp_j721e_enable(struct cdns_mhdp_device * mhdp)51afba7e6cSSwapnil Jakhade static void cdns_mhdp_j721e_enable(struct cdns_mhdp_device *mhdp)
52afba7e6cSSwapnil Jakhade {
53afba7e6cSSwapnil Jakhade 	/*
54afba7e6cSSwapnil Jakhade 	 * Enable VIF_0 and select DPI2 as its input. DSS0 DPI0 is connected
55afba7e6cSSwapnil Jakhade 	 * to eDP DPI2. This is the only supported SST configuration on
56afba7e6cSSwapnil Jakhade 	 * J721E.
57afba7e6cSSwapnil Jakhade 	 */
58afba7e6cSSwapnil Jakhade 	writel(DPTX_SRC_VIF_0_EN | DPTX_SRC_VIF_0_SEL_DPI2,
59afba7e6cSSwapnil Jakhade 	       mhdp->j721e_regs + DPTX_SRC_CFG);
60afba7e6cSSwapnil Jakhade }
61afba7e6cSSwapnil Jakhade 
cdns_mhdp_j721e_disable(struct cdns_mhdp_device * mhdp)62afba7e6cSSwapnil Jakhade static void cdns_mhdp_j721e_disable(struct cdns_mhdp_device *mhdp)
63afba7e6cSSwapnil Jakhade {
64afba7e6cSSwapnil Jakhade 	/* Put everything to defaults  */
65afba7e6cSSwapnil Jakhade 	writel(0, mhdp->j721e_regs + DPTX_DSC_CFG);
66afba7e6cSSwapnil Jakhade }
67afba7e6cSSwapnil Jakhade 
68afba7e6cSSwapnil Jakhade const struct mhdp_platform_ops mhdp_ti_j721e_ops = {
69afba7e6cSSwapnil Jakhade 	.init = cdns_mhdp_j721e_init,
70afba7e6cSSwapnil Jakhade 	.enable = cdns_mhdp_j721e_enable,
71afba7e6cSSwapnil Jakhade 	.disable = cdns_mhdp_j721e_disable,
72afba7e6cSSwapnil Jakhade };
73afba7e6cSSwapnil Jakhade 
74*1934bf53SNikhil Devshatwar const u32
75*1934bf53SNikhil Devshatwar mhdp_ti_j721e_bridge_input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
76afba7e6cSSwapnil Jakhade 				       DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE |
77*1934bf53SNikhil Devshatwar 				       DRM_BUS_FLAG_DE_HIGH;
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