1e098bc96SEvan Quan /*
2e098bc96SEvan Quan * Copyright 2020 Advanced Micro Devices, Inc.
3e098bc96SEvan Quan *
4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a
5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"),
6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation
7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the
9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions:
10e098bc96SEvan Quan *
11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in
12e098bc96SEvan Quan * all copies or substantial portions of the Software.
13e098bc96SEvan Quan *
14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE.
21e098bc96SEvan Quan */
22e098bc96SEvan Quan
23e098bc96SEvan Quan #ifndef __SMU_CMN_H__
24e098bc96SEvan Quan #define __SMU_CMN_H__
25e098bc96SEvan Quan
26e098bc96SEvan Quan #include "amdgpu_smu.h"
27e098bc96SEvan Quan
28e098bc96SEvan Quan #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
297689dab4SEvan Quan
307689dab4SEvan Quan #define FDO_PWM_MODE_STATIC 1
317689dab4SEvan Quan #define FDO_PWM_MODE_STATIC_RPM 5
327689dab4SEvan Quan
33*f1d1abd6SAsad Kamal extern const int link_speed[];
34*f1d1abd6SAsad Kamal
35*f1d1abd6SAsad Kamal /* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed units */
pcie_gen_to_speed(uint32_t gen)36*f1d1abd6SAsad Kamal static inline int pcie_gen_to_speed(uint32_t gen)
37*f1d1abd6SAsad Kamal {
38*f1d1abd6SAsad Kamal return ((gen == 0) ? link_speed[0] : link_speed[gen - 1]);
39*f1d1abd6SAsad Kamal }
40*f1d1abd6SAsad Kamal
4174353883SHuang Rui int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
425810323bSLuben Tuikov uint16_t msg_index,
435810323bSLuben Tuikov uint32_t param);
44e098bc96SEvan Quan int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
45e098bc96SEvan Quan enum smu_message_type msg,
46e098bc96SEvan Quan uint32_t param,
47e098bc96SEvan Quan uint32_t *read_arg);
48e098bc96SEvan Quan
49e098bc96SEvan Quan int smu_cmn_send_smc_msg(struct smu_context *smu,
50e098bc96SEvan Quan enum smu_message_type msg,
51e098bc96SEvan Quan uint32_t *read_arg);
52e098bc96SEvan Quan
5360cfad32SKenneth Feng int smu_cmn_send_debug_smc_msg(struct smu_context *smu,
5460cfad32SKenneth Feng uint32_t msg);
5560cfad32SKenneth Feng
5651097df1SCandice Li int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu,
5751097df1SCandice Li uint32_t msg, uint32_t param);
5851097df1SCandice Li
59e42569d0SLijo Lazar int smu_cmn_wait_for_response(struct smu_context *smu);
60e42569d0SLijo Lazar
61e098bc96SEvan Quan int smu_cmn_to_asic_specific_index(struct smu_context *smu,
62e098bc96SEvan Quan enum smu_cmn2asic_mapping_type type,
63e098bc96SEvan Quan uint32_t index);
64e098bc96SEvan Quan
65e098bc96SEvan Quan int smu_cmn_feature_is_supported(struct smu_context *smu,
66e098bc96SEvan Quan enum smu_feature_mask mask);
67e098bc96SEvan Quan
68e098bc96SEvan Quan int smu_cmn_feature_is_enabled(struct smu_context *smu,
69e098bc96SEvan Quan enum smu_feature_mask mask);
70e098bc96SEvan Quan
71e098bc96SEvan Quan bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
72e098bc96SEvan Quan enum smu_clk_type clk_type);
73e098bc96SEvan Quan
74e098bc96SEvan Quan int smu_cmn_get_enabled_mask(struct smu_context *smu,
752d282665SEvan Quan uint64_t *feature_mask);
76e098bc96SEvan Quan
77c23083cdSGraham Sider uint64_t smu_cmn_get_indep_throttler_status(
78c23083cdSGraham Sider const unsigned long dep_status,
79c23083cdSGraham Sider const uint8_t *throttler_map);
80c23083cdSGraham Sider
8110144762SEvan Quan int smu_cmn_feature_update_enable_state(struct smu_context *smu,
8210144762SEvan Quan uint64_t feature_mask,
8310144762SEvan Quan bool enabled);
8410144762SEvan Quan
85e098bc96SEvan Quan int smu_cmn_feature_set_enabled(struct smu_context *smu,
86e098bc96SEvan Quan enum smu_feature_mask mask,
87e098bc96SEvan Quan bool enable);
88e098bc96SEvan Quan
89e098bc96SEvan Quan size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
90e098bc96SEvan Quan char *buf);
91e098bc96SEvan Quan
92e098bc96SEvan Quan int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
93e098bc96SEvan Quan uint64_t new_mask);
94e098bc96SEvan Quan
95e098bc96SEvan Quan int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
96e098bc96SEvan Quan enum smu_feature_mask mask);
97e098bc96SEvan Quan
98e098bc96SEvan Quan int smu_cmn_get_smc_version(struct smu_context *smu,
99e098bc96SEvan Quan uint32_t *if_version,
100e098bc96SEvan Quan uint32_t *smu_version);
101e098bc96SEvan Quan
102e098bc96SEvan Quan int smu_cmn_update_table(struct smu_context *smu,
103e098bc96SEvan Quan enum smu_table_id table_index,
104e098bc96SEvan Quan int argument,
105e098bc96SEvan Quan void *table_data,
106e098bc96SEvan Quan bool drv2smu);
107e098bc96SEvan Quan
108e098bc96SEvan Quan int smu_cmn_write_watermarks_table(struct smu_context *smu);
109e098bc96SEvan Quan
110e098bc96SEvan Quan int smu_cmn_write_pptable(struct smu_context *smu);
111e098bc96SEvan Quan
112e098bc96SEvan Quan int smu_cmn_get_metrics_table(struct smu_context *smu,
113e098bc96SEvan Quan void *metrics_table,
114e098bc96SEvan Quan bool bypass_cache);
115e098bc96SEvan Quan
1166a2d7a22SEvan Quan int smu_cmn_get_combo_pptable(struct smu_context *smu);
1176a2d7a22SEvan Quan
118de4b7cd8SKevin Wang void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev);
119de4b7cd8SKevin Wang
1201689fca0SEvan Quan int smu_cmn_set_mp1_state(struct smu_context *smu,
1211689fca0SEvan Quan enum pp_mp1_state mp1_state);
1221689fca0SEvan Quan
1238f48ba30SLang Yu /*
1248f48ba30SLang Yu * Helper function to make sysfs_emit_at() happy. Align buf to
1258f48ba30SLang Yu * the current page boundary and record the offset.
1268f48ba30SLang Yu */
smu_cmn_get_sysfs_buf(char ** buf,int * offset)1278f48ba30SLang Yu static inline void smu_cmn_get_sysfs_buf(char **buf, int *offset)
1288f48ba30SLang Yu {
1298f48ba30SLang Yu if (!*buf || !offset)
1308f48ba30SLang Yu return;
1318f48ba30SLang Yu
1328f48ba30SLang Yu *offset = offset_in_page(*buf);
1338f48ba30SLang Yu *buf -= *offset;
1348f48ba30SLang Yu }
1358f48ba30SLang Yu
1368b514e89SEvan Quan bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev);
1378b514e89SEvan Quan
138e098bc96SEvan Quan #endif
139e098bc96SEvan Quan #endif
140