1*837d542aSEvan Quan /* 2*837d542aSEvan Quan * Copyright 2015 Advanced Micro Devices, Inc. 3*837d542aSEvan Quan * 4*837d542aSEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5*837d542aSEvan Quan * copy of this software and associated documentation files (the "Software"), 6*837d542aSEvan Quan * to deal in the Software without restriction, including without limitation 7*837d542aSEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*837d542aSEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9*837d542aSEvan Quan * Software is furnished to do so, subject to the following conditions: 10*837d542aSEvan Quan * 11*837d542aSEvan Quan * The above copyright notice and this permission notice shall be included in 12*837d542aSEvan Quan * all copies or substantial portions of the Software. 13*837d542aSEvan Quan * 14*837d542aSEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*837d542aSEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*837d542aSEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*837d542aSEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*837d542aSEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*837d542aSEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*837d542aSEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21*837d542aSEvan Quan * 22*837d542aSEvan Quan */ 23*837d542aSEvan Quan #ifndef _SMUMGR_H_ 24*837d542aSEvan Quan #define _SMUMGR_H_ 25*837d542aSEvan Quan #include <linux/types.h> 26*837d542aSEvan Quan #include "amd_powerplay.h" 27*837d542aSEvan Quan #include "hwmgr.h" 28*837d542aSEvan Quan 29*837d542aSEvan Quan enum SMU_TABLE { 30*837d542aSEvan Quan SMU_UVD_TABLE = 0, 31*837d542aSEvan Quan SMU_VCE_TABLE, 32*837d542aSEvan Quan SMU_BIF_TABLE, 33*837d542aSEvan Quan }; 34*837d542aSEvan Quan 35*837d542aSEvan Quan enum SMU_TYPE { 36*837d542aSEvan Quan SMU_SoftRegisters = 0, 37*837d542aSEvan Quan SMU_Discrete_DpmTable, 38*837d542aSEvan Quan }; 39*837d542aSEvan Quan 40*837d542aSEvan Quan enum SMU_MEMBER { 41*837d542aSEvan Quan HandshakeDisables = 0, 42*837d542aSEvan Quan VoltageChangeTimeout, 43*837d542aSEvan Quan AverageGraphicsActivity, 44*837d542aSEvan Quan AverageMemoryActivity, 45*837d542aSEvan Quan PreVBlankGap, 46*837d542aSEvan Quan VBlankTimeout, 47*837d542aSEvan Quan UcodeLoadStatus, 48*837d542aSEvan Quan UvdBootLevel, 49*837d542aSEvan Quan VceBootLevel, 50*837d542aSEvan Quan LowSclkInterruptThreshold, 51*837d542aSEvan Quan DRAM_LOG_ADDR_H, 52*837d542aSEvan Quan DRAM_LOG_ADDR_L, 53*837d542aSEvan Quan DRAM_LOG_PHY_ADDR_H, 54*837d542aSEvan Quan DRAM_LOG_PHY_ADDR_L, 55*837d542aSEvan Quan DRAM_LOG_BUFF_SIZE, 56*837d542aSEvan Quan }; 57*837d542aSEvan Quan 58*837d542aSEvan Quan 59*837d542aSEvan Quan enum SMU_MAC_DEFINITION { 60*837d542aSEvan Quan SMU_MAX_LEVELS_GRAPHICS = 0, 61*837d542aSEvan Quan SMU_MAX_LEVELS_MEMORY, 62*837d542aSEvan Quan SMU_MAX_LEVELS_LINK, 63*837d542aSEvan Quan SMU_MAX_ENTRIES_SMIO, 64*837d542aSEvan Quan SMU_MAX_LEVELS_VDDC, 65*837d542aSEvan Quan SMU_MAX_LEVELS_VDDGFX, 66*837d542aSEvan Quan SMU_MAX_LEVELS_VDDCI, 67*837d542aSEvan Quan SMU_MAX_LEVELS_MVDD, 68*837d542aSEvan Quan SMU_UVD_MCLK_HANDSHAKE_DISABLE, 69*837d542aSEvan Quan }; 70*837d542aSEvan Quan 71*837d542aSEvan Quan enum SMU9_TABLE_ID { 72*837d542aSEvan Quan PPTABLE = 0, 73*837d542aSEvan Quan WMTABLE, 74*837d542aSEvan Quan AVFSTABLE, 75*837d542aSEvan Quan TOOLSTABLE, 76*837d542aSEvan Quan AVFSFUSETABLE 77*837d542aSEvan Quan }; 78*837d542aSEvan Quan 79*837d542aSEvan Quan enum SMU10_TABLE_ID { 80*837d542aSEvan Quan SMU10_WMTABLE = 0, 81*837d542aSEvan Quan SMU10_CLOCKTABLE, 82*837d542aSEvan Quan }; 83*837d542aSEvan Quan 84*837d542aSEvan Quan extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table); 85*837d542aSEvan Quan 86*837d542aSEvan Quan extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr); 87*837d542aSEvan Quan 88*837d542aSEvan Quan extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t *resp); 89*837d542aSEvan Quan 90*837d542aSEvan Quan extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, 91*837d542aSEvan Quan uint16_t msg, uint32_t parameter, 92*837d542aSEvan Quan uint32_t *resp); 93*837d542aSEvan Quan 94*837d542aSEvan Quan extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr); 95*837d542aSEvan Quan 96*837d542aSEvan Quan extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type); 97*837d542aSEvan Quan extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr); 98*837d542aSEvan Quan extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr); 99*837d542aSEvan Quan extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr); 100*837d542aSEvan Quan extern int smum_init_smc_table(struct pp_hwmgr *hwmgr); 101*837d542aSEvan Quan extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr); 102*837d542aSEvan Quan extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr); 103*837d542aSEvan Quan extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr); 104*837d542aSEvan Quan extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, 105*837d542aSEvan Quan uint32_t type, uint32_t member); 106*837d542aSEvan Quan extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value); 107*837d542aSEvan Quan 108*837d542aSEvan Quan extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr); 109*837d542aSEvan Quan 110*837d542aSEvan Quan extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr); 111*837d542aSEvan Quan 112*837d542aSEvan Quan extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting); 113*837d542aSEvan Quan 114*837d542aSEvan Quan extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); 115*837d542aSEvan Quan 116*837d542aSEvan Quan extern int smum_stop_smc(struct pp_hwmgr *hwmgr); 117*837d542aSEvan Quan 118*837d542aSEvan Quan #endif 119