xref: /openbmc/linux/drivers/gpu/drm/amd/pm/legacy-dpm/r600_dpm.h (revision c900529f3d9161bfde5cca0754f83b4d3c3e0220)
1837d542aSEvan Quan /*
2837d542aSEvan Quan  * Copyright 2011 Advanced Micro Devices, Inc.
3837d542aSEvan Quan  *
4837d542aSEvan Quan  * Permission is hereby granted, free of charge, to any person obtaining a
5837d542aSEvan Quan  * copy of this software and associated documentation files (the "Software"),
6837d542aSEvan Quan  * to deal in the Software without restriction, including without limitation
7837d542aSEvan Quan  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8837d542aSEvan Quan  * and/or sell copies of the Software, and to permit persons to whom the
9837d542aSEvan Quan  * Software is furnished to do so, subject to the following conditions:
10837d542aSEvan Quan  *
11837d542aSEvan Quan  * The above copyright notice and this permission notice shall be included in
12837d542aSEvan Quan  * all copies or substantial portions of the Software.
13837d542aSEvan Quan  *
14837d542aSEvan Quan  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15837d542aSEvan Quan  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16837d542aSEvan Quan  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17837d542aSEvan Quan  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18837d542aSEvan Quan  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19837d542aSEvan Quan  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20837d542aSEvan Quan  * OTHER DEALINGS IN THE SOFTWARE.
21837d542aSEvan Quan  *
22837d542aSEvan Quan  */
23837d542aSEvan Quan #ifndef __R600_DPM_H__
24837d542aSEvan Quan #define __R600_DPM_H__
25837d542aSEvan Quan 
26837d542aSEvan Quan #define R600_ASI_DFLT                                10000
27837d542aSEvan Quan #define R600_BSP_DFLT                                0x41EB
28837d542aSEvan Quan #define R600_BSU_DFLT                                0x2
29837d542aSEvan Quan #define R600_AH_DFLT                                 5
30837d542aSEvan Quan #define R600_RLP_DFLT                                25
31837d542aSEvan Quan #define R600_RMP_DFLT                                65
32837d542aSEvan Quan #define R600_LHP_DFLT                                40
33837d542aSEvan Quan #define R600_LMP_DFLT                                15
34837d542aSEvan Quan #define R600_TD_DFLT                                 0
35837d542aSEvan Quan #define R600_UTC_DFLT_00                             0x24
36837d542aSEvan Quan #define R600_UTC_DFLT_01                             0x22
37837d542aSEvan Quan #define R600_UTC_DFLT_02                             0x22
38837d542aSEvan Quan #define R600_UTC_DFLT_03                             0x22
39837d542aSEvan Quan #define R600_UTC_DFLT_04                             0x22
40837d542aSEvan Quan #define R600_UTC_DFLT_05                             0x22
41837d542aSEvan Quan #define R600_UTC_DFLT_06                             0x22
42837d542aSEvan Quan #define R600_UTC_DFLT_07                             0x22
43837d542aSEvan Quan #define R600_UTC_DFLT_08                             0x22
44837d542aSEvan Quan #define R600_UTC_DFLT_09                             0x22
45837d542aSEvan Quan #define R600_UTC_DFLT_10                             0x22
46837d542aSEvan Quan #define R600_UTC_DFLT_11                             0x22
47837d542aSEvan Quan #define R600_UTC_DFLT_12                             0x22
48837d542aSEvan Quan #define R600_UTC_DFLT_13                             0x22
49837d542aSEvan Quan #define R600_UTC_DFLT_14                             0x22
50837d542aSEvan Quan #define R600_DTC_DFLT_00                             0x24
51837d542aSEvan Quan #define R600_DTC_DFLT_01                             0x22
52837d542aSEvan Quan #define R600_DTC_DFLT_02                             0x22
53837d542aSEvan Quan #define R600_DTC_DFLT_03                             0x22
54837d542aSEvan Quan #define R600_DTC_DFLT_04                             0x22
55837d542aSEvan Quan #define R600_DTC_DFLT_05                             0x22
56837d542aSEvan Quan #define R600_DTC_DFLT_06                             0x22
57837d542aSEvan Quan #define R600_DTC_DFLT_07                             0x22
58837d542aSEvan Quan #define R600_DTC_DFLT_08                             0x22
59837d542aSEvan Quan #define R600_DTC_DFLT_09                             0x22
60837d542aSEvan Quan #define R600_DTC_DFLT_10                             0x22
61837d542aSEvan Quan #define R600_DTC_DFLT_11                             0x22
62837d542aSEvan Quan #define R600_DTC_DFLT_12                             0x22
63837d542aSEvan Quan #define R600_DTC_DFLT_13                             0x22
64837d542aSEvan Quan #define R600_DTC_DFLT_14                             0x22
65837d542aSEvan Quan #define R600_VRC_DFLT                                0x0000C003
66837d542aSEvan Quan #define R600_VOLTAGERESPONSETIME_DFLT                1000
67837d542aSEvan Quan #define R600_BACKBIASRESPONSETIME_DFLT               1000
68837d542aSEvan Quan #define R600_VRU_DFLT                                0x3
69837d542aSEvan Quan #define R600_SPLLSTEPTIME_DFLT                       0x1000
70837d542aSEvan Quan #define R600_SPLLSTEPUNIT_DFLT                       0x3
71837d542aSEvan Quan #define R600_TPU_DFLT                                0
72837d542aSEvan Quan #define R600_TPC_DFLT                                0x200
73837d542aSEvan Quan #define R600_SSTU_DFLT                               0
74837d542aSEvan Quan #define R600_SST_DFLT                                0x00C8
75837d542aSEvan Quan #define R600_GICST_DFLT                              0x200
76837d542aSEvan Quan #define R600_FCT_DFLT                                0x0400
77837d542aSEvan Quan #define R600_FCTU_DFLT                               0
78837d542aSEvan Quan #define R600_CTXCGTT3DRPHC_DFLT                      0x20
79837d542aSEvan Quan #define R600_CTXCGTT3DRSDC_DFLT                      0x40
80837d542aSEvan Quan #define R600_VDDC3DOORPHC_DFLT                       0x100
81837d542aSEvan Quan #define R600_VDDC3DOORSDC_DFLT                       0x7
82837d542aSEvan Quan #define R600_VDDC3DOORSU_DFLT                        0
83837d542aSEvan Quan #define R600_MPLLLOCKTIME_DFLT                       100
84837d542aSEvan Quan #define R600_MPLLRESETTIME_DFLT                      150
85837d542aSEvan Quan #define R600_VCOSTEPPCT_DFLT                          20
86837d542aSEvan Quan #define R600_ENDINGVCOSTEPPCT_DFLT                    5
87837d542aSEvan Quan #define R600_REFERENCEDIVIDER_DFLT                    4
88837d542aSEvan Quan 
89837d542aSEvan Quan #define R600_PM_NUMBER_OF_TC 15
90837d542aSEvan Quan #define R600_PM_NUMBER_OF_SCLKS 20
91837d542aSEvan Quan #define R600_PM_NUMBER_OF_MCLKS 4
92837d542aSEvan Quan #define R600_PM_NUMBER_OF_VOLTAGE_LEVELS 4
93837d542aSEvan Quan #define R600_PM_NUMBER_OF_ACTIVITY_LEVELS 3
94837d542aSEvan Quan 
95837d542aSEvan Quan /* XXX are these ok? */
96837d542aSEvan Quan #define R600_TEMP_RANGE_MIN (90 * 1000)
97837d542aSEvan Quan #define R600_TEMP_RANGE_MAX (120 * 1000)
98837d542aSEvan Quan 
99837d542aSEvan Quan #define FDO_PWM_MODE_STATIC  1
100837d542aSEvan Quan #define FDO_PWM_MODE_STATIC_RPM 5
101837d542aSEvan Quan 
102837d542aSEvan Quan enum r600_power_level {
103837d542aSEvan Quan 	R600_POWER_LEVEL_LOW = 0,
104837d542aSEvan Quan 	R600_POWER_LEVEL_MEDIUM = 1,
105837d542aSEvan Quan 	R600_POWER_LEVEL_HIGH = 2,
106837d542aSEvan Quan 	R600_POWER_LEVEL_CTXSW = 3,
107837d542aSEvan Quan };
108837d542aSEvan Quan 
109837d542aSEvan Quan enum r600_td {
110837d542aSEvan Quan 	R600_TD_AUTO,
111837d542aSEvan Quan 	R600_TD_UP,
112837d542aSEvan Quan 	R600_TD_DOWN,
113837d542aSEvan Quan };
114837d542aSEvan Quan 
115837d542aSEvan Quan enum r600_display_watermark {
116837d542aSEvan Quan 	R600_DISPLAY_WATERMARK_LOW = 0,
117837d542aSEvan Quan 	R600_DISPLAY_WATERMARK_HIGH = 1,
118837d542aSEvan Quan };
119837d542aSEvan Quan 
120*803fe209SRan Sun enum r600_display_gap {
121837d542aSEvan Quan     R600_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
122837d542aSEvan Quan     R600_PM_DISPLAY_GAP_VBLANK       = 1,
123837d542aSEvan Quan     R600_PM_DISPLAY_GAP_WATERMARK    = 2,
124837d542aSEvan Quan     R600_PM_DISPLAY_GAP_IGNORE       = 3,
125837d542aSEvan Quan };
126837d542aSEvan Quan #endif
127