1*837d542aSEvan Quan /* 2*837d542aSEvan Quan * Copyright 2021 Advanced Micro Devices, Inc. 3*837d542aSEvan Quan * 4*837d542aSEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5*837d542aSEvan Quan * copy of this software and associated documentation files (the "Software"), 6*837d542aSEvan Quan * to deal in the Software without restriction, including without limitation 7*837d542aSEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*837d542aSEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9*837d542aSEvan Quan * Software is furnished to do so, subject to the following conditions: 10*837d542aSEvan Quan * 11*837d542aSEvan Quan * The above copyright notice and this permission notice shall be included in 12*837d542aSEvan Quan * all copies or substantial portions of the Software. 13*837d542aSEvan Quan * 14*837d542aSEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*837d542aSEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*837d542aSEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*837d542aSEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*837d542aSEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*837d542aSEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*837d542aSEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21*837d542aSEvan Quan * 22*837d542aSEvan Quan */ 23*837d542aSEvan Quan #ifndef __LEGACY_DPM_H__ 24*837d542aSEvan Quan #define __LEGACY_DPM_H__ 25*837d542aSEvan Quan 26*837d542aSEvan Quan void amdgpu_dpm_print_class_info(u32 class, u32 class2); 27*837d542aSEvan Quan void amdgpu_dpm_print_cap_info(u32 caps); 28*837d542aSEvan Quan void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, 29*837d542aSEvan Quan struct amdgpu_ps *rps); 30*837d542aSEvan Quan int amdgpu_get_platform_caps(struct amdgpu_device *adev); 31*837d542aSEvan Quan int amdgpu_parse_extended_power_table(struct amdgpu_device *adev); 32*837d542aSEvan Quan void amdgpu_free_extended_power_table(struct amdgpu_device *adev); 33*837d542aSEvan Quan void amdgpu_add_thermal_controller(struct amdgpu_device *adev); 34*837d542aSEvan Quan struct amd_vce_state* amdgpu_get_vce_clock_state(void *handle, u32 idx); 35*837d542aSEvan Quan void amdgpu_pm_print_power_states(struct amdgpu_device *adev); 36*837d542aSEvan Quan void amdgpu_legacy_dpm_compute_clocks(void *handle); 37*837d542aSEvan Quan void amdgpu_dpm_thermal_work_handler(struct work_struct *work); 38*837d542aSEvan Quan #endif 39