1bd95c144SAlex Deucher# SPDX-License-Identifier: MIT 24a488a7aSOded Gabbay# 3b4bc9d95SColin Ian King# Heterogeneous system architecture configuration 44a488a7aSOded Gabbay# 54a488a7aSOded Gabbay 64a488a7aSOded Gabbayconfig HSA_AMD 704d5e276SAmber Lin bool "HSA kernel driver for AMD GPU devices" 8c38402feSTimothy Pearson depends on DRM_AMDGPU && (X86_64 || ARM64 || PPC64) 9d1c234e2SFelix Kuehling imply AMD_IOMMU_V2 if X86_64 1019fef554SFelix Kuehling select HMM_MIRROR 117bbc0b95SRandy Dunlap select MMU_NOTIFIER 1219fef554SFelix Kuehling select DRM_AMDGPU_USERPTR 134a488a7aSOded Gabbay help 144a488a7aSOded Gabbay Enable this if you want to use HSA features on AMD GPU devices. 154ab159d2SFelix Kuehling 164ab159d2SFelix Kuehlingconfig HSA_AMD_SVM 174ab159d2SFelix Kuehling bool "Enable HMM-based shared virtual memory manager" 184ab159d2SFelix Kuehling depends on HSA_AMD && DEVICE_PRIVATE 194ab159d2SFelix Kuehling default y 204ab159d2SFelix Kuehling select HMM_MIRROR 214ab159d2SFelix Kuehling select MMU_NOTIFIER 224ab159d2SFelix Kuehling help 234ab159d2SFelix Kuehling Enable this to use unified memory and managed memory in HIP. This 244ab159d2SFelix Kuehling memory manager supports two modes of operation. One based on 254ab159d2SFelix Kuehling preemptions and one based on page faults. To enable page fault 264ab159d2SFelix Kuehling based memory management on most GFXv9 GPUs, set the module 274ab159d2SFelix Kuehling parameter amdgpu.noretry=0. 28*6fbfc3a2SRamesh Errabolu 29*6fbfc3a2SRamesh Erraboluconfig HSA_AMD_P2P 30*6fbfc3a2SRamesh Errabolu bool "HSA kernel driver support for peer-to-peer for AMD GPU devices" 31*6fbfc3a2SRamesh Errabolu depends on HSA_AMD && PCI_P2PDMA && DMABUF_MOVE_NOTIFY 32*6fbfc3a2SRamesh Errabolu help 33*6fbfc3a2SRamesh Errabolu Enable peer-to-peer (P2P) communication between AMD GPUs over 34*6fbfc3a2SRamesh Errabolu the PCIe bus. This can improve performance of multi-GPU compute 35*6fbfc3a2SRamesh Errabolu applications and libraries by enabling GPUs to access data directly 36*6fbfc3a2SRamesh Errabolu in peer GPUs' memory without intermediate copies in system memory. 37*6fbfc3a2SRamesh Errabolu 38*6fbfc3a2SRamesh Errabolu This P2P feature is only enabled on compatible chipsets, and between 39*6fbfc3a2SRamesh Errabolu GPUs with large memory BARs that expose the entire VRAM in PCIe bus 40*6fbfc3a2SRamesh Errabolu address space within the physical address limits of the GPUs. 41*6fbfc3a2SRamesh Errabolu 42