1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 35 #include "vcn/vcn_4_0_0_offset.h" 36 #include "vcn/vcn_4_0_0_sh_mask.h" 37 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 38 39 #include <drm/drm_drv.h> 40 41 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 42 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 43 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 44 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 45 46 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 47 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 48 49 #define VCN_HARVEST_MMSCH 0 50 51 #define RDECODE_MSG_CREATE 0x00000000 52 #define RDECODE_MESSAGE_CREATE 0x00000001 53 54 static int amdgpu_ih_clientid_vcns[] = { 55 SOC15_IH_CLIENTID_VCN, 56 SOC15_IH_CLIENTID_VCN1 57 }; 58 59 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev); 60 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); 61 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); 62 static int vcn_v4_0_set_powergating_state(void *handle, 63 enum amd_powergating_state state); 64 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, 65 int inst_idx, struct dpg_pause_state *new_state); 66 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 67 68 /** 69 * vcn_v4_0_early_init - set function pointers 70 * 71 * @handle: amdgpu_device pointer 72 * 73 * Set ring and irq function pointers 74 */ 75 static int vcn_v4_0_early_init(void *handle) 76 { 77 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 78 79 if (amdgpu_sriov_vf(adev)) 80 adev->vcn.harvest_config = VCN_HARVEST_MMSCH; 81 82 /* re-use enc ring as unified ring */ 83 adev->vcn.num_enc_rings = 1; 84 85 vcn_v4_0_set_unified_ring_funcs(adev); 86 vcn_v4_0_set_irq_funcs(adev); 87 88 return 0; 89 } 90 91 /** 92 * vcn_v4_0_sw_init - sw init for VCN block 93 * 94 * @handle: amdgpu_device pointer 95 * 96 * Load firmware and sw initialization 97 */ 98 static int vcn_v4_0_sw_init(void *handle) 99 { 100 struct amdgpu_ring *ring; 101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 102 int i, r; 103 104 r = amdgpu_vcn_sw_init(adev); 105 if (r) 106 return r; 107 108 amdgpu_vcn_setup_ucode(adev); 109 110 r = amdgpu_vcn_resume(adev); 111 if (r) 112 return r; 113 114 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 115 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 116 117 if (adev->vcn.harvest_config & (1 << i)) 118 continue; 119 120 atomic_set(&adev->vcn.inst[i].sched_score, 0); 121 122 /* VCN UNIFIED TRAP */ 123 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 124 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 125 if (r) 126 return r; 127 128 ring = &adev->vcn.inst[i].ring_enc[0]; 129 ring->use_doorbell = true; 130 if (amdgpu_sriov_vf(adev)) 131 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1; 132 else 133 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 134 135 sprintf(ring->name, "vcn_unified_%d", i); 136 137 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 138 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 139 if (r) 140 return r; 141 142 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 143 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 144 fw_shared->sq.is_enabled = 1; 145 146 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 147 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 148 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 149 150 if (amdgpu_sriov_vf(adev)) 151 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 152 153 if (amdgpu_vcnfw_log) 154 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 155 } 156 157 if (amdgpu_sriov_vf(adev)) { 158 r = amdgpu_virt_alloc_mm_table(adev); 159 if (r) 160 return r; 161 } 162 163 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 164 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; 165 166 return 0; 167 } 168 169 /** 170 * vcn_v4_0_sw_fini - sw fini for VCN block 171 * 172 * @handle: amdgpu_device pointer 173 * 174 * VCN suspend and free up sw allocation 175 */ 176 static int vcn_v4_0_sw_fini(void *handle) 177 { 178 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 179 int i, r, idx; 180 181 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 182 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 183 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 184 185 if (adev->vcn.harvest_config & (1 << i)) 186 continue; 187 188 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 189 fw_shared->present_flag_0 = 0; 190 fw_shared->sq.is_enabled = 0; 191 } 192 193 drm_dev_exit(idx); 194 } 195 196 if (amdgpu_sriov_vf(adev)) 197 amdgpu_virt_free_mm_table(adev); 198 199 r = amdgpu_vcn_suspend(adev); 200 if (r) 201 return r; 202 203 r = amdgpu_vcn_sw_fini(adev); 204 205 return r; 206 } 207 208 /** 209 * vcn_v4_0_hw_init - start and test VCN block 210 * 211 * @handle: amdgpu_device pointer 212 * 213 * Initialize the hardware, boot up the VCPU and do some testing 214 */ 215 static int vcn_v4_0_hw_init(void *handle) 216 { 217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 218 struct amdgpu_ring *ring; 219 int i, r; 220 221 if (amdgpu_sriov_vf(adev)) { 222 r = vcn_v4_0_start_sriov(adev); 223 if (r) 224 goto done; 225 226 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 227 if (adev->vcn.harvest_config & (1 << i)) 228 continue; 229 230 ring = &adev->vcn.inst[i].ring_enc[0]; 231 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 232 ring->sched.ready = false; 233 ring->no_scheduler = true; 234 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 235 } else { 236 ring->wptr = 0; 237 ring->wptr_old = 0; 238 vcn_v4_0_unified_ring_set_wptr(ring); 239 ring->sched.ready = true; 240 } 241 } 242 } else { 243 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 244 if (adev->vcn.harvest_config & (1 << i)) 245 continue; 246 247 ring = &adev->vcn.inst[i].ring_enc[0]; 248 249 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 250 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 251 252 r = amdgpu_ring_test_helper(ring); 253 if (r) 254 goto done; 255 256 } 257 } 258 259 done: 260 if (!r) 261 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 262 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 263 264 return r; 265 } 266 267 /** 268 * vcn_v4_0_hw_fini - stop the hardware block 269 * 270 * @handle: amdgpu_device pointer 271 * 272 * Stop the VCN block, mark ring as not ready any more 273 */ 274 static int vcn_v4_0_hw_fini(void *handle) 275 { 276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 277 int i; 278 279 cancel_delayed_work_sync(&adev->vcn.idle_work); 280 281 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 282 if (adev->vcn.harvest_config & (1 << i)) 283 continue; 284 if (!amdgpu_sriov_vf(adev)) { 285 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 286 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 287 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 288 vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 289 } 290 } 291 292 } 293 294 return 0; 295 } 296 297 /** 298 * vcn_v4_0_suspend - suspend VCN block 299 * 300 * @handle: amdgpu_device pointer 301 * 302 * HW fini and suspend VCN block 303 */ 304 static int vcn_v4_0_suspend(void *handle) 305 { 306 int r; 307 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 308 309 r = vcn_v4_0_hw_fini(adev); 310 if (r) 311 return r; 312 313 r = amdgpu_vcn_suspend(adev); 314 315 return r; 316 } 317 318 /** 319 * vcn_v4_0_resume - resume VCN block 320 * 321 * @handle: amdgpu_device pointer 322 * 323 * Resume firmware and hw init VCN block 324 */ 325 static int vcn_v4_0_resume(void *handle) 326 { 327 int r; 328 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 329 330 r = amdgpu_vcn_resume(adev); 331 if (r) 332 return r; 333 334 r = vcn_v4_0_hw_init(adev); 335 336 return r; 337 } 338 339 /** 340 * vcn_v4_0_mc_resume - memory controller programming 341 * 342 * @adev: amdgpu_device pointer 343 * @inst: instance number 344 * 345 * Let the VCN memory controller know it's offsets 346 */ 347 static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst) 348 { 349 uint32_t offset, size; 350 const struct common_firmware_header *hdr; 351 352 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 353 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 354 355 /* cache window 0: fw */ 356 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 357 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 358 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 359 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 360 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 361 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 362 offset = 0; 363 } else { 364 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 365 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 366 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 367 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 368 offset = size; 369 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 370 } 371 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 372 373 /* cache window 1: stack */ 374 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 375 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 376 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 377 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 378 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 379 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 380 381 /* cache window 2: context */ 382 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 383 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 384 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 385 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 386 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 387 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 388 389 /* non-cache window */ 390 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 391 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 392 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 393 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 394 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 395 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 396 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 397 } 398 399 /** 400 * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode 401 * 402 * @adev: amdgpu_device pointer 403 * @inst_idx: instance number index 404 * @indirect: indirectly write sram 405 * 406 * Let the VCN memory controller know it's offsets with dpg mode 407 */ 408 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 409 { 410 uint32_t offset, size; 411 const struct common_firmware_header *hdr; 412 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 413 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 414 415 /* cache window 0: fw */ 416 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 417 if (!indirect) { 418 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 419 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 420 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 421 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 422 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 423 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 424 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 425 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 426 } else { 427 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 428 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 429 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 430 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 431 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 432 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 433 } 434 offset = 0; 435 } else { 436 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 437 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 438 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 439 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 440 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 441 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 442 offset = size; 443 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 444 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 445 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 446 } 447 448 if (!indirect) 449 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 450 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 451 else 452 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 453 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 454 455 /* cache window 1: stack */ 456 if (!indirect) { 457 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 458 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 459 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 460 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 461 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 462 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 463 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 464 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 465 } else { 466 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 467 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 468 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 469 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 470 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 471 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 472 } 473 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 474 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 475 476 /* cache window 2: context */ 477 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 478 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 479 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 480 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 481 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 482 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 484 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 485 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 486 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 487 488 /* non-cache window */ 489 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 490 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 491 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 493 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 494 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 496 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 498 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 499 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 500 501 /* VCN global tiling registers */ 502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 503 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 504 } 505 506 /** 507 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating 508 * 509 * @adev: amdgpu_device pointer 510 * @inst: instance number 511 * 512 * Disable static power gating for VCN block 513 */ 514 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 515 { 516 uint32_t data = 0; 517 518 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 519 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 520 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 521 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 522 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 523 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 524 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 525 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 526 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 527 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 528 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 529 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 530 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 531 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 532 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 533 534 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 535 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, 536 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 537 } else { 538 uint32_t value; 539 540 value = (inst) ? 0x2200800 : 0; 541 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 542 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 543 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 544 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 545 | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 546 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 547 | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 548 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 549 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 550 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 551 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 552 | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 553 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 554 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 555 556 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 557 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF); 558 } 559 560 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 561 data &= ~0x103; 562 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 563 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 564 UVD_POWER_STATUS__UVD_PG_EN_MASK; 565 566 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 567 568 return; 569 } 570 571 /** 572 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating 573 * 574 * @adev: amdgpu_device pointer 575 * @inst: instance number 576 * 577 * Enable static power gating for VCN block 578 */ 579 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 580 { 581 uint32_t data; 582 583 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 584 /* Before power off, this indicator has to be turned on */ 585 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 586 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 587 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 588 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 589 590 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 591 | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 592 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 593 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 594 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 595 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 596 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 597 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 598 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 599 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 600 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 601 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 602 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 603 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 604 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 605 606 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 607 | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 608 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 609 | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 610 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 611 | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 612 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 613 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 614 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 615 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 616 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 617 | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 618 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 619 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 620 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 621 } 622 623 return; 624 } 625 626 /** 627 * vcn_v4_0_disable_clock_gating - disable VCN clock gating 628 * 629 * @adev: amdgpu_device pointer 630 * @inst: instance number 631 * 632 * Disable clock gating for VCN block 633 */ 634 static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 635 { 636 uint32_t data; 637 638 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 639 return; 640 641 /* VCN disable CGC */ 642 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 643 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 644 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 645 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 646 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 647 648 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 649 data &= ~(UVD_CGC_GATE__SYS_MASK 650 | UVD_CGC_GATE__UDEC_MASK 651 | UVD_CGC_GATE__MPEG2_MASK 652 | UVD_CGC_GATE__REGS_MASK 653 | UVD_CGC_GATE__RBC_MASK 654 | UVD_CGC_GATE__LMI_MC_MASK 655 | UVD_CGC_GATE__LMI_UMC_MASK 656 | UVD_CGC_GATE__IDCT_MASK 657 | UVD_CGC_GATE__MPRD_MASK 658 | UVD_CGC_GATE__MPC_MASK 659 | UVD_CGC_GATE__LBSI_MASK 660 | UVD_CGC_GATE__LRBBM_MASK 661 | UVD_CGC_GATE__UDEC_RE_MASK 662 | UVD_CGC_GATE__UDEC_CM_MASK 663 | UVD_CGC_GATE__UDEC_IT_MASK 664 | UVD_CGC_GATE__UDEC_DB_MASK 665 | UVD_CGC_GATE__UDEC_MP_MASK 666 | UVD_CGC_GATE__WCB_MASK 667 | UVD_CGC_GATE__VCPU_MASK 668 | UVD_CGC_GATE__MMSCH_MASK); 669 670 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 671 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 672 673 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 674 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 675 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 676 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 677 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 678 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 679 | UVD_CGC_CTRL__SYS_MODE_MASK 680 | UVD_CGC_CTRL__UDEC_MODE_MASK 681 | UVD_CGC_CTRL__MPEG2_MODE_MASK 682 | UVD_CGC_CTRL__REGS_MODE_MASK 683 | UVD_CGC_CTRL__RBC_MODE_MASK 684 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 685 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 686 | UVD_CGC_CTRL__IDCT_MODE_MASK 687 | UVD_CGC_CTRL__MPRD_MODE_MASK 688 | UVD_CGC_CTRL__MPC_MODE_MASK 689 | UVD_CGC_CTRL__LBSI_MODE_MASK 690 | UVD_CGC_CTRL__LRBBM_MODE_MASK 691 | UVD_CGC_CTRL__WCB_MODE_MASK 692 | UVD_CGC_CTRL__VCPU_MODE_MASK 693 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 694 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 695 696 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 697 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 698 | UVD_SUVD_CGC_GATE__SIT_MASK 699 | UVD_SUVD_CGC_GATE__SMP_MASK 700 | UVD_SUVD_CGC_GATE__SCM_MASK 701 | UVD_SUVD_CGC_GATE__SDB_MASK 702 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 703 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 704 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 705 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 706 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 707 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 708 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 709 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 710 | UVD_SUVD_CGC_GATE__SCLR_MASK 711 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 712 | UVD_SUVD_CGC_GATE__ENT_MASK 713 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 714 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 715 | UVD_SUVD_CGC_GATE__SITE_MASK 716 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 717 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 718 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 719 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 720 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 721 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 722 723 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 724 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 725 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 726 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 727 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 728 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 729 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 730 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 731 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 732 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 733 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 734 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 735 } 736 737 /** 738 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 739 * 740 * @adev: amdgpu_device pointer 741 * @sram_sel: sram select 742 * @inst_idx: instance number index 743 * @indirect: indirectly write sram 744 * 745 * Disable clock gating for VCN block with dpg mode 746 */ 747 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 748 int inst_idx, uint8_t indirect) 749 { 750 uint32_t reg_data = 0; 751 752 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 753 return; 754 755 /* enable sw clock gating control */ 756 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 757 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 758 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 759 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 760 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 761 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 762 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 763 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 764 UVD_CGC_CTRL__SYS_MODE_MASK | 765 UVD_CGC_CTRL__UDEC_MODE_MASK | 766 UVD_CGC_CTRL__MPEG2_MODE_MASK | 767 UVD_CGC_CTRL__REGS_MODE_MASK | 768 UVD_CGC_CTRL__RBC_MODE_MASK | 769 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 770 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 771 UVD_CGC_CTRL__IDCT_MODE_MASK | 772 UVD_CGC_CTRL__MPRD_MODE_MASK | 773 UVD_CGC_CTRL__MPC_MODE_MASK | 774 UVD_CGC_CTRL__LBSI_MODE_MASK | 775 UVD_CGC_CTRL__LRBBM_MODE_MASK | 776 UVD_CGC_CTRL__WCB_MODE_MASK | 777 UVD_CGC_CTRL__VCPU_MODE_MASK); 778 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 779 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 780 781 /* turn off clock gating */ 782 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 783 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 784 785 /* turn on SUVD clock gating */ 786 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 787 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 788 789 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 790 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 791 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 792 } 793 794 /** 795 * vcn_v4_0_enable_clock_gating - enable VCN clock gating 796 * 797 * @adev: amdgpu_device pointer 798 * @inst: instance number 799 * 800 * Enable clock gating for VCN block 801 */ 802 static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 803 { 804 uint32_t data; 805 806 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 807 return; 808 809 /* enable VCN CGC */ 810 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 811 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 812 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 813 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 814 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 815 816 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 817 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 818 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 819 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 820 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 821 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 822 | UVD_CGC_CTRL__SYS_MODE_MASK 823 | UVD_CGC_CTRL__UDEC_MODE_MASK 824 | UVD_CGC_CTRL__MPEG2_MODE_MASK 825 | UVD_CGC_CTRL__REGS_MODE_MASK 826 | UVD_CGC_CTRL__RBC_MODE_MASK 827 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 828 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 829 | UVD_CGC_CTRL__IDCT_MODE_MASK 830 | UVD_CGC_CTRL__MPRD_MODE_MASK 831 | UVD_CGC_CTRL__MPC_MODE_MASK 832 | UVD_CGC_CTRL__LBSI_MODE_MASK 833 | UVD_CGC_CTRL__LRBBM_MODE_MASK 834 | UVD_CGC_CTRL__WCB_MODE_MASK 835 | UVD_CGC_CTRL__VCPU_MODE_MASK 836 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 837 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 838 839 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 840 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 841 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 842 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 843 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 844 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 845 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 846 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 847 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 848 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 849 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 850 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 851 852 return; 853 } 854 855 /** 856 * vcn_v4_0_start_dpg_mode - VCN start with dpg mode 857 * 858 * @adev: amdgpu_device pointer 859 * @inst_idx: instance number index 860 * @indirect: indirectly write sram 861 * 862 * Start VCN block with dpg mode 863 */ 864 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 865 { 866 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 867 struct amdgpu_ring *ring; 868 uint32_t tmp; 869 870 /* disable register anti-hang mechanism */ 871 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 872 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 873 /* enable dynamic power gating mode */ 874 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 875 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 876 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 877 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 878 879 if (indirect) 880 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 881 882 /* enable clock gating */ 883 vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 884 885 /* enable VCPU clock */ 886 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 887 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 888 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 889 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 890 891 /* disable master interupt */ 892 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 893 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 894 895 /* setup regUVD_LMI_CTRL */ 896 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 897 UVD_LMI_CTRL__REQ_MODE_MASK | 898 UVD_LMI_CTRL__CRC_RESET_MASK | 899 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 900 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 901 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 902 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 903 0x00100000L); 904 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 905 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 906 907 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 908 VCN, inst_idx, regUVD_MPC_CNTL), 909 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 910 911 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 912 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 913 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 914 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 915 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 916 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 917 918 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 919 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 920 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 921 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 922 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 923 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 924 925 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 926 VCN, inst_idx, regUVD_MPC_SET_MUX), 927 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 928 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 929 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 930 931 vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 932 933 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 934 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 935 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 936 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 937 938 /* enable LMI MC and UMC channels */ 939 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 940 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 941 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 942 943 /* enable master interrupt */ 944 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 945 VCN, inst_idx, regUVD_MASTINT_EN), 946 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 947 948 949 if (indirect) 950 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 951 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 952 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 953 954 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 955 956 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 957 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 958 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 959 960 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 961 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 962 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 963 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 964 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 965 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 966 967 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 968 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 969 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 970 971 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 972 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 973 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 974 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 975 976 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 977 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 978 VCN_RB1_DB_CTRL__EN_MASK); 979 980 return 0; 981 } 982 983 984 /** 985 * vcn_v4_0_start - VCN start 986 * 987 * @adev: amdgpu_device pointer 988 * 989 * Start VCN block 990 */ 991 static int vcn_v4_0_start(struct amdgpu_device *adev) 992 { 993 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 994 struct amdgpu_ring *ring; 995 uint32_t tmp; 996 int i, j, k, r; 997 998 if (adev->pm.dpm_enabled) 999 amdgpu_dpm_enable_uvd(adev, true); 1000 1001 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1002 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1003 1004 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1005 r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1006 continue; 1007 } 1008 1009 /* disable VCN power gating */ 1010 vcn_v4_0_disable_static_power_gating(adev, i); 1011 1012 /* set VCN status busy */ 1013 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1014 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1015 1016 /*SW clock gating */ 1017 vcn_v4_0_disable_clock_gating(adev, i); 1018 1019 /* enable VCPU clock */ 1020 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1021 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1022 1023 /* disable master interrupt */ 1024 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1025 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1026 1027 /* enable LMI MC and UMC channels */ 1028 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1029 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1030 1031 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1032 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1033 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1034 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1035 1036 /* setup regUVD_LMI_CTRL */ 1037 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1038 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1039 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1040 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1041 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1042 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1043 1044 /* setup regUVD_MPC_CNTL */ 1045 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1046 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1047 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1048 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1049 1050 /* setup UVD_MPC_SET_MUXA0 */ 1051 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1052 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1053 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1054 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1055 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1056 1057 /* setup UVD_MPC_SET_MUXB0 */ 1058 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1059 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1060 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1061 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1062 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1063 1064 /* setup UVD_MPC_SET_MUX */ 1065 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1066 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1067 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1068 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1069 1070 vcn_v4_0_mc_resume(adev, i); 1071 1072 /* VCN global tiling registers */ 1073 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1074 adev->gfx.config.gb_addr_config); 1075 1076 /* unblock VCPU register access */ 1077 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1078 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1079 1080 /* release VCPU reset to boot */ 1081 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1082 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1083 1084 for (j = 0; j < 10; ++j) { 1085 uint32_t status; 1086 1087 for (k = 0; k < 100; ++k) { 1088 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1089 if (status & 2) 1090 break; 1091 mdelay(10); 1092 if (amdgpu_emu_mode==1) 1093 msleep(1); 1094 } 1095 1096 if (amdgpu_emu_mode==1) { 1097 r = -1; 1098 if (status & 2) { 1099 r = 0; 1100 break; 1101 } 1102 } else { 1103 r = 0; 1104 if (status & 2) 1105 break; 1106 1107 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 1108 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1109 UVD_VCPU_CNTL__BLK_RST_MASK, 1110 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1111 mdelay(10); 1112 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1113 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1114 1115 mdelay(10); 1116 r = -1; 1117 } 1118 } 1119 1120 if (r) { 1121 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1122 return r; 1123 } 1124 1125 /* enable master interrupt */ 1126 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1127 UVD_MASTINT_EN__VCPU_EN_MASK, 1128 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1129 1130 /* clear the busy bit of VCN_STATUS */ 1131 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1132 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1133 1134 ring = &adev->vcn.inst[i].ring_enc[0]; 1135 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1136 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1137 VCN_RB1_DB_CTRL__EN_MASK); 1138 1139 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1140 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1141 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1142 1143 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1144 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1145 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1146 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1147 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1148 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1149 1150 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1151 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1152 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1153 1154 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1155 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1156 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1157 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1158 } 1159 1160 return 0; 1161 } 1162 1163 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev) 1164 { 1165 int i; 1166 struct amdgpu_ring *ring_enc; 1167 uint64_t cache_addr; 1168 uint64_t rb_enc_addr; 1169 uint64_t ctx_addr; 1170 uint32_t param, resp, expected; 1171 uint32_t offset, cache_size; 1172 uint32_t tmp, timeout; 1173 1174 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1175 uint32_t *table_loc; 1176 uint32_t table_size; 1177 uint32_t size, size_dw; 1178 uint32_t init_status; 1179 uint32_t enabled_vcn; 1180 1181 struct mmsch_v4_0_cmd_direct_write 1182 direct_wt = { {0} }; 1183 struct mmsch_v4_0_cmd_direct_read_modify_write 1184 direct_rd_mod_wt = { {0} }; 1185 struct mmsch_v4_0_cmd_end end = { {0} }; 1186 struct mmsch_v4_0_init_header header; 1187 1188 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1189 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1190 1191 direct_wt.cmd_header.command_type = 1192 MMSCH_COMMAND__DIRECT_REG_WRITE; 1193 direct_rd_mod_wt.cmd_header.command_type = 1194 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1195 end.cmd_header.command_type = 1196 MMSCH_COMMAND__END; 1197 1198 header.version = MMSCH_VERSION; 1199 header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2; 1200 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1201 header.inst[i].init_status = 0; 1202 header.inst[i].table_offset = 0; 1203 header.inst[i].table_size = 0; 1204 } 1205 1206 table_loc = (uint32_t *)table->cpu_addr; 1207 table_loc += header.total_size; 1208 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1209 if (adev->vcn.harvest_config & (1 << i)) 1210 continue; 1211 1212 table_size = 0; 1213 1214 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1215 regUVD_STATUS), 1216 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1217 1218 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1219 1220 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1221 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1222 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1223 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1224 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1225 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1226 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1227 offset = 0; 1228 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1229 regUVD_VCPU_CACHE_OFFSET0), 1230 0); 1231 } else { 1232 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1233 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1234 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1235 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1236 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1237 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1238 offset = cache_size; 1239 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1240 regUVD_VCPU_CACHE_OFFSET0), 1241 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1242 } 1243 1244 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1245 regUVD_VCPU_CACHE_SIZE0), 1246 cache_size); 1247 1248 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1249 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1250 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1251 lower_32_bits(cache_addr)); 1252 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1253 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1254 upper_32_bits(cache_addr)); 1255 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1256 regUVD_VCPU_CACHE_OFFSET1), 1257 0); 1258 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1259 regUVD_VCPU_CACHE_SIZE1), 1260 AMDGPU_VCN_STACK_SIZE); 1261 1262 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1263 AMDGPU_VCN_STACK_SIZE; 1264 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1265 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1266 lower_32_bits(cache_addr)); 1267 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1268 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1269 upper_32_bits(cache_addr)); 1270 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1271 regUVD_VCPU_CACHE_OFFSET2), 1272 0); 1273 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1274 regUVD_VCPU_CACHE_SIZE2), 1275 AMDGPU_VCN_CONTEXT_SIZE); 1276 1277 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1278 rb_setup = &fw_shared->rb_setup; 1279 1280 ring_enc = &adev->vcn.inst[i].ring_enc[0]; 1281 ring_enc->wptr = 0; 1282 rb_enc_addr = ring_enc->gpu_addr; 1283 1284 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1285 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1286 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1287 rb_setup->rb_size = ring_enc->ring_size / 4; 1288 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1289 1290 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1291 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1292 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1293 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1294 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1295 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1296 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1297 regUVD_VCPU_NONCACHE_SIZE0), 1298 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1299 1300 /* add end packet */ 1301 MMSCH_V4_0_INSERT_END(); 1302 1303 /* refine header */ 1304 header.inst[i].init_status = 0; 1305 header.inst[i].table_offset = header.total_size; 1306 header.inst[i].table_size = table_size; 1307 header.total_size += table_size; 1308 } 1309 1310 /* Update init table header in memory */ 1311 size = sizeof(struct mmsch_v4_0_init_header); 1312 table_loc = (uint32_t *)table->cpu_addr; 1313 memcpy((void *)table_loc, &header, size); 1314 1315 /* message MMSCH (in VCN[0]) to initialize this client 1316 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1317 * of memory descriptor location 1318 */ 1319 ctx_addr = table->gpu_addr; 1320 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1321 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1322 1323 /* 2, update vmid of descriptor */ 1324 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 1325 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1326 /* use domain0 for MM scheduler */ 1327 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1328 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 1329 1330 /* 3, notify mmsch about the size of this descriptor */ 1331 size = header.total_size; 1332 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 1333 1334 /* 4, set resp to zero */ 1335 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 1336 1337 /* 5, kick off the initialization and wait until 1338 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1339 */ 1340 param = 0x00000001; 1341 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 1342 tmp = 0; 1343 timeout = 1000; 1344 resp = 0; 1345 expected = MMSCH_VF_MAILBOX_RESP__OK; 1346 while (resp != expected) { 1347 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 1348 if (resp != 0) 1349 break; 1350 1351 udelay(10); 1352 tmp = tmp + 10; 1353 if (tmp >= timeout) { 1354 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1355 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1356 "(expected=0x%08x, readback=0x%08x)\n", 1357 tmp, expected, resp); 1358 return -EBUSY; 1359 } 1360 } 1361 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1362 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status; 1363 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1364 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) 1365 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1366 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1367 1368 return 0; 1369 } 1370 1371 /** 1372 * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode 1373 * 1374 * @adev: amdgpu_device pointer 1375 * @inst_idx: instance number index 1376 * 1377 * Stop VCN block with dpg mode 1378 */ 1379 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1380 { 1381 uint32_t tmp; 1382 1383 /* Wait for power status to be 1 */ 1384 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1385 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1386 1387 /* wait for read ptr to be equal to write ptr */ 1388 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1389 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1390 1391 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1392 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1393 1394 /* disable dynamic power gating mode */ 1395 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1396 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1397 } 1398 1399 /** 1400 * vcn_v4_0_stop - VCN stop 1401 * 1402 * @adev: amdgpu_device pointer 1403 * 1404 * Stop VCN block 1405 */ 1406 static int vcn_v4_0_stop(struct amdgpu_device *adev) 1407 { 1408 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1409 uint32_t tmp; 1410 int i, r = 0; 1411 1412 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1413 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1414 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1415 1416 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1417 vcn_v4_0_stop_dpg_mode(adev, i); 1418 continue; 1419 } 1420 1421 /* wait for vcn idle */ 1422 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1423 if (r) 1424 return r; 1425 1426 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1427 UVD_LMI_STATUS__READ_CLEAN_MASK | 1428 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1429 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1430 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1431 if (r) 1432 return r; 1433 1434 /* disable LMI UMC channel */ 1435 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1436 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1437 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1438 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1439 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1440 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1441 if (r) 1442 return r; 1443 1444 /* block VCPU register access */ 1445 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1446 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1447 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1448 1449 /* reset VCPU */ 1450 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1451 UVD_VCPU_CNTL__BLK_RST_MASK, 1452 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1453 1454 /* disable VCPU clock */ 1455 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1456 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1457 1458 /* apply soft reset */ 1459 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1460 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1461 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1462 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1463 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1464 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1465 1466 /* clear status */ 1467 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1468 1469 /* apply HW clock gating */ 1470 vcn_v4_0_enable_clock_gating(adev, i); 1471 1472 /* enable VCN power gating */ 1473 vcn_v4_0_enable_static_power_gating(adev, i); 1474 } 1475 1476 if (adev->pm.dpm_enabled) 1477 amdgpu_dpm_enable_uvd(adev, false); 1478 1479 return 0; 1480 } 1481 1482 /** 1483 * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode 1484 * 1485 * @adev: amdgpu_device pointer 1486 * @inst_idx: instance number index 1487 * @new_state: pause state 1488 * 1489 * Pause dpg mode for VCN block 1490 */ 1491 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1492 struct dpg_pause_state *new_state) 1493 { 1494 uint32_t reg_data = 0; 1495 int ret_code; 1496 1497 /* pause/unpause if state is changed */ 1498 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1499 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1500 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1501 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1502 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1503 1504 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1505 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1506 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1507 1508 if (!ret_code) { 1509 /* pause DPG */ 1510 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1511 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1512 1513 /* wait for ACK */ 1514 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1515 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1516 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1517 1518 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1519 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1520 } 1521 } else { 1522 /* unpause dpg, no need to wait */ 1523 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1524 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1525 } 1526 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1527 } 1528 1529 return 0; 1530 } 1531 1532 /** 1533 * vcn_v4_0_unified_ring_get_rptr - get unified read pointer 1534 * 1535 * @ring: amdgpu_ring pointer 1536 * 1537 * Returns the current hardware unified read pointer 1538 */ 1539 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1540 { 1541 struct amdgpu_device *adev = ring->adev; 1542 1543 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1544 DRM_ERROR("wrong ring id is identified in %s", __func__); 1545 1546 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1547 } 1548 1549 /** 1550 * vcn_v4_0_unified_ring_get_wptr - get unified write pointer 1551 * 1552 * @ring: amdgpu_ring pointer 1553 * 1554 * Returns the current hardware unified write pointer 1555 */ 1556 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1557 { 1558 struct amdgpu_device *adev = ring->adev; 1559 1560 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1561 DRM_ERROR("wrong ring id is identified in %s", __func__); 1562 1563 if (ring->use_doorbell) 1564 return *ring->wptr_cpu_addr; 1565 else 1566 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1567 } 1568 1569 /** 1570 * vcn_v4_0_unified_ring_set_wptr - set enc write pointer 1571 * 1572 * @ring: amdgpu_ring pointer 1573 * 1574 * Commits the enc write pointer to the hardware 1575 */ 1576 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1577 { 1578 struct amdgpu_device *adev = ring->adev; 1579 1580 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1581 DRM_ERROR("wrong ring id is identified in %s", __func__); 1582 1583 if (ring->use_doorbell) { 1584 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1585 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1586 } else { 1587 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1588 } 1589 } 1590 1591 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, 1592 struct amdgpu_job *job) 1593 { 1594 struct drm_gpu_scheduler **scheds; 1595 1596 /* The create msg must be in the first IB submitted */ 1597 if (atomic_read(&job->base.entity->fence_seq)) 1598 return -EINVAL; 1599 1600 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] 1601 [AMDGPU_RING_PRIO_0].sched; 1602 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1603 return 0; 1604 } 1605 1606 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1607 uint64_t addr) 1608 { 1609 struct ttm_operation_ctx ctx = { false, false }; 1610 struct amdgpu_bo_va_mapping *map; 1611 uint32_t *msg, num_buffers; 1612 struct amdgpu_bo *bo; 1613 uint64_t start, end; 1614 unsigned int i; 1615 void *ptr; 1616 int r; 1617 1618 addr &= AMDGPU_GMC_HOLE_MASK; 1619 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1620 if (r) { 1621 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 1622 return r; 1623 } 1624 1625 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1626 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1627 if (addr & 0x7) { 1628 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1629 return -EINVAL; 1630 } 1631 1632 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1633 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1634 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1635 if (r) { 1636 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1637 return r; 1638 } 1639 1640 r = amdgpu_bo_kmap(bo, &ptr); 1641 if (r) { 1642 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1643 return r; 1644 } 1645 1646 msg = ptr + addr - start; 1647 1648 /* Check length */ 1649 if (msg[1] > end - addr) { 1650 r = -EINVAL; 1651 goto out; 1652 } 1653 1654 if (msg[3] != RDECODE_MSG_CREATE) 1655 goto out; 1656 1657 num_buffers = msg[2]; 1658 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1659 uint32_t offset, size, *create; 1660 1661 if (msg[0] != RDECODE_MESSAGE_CREATE) 1662 continue; 1663 1664 offset = msg[1]; 1665 size = msg[2]; 1666 1667 if (offset + size > end) { 1668 r = -EINVAL; 1669 goto out; 1670 } 1671 1672 create = ptr + addr + offset - start; 1673 1674 /* H246, HEVC and VP9 can run on any instance */ 1675 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1676 continue; 1677 1678 r = vcn_v4_0_limit_sched(p, job); 1679 if (r) 1680 goto out; 1681 } 1682 1683 out: 1684 amdgpu_bo_kunmap(bo); 1685 return r; 1686 } 1687 1688 #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) 1689 1690 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1691 struct amdgpu_job *job, 1692 struct amdgpu_ib *ib) 1693 { 1694 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1695 struct amdgpu_vcn_decode_buffer *decode_buffer; 1696 uint64_t addr; 1697 uint32_t val; 1698 1699 /* The first instance can decode anything */ 1700 if (!ring->me) 1701 return 0; 1702 1703 /* unified queue ib header has 8 double words. */ 1704 if (ib->length_dw < 8) 1705 return 0; 1706 1707 val = amdgpu_ib_get_value(ib, 6); //RADEON_VCN_ENGINE_TYPE 1708 if (val != RADEON_VCN_ENGINE_TYPE_DECODE) 1709 return 0; 1710 1711 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[10]; 1712 1713 if (!(decode_buffer->valid_buf_flag & 0x1)) 1714 return 0; 1715 1716 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1717 decode_buffer->msg_buffer_address_lo; 1718 return vcn_v4_0_dec_msg(p, job, addr); 1719 } 1720 1721 static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { 1722 .type = AMDGPU_RING_TYPE_VCN_ENC, 1723 .align_mask = 0x3f, 1724 .nop = VCN_ENC_CMD_NO_OP, 1725 .vmhub = AMDGPU_MMHUB_0, 1726 .get_rptr = vcn_v4_0_unified_ring_get_rptr, 1727 .get_wptr = vcn_v4_0_unified_ring_get_wptr, 1728 .set_wptr = vcn_v4_0_unified_ring_set_wptr, 1729 .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place, 1730 .emit_frame_size = 1731 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1732 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1733 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1734 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1735 1, /* vcn_v2_0_enc_ring_insert_end */ 1736 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1737 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1738 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1739 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1740 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1741 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1742 .insert_nop = amdgpu_ring_insert_nop, 1743 .insert_end = vcn_v2_0_enc_ring_insert_end, 1744 .pad_ib = amdgpu_ring_generic_pad_ib, 1745 .begin_use = amdgpu_vcn_ring_begin_use, 1746 .end_use = amdgpu_vcn_ring_end_use, 1747 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1748 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1749 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1750 }; 1751 1752 /** 1753 * vcn_v4_0_set_unified_ring_funcs - set unified ring functions 1754 * 1755 * @adev: amdgpu_device pointer 1756 * 1757 * Set unified ring functions 1758 */ 1759 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1760 { 1761 int i; 1762 1763 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1764 if (adev->vcn.harvest_config & (1 << i)) 1765 continue; 1766 1767 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_unified_ring_vm_funcs; 1768 adev->vcn.inst[i].ring_enc[0].me = i; 1769 1770 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i); 1771 } 1772 } 1773 1774 /** 1775 * vcn_v4_0_is_idle - check VCN block is idle 1776 * 1777 * @handle: amdgpu_device pointer 1778 * 1779 * Check whether VCN block is idle 1780 */ 1781 static bool vcn_v4_0_is_idle(void *handle) 1782 { 1783 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1784 int i, ret = 1; 1785 1786 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1787 if (adev->vcn.harvest_config & (1 << i)) 1788 continue; 1789 1790 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1791 } 1792 1793 return ret; 1794 } 1795 1796 /** 1797 * vcn_v4_0_wait_for_idle - wait for VCN block idle 1798 * 1799 * @handle: amdgpu_device pointer 1800 * 1801 * Wait for VCN block idle 1802 */ 1803 static int vcn_v4_0_wait_for_idle(void *handle) 1804 { 1805 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1806 int i, ret = 0; 1807 1808 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1809 if (adev->vcn.harvest_config & (1 << i)) 1810 continue; 1811 1812 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1813 UVD_STATUS__IDLE); 1814 if (ret) 1815 return ret; 1816 } 1817 1818 return ret; 1819 } 1820 1821 /** 1822 * vcn_v4_0_set_clockgating_state - set VCN block clockgating state 1823 * 1824 * @handle: amdgpu_device pointer 1825 * @state: clock gating state 1826 * 1827 * Set VCN block clockgating state 1828 */ 1829 static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) 1830 { 1831 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1832 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1833 int i; 1834 1835 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1836 if (adev->vcn.harvest_config & (1 << i)) 1837 continue; 1838 1839 if (enable) { 1840 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1841 return -EBUSY; 1842 vcn_v4_0_enable_clock_gating(adev, i); 1843 } else { 1844 vcn_v4_0_disable_clock_gating(adev, i); 1845 } 1846 } 1847 1848 return 0; 1849 } 1850 1851 /** 1852 * vcn_v4_0_set_powergating_state - set VCN block powergating state 1853 * 1854 * @handle: amdgpu_device pointer 1855 * @state: power gating state 1856 * 1857 * Set VCN block powergating state 1858 */ 1859 static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state) 1860 { 1861 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1862 int ret; 1863 1864 /* for SRIOV, guest should not control VCN Power-gating 1865 * MMSCH FW should control Power-gating and clock-gating 1866 * guest should avoid touching CGC and PG 1867 */ 1868 if (amdgpu_sriov_vf(adev)) { 1869 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1870 return 0; 1871 } 1872 1873 if(state == adev->vcn.cur_state) 1874 return 0; 1875 1876 if (state == AMD_PG_STATE_GATE) 1877 ret = vcn_v4_0_stop(adev); 1878 else 1879 ret = vcn_v4_0_start(adev); 1880 1881 if(!ret) 1882 adev->vcn.cur_state = state; 1883 1884 return ret; 1885 } 1886 1887 /** 1888 * vcn_v4_0_set_interrupt_state - set VCN block interrupt state 1889 * 1890 * @adev: amdgpu_device pointer 1891 * @source: interrupt sources 1892 * @type: interrupt types 1893 * @state: interrupt states 1894 * 1895 * Set VCN block interrupt state 1896 */ 1897 static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1898 unsigned type, enum amdgpu_interrupt_state state) 1899 { 1900 return 0; 1901 } 1902 1903 /** 1904 * vcn_v4_0_process_interrupt - process VCN block interrupt 1905 * 1906 * @adev: amdgpu_device pointer 1907 * @source: interrupt sources 1908 * @entry: interrupt entry from clients and sources 1909 * 1910 * Process VCN block interrupt 1911 */ 1912 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1913 struct amdgpu_iv_entry *entry) 1914 { 1915 uint32_t ip_instance; 1916 1917 switch (entry->client_id) { 1918 case SOC15_IH_CLIENTID_VCN: 1919 ip_instance = 0; 1920 break; 1921 case SOC15_IH_CLIENTID_VCN1: 1922 ip_instance = 1; 1923 break; 1924 default: 1925 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1926 return 0; 1927 } 1928 1929 DRM_DEBUG("IH: VCN TRAP\n"); 1930 1931 switch (entry->src_id) { 1932 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1933 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1934 break; 1935 default: 1936 DRM_ERROR("Unhandled interrupt: %d %d\n", 1937 entry->src_id, entry->src_data[0]); 1938 break; 1939 } 1940 1941 return 0; 1942 } 1943 1944 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { 1945 .set = vcn_v4_0_set_interrupt_state, 1946 .process = vcn_v4_0_process_interrupt, 1947 }; 1948 1949 /** 1950 * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions 1951 * 1952 * @adev: amdgpu_device pointer 1953 * 1954 * Set VCN block interrupt irq functions 1955 */ 1956 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1957 { 1958 int i; 1959 1960 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1961 if (adev->vcn.harvest_config & (1 << i)) 1962 continue; 1963 1964 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1965 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs; 1966 } 1967 } 1968 1969 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { 1970 .name = "vcn_v4_0", 1971 .early_init = vcn_v4_0_early_init, 1972 .late_init = NULL, 1973 .sw_init = vcn_v4_0_sw_init, 1974 .sw_fini = vcn_v4_0_sw_fini, 1975 .hw_init = vcn_v4_0_hw_init, 1976 .hw_fini = vcn_v4_0_hw_fini, 1977 .suspend = vcn_v4_0_suspend, 1978 .resume = vcn_v4_0_resume, 1979 .is_idle = vcn_v4_0_is_idle, 1980 .wait_for_idle = vcn_v4_0_wait_for_idle, 1981 .check_soft_reset = NULL, 1982 .pre_soft_reset = NULL, 1983 .soft_reset = NULL, 1984 .post_soft_reset = NULL, 1985 .set_clockgating_state = vcn_v4_0_set_clockgating_state, 1986 .set_powergating_state = vcn_v4_0_set_powergating_state, 1987 }; 1988 1989 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = 1990 { 1991 .type = AMD_IP_BLOCK_TYPE_VCN, 1992 .major = 4, 1993 .minor = 0, 1994 .rev = 0, 1995 .funcs = &vcn_v4_0_ip_funcs, 1996 }; 1997