1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/vmalloc.h> 26 #include <drm/drm_drv.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ras.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v11_0.h" 34 35 #include "mp/mp_11_0_offset.h" 36 #include "mp/mp_11_0_sh_mask.h" 37 #include "gc/gc_9_0_offset.h" 38 #include "sdma0/sdma0_4_0_offset.h" 39 #include "nbio/nbio_7_4_offset.h" 40 41 #include "oss/osssys_4_0_offset.h" 42 #include "oss/osssys_4_0_sh_mask.h" 43 44 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 46 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 49 MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 51 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 52 MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); 53 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 54 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 55 MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/navi12_cap.bin"); 57 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 58 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 59 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin"); 61 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin"); 62 MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin"); 63 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin"); 64 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin"); 65 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin"); 66 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin"); 67 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin"); 68 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin"); 69 MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin"); 70 MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin"); 71 72 /* address block */ 73 #define smnMP1_FIRMWARE_FLAGS 0x3010024 74 /* navi10 reg offset define */ 75 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 76 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 77 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 78 #define mmSDMA0_UCODE_DATA_NV10 0x5881 79 /* memory training timeout define */ 80 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 81 82 /* For large FW files the time to complete can be very long */ 83 #define USBC_PD_POLLING_LIMIT_S 240 84 85 /* Read USB-PD from LFB */ 86 #define GFX_CMD_USB_PD_USE_LFB 0x480 87 88 static int psp_v11_0_init_microcode(struct psp_context *psp) 89 { 90 struct amdgpu_device *adev = psp->adev; 91 const char *chip_name; 92 char ucode_prefix[30]; 93 int err = 0; 94 95 DRM_DEBUG("\n"); 96 97 switch (adev->ip_versions[MP0_HWIP][0]) { 98 case IP_VERSION(11, 0, 2): 99 chip_name = "vega20"; 100 break; 101 case IP_VERSION(11, 0, 0): 102 chip_name = "navi10"; 103 break; 104 case IP_VERSION(11, 0, 5): 105 chip_name = "navi14"; 106 break; 107 case IP_VERSION(11, 0, 9): 108 chip_name = "navi12"; 109 break; 110 case IP_VERSION(11, 0, 4): 111 chip_name = "arcturus"; 112 break; 113 case IP_VERSION(11, 0, 7): 114 chip_name = "sienna_cichlid"; 115 break; 116 case IP_VERSION(11, 0, 11): 117 chip_name = "navy_flounder"; 118 break; 119 case IP_VERSION(11, 5, 0): 120 chip_name = "vangogh"; 121 break; 122 case IP_VERSION(11, 0, 12): 123 chip_name = "dimgrey_cavefish"; 124 break; 125 case IP_VERSION(11, 0, 13): 126 chip_name = "beige_goby"; 127 break; 128 default: 129 BUG(); 130 } 131 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 132 133 switch (adev->ip_versions[MP0_HWIP][0]) { 134 case IP_VERSION(11, 0, 2): 135 case IP_VERSION(11, 0, 4): 136 err = psp_init_sos_microcode(psp, chip_name); 137 if (err) 138 return err; 139 err = psp_init_asd_microcode(psp, chip_name); 140 if (err) 141 return err; 142 err = psp_init_ta_microcode(psp, ucode_prefix); 143 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 144 break; 145 case IP_VERSION(11, 0, 0): 146 case IP_VERSION(11, 0, 5): 147 case IP_VERSION(11, 0, 9): 148 err = psp_init_sos_microcode(psp, chip_name); 149 if (err) 150 return err; 151 err = psp_init_asd_microcode(psp, chip_name); 152 if (err) 153 return err; 154 err = psp_init_ta_microcode(psp, ucode_prefix); 155 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 156 break; 157 case IP_VERSION(11, 0, 7): 158 case IP_VERSION(11, 0, 11): 159 case IP_VERSION(11, 0, 12): 160 case IP_VERSION(11, 0, 13): 161 err = psp_init_sos_microcode(psp, chip_name); 162 if (err) 163 return err; 164 err = psp_init_ta_microcode(psp, chip_name); 165 break; 166 case IP_VERSION(11, 5, 0): 167 err = psp_init_asd_microcode(psp, chip_name); 168 if (err) 169 return err; 170 err = psp_init_toc_microcode(psp, chip_name); 171 break; 172 default: 173 BUG(); 174 } 175 176 return err; 177 } 178 179 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 180 { 181 struct amdgpu_device *adev = psp->adev; 182 183 int ret; 184 int retry_loop; 185 186 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 187 /* Wait for bootloader to signify that is 188 ready having bit 31 of C2PMSG_35 set to 1 */ 189 ret = psp_wait_for(psp, 190 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 191 0x80000000, 192 0x80000000, 193 false); 194 195 if (ret == 0) 196 return 0; 197 } 198 199 return ret; 200 } 201 202 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 203 { 204 struct amdgpu_device *adev = psp->adev; 205 uint32_t sol_reg; 206 207 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 208 209 return sol_reg != 0x0; 210 } 211 212 static int psp_v11_0_bootloader_load_component(struct psp_context *psp, 213 struct psp_bin_desc *bin_desc, 214 enum psp_bootloader_cmd bl_cmd) 215 { 216 int ret; 217 uint32_t psp_gfxdrv_command_reg = 0; 218 struct amdgpu_device *adev = psp->adev; 219 220 /* Check sOS sign of life register to confirm sys driver and sOS 221 * are already been loaded. 222 */ 223 if (psp_v11_0_is_sos_alive(psp)) 224 return 0; 225 226 ret = psp_v11_0_wait_for_bootloader(psp); 227 if (ret) 228 return ret; 229 230 /* Copy PSP System Driver binary to memory */ 231 psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); 232 233 /* Provide the sys driver to bootloader */ 234 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 235 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 236 psp_gfxdrv_command_reg = bl_cmd; 237 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 238 psp_gfxdrv_command_reg); 239 240 ret = psp_v11_0_wait_for_bootloader(psp); 241 242 return ret; 243 } 244 245 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 246 { 247 return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 248 } 249 250 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp) 251 { 252 return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE); 253 } 254 255 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 256 { 257 return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 258 } 259 260 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 261 { 262 int ret; 263 unsigned int psp_gfxdrv_command_reg = 0; 264 struct amdgpu_device *adev = psp->adev; 265 266 /* Check sOS sign of life register to confirm sys driver and sOS 267 * are already been loaded. 268 */ 269 if (psp_v11_0_is_sos_alive(psp)) 270 return 0; 271 272 ret = psp_v11_0_wait_for_bootloader(psp); 273 if (ret) 274 return ret; 275 276 /* Copy Secure OS binary to PSP memory */ 277 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); 278 279 /* Provide the PSP secure OS to bootloader */ 280 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 281 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 282 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 283 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 284 psp_gfxdrv_command_reg); 285 286 /* there might be handshake issue with hardware which needs delay */ 287 mdelay(20); 288 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 289 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 290 0, true); 291 292 return ret; 293 } 294 295 static int psp_v11_0_ring_stop(struct psp_context *psp, 296 enum psp_ring_type ring_type) 297 { 298 int ret = 0; 299 struct amdgpu_device *adev = psp->adev; 300 301 /* Write the ring destroy command*/ 302 if (amdgpu_sriov_vf(adev)) 303 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 304 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 305 else 306 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 307 GFX_CTRL_CMD_ID_DESTROY_RINGS); 308 309 /* there might be handshake issue with hardware which needs delay */ 310 mdelay(20); 311 312 /* Wait for response flag (bit 31) */ 313 if (amdgpu_sriov_vf(adev)) 314 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 315 0x80000000, 0x80000000, false); 316 else 317 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 318 0x80000000, 0x80000000, false); 319 320 return ret; 321 } 322 323 static int psp_v11_0_ring_create(struct psp_context *psp, 324 enum psp_ring_type ring_type) 325 { 326 int ret = 0; 327 unsigned int psp_ring_reg = 0; 328 struct psp_ring *ring = &psp->km_ring; 329 struct amdgpu_device *adev = psp->adev; 330 331 if (amdgpu_sriov_vf(adev)) { 332 ring->ring_wptr = 0; 333 ret = psp_v11_0_ring_stop(psp, ring_type); 334 if (ret) { 335 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 336 return ret; 337 } 338 339 /* Write low address of the ring to C2PMSG_102 */ 340 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 341 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 342 /* Write high address of the ring to C2PMSG_103 */ 343 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 344 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 345 346 /* Write the ring initialization command to C2PMSG_101 */ 347 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 348 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 349 350 /* there might be handshake issue with hardware which needs delay */ 351 mdelay(20); 352 353 /* Wait for response flag (bit 31) in C2PMSG_101 */ 354 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 355 0x80000000, 0x8000FFFF, false); 356 357 } else { 358 /* Wait for sOS ready for ring creation */ 359 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 360 0x80000000, 0x80000000, false); 361 if (ret) { 362 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 363 return ret; 364 } 365 366 /* Write low address of the ring to C2PMSG_69 */ 367 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 368 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 369 /* Write high address of the ring to C2PMSG_70 */ 370 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 371 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 372 /* Write size of ring to C2PMSG_71 */ 373 psp_ring_reg = ring->ring_size; 374 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 375 /* Write the ring initialization command to C2PMSG_64 */ 376 psp_ring_reg = ring_type; 377 psp_ring_reg = psp_ring_reg << 16; 378 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 379 380 /* there might be handshake issue with hardware which needs delay */ 381 mdelay(20); 382 383 /* Wait for response flag (bit 31) in C2PMSG_64 */ 384 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 385 0x80000000, 0x8000FFFF, false); 386 } 387 388 return ret; 389 } 390 391 392 static int psp_v11_0_ring_destroy(struct psp_context *psp, 393 enum psp_ring_type ring_type) 394 { 395 int ret = 0; 396 struct psp_ring *ring = &psp->km_ring; 397 struct amdgpu_device *adev = psp->adev; 398 399 ret = psp_v11_0_ring_stop(psp, ring_type); 400 if (ret) 401 DRM_ERROR("Fail to stop psp ring\n"); 402 403 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 404 &ring->ring_mem_mc_addr, 405 (void **)&ring->ring_mem); 406 407 return ret; 408 } 409 410 static int psp_v11_0_mode1_reset(struct psp_context *psp) 411 { 412 int ret; 413 uint32_t offset; 414 struct amdgpu_device *adev = psp->adev; 415 416 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 417 418 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 419 420 if (ret) { 421 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 422 return -EINVAL; 423 } 424 425 /*send the mode 1 reset command*/ 426 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 427 428 msleep(500); 429 430 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 431 432 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 433 434 if (ret) { 435 DRM_INFO("psp mode 1 reset failed!\n"); 436 return -EINVAL; 437 } 438 439 DRM_INFO("psp mode1 reset succeed \n"); 440 441 return 0; 442 } 443 444 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 445 { 446 int ret; 447 int i; 448 uint32_t data_32; 449 int max_wait; 450 struct amdgpu_device *adev = psp->adev; 451 452 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 453 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 454 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 455 456 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 457 for (i = 0; i < max_wait; i++) { 458 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 459 0x80000000, 0x80000000, false); 460 if (ret == 0) 461 break; 462 } 463 if (i < max_wait) 464 ret = 0; 465 else 466 ret = -ETIME; 467 468 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 469 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 470 (ret == 0) ? "succeed" : "failed", 471 i, adev->usec_timeout/1000); 472 return ret; 473 } 474 475 /* 476 * save and restore process 477 */ 478 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 479 { 480 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 481 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 482 struct amdgpu_device *adev = psp->adev; 483 uint32_t p2c_header[4]; 484 uint32_t sz; 485 void *buf; 486 int ret, idx; 487 488 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 489 DRM_DEBUG("Memory training is not supported.\n"); 490 return 0; 491 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 492 DRM_ERROR("Memory training initialization failure.\n"); 493 return -EINVAL; 494 } 495 496 if (psp_v11_0_is_sos_alive(psp)) { 497 DRM_DEBUG("SOS is alive, skip memory training.\n"); 498 return 0; 499 } 500 501 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 502 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 503 pcache[0], pcache[1], pcache[2], pcache[3], 504 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 505 506 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 507 DRM_DEBUG("Short training depends on restore.\n"); 508 ops |= PSP_MEM_TRAIN_RESTORE; 509 } 510 511 if ((ops & PSP_MEM_TRAIN_RESTORE) && 512 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 513 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 514 ops |= PSP_MEM_TRAIN_SAVE; 515 } 516 517 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 518 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 519 pcache[3] == p2c_header[3])) { 520 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 521 ops |= PSP_MEM_TRAIN_SAVE; 522 } 523 524 if ((ops & PSP_MEM_TRAIN_SAVE) && 525 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 526 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 527 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 528 } 529 530 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 531 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 532 ops |= PSP_MEM_TRAIN_SAVE; 533 } 534 535 DRM_DEBUG("Memory training ops:%x.\n", ops); 536 537 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 538 /* 539 * Long training will encroach a certain amount on the bottom of VRAM; 540 * save the content from the bottom of VRAM to system memory 541 * before training, and restore it after training to avoid 542 * VRAM corruption. 543 */ 544 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 545 546 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 547 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 548 adev->gmc.visible_vram_size, 549 adev->mman.aper_base_kaddr); 550 return -EINVAL; 551 } 552 553 buf = vmalloc(sz); 554 if (!buf) { 555 DRM_ERROR("failed to allocate system memory.\n"); 556 return -ENOMEM; 557 } 558 559 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 560 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 561 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 562 if (ret) { 563 DRM_ERROR("Send long training msg failed.\n"); 564 vfree(buf); 565 drm_dev_exit(idx); 566 return ret; 567 } 568 569 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 570 adev->hdp.funcs->flush_hdp(adev, NULL); 571 vfree(buf); 572 drm_dev_exit(idx); 573 } else { 574 vfree(buf); 575 return -ENODEV; 576 } 577 } 578 579 if (ops & PSP_MEM_TRAIN_SAVE) { 580 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 581 } 582 583 if (ops & PSP_MEM_TRAIN_RESTORE) { 584 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 585 } 586 587 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 588 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 589 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 590 if (ret) { 591 DRM_ERROR("send training msg failed.\n"); 592 return ret; 593 } 594 } 595 ctx->training_cnt++; 596 return 0; 597 } 598 599 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 600 { 601 uint32_t data; 602 struct amdgpu_device *adev = psp->adev; 603 604 if (amdgpu_sriov_vf(adev)) 605 data = psp->km_ring.ring_wptr; 606 else 607 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 608 609 return data; 610 } 611 612 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 613 { 614 struct amdgpu_device *adev = psp->adev; 615 616 if (amdgpu_sriov_vf(adev)) { 617 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 618 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 619 psp->km_ring.ring_wptr = value; 620 } else 621 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 622 } 623 624 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 625 { 626 struct amdgpu_device *adev = psp->adev; 627 uint32_t reg_status; 628 int ret, i = 0; 629 630 /* 631 * LFB address which is aligned to 1MB address and has to be 632 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 633 * register 634 */ 635 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 636 637 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 638 0x80000000, 0x80000000, false); 639 if (ret) 640 return ret; 641 642 /* Fireup interrupt so PSP can pick up the address */ 643 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 644 645 /* FW load takes very long time */ 646 do { 647 msleep(1000); 648 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 649 650 if (reg_status & 0x80000000) 651 goto done; 652 653 } while (++i < USBC_PD_POLLING_LIMIT_S); 654 655 return -ETIME; 656 done: 657 658 if ((reg_status & 0xFFFF) != 0) { 659 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n", 660 reg_status & 0xFFFF); 661 return -EIO; 662 } 663 664 return 0; 665 } 666 667 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 668 { 669 struct amdgpu_device *adev = psp->adev; 670 int ret; 671 672 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 673 674 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 675 0x80000000, 0x80000000, false); 676 if (!ret) 677 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 678 679 return ret; 680 } 681 682 static const struct psp_funcs psp_v11_0_funcs = { 683 .init_microcode = psp_v11_0_init_microcode, 684 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 685 .bootloader_load_spl = psp_v11_0_bootloader_load_spl, 686 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 687 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 688 .ring_create = psp_v11_0_ring_create, 689 .ring_stop = psp_v11_0_ring_stop, 690 .ring_destroy = psp_v11_0_ring_destroy, 691 .mode1_reset = psp_v11_0_mode1_reset, 692 .mem_training = psp_v11_0_memory_training, 693 .ring_get_wptr = psp_v11_0_ring_get_wptr, 694 .ring_set_wptr = psp_v11_0_ring_set_wptr, 695 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 696 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw 697 }; 698 699 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 700 { 701 psp->funcs = &psp_v11_0_funcs; 702 } 703