1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 36 /* These are memory addresses as would be seen by one or more EEPROM 37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 38 * set of EEPROM devices. They form a continuous memory space. 39 * 40 * The I2C device address includes the device type identifier, 1010b, 41 * which is a reserved value and indicates that this is an I2C EEPROM 42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 43 * address, namely bits 18, 17, and 16. This makes up the 7 bit 44 * address sent on the I2C bus with bit 0 being the direction bit, 45 * which is not represented here, and sent by the hardware directly. 46 * 47 * For instance, 48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 52 * address memory in a device or a device on the I2C bus, depending on 53 * the status of pins 1-3. See top of amdgpu_eeprom.c. 54 * 55 * The RAS table lives either at address 0 or address 40000h of EEPROM. 56 */ 57 #define EEPROM_I2C_MADDR_0 0x0 58 #define EEPROM_I2C_MADDR_4 0x40000 59 60 /* 61 * The 2 macros bellow represent the actual size in bytes that 62 * those entities occupy in the EEPROM memory. 63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 64 * uses uint64 to store 6b fields such as retired_page. 65 */ 66 #define RAS_TABLE_HEADER_SIZE 20 67 #define RAS_TABLE_RECORD_SIZE 24 68 69 /* Table hdr is 'AMDR' */ 70 #define RAS_TABLE_HDR_VAL 0x414d4452 71 72 /* Bad GPU tag ‘BADG’ */ 73 #define RAS_TABLE_HDR_BAD 0x42414447 74 75 /* 76 * EEPROM Table structure v1 77 * --------------------------------- 78 * | | 79 * | EEPROM TABLE HEADER | 80 * | ( size 20 Bytes ) | 81 * | | 82 * --------------------------------- 83 * | | 84 * | BAD PAGE RECORD AREA | 85 * | | 86 * --------------------------------- 87 */ 88 89 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 90 #define RAS_TBL_SIZE_BYTES (256 * 1024) 91 #define RAS_TABLE_START 0 92 #define RAS_HDR_START RAS_TABLE_START 93 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 94 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 95 / RAS_TABLE_RECORD_SIZE) 96 97 /* 98 * EEPROM Table structrue v2.1 99 * --------------------------------- 100 * | | 101 * | EEPROM TABLE HEADER | 102 * | ( size 20 Bytes ) | 103 * | | 104 * --------------------------------- 105 * | | 106 * | EEPROM TABLE RAS INFO | 107 * | (available info size 4 Bytes) | 108 * | ( reserved size 252 Bytes ) | 109 * | | 110 * --------------------------------- 111 * | | 112 * | BAD PAGE RECORD AREA | 113 * | | 114 * --------------------------------- 115 */ 116 117 /* EEPROM Table V2_1 */ 118 #define RAS_TABLE_V2_1_INFO_SIZE 256 119 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 120 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 121 RAS_TABLE_V2_1_INFO_SIZE) 122 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 123 RAS_TABLE_V2_1_INFO_SIZE) \ 124 / RAS_TABLE_RECORD_SIZE) 125 126 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 127 * offset off of RAS_TABLE_START. That is, this is something you can 128 * add to control->i2c_address, and then tell I2C layer to read 129 * from/write to there. _N is the so called absolute index, 130 * because it starts right after the table header. 131 */ 132 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 133 (_N) * RAS_TABLE_RECORD_SIZE) 134 135 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 136 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 137 138 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 139 * of "fri", return the absolute record index off of the end of 140 * the table header. 141 */ 142 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 143 (_C)->ras_max_record_count) 144 145 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 146 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 147 148 #define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 149 RAS_TABLE_HEADER_SIZE - \ 150 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE) 151 152 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev 153 154 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 155 { 156 switch (adev->ip_versions[MP1_HWIP][0]) { 157 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 158 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 159 case IP_VERSION(13, 0, 0): 160 case IP_VERSION(13, 0, 2): /* Aldebaran */ 161 case IP_VERSION(13, 0, 6): 162 case IP_VERSION(13, 0, 10): 163 return true; 164 default: 165 return false; 166 } 167 } 168 169 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 170 struct amdgpu_ras_eeprom_control *control) 171 { 172 struct atom_context *atom_ctx = adev->mode_info.atom_context; 173 u8 i2c_addr; 174 175 if (!control) 176 return false; 177 178 if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 179 /* The address given by VBIOS is an 8-bit, wire-format 180 * address, i.e. the most significant byte. 181 * 182 * Normalize it to a 19-bit EEPROM address. Remove the 183 * device type identifier and make it a 7-bit address; 184 * then make it a 19-bit EEPROM address. See top of 185 * amdgpu_eeprom.c. 186 */ 187 i2c_addr = (i2c_addr & 0x0F) >> 1; 188 control->i2c_address = ((u32) i2c_addr) << 16; 189 190 return true; 191 } 192 193 switch (adev->ip_versions[MP1_HWIP][0]) { 194 case IP_VERSION(11, 0, 2): 195 /* VEGA20 and ARCTURUS */ 196 if (adev->asic_type == CHIP_VEGA20) 197 control->i2c_address = EEPROM_I2C_MADDR_0; 198 else if (strnstr(atom_ctx->vbios_pn, 199 "D342", 200 sizeof(atom_ctx->vbios_pn))) 201 control->i2c_address = EEPROM_I2C_MADDR_0; 202 else 203 control->i2c_address = EEPROM_I2C_MADDR_4; 204 return true; 205 case IP_VERSION(11, 0, 7): 206 control->i2c_address = EEPROM_I2C_MADDR_0; 207 return true; 208 case IP_VERSION(13, 0, 2): 209 if (strnstr(atom_ctx->vbios_pn, "D673", 210 sizeof(atom_ctx->vbios_pn))) 211 control->i2c_address = EEPROM_I2C_MADDR_4; 212 else 213 control->i2c_address = EEPROM_I2C_MADDR_0; 214 return true; 215 case IP_VERSION(13, 0, 0): 216 case IP_VERSION(13, 0, 6): 217 case IP_VERSION(13, 0, 10): 218 control->i2c_address = EEPROM_I2C_MADDR_4; 219 return true; 220 default: 221 return false; 222 } 223 } 224 225 static void 226 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 227 unsigned char *buf) 228 { 229 u32 *pp = (uint32_t *)buf; 230 231 pp[0] = cpu_to_le32(hdr->header); 232 pp[1] = cpu_to_le32(hdr->version); 233 pp[2] = cpu_to_le32(hdr->first_rec_offset); 234 pp[3] = cpu_to_le32(hdr->tbl_size); 235 pp[4] = cpu_to_le32(hdr->checksum); 236 } 237 238 static void 239 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 240 unsigned char *buf) 241 { 242 u32 *pp = (uint32_t *)buf; 243 244 hdr->header = le32_to_cpu(pp[0]); 245 hdr->version = le32_to_cpu(pp[1]); 246 hdr->first_rec_offset = le32_to_cpu(pp[2]); 247 hdr->tbl_size = le32_to_cpu(pp[3]); 248 hdr->checksum = le32_to_cpu(pp[4]); 249 } 250 251 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 252 { 253 u8 buf[RAS_TABLE_HEADER_SIZE]; 254 struct amdgpu_device *adev = to_amdgpu_device(control); 255 int res; 256 257 memset(buf, 0, sizeof(buf)); 258 __encode_table_header_to_buf(&control->tbl_hdr, buf); 259 260 /* i2c may be unstable in gpu reset */ 261 down_read(&adev->reset_domain->sem); 262 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 263 control->i2c_address + 264 control->ras_header_offset, 265 buf, RAS_TABLE_HEADER_SIZE); 266 up_read(&adev->reset_domain->sem); 267 268 if (res < 0) { 269 DRM_ERROR("Failed to write EEPROM table header:%d", res); 270 } else if (res < RAS_TABLE_HEADER_SIZE) { 271 DRM_ERROR("Short write:%d out of %d\n", 272 res, RAS_TABLE_HEADER_SIZE); 273 res = -EIO; 274 } else { 275 res = 0; 276 } 277 278 return res; 279 } 280 281 static void 282 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 283 unsigned char *buf) 284 { 285 u32 *pp = (uint32_t *)buf; 286 u32 tmp; 287 288 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 289 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 290 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 291 pp[0] = cpu_to_le32(tmp); 292 } 293 294 static void 295 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai, 296 unsigned char *buf) 297 { 298 u32 *pp = (uint32_t *)buf; 299 u32 tmp; 300 301 tmp = le32_to_cpu(pp[0]); 302 rai->rma_status = tmp & 0xFF; 303 rai->health_percent = (tmp >> 8) & 0xFF; 304 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 305 } 306 307 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) 308 { 309 struct amdgpu_device *adev = to_amdgpu_device(control); 310 u8 *buf; 311 int res; 312 313 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 314 if (!buf) { 315 DRM_ERROR("Failed to alloc buf to write table ras info\n"); 316 return -ENOMEM; 317 } 318 319 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 320 321 /* i2c may be unstable in gpu reset */ 322 down_read(&adev->reset_domain->sem); 323 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 324 control->i2c_address + 325 control->ras_info_offset, 326 buf, RAS_TABLE_V2_1_INFO_SIZE); 327 up_read(&adev->reset_domain->sem); 328 329 if (res < 0) { 330 DRM_ERROR("Failed to write EEPROM table ras info:%d", res); 331 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 332 DRM_ERROR("Short write:%d out of %d\n", 333 res, RAS_TABLE_V2_1_INFO_SIZE); 334 res = -EIO; 335 } else { 336 res = 0; 337 } 338 339 kfree(buf); 340 341 return res; 342 } 343 344 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 345 { 346 int ii; 347 u8 *pp, csum; 348 size_t sz; 349 350 /* Header checksum, skip checksum field in the calculation */ 351 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 352 pp = (u8 *) &control->tbl_hdr; 353 csum = 0; 354 for (ii = 0; ii < sz; ii++, pp++) 355 csum += *pp; 356 357 return csum; 358 } 359 360 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) 361 { 362 int ii; 363 u8 *pp, csum; 364 size_t sz; 365 366 sz = sizeof(control->tbl_rai); 367 pp = (u8 *) &control->tbl_rai; 368 csum = 0; 369 for (ii = 0; ii < sz; ii++, pp++) 370 csum += *pp; 371 372 return csum; 373 } 374 375 static int amdgpu_ras_eeprom_correct_header_tag( 376 struct amdgpu_ras_eeprom_control *control, 377 uint32_t header) 378 { 379 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 380 u8 *hh; 381 int res; 382 u8 csum; 383 384 csum = -hdr->checksum; 385 386 hh = (void *) &hdr->header; 387 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 388 hh = (void *) &header; 389 csum += hh[0] + hh[1] + hh[2] + hh[3]; 390 csum = -csum; 391 mutex_lock(&control->ras_tbl_mutex); 392 hdr->header = header; 393 hdr->checksum = csum; 394 res = __write_table_header(control); 395 mutex_unlock(&control->ras_tbl_mutex); 396 397 return res; 398 } 399 400 /** 401 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 402 * @control: pointer to control structure 403 * 404 * Reset the contents of the header of the RAS EEPROM table. 405 * Return 0 on success, -errno on error. 406 */ 407 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 408 { 409 struct amdgpu_device *adev = to_amdgpu_device(control); 410 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 411 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 412 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 413 u8 csum; 414 int res; 415 416 mutex_lock(&control->ras_tbl_mutex); 417 418 hdr->header = RAS_TABLE_HDR_VAL; 419 if (adev->umc.ras && 420 adev->umc.ras->set_eeprom_table_version) 421 adev->umc.ras->set_eeprom_table_version(hdr); 422 else 423 hdr->version = RAS_TABLE_VER_V1; 424 425 if (hdr->version == RAS_TABLE_VER_V2_1) { 426 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 427 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 428 RAS_TABLE_V2_1_INFO_SIZE; 429 rai->rma_status = GPU_HEALTH_USABLE; 430 /** 431 * GPU health represented as a percentage. 432 * 0 means worst health, 100 means fully health. 433 */ 434 rai->health_percent = 100; 435 /* ecc_page_threshold = 0 means disable bad page retirement */ 436 rai->ecc_page_threshold = con->bad_page_cnt_threshold; 437 } else { 438 hdr->first_rec_offset = RAS_RECORD_START; 439 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 440 } 441 442 csum = __calc_hdr_byte_sum(control); 443 if (hdr->version == RAS_TABLE_VER_V2_1) 444 csum += __calc_ras_info_byte_sum(control); 445 csum = -csum; 446 hdr->checksum = csum; 447 res = __write_table_header(control); 448 if (!res && hdr->version > RAS_TABLE_VER_V1) 449 res = __write_table_ras_info(control); 450 451 control->ras_num_recs = 0; 452 control->ras_fri = 0; 453 454 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs); 455 456 control->bad_channel_bitmap = 0; 457 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 458 con->update_channel_flag = false; 459 460 amdgpu_ras_debugfs_set_ret_size(control); 461 462 mutex_unlock(&control->ras_tbl_mutex); 463 464 return res; 465 } 466 467 static void 468 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 469 struct eeprom_table_record *record, 470 unsigned char *buf) 471 { 472 __le64 tmp = 0; 473 int i = 0; 474 475 /* Next are all record fields according to EEPROM page spec in LE foramt */ 476 buf[i++] = record->err_type; 477 478 buf[i++] = record->bank; 479 480 tmp = cpu_to_le64(record->ts); 481 memcpy(buf + i, &tmp, 8); 482 i += 8; 483 484 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 485 memcpy(buf + i, &tmp, 6); 486 i += 6; 487 488 buf[i++] = record->mem_channel; 489 buf[i++] = record->mcumc_id; 490 491 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 492 memcpy(buf + i, &tmp, 6); 493 } 494 495 static void 496 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 497 struct eeprom_table_record *record, 498 unsigned char *buf) 499 { 500 __le64 tmp = 0; 501 int i = 0; 502 503 /* Next are all record fields according to EEPROM page spec in LE foramt */ 504 record->err_type = buf[i++]; 505 506 record->bank = buf[i++]; 507 508 memcpy(&tmp, buf + i, 8); 509 record->ts = le64_to_cpu(tmp); 510 i += 8; 511 512 memcpy(&tmp, buf + i, 6); 513 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 514 i += 6; 515 516 record->mem_channel = buf[i++]; 517 record->mcumc_id = buf[i++]; 518 519 memcpy(&tmp, buf + i, 6); 520 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 521 } 522 523 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 524 { 525 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 526 527 if (!__is_ras_eeprom_supported(adev) || 528 !amdgpu_bad_page_threshold) 529 return false; 530 531 /* skip check eeprom table for VEGA20 Gaming */ 532 if (!con) 533 return false; 534 else 535 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 536 return false; 537 538 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 539 if (amdgpu_bad_page_threshold == -1) { 540 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d", 541 con->eeprom_control.ras_num_recs, con->bad_page_cnt_threshold); 542 dev_warn(adev->dev, 543 "But GPU can be operated due to bad_page_threshold = -1.\n"); 544 return false; 545 } else { 546 dev_warn(adev->dev, "This GPU is in BAD status."); 547 dev_warn(adev->dev, "Please retire it or set a larger " 548 "threshold value when reloading driver.\n"); 549 return true; 550 } 551 } 552 553 return false; 554 } 555 556 /** 557 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 558 * @control: pointer to control structure 559 * @buf: pointer to buffer containing data to write 560 * @fri: start writing at this index 561 * @num: number of records to write 562 * 563 * The caller must hold the table mutex in @control. 564 * Return 0 on success, -errno otherwise. 565 */ 566 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 567 u8 *buf, const u32 fri, const u32 num) 568 { 569 struct amdgpu_device *adev = to_amdgpu_device(control); 570 u32 buf_size; 571 int res; 572 573 /* i2c may be unstable in gpu reset */ 574 down_read(&adev->reset_domain->sem); 575 buf_size = num * RAS_TABLE_RECORD_SIZE; 576 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 577 control->i2c_address + 578 RAS_INDEX_TO_OFFSET(control, fri), 579 buf, buf_size); 580 up_read(&adev->reset_domain->sem); 581 if (res < 0) { 582 DRM_ERROR("Writing %d EEPROM table records error:%d", 583 num, res); 584 } else if (res < buf_size) { 585 /* Short write, return error. 586 */ 587 DRM_ERROR("Wrote %d records out of %d", 588 res / RAS_TABLE_RECORD_SIZE, num); 589 res = -EIO; 590 } else { 591 res = 0; 592 } 593 594 return res; 595 } 596 597 static int 598 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 599 struct eeprom_table_record *record, 600 const u32 num) 601 { 602 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 603 u32 a, b, i; 604 u8 *buf, *pp; 605 int res; 606 607 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 608 if (!buf) 609 return -ENOMEM; 610 611 /* Encode all of them in one go. 612 */ 613 pp = buf; 614 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 615 __encode_table_record_to_buf(control, &record[i], pp); 616 617 /* update bad channel bitmap */ 618 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 619 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 620 con->update_channel_flag = true; 621 } 622 } 623 624 /* a, first record index to write into. 625 * b, last record index to write into. 626 * a = first index to read (fri) + number of records in the table, 627 * b = a + @num - 1. 628 * Let N = control->ras_max_num_record_count, then we have, 629 * case 0: 0 <= a <= b < N, 630 * just append @num records starting at a; 631 * case 1: 0 <= a < N <= b, 632 * append (N - a) records starting at a, and 633 * append the remainder, b % N + 1, starting at 0. 634 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 635 * case 2a: 0 <= a <= b < N 636 * append num records starting at a; and fix fri if b overwrote it, 637 * and since a <= b, if b overwrote it then a must've also, 638 * and if b didn't overwrite it, then a didn't also. 639 * case 2b: 0 <= b < a < N 640 * write num records starting at a, which wraps around 0=N 641 * and overwrite fri unconditionally. Now from case 2a, 642 * this means that b eclipsed fri to overwrite it and wrap 643 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 644 * set fri = b + 1 (mod N). 645 * Now, since fri is updated in every case, except the trivial case 0, 646 * the number of records present in the table after writing, is, 647 * num_recs - 1 = b - fri (mod N), and we take the positive value, 648 * by adding an arbitrary multiple of N before taking the modulo N 649 * as shown below. 650 */ 651 a = control->ras_fri + control->ras_num_recs; 652 b = a + num - 1; 653 if (b < control->ras_max_record_count) { 654 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 655 } else if (a < control->ras_max_record_count) { 656 u32 g0, g1; 657 658 g0 = control->ras_max_record_count - a; 659 g1 = b % control->ras_max_record_count + 1; 660 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 661 if (res) 662 goto Out; 663 res = __amdgpu_ras_eeprom_write(control, 664 buf + g0 * RAS_TABLE_RECORD_SIZE, 665 0, g1); 666 if (res) 667 goto Out; 668 if (g1 > control->ras_fri) 669 control->ras_fri = g1 % control->ras_max_record_count; 670 } else { 671 a %= control->ras_max_record_count; 672 b %= control->ras_max_record_count; 673 674 if (a <= b) { 675 /* Note that, b - a + 1 = num. */ 676 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 677 if (res) 678 goto Out; 679 if (b >= control->ras_fri) 680 control->ras_fri = (b + 1) % control->ras_max_record_count; 681 } else { 682 u32 g0, g1; 683 684 /* b < a, which means, we write from 685 * a to the end of the table, and from 686 * the start of the table to b. 687 */ 688 g0 = control->ras_max_record_count - a; 689 g1 = b + 1; 690 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 691 if (res) 692 goto Out; 693 res = __amdgpu_ras_eeprom_write(control, 694 buf + g0 * RAS_TABLE_RECORD_SIZE, 695 0, g1); 696 if (res) 697 goto Out; 698 control->ras_fri = g1 % control->ras_max_record_count; 699 } 700 } 701 control->ras_num_recs = 1 + (control->ras_max_record_count + b 702 - control->ras_fri) 703 % control->ras_max_record_count; 704 Out: 705 kfree(buf); 706 return res; 707 } 708 709 static int 710 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 711 { 712 struct amdgpu_device *adev = to_amdgpu_device(control); 713 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 714 u8 *buf, *pp, csum; 715 u32 buf_size; 716 int res; 717 718 /* Modify the header if it exceeds. 719 */ 720 if (amdgpu_bad_page_threshold != 0 && 721 control->ras_num_recs >= ras->bad_page_cnt_threshold) { 722 dev_warn(adev->dev, 723 "Saved bad pages %d reaches threshold value %d\n", 724 control->ras_num_recs, ras->bad_page_cnt_threshold); 725 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 726 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) { 727 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; 728 control->tbl_rai.health_percent = 0; 729 } 730 } 731 732 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 733 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 734 RAS_TABLE_V2_1_INFO_SIZE + 735 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 736 else 737 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 738 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 739 control->tbl_hdr.checksum = 0; 740 741 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 742 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 743 if (!buf) { 744 DRM_ERROR("allocating memory for table of size %d bytes failed\n", 745 control->tbl_hdr.tbl_size); 746 res = -ENOMEM; 747 goto Out; 748 } 749 750 down_read(&adev->reset_domain->sem); 751 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 752 control->i2c_address + 753 control->ras_record_offset, 754 buf, buf_size); 755 up_read(&adev->reset_domain->sem); 756 if (res < 0) { 757 DRM_ERROR("EEPROM failed reading records:%d\n", 758 res); 759 goto Out; 760 } else if (res < buf_size) { 761 DRM_ERROR("EEPROM read %d out of %d bytes\n", 762 res, buf_size); 763 res = -EIO; 764 goto Out; 765 } 766 767 /** 768 * bad page records have been stored in eeprom, 769 * now calculate gpu health percent 770 */ 771 if (amdgpu_bad_page_threshold != 0 && 772 control->tbl_hdr.version == RAS_TABLE_VER_V2_1 && 773 control->ras_num_recs < ras->bad_page_cnt_threshold) 774 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - 775 control->ras_num_recs) * 100) / 776 ras->bad_page_cnt_threshold; 777 778 /* Recalc the checksum. 779 */ 780 csum = 0; 781 for (pp = buf; pp < buf + buf_size; pp++) 782 csum += *pp; 783 784 csum += __calc_hdr_byte_sum(control); 785 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 786 csum += __calc_ras_info_byte_sum(control); 787 /* avoid sign extension when assigning to "checksum" */ 788 csum = -csum; 789 control->tbl_hdr.checksum = csum; 790 res = __write_table_header(control); 791 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 792 res = __write_table_ras_info(control); 793 Out: 794 kfree(buf); 795 return res; 796 } 797 798 /** 799 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 800 * @control: pointer to control structure 801 * @record: array of records to append 802 * @num: number of records in @record array 803 * 804 * Append @num records to the table, calculate the checksum and write 805 * the table back to EEPROM. The maximum number of records that 806 * can be appended is between 1 and control->ras_max_record_count, 807 * regardless of how many records are already stored in the table. 808 * 809 * Return 0 on success or if EEPROM is not supported, -errno on error. 810 */ 811 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 812 struct eeprom_table_record *record, 813 const u32 num) 814 { 815 struct amdgpu_device *adev = to_amdgpu_device(control); 816 int res; 817 818 if (!__is_ras_eeprom_supported(adev)) 819 return 0; 820 821 if (num == 0) { 822 DRM_ERROR("will not append 0 records\n"); 823 return -EINVAL; 824 } else if (num > control->ras_max_record_count) { 825 DRM_ERROR("cannot append %d records than the size of table %d\n", 826 num, control->ras_max_record_count); 827 return -EINVAL; 828 } 829 830 mutex_lock(&control->ras_tbl_mutex); 831 832 res = amdgpu_ras_eeprom_append_table(control, record, num); 833 if (!res) 834 res = amdgpu_ras_eeprom_update_header(control); 835 if (!res) 836 amdgpu_ras_debugfs_set_ret_size(control); 837 838 mutex_unlock(&control->ras_tbl_mutex); 839 return res; 840 } 841 842 /** 843 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 844 * @control: pointer to control structure 845 * @buf: pointer to buffer to read into 846 * @fri: first record index, start reading at this index, absolute index 847 * @num: number of records to read 848 * 849 * The caller must hold the table mutex in @control. 850 * Return 0 on success, -errno otherwise. 851 */ 852 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 853 u8 *buf, const u32 fri, const u32 num) 854 { 855 struct amdgpu_device *adev = to_amdgpu_device(control); 856 u32 buf_size; 857 int res; 858 859 /* i2c may be unstable in gpu reset */ 860 down_read(&adev->reset_domain->sem); 861 buf_size = num * RAS_TABLE_RECORD_SIZE; 862 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 863 control->i2c_address + 864 RAS_INDEX_TO_OFFSET(control, fri), 865 buf, buf_size); 866 up_read(&adev->reset_domain->sem); 867 if (res < 0) { 868 DRM_ERROR("Reading %d EEPROM table records error:%d", 869 num, res); 870 } else if (res < buf_size) { 871 /* Short read, return error. 872 */ 873 DRM_ERROR("Read %d records out of %d", 874 res / RAS_TABLE_RECORD_SIZE, num); 875 res = -EIO; 876 } else { 877 res = 0; 878 } 879 880 return res; 881 } 882 883 /** 884 * amdgpu_ras_eeprom_read -- read EEPROM 885 * @control: pointer to control structure 886 * @record: array of records to read into 887 * @num: number of records in @record 888 * 889 * Reads num records from the RAS table in EEPROM and 890 * writes the data into @record array. 891 * 892 * Returns 0 on success, -errno on error. 893 */ 894 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 895 struct eeprom_table_record *record, 896 const u32 num) 897 { 898 struct amdgpu_device *adev = to_amdgpu_device(control); 899 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 900 int i, res; 901 u8 *buf, *pp; 902 u32 g0, g1; 903 904 if (!__is_ras_eeprom_supported(adev)) 905 return 0; 906 907 if (num == 0) { 908 DRM_ERROR("will not read 0 records\n"); 909 return -EINVAL; 910 } else if (num > control->ras_num_recs) { 911 DRM_ERROR("too many records to read:%d available:%d\n", 912 num, control->ras_num_recs); 913 return -EINVAL; 914 } 915 916 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 917 if (!buf) 918 return -ENOMEM; 919 920 /* Determine how many records to read, from the first record 921 * index, fri, to the end of the table, and from the beginning 922 * of the table, such that the total number of records is 923 * @num, and we handle wrap around when fri > 0 and 924 * fri + num > RAS_MAX_RECORD_COUNT. 925 * 926 * First we compute the index of the last element 927 * which would be fetched from each region, 928 * g0 is in [fri, fri + num - 1], and 929 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 930 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 931 * the last element to fetch, we set g0 to _the number_ 932 * of elements to fetch, @num, since we know that the last 933 * indexed to be fetched does not exceed the table. 934 * 935 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 936 * we set g0 to the number of elements to read 937 * until the end of the table, and g1 to the number of 938 * elements to read from the beginning of the table. 939 */ 940 g0 = control->ras_fri + num - 1; 941 g1 = g0 % control->ras_max_record_count; 942 if (g0 < control->ras_max_record_count) { 943 g0 = num; 944 g1 = 0; 945 } else { 946 g0 = control->ras_max_record_count - control->ras_fri; 947 g1 += 1; 948 } 949 950 mutex_lock(&control->ras_tbl_mutex); 951 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 952 if (res) 953 goto Out; 954 if (g1) { 955 res = __amdgpu_ras_eeprom_read(control, 956 buf + g0 * RAS_TABLE_RECORD_SIZE, 957 0, g1); 958 if (res) 959 goto Out; 960 } 961 962 res = 0; 963 964 /* Read up everything? Then transform. 965 */ 966 pp = buf; 967 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 968 __decode_table_record_from_buf(control, &record[i], pp); 969 970 /* update bad channel bitmap */ 971 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 972 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 973 con->update_channel_flag = true; 974 } 975 } 976 Out: 977 kfree(buf); 978 mutex_unlock(&control->ras_tbl_mutex); 979 980 return res; 981 } 982 983 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) 984 { 985 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 986 return RAS_MAX_RECORD_COUNT_V2_1; 987 else 988 return RAS_MAX_RECORD_COUNT; 989 } 990 991 static ssize_t 992 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 993 size_t size, loff_t *pos) 994 { 995 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 996 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 997 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 998 u8 data[50]; 999 int res; 1000 1001 if (!size) 1002 return size; 1003 1004 if (!ras || !control) { 1005 res = snprintf(data, sizeof(data), "Not supported\n"); 1006 } else { 1007 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 1008 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 1009 } 1010 1011 if (*pos >= res) 1012 return 0; 1013 1014 res -= *pos; 1015 res = min_t(size_t, res, size); 1016 1017 if (copy_to_user(buf, &data[*pos], res)) 1018 return -EFAULT; 1019 1020 *pos += res; 1021 1022 return res; 1023 } 1024 1025 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 1026 .owner = THIS_MODULE, 1027 .read = amdgpu_ras_debugfs_eeprom_size_read, 1028 .write = NULL, 1029 .llseek = default_llseek, 1030 }; 1031 1032 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 1033 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 1034 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 1035 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 1036 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 1037 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 1038 1039 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 1040 "ignore", 1041 "re", 1042 "ue", 1043 }; 1044 1045 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 1046 { 1047 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 1048 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 1049 } 1050 1051 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1052 { 1053 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 1054 eeprom_control); 1055 struct dentry *de = ras->de_ras_eeprom_table; 1056 1057 if (de) 1058 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 1059 } 1060 1061 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 1062 size_t size, loff_t *pos) 1063 { 1064 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1065 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1066 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 1067 const size_t orig_size = size; 1068 int res = -EFAULT; 1069 size_t data_len; 1070 1071 mutex_lock(&control->ras_tbl_mutex); 1072 1073 /* We want *pos - data_len > 0, which means there's 1074 * bytes to be printed from data. 1075 */ 1076 data_len = strlen(tbl_hdr_str); 1077 if (*pos < data_len) { 1078 data_len -= *pos; 1079 data_len = min_t(size_t, data_len, size); 1080 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 1081 goto Out; 1082 buf += data_len; 1083 size -= data_len; 1084 *pos += data_len; 1085 } 1086 1087 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 1088 if (*pos < data_len && size > 0) { 1089 u8 data[tbl_hdr_fmt_size + 1]; 1090 loff_t lpos; 1091 1092 snprintf(data, sizeof(data), tbl_hdr_fmt, 1093 control->tbl_hdr.header, 1094 control->tbl_hdr.version, 1095 control->tbl_hdr.first_rec_offset, 1096 control->tbl_hdr.tbl_size, 1097 control->tbl_hdr.checksum); 1098 1099 data_len -= *pos; 1100 data_len = min_t(size_t, data_len, size); 1101 lpos = *pos - strlen(tbl_hdr_str); 1102 if (copy_to_user(buf, &data[lpos], data_len)) 1103 goto Out; 1104 buf += data_len; 1105 size -= data_len; 1106 *pos += data_len; 1107 } 1108 1109 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 1110 if (*pos < data_len && size > 0) { 1111 loff_t lpos; 1112 1113 data_len -= *pos; 1114 data_len = min_t(size_t, data_len, size); 1115 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 1116 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 1117 goto Out; 1118 buf += data_len; 1119 size -= data_len; 1120 *pos += data_len; 1121 } 1122 1123 data_len = amdgpu_ras_debugfs_table_size(control); 1124 if (*pos < data_len && size > 0) { 1125 u8 dare[RAS_TABLE_RECORD_SIZE]; 1126 u8 data[rec_hdr_fmt_size + 1]; 1127 struct eeprom_table_record record; 1128 int s, r; 1129 1130 /* Find the starting record index 1131 */ 1132 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1133 strlen(rec_hdr_str); 1134 s = s / rec_hdr_fmt_size; 1135 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 1136 strlen(rec_hdr_str); 1137 r = r % rec_hdr_fmt_size; 1138 1139 for ( ; size > 0 && s < control->ras_num_recs; s++) { 1140 u32 ai = RAS_RI_TO_AI(control, s); 1141 /* Read a single record 1142 */ 1143 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 1144 if (res) 1145 goto Out; 1146 __decode_table_record_from_buf(control, &record, dare); 1147 snprintf(data, sizeof(data), rec_hdr_fmt, 1148 s, 1149 RAS_INDEX_TO_OFFSET(control, ai), 1150 record_err_type_str[record.err_type], 1151 record.bank, 1152 record.ts, 1153 record.offset, 1154 record.mem_channel, 1155 record.mcumc_id, 1156 record.retired_page); 1157 1158 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 1159 if (copy_to_user(buf, &data[r], data_len)) { 1160 res = -EFAULT; 1161 goto Out; 1162 } 1163 buf += data_len; 1164 size -= data_len; 1165 *pos += data_len; 1166 r = 0; 1167 } 1168 } 1169 res = 0; 1170 Out: 1171 mutex_unlock(&control->ras_tbl_mutex); 1172 return res < 0 ? res : orig_size - size; 1173 } 1174 1175 static ssize_t 1176 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1177 size_t size, loff_t *pos) 1178 { 1179 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1180 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1181 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1182 u8 data[81]; 1183 int res; 1184 1185 if (!size) 1186 return size; 1187 1188 if (!ras || !control) { 1189 res = snprintf(data, sizeof(data), "Not supported\n"); 1190 if (*pos >= res) 1191 return 0; 1192 1193 res -= *pos; 1194 res = min_t(size_t, res, size); 1195 1196 if (copy_to_user(buf, &data[*pos], res)) 1197 return -EFAULT; 1198 1199 *pos += res; 1200 1201 return res; 1202 } else { 1203 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1204 } 1205 } 1206 1207 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1208 .owner = THIS_MODULE, 1209 .read = amdgpu_ras_debugfs_eeprom_table_read, 1210 .write = NULL, 1211 .llseek = default_llseek, 1212 }; 1213 1214 /** 1215 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1216 * @control: pointer to control structure 1217 * 1218 * Check the checksum of the stored in EEPROM RAS table. 1219 * 1220 * Return 0 if the checksum is correct, 1221 * positive if it is not correct, and 1222 * -errno on I/O error. 1223 */ 1224 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1225 { 1226 struct amdgpu_device *adev = to_amdgpu_device(control); 1227 int buf_size, res; 1228 u8 csum, *buf, *pp; 1229 1230 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) 1231 buf_size = RAS_TABLE_HEADER_SIZE + 1232 RAS_TABLE_V2_1_INFO_SIZE + 1233 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1234 else 1235 buf_size = RAS_TABLE_HEADER_SIZE + 1236 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1237 1238 buf = kzalloc(buf_size, GFP_KERNEL); 1239 if (!buf) { 1240 DRM_ERROR("Out of memory checking RAS table checksum.\n"); 1241 return -ENOMEM; 1242 } 1243 1244 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1245 control->i2c_address + 1246 control->ras_header_offset, 1247 buf, buf_size); 1248 if (res < buf_size) { 1249 DRM_ERROR("Partial read for checksum, res:%d\n", res); 1250 /* On partial reads, return -EIO. 1251 */ 1252 if (res >= 0) 1253 res = -EIO; 1254 goto Out; 1255 } 1256 1257 csum = 0; 1258 for (pp = buf; pp < buf + buf_size; pp++) 1259 csum += *pp; 1260 Out: 1261 kfree(buf); 1262 return res < 0 ? res : csum; 1263 } 1264 1265 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) 1266 { 1267 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1268 struct amdgpu_device *adev = to_amdgpu_device(control); 1269 unsigned char *buf; 1270 int res; 1271 1272 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1273 if (!buf) { 1274 DRM_ERROR("Failed to alloc buf to read EEPROM table ras info\n"); 1275 return -ENOMEM; 1276 } 1277 1278 /** 1279 * EEPROM table V2_1 supports ras info, 1280 * read EEPROM table ras info 1281 */ 1282 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1283 control->i2c_address + control->ras_info_offset, 1284 buf, RAS_TABLE_V2_1_INFO_SIZE); 1285 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1286 DRM_ERROR("Failed to read EEPROM table ras info, res:%d", res); 1287 res = res >= 0 ? -EIO : res; 1288 goto Out; 1289 } 1290 1291 __decode_table_ras_info_from_buf(rai, buf); 1292 1293 Out: 1294 kfree(buf); 1295 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1296 } 1297 1298 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control, 1299 bool *exceed_err_limit) 1300 { 1301 struct amdgpu_device *adev = to_amdgpu_device(control); 1302 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1303 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1304 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1305 int res; 1306 1307 *exceed_err_limit = false; 1308 1309 if (!__is_ras_eeprom_supported(adev)) 1310 return 0; 1311 1312 /* Verify i2c adapter is initialized */ 1313 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1314 return -ENOENT; 1315 1316 if (!__get_eeprom_i2c_addr(adev, control)) 1317 return -EINVAL; 1318 1319 control->ras_header_offset = RAS_HDR_START; 1320 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1321 mutex_init(&control->ras_tbl_mutex); 1322 1323 /* Read the table header from EEPROM address */ 1324 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1325 control->i2c_address + control->ras_header_offset, 1326 buf, RAS_TABLE_HEADER_SIZE); 1327 if (res < RAS_TABLE_HEADER_SIZE) { 1328 DRM_ERROR("Failed to read EEPROM table header, res:%d", res); 1329 return res >= 0 ? -EIO : res; 1330 } 1331 1332 __decode_table_header_from_buf(hdr, buf); 1333 1334 if (hdr->version == RAS_TABLE_VER_V2_1) { 1335 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1336 control->ras_record_offset = RAS_RECORD_START_V2_1; 1337 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1338 } else { 1339 control->ras_num_recs = RAS_NUM_RECS(hdr); 1340 control->ras_record_offset = RAS_RECORD_START; 1341 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1342 } 1343 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1344 1345 if (hdr->header == RAS_TABLE_HDR_VAL) { 1346 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", 1347 control->ras_num_recs); 1348 1349 if (hdr->version == RAS_TABLE_VER_V2_1) { 1350 res = __read_table_ras_info(control); 1351 if (res) 1352 return res; 1353 } 1354 1355 res = __verify_ras_table_checksum(control); 1356 if (res) 1357 DRM_ERROR("RAS table incorrect checksum or error:%d\n", 1358 res); 1359 1360 /* Warn if we are at 90% of the threshold or above 1361 */ 1362 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold) 1363 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1364 control->ras_num_recs, 1365 ras->bad_page_cnt_threshold); 1366 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1367 amdgpu_bad_page_threshold != 0) { 1368 if (hdr->version == RAS_TABLE_VER_V2_1) { 1369 res = __read_table_ras_info(control); 1370 if (res) 1371 return res; 1372 } 1373 1374 res = __verify_ras_table_checksum(control); 1375 if (res) 1376 DRM_ERROR("RAS Table incorrect checksum or error:%d\n", 1377 res); 1378 if (ras->bad_page_cnt_threshold > control->ras_num_recs) { 1379 /* This means that, the threshold was increased since 1380 * the last time the system was booted, and now, 1381 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1382 * so that at least one more record can be saved, 1383 * before the page count threshold is reached. 1384 */ 1385 dev_info(adev->dev, 1386 "records:%d threshold:%d, resetting " 1387 "RAS table header signature", 1388 control->ras_num_recs, 1389 ras->bad_page_cnt_threshold); 1390 res = amdgpu_ras_eeprom_correct_header_tag(control, 1391 RAS_TABLE_HDR_VAL); 1392 } else { 1393 dev_err(adev->dev, "RAS records:%d exceed threshold:%d", 1394 control->ras_num_recs, ras->bad_page_cnt_threshold); 1395 if (amdgpu_bad_page_threshold == -1) { 1396 dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -1."); 1397 res = 0; 1398 } else { 1399 *exceed_err_limit = true; 1400 dev_err(adev->dev, 1401 "RAS records:%d exceed threshold:%d, " 1402 "GPU will not be initialized. Replace this GPU or increase the threshold", 1403 control->ras_num_recs, ras->bad_page_cnt_threshold); 1404 } 1405 } 1406 } else { 1407 DRM_INFO("Creating a new EEPROM table"); 1408 1409 res = amdgpu_ras_eeprom_reset_table(control); 1410 } 1411 1412 return res < 0 ? res : 0; 1413 } 1414