1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 /* 56 * Due to DF Cstate management centralized to PMFW, the firmware 57 * loading sequence will be updated as below: 58 * - Load KDB 59 * - Load SYS_DRV 60 * - Load tOS 61 * - Load PMFW 62 * - Setup TMR 63 * - Load other non-psp fw 64 * - Load ASD 65 * - Load XGMI/RAS/HDCP/DTM TA if any 66 * 67 * This new sequence is required for 68 * - Arcturus and onwards 69 */ 70 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 71 { 72 struct amdgpu_device *adev = psp->adev; 73 74 if (amdgpu_sriov_vf(adev)) { 75 psp->pmfw_centralized_cstate_management = false; 76 return; 77 } 78 79 switch (adev->ip_versions[MP0_HWIP][0]) { 80 case IP_VERSION(11, 0, 0): 81 case IP_VERSION(11, 0, 4): 82 case IP_VERSION(11, 0, 5): 83 case IP_VERSION(11, 0, 7): 84 case IP_VERSION(11, 0, 9): 85 case IP_VERSION(11, 0, 11): 86 case IP_VERSION(11, 0, 12): 87 case IP_VERSION(11, 0, 13): 88 case IP_VERSION(13, 0, 0): 89 case IP_VERSION(13, 0, 2): 90 case IP_VERSION(13, 0, 7): 91 psp->pmfw_centralized_cstate_management = true; 92 break; 93 default: 94 psp->pmfw_centralized_cstate_management = false; 95 break; 96 } 97 } 98 99 static int psp_early_init(void *handle) 100 { 101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 102 struct psp_context *psp = &adev->psp; 103 104 switch (adev->ip_versions[MP0_HWIP][0]) { 105 case IP_VERSION(9, 0, 0): 106 psp_v3_1_set_psp_funcs(psp); 107 psp->autoload_supported = false; 108 break; 109 case IP_VERSION(10, 0, 0): 110 case IP_VERSION(10, 0, 1): 111 psp_v10_0_set_psp_funcs(psp); 112 psp->autoload_supported = false; 113 break; 114 case IP_VERSION(11, 0, 2): 115 case IP_VERSION(11, 0, 4): 116 psp_v11_0_set_psp_funcs(psp); 117 psp->autoload_supported = false; 118 break; 119 case IP_VERSION(11, 0, 0): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 9): 122 case IP_VERSION(11, 0, 7): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 5, 0): 125 case IP_VERSION(11, 0, 12): 126 case IP_VERSION(11, 0, 13): 127 psp_v11_0_set_psp_funcs(psp); 128 psp->autoload_supported = true; 129 break; 130 case IP_VERSION(11, 0, 3): 131 case IP_VERSION(12, 0, 1): 132 psp_v12_0_set_psp_funcs(psp); 133 break; 134 case IP_VERSION(13, 0, 2): 135 psp_v13_0_set_psp_funcs(psp); 136 break; 137 case IP_VERSION(13, 0, 1): 138 case IP_VERSION(13, 0, 3): 139 case IP_VERSION(13, 0, 5): 140 case IP_VERSION(13, 0, 8): 141 case IP_VERSION(13, 0, 10): 142 psp_v13_0_set_psp_funcs(psp); 143 psp->autoload_supported = true; 144 break; 145 case IP_VERSION(11, 0, 8): 146 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 147 psp_v11_0_8_set_psp_funcs(psp); 148 psp->autoload_supported = false; 149 } 150 break; 151 case IP_VERSION(13, 0, 0): 152 case IP_VERSION(13, 0, 7): 153 psp_v13_0_set_psp_funcs(psp); 154 psp->autoload_supported = true; 155 break; 156 case IP_VERSION(13, 0, 4): 157 psp_v13_0_4_set_psp_funcs(psp); 158 psp->autoload_supported = true; 159 break; 160 default: 161 return -EINVAL; 162 } 163 164 psp->adev = adev; 165 166 psp_check_pmfw_centralized_cstate_management(psp); 167 168 return 0; 169 } 170 171 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 172 { 173 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 174 &mem_ctx->shared_buf); 175 mem_ctx->shared_bo = NULL; 176 } 177 178 static void psp_free_shared_bufs(struct psp_context *psp) 179 { 180 void *tmr_buf; 181 void **pptr; 182 183 /* free TMR memory buffer */ 184 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 185 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 186 psp->tmr_bo = NULL; 187 188 /* free xgmi shared memory */ 189 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 190 191 /* free ras shared memory */ 192 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 193 194 /* free hdcp shared memory */ 195 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 196 197 /* free dtm shared memory */ 198 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 199 200 /* free rap shared memory */ 201 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 202 203 /* free securedisplay shared memory */ 204 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 205 206 207 } 208 209 static void psp_memory_training_fini(struct psp_context *psp) 210 { 211 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 212 213 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 214 kfree(ctx->sys_cache); 215 ctx->sys_cache = NULL; 216 } 217 218 static int psp_memory_training_init(struct psp_context *psp) 219 { 220 int ret; 221 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 222 223 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 224 DRM_DEBUG("memory training is not supported!\n"); 225 return 0; 226 } 227 228 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 229 if (ctx->sys_cache == NULL) { 230 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 231 ret = -ENOMEM; 232 goto Err_out; 233 } 234 235 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 236 ctx->train_data_size, 237 ctx->p2c_train_data_offset, 238 ctx->c2p_train_data_offset); 239 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 240 return 0; 241 242 Err_out: 243 psp_memory_training_fini(psp); 244 return ret; 245 } 246 247 /* 248 * Helper funciton to query psp runtime database entry 249 * 250 * @adev: amdgpu_device pointer 251 * @entry_type: the type of psp runtime database entry 252 * @db_entry: runtime database entry pointer 253 * 254 * Return false if runtime database doesn't exit or entry is invalid 255 * or true if the specific database entry is found, and copy to @db_entry 256 */ 257 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 258 enum psp_runtime_entry_type entry_type, 259 void *db_entry) 260 { 261 uint64_t db_header_pos, db_dir_pos; 262 struct psp_runtime_data_header db_header = {0}; 263 struct psp_runtime_data_directory db_dir = {0}; 264 bool ret = false; 265 int i; 266 267 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 268 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 269 270 /* read runtime db header from vram */ 271 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 272 sizeof(struct psp_runtime_data_header), false); 273 274 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 275 /* runtime db doesn't exist, exit */ 276 dev_warn(adev->dev, "PSP runtime database doesn't exist\n"); 277 return false; 278 } 279 280 /* read runtime database entry from vram */ 281 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 282 sizeof(struct psp_runtime_data_directory), false); 283 284 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 285 /* invalid db entry count, exit */ 286 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 287 return false; 288 } 289 290 /* look up for requested entry type */ 291 for (i = 0; i < db_dir.entry_count && !ret; i++) { 292 if (db_dir.entry_list[i].entry_type == entry_type) { 293 switch (entry_type) { 294 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 295 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 296 /* invalid db entry size */ 297 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 298 return false; 299 } 300 /* read runtime database entry */ 301 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 302 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 303 ret = true; 304 break; 305 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 306 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 307 /* invalid db entry size */ 308 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 309 return false; 310 } 311 /* read runtime database entry */ 312 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 313 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 314 ret = true; 315 break; 316 default: 317 ret = false; 318 break; 319 } 320 } 321 } 322 323 return ret; 324 } 325 326 static int psp_init_sriov_microcode(struct psp_context *psp) 327 { 328 struct amdgpu_device *adev = psp->adev; 329 int ret = 0; 330 331 switch (adev->ip_versions[MP0_HWIP][0]) { 332 case IP_VERSION(9, 0, 0): 333 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 334 ret = psp_init_cap_microcode(psp, "vega10"); 335 break; 336 case IP_VERSION(11, 0, 9): 337 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 338 ret = psp_init_cap_microcode(psp, "navi12"); 339 break; 340 case IP_VERSION(11, 0, 7): 341 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 342 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 343 break; 344 case IP_VERSION(13, 0, 2): 345 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 346 ret = psp_init_cap_microcode(psp, "aldebaran"); 347 ret &= psp_init_ta_microcode(psp, "aldebaran"); 348 break; 349 case IP_VERSION(13, 0, 0): 350 adev->virt.autoload_ucode_id = 0; 351 break; 352 case IP_VERSION(13, 0, 10): 353 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 354 break; 355 default: 356 BUG(); 357 break; 358 } 359 return ret; 360 } 361 362 static int psp_sw_init(void *handle) 363 { 364 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 365 struct psp_context *psp = &adev->psp; 366 int ret; 367 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 368 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 369 struct psp_runtime_scpm_entry scpm_entry; 370 371 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 372 if (!psp->cmd) { 373 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 374 ret = -ENOMEM; 375 } 376 377 if (amdgpu_sriov_vf(adev)) 378 ret = psp_init_sriov_microcode(psp); 379 else 380 ret = psp_init_microcode(psp); 381 if (ret) { 382 DRM_ERROR("Failed to load psp firmware!\n"); 383 return ret; 384 } 385 386 adev->psp.xgmi_context.supports_extended_data = 387 !adev->gmc.xgmi.connected_to_cpu && 388 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 389 390 memset(&scpm_entry, 0, sizeof(scpm_entry)); 391 if ((psp_get_runtime_db_entry(adev, 392 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 393 &scpm_entry)) && 394 (SCPM_DISABLE != scpm_entry.scpm_status)) { 395 adev->scpm_enabled = true; 396 adev->scpm_status = scpm_entry.scpm_status; 397 } else { 398 adev->scpm_enabled = false; 399 adev->scpm_status = SCPM_DISABLE; 400 } 401 402 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 403 404 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 405 if (psp_get_runtime_db_entry(adev, 406 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 407 &boot_cfg_entry)) { 408 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 409 if ((psp->boot_cfg_bitmask) & 410 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 411 /* If psp runtime database exists, then 412 * only enable two stage memory training 413 * when TWO_STAGE_DRAM_TRAINING bit is set 414 * in runtime database */ 415 mem_training_ctx->enable_mem_training = true; 416 } 417 418 } else { 419 /* If psp runtime database doesn't exist or 420 * is invalid, force enable two stage memory 421 * training */ 422 mem_training_ctx->enable_mem_training = true; 423 } 424 425 if (mem_training_ctx->enable_mem_training) { 426 ret = psp_memory_training_init(psp); 427 if (ret) { 428 DRM_ERROR("Failed to initialize memory training!\n"); 429 return ret; 430 } 431 432 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 433 if (ret) { 434 DRM_ERROR("Failed to process memory training!\n"); 435 return ret; 436 } 437 } 438 439 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 440 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 441 ret= psp_sysfs_init(adev); 442 if (ret) { 443 return ret; 444 } 445 } 446 447 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 448 amdgpu_sriov_vf(adev) ? 449 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 450 &psp->fw_pri_bo, 451 &psp->fw_pri_mc_addr, 452 &psp->fw_pri_buf); 453 if (ret) 454 return ret; 455 456 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 457 AMDGPU_GEM_DOMAIN_VRAM, 458 &psp->fence_buf_bo, 459 &psp->fence_buf_mc_addr, 460 &psp->fence_buf); 461 if (ret) 462 goto failed1; 463 464 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 465 AMDGPU_GEM_DOMAIN_VRAM, 466 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 467 (void **)&psp->cmd_buf_mem); 468 if (ret) 469 goto failed2; 470 471 return 0; 472 473 failed2: 474 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 475 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 476 failed1: 477 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 478 &psp->fence_buf_mc_addr, &psp->fence_buf); 479 return ret; 480 } 481 482 static int psp_sw_fini(void *handle) 483 { 484 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 485 struct psp_context *psp = &adev->psp; 486 struct psp_gfx_cmd_resp *cmd = psp->cmd; 487 488 psp_memory_training_fini(psp); 489 if (psp->sos_fw) { 490 release_firmware(psp->sos_fw); 491 psp->sos_fw = NULL; 492 } 493 if (psp->asd_fw) { 494 release_firmware(psp->asd_fw); 495 psp->asd_fw = NULL; 496 } 497 if (psp->ta_fw) { 498 release_firmware(psp->ta_fw); 499 psp->ta_fw = NULL; 500 } 501 if (psp->cap_fw) { 502 release_firmware(psp->cap_fw); 503 psp->cap_fw = NULL; 504 } 505 if (psp->toc_fw) { 506 release_firmware(psp->toc_fw); 507 psp->toc_fw = NULL; 508 } 509 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 510 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 511 psp_sysfs_fini(adev); 512 513 kfree(cmd); 514 cmd = NULL; 515 516 if (psp->km_ring.ring_mem) 517 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 518 &psp->km_ring.ring_mem_mc_addr, 519 (void **)&psp->km_ring.ring_mem); 520 521 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 522 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 523 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 524 &psp->fence_buf_mc_addr, &psp->fence_buf); 525 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 526 (void **)&psp->cmd_buf_mem); 527 528 return 0; 529 } 530 531 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 532 uint32_t reg_val, uint32_t mask, bool check_changed) 533 { 534 uint32_t val; 535 int i; 536 struct amdgpu_device *adev = psp->adev; 537 538 if (psp->adev->no_hw_access) 539 return 0; 540 541 for (i = 0; i < adev->usec_timeout; i++) { 542 val = RREG32(reg_index); 543 if (check_changed) { 544 if (val != reg_val) 545 return 0; 546 } else { 547 if ((val & mask) == reg_val) 548 return 0; 549 } 550 udelay(1); 551 } 552 553 return -ETIME; 554 } 555 556 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 557 { 558 switch (cmd_id) { 559 case GFX_CMD_ID_LOAD_TA: 560 return "LOAD_TA"; 561 case GFX_CMD_ID_UNLOAD_TA: 562 return "UNLOAD_TA"; 563 case GFX_CMD_ID_INVOKE_CMD: 564 return "INVOKE_CMD"; 565 case GFX_CMD_ID_LOAD_ASD: 566 return "LOAD_ASD"; 567 case GFX_CMD_ID_SETUP_TMR: 568 return "SETUP_TMR"; 569 case GFX_CMD_ID_LOAD_IP_FW: 570 return "LOAD_IP_FW"; 571 case GFX_CMD_ID_DESTROY_TMR: 572 return "DESTROY_TMR"; 573 case GFX_CMD_ID_SAVE_RESTORE: 574 return "SAVE_RESTORE_IP_FW"; 575 case GFX_CMD_ID_SETUP_VMR: 576 return "SETUP_VMR"; 577 case GFX_CMD_ID_DESTROY_VMR: 578 return "DESTROY_VMR"; 579 case GFX_CMD_ID_PROG_REG: 580 return "PROG_REG"; 581 case GFX_CMD_ID_GET_FW_ATTESTATION: 582 return "GET_FW_ATTESTATION"; 583 case GFX_CMD_ID_LOAD_TOC: 584 return "ID_LOAD_TOC"; 585 case GFX_CMD_ID_AUTOLOAD_RLC: 586 return "AUTOLOAD_RLC"; 587 case GFX_CMD_ID_BOOT_CFG: 588 return "BOOT_CFG"; 589 default: 590 return "UNKNOWN CMD"; 591 } 592 } 593 594 static int 595 psp_cmd_submit_buf(struct psp_context *psp, 596 struct amdgpu_firmware_info *ucode, 597 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 598 { 599 int ret; 600 int index, idx; 601 int timeout = 20000; 602 bool ras_intr = false; 603 bool skip_unsupport = false; 604 605 if (psp->adev->no_hw_access) 606 return 0; 607 608 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 609 return 0; 610 611 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 612 613 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 614 615 index = atomic_inc_return(&psp->fence_value); 616 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 617 if (ret) { 618 atomic_dec(&psp->fence_value); 619 goto exit; 620 } 621 622 amdgpu_device_invalidate_hdp(psp->adev, NULL); 623 while (*((unsigned int *)psp->fence_buf) != index) { 624 if (--timeout == 0) 625 break; 626 /* 627 * Shouldn't wait for timeout when err_event_athub occurs, 628 * because gpu reset thread triggered and lock resource should 629 * be released for psp resume sequence. 630 */ 631 ras_intr = amdgpu_ras_intr_triggered(); 632 if (ras_intr) 633 break; 634 usleep_range(10, 100); 635 amdgpu_device_invalidate_hdp(psp->adev, NULL); 636 } 637 638 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 639 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 640 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 641 642 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 643 644 /* In some cases, psp response status is not 0 even there is no 645 * problem while the command is submitted. Some version of PSP FW 646 * doesn't write 0 to that field. 647 * So here we would like to only print a warning instead of an error 648 * during psp initialization to avoid breaking hw_init and it doesn't 649 * return -EINVAL. 650 */ 651 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 652 if (ucode) 653 DRM_WARN("failed to load ucode %s(0x%X) ", 654 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 655 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 656 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 657 psp->cmd_buf_mem->resp.status); 658 /* If any firmware (including CAP) load fails under SRIOV, it should 659 * return failure to stop the VF from initializing. 660 * Also return failure in case of timeout 661 */ 662 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 663 ret = -EINVAL; 664 goto exit; 665 } 666 } 667 668 if (ucode) { 669 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 670 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 671 } 672 673 exit: 674 drm_dev_exit(idx); 675 return ret; 676 } 677 678 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 679 { 680 struct psp_gfx_cmd_resp *cmd = psp->cmd; 681 682 mutex_lock(&psp->mutex); 683 684 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 685 686 return cmd; 687 } 688 689 static void release_psp_cmd_buf(struct psp_context *psp) 690 { 691 mutex_unlock(&psp->mutex); 692 } 693 694 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 695 struct psp_gfx_cmd_resp *cmd, 696 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 697 { 698 struct amdgpu_device *adev = psp->adev; 699 uint32_t size = amdgpu_bo_size(tmr_bo); 700 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 701 702 if (amdgpu_sriov_vf(psp->adev)) 703 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 704 else 705 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 706 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 707 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 708 cmd->cmd.cmd_setup_tmr.buf_size = size; 709 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 710 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 711 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 712 } 713 714 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 715 uint64_t pri_buf_mc, uint32_t size) 716 { 717 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 718 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 719 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 720 cmd->cmd.cmd_load_toc.toc_size = size; 721 } 722 723 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 724 static int psp_load_toc(struct psp_context *psp, 725 uint32_t *tmr_size) 726 { 727 int ret; 728 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 729 730 /* Copy toc to psp firmware private buffer */ 731 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 732 733 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 734 735 ret = psp_cmd_submit_buf(psp, NULL, cmd, 736 psp->fence_buf_mc_addr); 737 if (!ret) 738 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 739 740 release_psp_cmd_buf(psp); 741 742 return ret; 743 } 744 745 /* Set up Trusted Memory Region */ 746 static int psp_tmr_init(struct psp_context *psp) 747 { 748 int ret = 0; 749 int tmr_size; 750 void *tmr_buf; 751 void **pptr; 752 753 /* 754 * According to HW engineer, they prefer the TMR address be "naturally 755 * aligned" , e.g. the start address be an integer divide of TMR size. 756 * 757 * Note: this memory need be reserved till the driver 758 * uninitializes. 759 */ 760 tmr_size = PSP_TMR_SIZE(psp->adev); 761 762 /* For ASICs support RLC autoload, psp will parse the toc 763 * and calculate the total size of TMR needed */ 764 if (!amdgpu_sriov_vf(psp->adev) && 765 psp->toc.start_addr && 766 psp->toc.size_bytes && 767 psp->fw_pri_buf) { 768 ret = psp_load_toc(psp, &tmr_size); 769 if (ret) { 770 DRM_ERROR("Failed to load toc\n"); 771 return ret; 772 } 773 } 774 775 if (!psp->tmr_bo) { 776 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 777 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT, 778 AMDGPU_GEM_DOMAIN_VRAM, 779 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 780 } 781 782 return ret; 783 } 784 785 static bool psp_skip_tmr(struct psp_context *psp) 786 { 787 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 788 case IP_VERSION(11, 0, 9): 789 case IP_VERSION(11, 0, 7): 790 case IP_VERSION(13, 0, 2): 791 case IP_VERSION(13, 0, 10): 792 return true; 793 default: 794 return false; 795 } 796 } 797 798 static int psp_tmr_load(struct psp_context *psp) 799 { 800 int ret; 801 struct psp_gfx_cmd_resp *cmd; 802 803 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 804 * Already set up by host driver. 805 */ 806 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 807 return 0; 808 809 cmd = acquire_psp_cmd_buf(psp); 810 811 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 812 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 813 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 814 815 ret = psp_cmd_submit_buf(psp, NULL, cmd, 816 psp->fence_buf_mc_addr); 817 818 release_psp_cmd_buf(psp); 819 820 return ret; 821 } 822 823 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 824 struct psp_gfx_cmd_resp *cmd) 825 { 826 if (amdgpu_sriov_vf(psp->adev)) 827 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 828 else 829 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 830 } 831 832 static int psp_tmr_unload(struct psp_context *psp) 833 { 834 int ret; 835 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 836 837 psp_prep_tmr_unload_cmd_buf(psp, cmd); 838 dev_info(psp->adev->dev, "free PSP TMR buffer\n"); 839 840 ret = psp_cmd_submit_buf(psp, NULL, cmd, 841 psp->fence_buf_mc_addr); 842 843 release_psp_cmd_buf(psp); 844 845 return ret; 846 } 847 848 static int psp_tmr_terminate(struct psp_context *psp) 849 { 850 return psp_tmr_unload(psp); 851 } 852 853 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 854 uint64_t *output_ptr) 855 { 856 int ret; 857 struct psp_gfx_cmd_resp *cmd; 858 859 if (!output_ptr) 860 return -EINVAL; 861 862 if (amdgpu_sriov_vf(psp->adev)) 863 return 0; 864 865 cmd = acquire_psp_cmd_buf(psp); 866 867 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 868 869 ret = psp_cmd_submit_buf(psp, NULL, cmd, 870 psp->fence_buf_mc_addr); 871 872 if (!ret) { 873 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 874 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 875 } 876 877 release_psp_cmd_buf(psp); 878 879 return ret; 880 } 881 882 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 883 { 884 struct psp_context *psp = &adev->psp; 885 struct psp_gfx_cmd_resp *cmd; 886 int ret; 887 888 if (amdgpu_sriov_vf(adev)) 889 return 0; 890 891 cmd = acquire_psp_cmd_buf(psp); 892 893 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 894 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 895 896 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 897 if (!ret) { 898 *boot_cfg = 899 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 900 } 901 902 release_psp_cmd_buf(psp); 903 904 return ret; 905 } 906 907 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 908 { 909 int ret; 910 struct psp_context *psp = &adev->psp; 911 struct psp_gfx_cmd_resp *cmd; 912 913 if (amdgpu_sriov_vf(adev)) 914 return 0; 915 916 cmd = acquire_psp_cmd_buf(psp); 917 918 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 919 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 920 cmd->cmd.boot_cfg.boot_config = boot_cfg; 921 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 922 923 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 924 925 release_psp_cmd_buf(psp); 926 927 return ret; 928 } 929 930 static int psp_rl_load(struct amdgpu_device *adev) 931 { 932 int ret; 933 struct psp_context *psp = &adev->psp; 934 struct psp_gfx_cmd_resp *cmd; 935 936 if (!is_psp_fw_valid(psp->rl)) 937 return 0; 938 939 cmd = acquire_psp_cmd_buf(psp); 940 941 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 942 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 943 944 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 945 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 946 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 947 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 948 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 949 950 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 951 952 release_psp_cmd_buf(psp); 953 954 return ret; 955 } 956 957 static int psp_asd_initialize(struct psp_context *psp) 958 { 959 int ret; 960 961 /* If PSP version doesn't match ASD version, asd loading will be failed. 962 * add workaround to bypass it for sriov now. 963 * TODO: add version check to make it common 964 */ 965 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 966 return 0; 967 968 psp->asd_context.mem_context.shared_mc_addr = 0; 969 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 970 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 971 972 ret = psp_ta_load(psp, &psp->asd_context); 973 if (!ret) 974 psp->asd_context.initialized = true; 975 976 return ret; 977 } 978 979 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 980 uint32_t session_id) 981 { 982 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 983 cmd->cmd.cmd_unload_ta.session_id = session_id; 984 } 985 986 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 987 { 988 int ret; 989 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 990 991 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 992 993 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 994 995 release_psp_cmd_buf(psp); 996 997 return ret; 998 } 999 1000 static int psp_asd_terminate(struct psp_context *psp) 1001 { 1002 int ret; 1003 1004 if (amdgpu_sriov_vf(psp->adev)) 1005 return 0; 1006 1007 if (!psp->asd_context.initialized) 1008 return 0; 1009 1010 ret = psp_ta_unload(psp, &psp->asd_context); 1011 if (!ret) 1012 psp->asd_context.initialized = false; 1013 1014 return ret; 1015 } 1016 1017 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1018 uint32_t id, uint32_t value) 1019 { 1020 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1021 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1022 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1023 } 1024 1025 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1026 uint32_t value) 1027 { 1028 struct psp_gfx_cmd_resp *cmd; 1029 int ret = 0; 1030 1031 if (reg >= PSP_REG_LAST) 1032 return -EINVAL; 1033 1034 cmd = acquire_psp_cmd_buf(psp); 1035 1036 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1037 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1038 if (ret) 1039 DRM_ERROR("PSP failed to program reg id %d", reg); 1040 1041 release_psp_cmd_buf(psp); 1042 1043 return ret; 1044 } 1045 1046 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1047 uint64_t ta_bin_mc, 1048 struct ta_context *context) 1049 { 1050 cmd->cmd_id = context->ta_load_type; 1051 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1052 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1053 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1054 1055 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1056 lower_32_bits(context->mem_context.shared_mc_addr); 1057 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1058 upper_32_bits(context->mem_context.shared_mc_addr); 1059 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1060 } 1061 1062 int psp_ta_init_shared_buf(struct psp_context *psp, 1063 struct ta_mem_context *mem_ctx) 1064 { 1065 /* 1066 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1067 * physical) for ta to host memory 1068 */ 1069 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1070 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1071 &mem_ctx->shared_bo, 1072 &mem_ctx->shared_mc_addr, 1073 &mem_ctx->shared_buf); 1074 } 1075 1076 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1077 uint32_t ta_cmd_id, 1078 struct ta_context *context) 1079 { 1080 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1081 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id; 1082 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1083 1084 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1; 1085 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size; 1086 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size; 1087 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo = 1088 lower_32_bits(context->mem_context.shared_mc_addr); 1089 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi = 1090 upper_32_bits(context->mem_context.shared_mc_addr); 1091 } 1092 1093 int psp_ta_invoke_indirect(struct psp_context *psp, 1094 uint32_t ta_cmd_id, 1095 struct ta_context *context) 1096 { 1097 int ret; 1098 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1099 1100 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context); 1101 1102 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1103 psp->fence_buf_mc_addr); 1104 1105 context->resp_status = cmd->resp.status; 1106 1107 release_psp_cmd_buf(psp); 1108 1109 return ret; 1110 } 1111 1112 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1113 uint32_t ta_cmd_id, 1114 uint32_t session_id) 1115 { 1116 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1117 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1118 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1119 } 1120 1121 int psp_ta_invoke(struct psp_context *psp, 1122 uint32_t ta_cmd_id, 1123 struct ta_context *context) 1124 { 1125 int ret; 1126 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1127 1128 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1129 1130 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1131 psp->fence_buf_mc_addr); 1132 1133 context->resp_status = cmd->resp.status; 1134 1135 release_psp_cmd_buf(psp); 1136 1137 return ret; 1138 } 1139 1140 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1141 { 1142 int ret; 1143 struct psp_gfx_cmd_resp *cmd; 1144 1145 cmd = acquire_psp_cmd_buf(psp); 1146 1147 psp_copy_fw(psp, context->bin_desc.start_addr, 1148 context->bin_desc.size_bytes); 1149 1150 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1151 1152 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1153 psp->fence_buf_mc_addr); 1154 1155 context->resp_status = cmd->resp.status; 1156 1157 if (!ret) { 1158 context->session_id = cmd->resp.session_id; 1159 } 1160 1161 release_psp_cmd_buf(psp); 1162 1163 return ret; 1164 } 1165 1166 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1167 { 1168 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1169 } 1170 1171 int psp_xgmi_terminate(struct psp_context *psp) 1172 { 1173 int ret; 1174 struct amdgpu_device *adev = psp->adev; 1175 1176 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1177 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1178 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1179 adev->gmc.xgmi.connected_to_cpu)) 1180 return 0; 1181 1182 if (!psp->xgmi_context.context.initialized) 1183 return 0; 1184 1185 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1186 1187 psp->xgmi_context.context.initialized = false; 1188 1189 return ret; 1190 } 1191 1192 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1193 { 1194 struct ta_xgmi_shared_memory *xgmi_cmd; 1195 int ret; 1196 1197 if (!psp->ta_fw || 1198 !psp->xgmi_context.context.bin_desc.size_bytes || 1199 !psp->xgmi_context.context.bin_desc.start_addr) 1200 return -ENOENT; 1201 1202 if (!load_ta) 1203 goto invoke; 1204 1205 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1206 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1207 1208 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1209 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1210 if (ret) 1211 return ret; 1212 } 1213 1214 /* Load XGMI TA */ 1215 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1216 if (!ret) 1217 psp->xgmi_context.context.initialized = true; 1218 else 1219 return ret; 1220 1221 invoke: 1222 /* Initialize XGMI session */ 1223 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1224 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1225 xgmi_cmd->flag_extend_link_record = set_extended_data; 1226 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1227 1228 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1229 1230 return ret; 1231 } 1232 1233 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1234 { 1235 struct ta_xgmi_shared_memory *xgmi_cmd; 1236 int ret; 1237 1238 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1239 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1240 1241 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1242 1243 /* Invoke xgmi ta to get hive id */ 1244 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1245 if (ret) 1246 return ret; 1247 1248 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1249 1250 return 0; 1251 } 1252 1253 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1254 { 1255 struct ta_xgmi_shared_memory *xgmi_cmd; 1256 int ret; 1257 1258 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1259 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1260 1261 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1262 1263 /* Invoke xgmi ta to get the node id */ 1264 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1265 if (ret) 1266 return ret; 1267 1268 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1269 1270 return 0; 1271 } 1272 1273 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1274 { 1275 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1276 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1277 } 1278 1279 /* 1280 * Chips that support extended topology information require the driver to 1281 * reflect topology information in the opposite direction. This is 1282 * because the TA has already exceeded its link record limit and if the 1283 * TA holds bi-directional information, the driver would have to do 1284 * multiple fetches instead of just two. 1285 */ 1286 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1287 struct psp_xgmi_node_info node_info) 1288 { 1289 struct amdgpu_device *mirror_adev; 1290 struct amdgpu_hive_info *hive; 1291 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1292 uint64_t dst_node_id = node_info.node_id; 1293 uint8_t dst_num_hops = node_info.num_hops; 1294 uint8_t dst_num_links = node_info.num_links; 1295 1296 hive = amdgpu_get_xgmi_hive(psp->adev); 1297 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1298 struct psp_xgmi_topology_info *mirror_top_info; 1299 int j; 1300 1301 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1302 continue; 1303 1304 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1305 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1306 if (mirror_top_info->nodes[j].node_id != src_node_id) 1307 continue; 1308 1309 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1310 /* 1311 * prevent 0 num_links value re-reflection since reflection 1312 * criteria is based on num_hops (direct or indirect). 1313 * 1314 */ 1315 if (dst_num_links) 1316 mirror_top_info->nodes[j].num_links = dst_num_links; 1317 1318 break; 1319 } 1320 1321 break; 1322 } 1323 1324 amdgpu_put_xgmi_hive(hive); 1325 } 1326 1327 int psp_xgmi_get_topology_info(struct psp_context *psp, 1328 int number_devices, 1329 struct psp_xgmi_topology_info *topology, 1330 bool get_extended_data) 1331 { 1332 struct ta_xgmi_shared_memory *xgmi_cmd; 1333 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1334 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1335 int i; 1336 int ret; 1337 1338 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1339 return -EINVAL; 1340 1341 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1342 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1343 xgmi_cmd->flag_extend_link_record = get_extended_data; 1344 1345 /* Fill in the shared memory with topology information as input */ 1346 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1347 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1348 topology_info_input->num_nodes = number_devices; 1349 1350 for (i = 0; i < topology_info_input->num_nodes; i++) { 1351 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1352 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1353 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1354 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1355 } 1356 1357 /* Invoke xgmi ta to get the topology information */ 1358 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1359 if (ret) 1360 return ret; 1361 1362 /* Read the output topology information from the shared memory */ 1363 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1364 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1365 for (i = 0; i < topology->num_nodes; i++) { 1366 /* extended data will either be 0 or equal to non-extended data */ 1367 if (topology_info_output->nodes[i].num_hops) 1368 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1369 1370 /* non-extended data gets everything here so no need to update */ 1371 if (!get_extended_data) { 1372 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1373 topology->nodes[i].is_sharing_enabled = 1374 topology_info_output->nodes[i].is_sharing_enabled; 1375 topology->nodes[i].sdma_engine = 1376 topology_info_output->nodes[i].sdma_engine; 1377 } 1378 1379 } 1380 1381 /* Invoke xgmi ta again to get the link information */ 1382 if (psp_xgmi_peer_link_info_supported(psp)) { 1383 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1384 1385 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1386 1387 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1388 1389 if (ret) 1390 return ret; 1391 1392 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1393 for (i = 0; i < topology->num_nodes; i++) { 1394 /* accumulate num_links on extended data */ 1395 topology->nodes[i].num_links = get_extended_data ? 1396 topology->nodes[i].num_links + 1397 link_info_output->nodes[i].num_links : 1398 link_info_output->nodes[i].num_links; 1399 1400 /* reflect the topology information for bi-directionality */ 1401 if (psp->xgmi_context.supports_extended_data && 1402 get_extended_data && topology->nodes[i].num_hops) 1403 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1404 } 1405 } 1406 1407 return 0; 1408 } 1409 1410 int psp_xgmi_set_topology_info(struct psp_context *psp, 1411 int number_devices, 1412 struct psp_xgmi_topology_info *topology) 1413 { 1414 struct ta_xgmi_shared_memory *xgmi_cmd; 1415 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1416 int i; 1417 1418 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1419 return -EINVAL; 1420 1421 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1422 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1423 1424 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1425 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1426 topology_info_input->num_nodes = number_devices; 1427 1428 for (i = 0; i < topology_info_input->num_nodes; i++) { 1429 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1430 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1431 topology_info_input->nodes[i].is_sharing_enabled = 1; 1432 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1433 } 1434 1435 /* Invoke xgmi ta to set topology information */ 1436 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1437 } 1438 1439 // ras begin 1440 static void psp_ras_ta_check_status(struct psp_context *psp) 1441 { 1442 struct ta_ras_shared_memory *ras_cmd = 1443 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1444 1445 switch (ras_cmd->ras_status) { 1446 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1447 dev_warn(psp->adev->dev, 1448 "RAS WARNING: cmd failed due to unsupported ip\n"); 1449 break; 1450 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1451 dev_warn(psp->adev->dev, 1452 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1453 break; 1454 case TA_RAS_STATUS__SUCCESS: 1455 break; 1456 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1457 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1458 dev_warn(psp->adev->dev, 1459 "RAS WARNING: Inject error to critical region is not allowed\n"); 1460 break; 1461 default: 1462 dev_warn(psp->adev->dev, 1463 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1464 break; 1465 } 1466 } 1467 1468 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1469 { 1470 struct ta_ras_shared_memory *ras_cmd; 1471 int ret; 1472 1473 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1474 1475 /* 1476 * TODO: bypass the loading in sriov for now 1477 */ 1478 if (amdgpu_sriov_vf(psp->adev)) 1479 return 0; 1480 1481 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1482 1483 if (amdgpu_ras_intr_triggered()) 1484 return ret; 1485 1486 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1487 { 1488 DRM_WARN("RAS: Unsupported Interface"); 1489 return -EINVAL; 1490 } 1491 1492 if (!ret) { 1493 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1494 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1495 1496 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1497 } 1498 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1499 dev_warn(psp->adev->dev, 1500 "RAS internal register access blocked\n"); 1501 1502 psp_ras_ta_check_status(psp); 1503 } 1504 1505 return ret; 1506 } 1507 1508 int psp_ras_enable_features(struct psp_context *psp, 1509 union ta_ras_cmd_input *info, bool enable) 1510 { 1511 struct ta_ras_shared_memory *ras_cmd; 1512 int ret; 1513 1514 if (!psp->ras_context.context.initialized) 1515 return -EINVAL; 1516 1517 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1518 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1519 1520 if (enable) 1521 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1522 else 1523 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1524 1525 ras_cmd->ras_in_message = *info; 1526 1527 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1528 if (ret) 1529 return -EINVAL; 1530 1531 return 0; 1532 } 1533 1534 int psp_ras_terminate(struct psp_context *psp) 1535 { 1536 int ret; 1537 1538 /* 1539 * TODO: bypass the terminate in sriov for now 1540 */ 1541 if (amdgpu_sriov_vf(psp->adev)) 1542 return 0; 1543 1544 if (!psp->ras_context.context.initialized) 1545 return 0; 1546 1547 ret = psp_ta_unload(psp, &psp->ras_context.context); 1548 1549 psp->ras_context.context.initialized = false; 1550 1551 return ret; 1552 } 1553 1554 static int psp_ras_initialize(struct psp_context *psp) 1555 { 1556 int ret; 1557 uint32_t boot_cfg = 0xFF; 1558 struct amdgpu_device *adev = psp->adev; 1559 struct ta_ras_shared_memory *ras_cmd; 1560 1561 /* 1562 * TODO: bypass the initialize in sriov for now 1563 */ 1564 if (amdgpu_sriov_vf(adev)) 1565 return 0; 1566 1567 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1568 !adev->psp.ras_context.context.bin_desc.start_addr) { 1569 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1570 return 0; 1571 } 1572 1573 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1574 /* query GECC enablement status from boot config 1575 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1576 */ 1577 ret = psp_boot_config_get(adev, &boot_cfg); 1578 if (ret) 1579 dev_warn(adev->dev, "PSP get boot config failed\n"); 1580 1581 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1582 if (!boot_cfg) { 1583 dev_info(adev->dev, "GECC is disabled\n"); 1584 } else { 1585 /* disable GECC in next boot cycle if ras is 1586 * disabled by module parameter amdgpu_ras_enable 1587 * and/or amdgpu_ras_mask, or boot_config_get call 1588 * is failed 1589 */ 1590 ret = psp_boot_config_set(adev, 0); 1591 if (ret) 1592 dev_warn(adev->dev, "PSP set boot config failed\n"); 1593 else 1594 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1595 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1596 } 1597 } else { 1598 if (1 == boot_cfg) { 1599 dev_info(adev->dev, "GECC is enabled\n"); 1600 } else { 1601 /* enable GECC in next boot cycle if it is disabled 1602 * in boot config, or force enable GECC if failed to 1603 * get boot configuration 1604 */ 1605 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1606 if (ret) 1607 dev_warn(adev->dev, "PSP set boot config failed\n"); 1608 else 1609 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1610 } 1611 } 1612 } 1613 1614 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1615 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1616 1617 if (!psp->ras_context.context.initialized) { 1618 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1619 if (ret) 1620 return ret; 1621 } 1622 1623 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1624 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1625 1626 if (amdgpu_ras_is_poison_mode_supported(adev)) 1627 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1628 if (!adev->gmc.xgmi.connected_to_cpu) 1629 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1630 1631 ret = psp_ta_load(psp, &psp->ras_context.context); 1632 1633 if (!ret && !ras_cmd->ras_status) 1634 psp->ras_context.context.initialized = true; 1635 else { 1636 if (ras_cmd->ras_status) 1637 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1638 amdgpu_ras_fini(psp->adev); 1639 } 1640 1641 return ret; 1642 } 1643 1644 int psp_ras_trigger_error(struct psp_context *psp, 1645 struct ta_ras_trigger_error_input *info) 1646 { 1647 struct ta_ras_shared_memory *ras_cmd; 1648 int ret; 1649 1650 if (!psp->ras_context.context.initialized) 1651 return -EINVAL; 1652 1653 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1654 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1655 1656 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1657 ras_cmd->ras_in_message.trigger_error = *info; 1658 1659 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1660 if (ret) 1661 return -EINVAL; 1662 1663 /* If err_event_athub occurs error inject was successful, however 1664 return status from TA is no long reliable */ 1665 if (amdgpu_ras_intr_triggered()) 1666 return 0; 1667 1668 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1669 return -EACCES; 1670 else if (ras_cmd->ras_status) 1671 return -EINVAL; 1672 1673 return 0; 1674 } 1675 // ras end 1676 1677 // HDCP start 1678 static int psp_hdcp_initialize(struct psp_context *psp) 1679 { 1680 int ret; 1681 1682 /* 1683 * TODO: bypass the initialize in sriov for now 1684 */ 1685 if (amdgpu_sriov_vf(psp->adev)) 1686 return 0; 1687 1688 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1689 !psp->hdcp_context.context.bin_desc.start_addr) { 1690 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1691 return 0; 1692 } 1693 1694 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1695 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1696 1697 if (!psp->hdcp_context.context.initialized) { 1698 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1699 if (ret) 1700 return ret; 1701 } 1702 1703 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1704 if (!ret) { 1705 psp->hdcp_context.context.initialized = true; 1706 mutex_init(&psp->hdcp_context.mutex); 1707 } 1708 1709 return ret; 1710 } 1711 1712 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1713 { 1714 /* 1715 * TODO: bypass the loading in sriov for now 1716 */ 1717 if (amdgpu_sriov_vf(psp->adev)) 1718 return 0; 1719 1720 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1721 } 1722 1723 static int psp_hdcp_terminate(struct psp_context *psp) 1724 { 1725 int ret; 1726 1727 /* 1728 * TODO: bypass the terminate in sriov for now 1729 */ 1730 if (amdgpu_sriov_vf(psp->adev)) 1731 return 0; 1732 1733 if (!psp->hdcp_context.context.initialized) 1734 return 0; 1735 1736 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1737 1738 psp->hdcp_context.context.initialized = false; 1739 1740 return ret; 1741 } 1742 // HDCP end 1743 1744 // DTM start 1745 static int psp_dtm_initialize(struct psp_context *psp) 1746 { 1747 int ret; 1748 1749 /* 1750 * TODO: bypass the initialize in sriov for now 1751 */ 1752 if (amdgpu_sriov_vf(psp->adev)) 1753 return 0; 1754 1755 if (!psp->dtm_context.context.bin_desc.size_bytes || 1756 !psp->dtm_context.context.bin_desc.start_addr) { 1757 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1758 return 0; 1759 } 1760 1761 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1762 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1763 1764 if (!psp->dtm_context.context.initialized) { 1765 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1766 if (ret) 1767 return ret; 1768 } 1769 1770 ret = psp_ta_load(psp, &psp->dtm_context.context); 1771 if (!ret) { 1772 psp->dtm_context.context.initialized = true; 1773 mutex_init(&psp->dtm_context.mutex); 1774 } 1775 1776 return ret; 1777 } 1778 1779 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1780 { 1781 /* 1782 * TODO: bypass the loading in sriov for now 1783 */ 1784 if (amdgpu_sriov_vf(psp->adev)) 1785 return 0; 1786 1787 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1788 } 1789 1790 static int psp_dtm_terminate(struct psp_context *psp) 1791 { 1792 int ret; 1793 1794 /* 1795 * TODO: bypass the terminate in sriov for now 1796 */ 1797 if (amdgpu_sriov_vf(psp->adev)) 1798 return 0; 1799 1800 if (!psp->dtm_context.context.initialized) 1801 return 0; 1802 1803 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1804 1805 psp->dtm_context.context.initialized = false; 1806 1807 return ret; 1808 } 1809 // DTM end 1810 1811 // RAP start 1812 static int psp_rap_initialize(struct psp_context *psp) 1813 { 1814 int ret; 1815 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1816 1817 /* 1818 * TODO: bypass the initialize in sriov for now 1819 */ 1820 if (amdgpu_sriov_vf(psp->adev)) 1821 return 0; 1822 1823 if (!psp->rap_context.context.bin_desc.size_bytes || 1824 !psp->rap_context.context.bin_desc.start_addr) { 1825 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1826 return 0; 1827 } 1828 1829 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1830 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1831 1832 if (!psp->rap_context.context.initialized) { 1833 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1834 if (ret) 1835 return ret; 1836 } 1837 1838 ret = psp_ta_load(psp, &psp->rap_context.context); 1839 if (!ret) { 1840 psp->rap_context.context.initialized = true; 1841 mutex_init(&psp->rap_context.mutex); 1842 } else 1843 return ret; 1844 1845 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1846 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1847 psp_rap_terminate(psp); 1848 /* free rap shared memory */ 1849 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1850 1851 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1852 ret, status); 1853 1854 return ret; 1855 } 1856 1857 return 0; 1858 } 1859 1860 static int psp_rap_terminate(struct psp_context *psp) 1861 { 1862 int ret; 1863 1864 if (!psp->rap_context.context.initialized) 1865 return 0; 1866 1867 ret = psp_ta_unload(psp, &psp->rap_context.context); 1868 1869 psp->rap_context.context.initialized = false; 1870 1871 return ret; 1872 } 1873 1874 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1875 { 1876 struct ta_rap_shared_memory *rap_cmd; 1877 int ret = 0; 1878 1879 if (!psp->rap_context.context.initialized) 1880 return 0; 1881 1882 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1883 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1884 return -EINVAL; 1885 1886 mutex_lock(&psp->rap_context.mutex); 1887 1888 rap_cmd = (struct ta_rap_shared_memory *) 1889 psp->rap_context.context.mem_context.shared_buf; 1890 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1891 1892 rap_cmd->cmd_id = ta_cmd_id; 1893 rap_cmd->validation_method_id = METHOD_A; 1894 1895 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1896 if (ret) 1897 goto out_unlock; 1898 1899 if (status) 1900 *status = rap_cmd->rap_status; 1901 1902 out_unlock: 1903 mutex_unlock(&psp->rap_context.mutex); 1904 1905 return ret; 1906 } 1907 // RAP end 1908 1909 /* securedisplay start */ 1910 static int psp_securedisplay_initialize(struct psp_context *psp) 1911 { 1912 int ret; 1913 struct securedisplay_cmd *securedisplay_cmd; 1914 1915 /* 1916 * TODO: bypass the initialize in sriov for now 1917 */ 1918 if (amdgpu_sriov_vf(psp->adev)) 1919 return 0; 1920 1921 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1922 !psp->securedisplay_context.context.bin_desc.start_addr) { 1923 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1924 return 0; 1925 } 1926 1927 psp->securedisplay_context.context.mem_context.shared_mem_size = 1928 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1929 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1930 1931 if (!psp->securedisplay_context.context.initialized) { 1932 ret = psp_ta_init_shared_buf(psp, 1933 &psp->securedisplay_context.context.mem_context); 1934 if (ret) 1935 return ret; 1936 } 1937 1938 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1939 if (!ret) { 1940 psp->securedisplay_context.context.initialized = true; 1941 mutex_init(&psp->securedisplay_context.mutex); 1942 } else 1943 return ret; 1944 1945 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1946 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1947 1948 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1949 if (ret) { 1950 psp_securedisplay_terminate(psp); 1951 /* free securedisplay shared memory */ 1952 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1953 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1954 return -EINVAL; 1955 } 1956 1957 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1958 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1959 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1960 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1961 } 1962 1963 return 0; 1964 } 1965 1966 static int psp_securedisplay_terminate(struct psp_context *psp) 1967 { 1968 int ret; 1969 1970 /* 1971 * TODO:bypass the terminate in sriov for now 1972 */ 1973 if (amdgpu_sriov_vf(psp->adev)) 1974 return 0; 1975 1976 if (!psp->securedisplay_context.context.initialized) 1977 return 0; 1978 1979 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1980 1981 psp->securedisplay_context.context.initialized = false; 1982 1983 return ret; 1984 } 1985 1986 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1987 { 1988 int ret; 1989 1990 if (!psp->securedisplay_context.context.initialized) 1991 return -EINVAL; 1992 1993 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 1994 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 1995 return -EINVAL; 1996 1997 mutex_lock(&psp->securedisplay_context.mutex); 1998 1999 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2000 2001 mutex_unlock(&psp->securedisplay_context.mutex); 2002 2003 return ret; 2004 } 2005 /* SECUREDISPLAY end */ 2006 2007 static int psp_hw_start(struct psp_context *psp) 2008 { 2009 struct amdgpu_device *adev = psp->adev; 2010 int ret; 2011 2012 if (!amdgpu_sriov_vf(adev)) { 2013 if ((is_psp_fw_valid(psp->kdb)) && 2014 (psp->funcs->bootloader_load_kdb != NULL)) { 2015 ret = psp_bootloader_load_kdb(psp); 2016 if (ret) { 2017 DRM_ERROR("PSP load kdb failed!\n"); 2018 return ret; 2019 } 2020 } 2021 2022 if ((is_psp_fw_valid(psp->spl)) && 2023 (psp->funcs->bootloader_load_spl != NULL)) { 2024 ret = psp_bootloader_load_spl(psp); 2025 if (ret) { 2026 DRM_ERROR("PSP load spl failed!\n"); 2027 return ret; 2028 } 2029 } 2030 2031 if ((is_psp_fw_valid(psp->sys)) && 2032 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2033 ret = psp_bootloader_load_sysdrv(psp); 2034 if (ret) { 2035 DRM_ERROR("PSP load sys drv failed!\n"); 2036 return ret; 2037 } 2038 } 2039 2040 if ((is_psp_fw_valid(psp->soc_drv)) && 2041 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2042 ret = psp_bootloader_load_soc_drv(psp); 2043 if (ret) { 2044 DRM_ERROR("PSP load soc drv failed!\n"); 2045 return ret; 2046 } 2047 } 2048 2049 if ((is_psp_fw_valid(psp->intf_drv)) && 2050 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2051 ret = psp_bootloader_load_intf_drv(psp); 2052 if (ret) { 2053 DRM_ERROR("PSP load intf drv failed!\n"); 2054 return ret; 2055 } 2056 } 2057 2058 if ((is_psp_fw_valid(psp->dbg_drv)) && 2059 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2060 ret = psp_bootloader_load_dbg_drv(psp); 2061 if (ret) { 2062 DRM_ERROR("PSP load dbg drv failed!\n"); 2063 return ret; 2064 } 2065 } 2066 2067 if ((is_psp_fw_valid(psp->ras_drv)) && 2068 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2069 ret = psp_bootloader_load_ras_drv(psp); 2070 if (ret) { 2071 DRM_ERROR("PSP load ras_drv failed!\n"); 2072 return ret; 2073 } 2074 } 2075 2076 if ((is_psp_fw_valid(psp->sos)) && 2077 (psp->funcs->bootloader_load_sos != NULL)) { 2078 ret = psp_bootloader_load_sos(psp); 2079 if (ret) { 2080 DRM_ERROR("PSP load sos failed!\n"); 2081 return ret; 2082 } 2083 } 2084 } 2085 2086 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2087 if (ret) { 2088 DRM_ERROR("PSP create ring failed!\n"); 2089 return ret; 2090 } 2091 2092 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2093 goto skip_pin_bo; 2094 2095 ret = psp_tmr_init(psp); 2096 if (ret) { 2097 DRM_ERROR("PSP tmr init failed!\n"); 2098 return ret; 2099 } 2100 2101 skip_pin_bo: 2102 /* 2103 * For ASICs with DF Cstate management centralized 2104 * to PMFW, TMR setup should be performed after PMFW 2105 * loaded and before other non-psp firmware loaded. 2106 */ 2107 if (psp->pmfw_centralized_cstate_management) { 2108 ret = psp_load_smu_fw(psp); 2109 if (ret) 2110 return ret; 2111 } 2112 2113 ret = psp_tmr_load(psp); 2114 if (ret) { 2115 DRM_ERROR("PSP load tmr failed!\n"); 2116 return ret; 2117 } 2118 2119 return 0; 2120 } 2121 2122 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2123 enum psp_gfx_fw_type *type) 2124 { 2125 switch (ucode->ucode_id) { 2126 case AMDGPU_UCODE_ID_CAP: 2127 *type = GFX_FW_TYPE_CAP; 2128 break; 2129 case AMDGPU_UCODE_ID_SDMA0: 2130 *type = GFX_FW_TYPE_SDMA0; 2131 break; 2132 case AMDGPU_UCODE_ID_SDMA1: 2133 *type = GFX_FW_TYPE_SDMA1; 2134 break; 2135 case AMDGPU_UCODE_ID_SDMA2: 2136 *type = GFX_FW_TYPE_SDMA2; 2137 break; 2138 case AMDGPU_UCODE_ID_SDMA3: 2139 *type = GFX_FW_TYPE_SDMA3; 2140 break; 2141 case AMDGPU_UCODE_ID_SDMA4: 2142 *type = GFX_FW_TYPE_SDMA4; 2143 break; 2144 case AMDGPU_UCODE_ID_SDMA5: 2145 *type = GFX_FW_TYPE_SDMA5; 2146 break; 2147 case AMDGPU_UCODE_ID_SDMA6: 2148 *type = GFX_FW_TYPE_SDMA6; 2149 break; 2150 case AMDGPU_UCODE_ID_SDMA7: 2151 *type = GFX_FW_TYPE_SDMA7; 2152 break; 2153 case AMDGPU_UCODE_ID_CP_MES: 2154 *type = GFX_FW_TYPE_CP_MES; 2155 break; 2156 case AMDGPU_UCODE_ID_CP_MES_DATA: 2157 *type = GFX_FW_TYPE_MES_STACK; 2158 break; 2159 case AMDGPU_UCODE_ID_CP_MES1: 2160 *type = GFX_FW_TYPE_CP_MES_KIQ; 2161 break; 2162 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2163 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2164 break; 2165 case AMDGPU_UCODE_ID_CP_CE: 2166 *type = GFX_FW_TYPE_CP_CE; 2167 break; 2168 case AMDGPU_UCODE_ID_CP_PFP: 2169 *type = GFX_FW_TYPE_CP_PFP; 2170 break; 2171 case AMDGPU_UCODE_ID_CP_ME: 2172 *type = GFX_FW_TYPE_CP_ME; 2173 break; 2174 case AMDGPU_UCODE_ID_CP_MEC1: 2175 *type = GFX_FW_TYPE_CP_MEC; 2176 break; 2177 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2178 *type = GFX_FW_TYPE_CP_MEC_ME1; 2179 break; 2180 case AMDGPU_UCODE_ID_CP_MEC2: 2181 *type = GFX_FW_TYPE_CP_MEC; 2182 break; 2183 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2184 *type = GFX_FW_TYPE_CP_MEC_ME2; 2185 break; 2186 case AMDGPU_UCODE_ID_RLC_P: 2187 *type = GFX_FW_TYPE_RLC_P; 2188 break; 2189 case AMDGPU_UCODE_ID_RLC_V: 2190 *type = GFX_FW_TYPE_RLC_V; 2191 break; 2192 case AMDGPU_UCODE_ID_RLC_G: 2193 *type = GFX_FW_TYPE_RLC_G; 2194 break; 2195 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2196 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2197 break; 2198 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2199 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2200 break; 2201 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2202 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2203 break; 2204 case AMDGPU_UCODE_ID_RLC_IRAM: 2205 *type = GFX_FW_TYPE_RLC_IRAM; 2206 break; 2207 case AMDGPU_UCODE_ID_RLC_DRAM: 2208 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2209 break; 2210 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2211 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2212 break; 2213 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2214 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2215 break; 2216 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2217 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2218 break; 2219 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2220 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2221 break; 2222 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2223 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2224 break; 2225 case AMDGPU_UCODE_ID_SMC: 2226 *type = GFX_FW_TYPE_SMU; 2227 break; 2228 case AMDGPU_UCODE_ID_PPTABLE: 2229 *type = GFX_FW_TYPE_PPTABLE; 2230 break; 2231 case AMDGPU_UCODE_ID_UVD: 2232 *type = GFX_FW_TYPE_UVD; 2233 break; 2234 case AMDGPU_UCODE_ID_UVD1: 2235 *type = GFX_FW_TYPE_UVD1; 2236 break; 2237 case AMDGPU_UCODE_ID_VCE: 2238 *type = GFX_FW_TYPE_VCE; 2239 break; 2240 case AMDGPU_UCODE_ID_VCN: 2241 *type = GFX_FW_TYPE_VCN; 2242 break; 2243 case AMDGPU_UCODE_ID_VCN1: 2244 *type = GFX_FW_TYPE_VCN1; 2245 break; 2246 case AMDGPU_UCODE_ID_DMCU_ERAM: 2247 *type = GFX_FW_TYPE_DMCU_ERAM; 2248 break; 2249 case AMDGPU_UCODE_ID_DMCU_INTV: 2250 *type = GFX_FW_TYPE_DMCU_ISR; 2251 break; 2252 case AMDGPU_UCODE_ID_VCN0_RAM: 2253 *type = GFX_FW_TYPE_VCN0_RAM; 2254 break; 2255 case AMDGPU_UCODE_ID_VCN1_RAM: 2256 *type = GFX_FW_TYPE_VCN1_RAM; 2257 break; 2258 case AMDGPU_UCODE_ID_DMCUB: 2259 *type = GFX_FW_TYPE_DMUB; 2260 break; 2261 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2262 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2263 break; 2264 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2265 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2266 break; 2267 case AMDGPU_UCODE_ID_IMU_I: 2268 *type = GFX_FW_TYPE_IMU_I; 2269 break; 2270 case AMDGPU_UCODE_ID_IMU_D: 2271 *type = GFX_FW_TYPE_IMU_D; 2272 break; 2273 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2274 *type = GFX_FW_TYPE_RS64_PFP; 2275 break; 2276 case AMDGPU_UCODE_ID_CP_RS64_ME: 2277 *type = GFX_FW_TYPE_RS64_ME; 2278 break; 2279 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2280 *type = GFX_FW_TYPE_RS64_MEC; 2281 break; 2282 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2283 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2284 break; 2285 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2286 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2287 break; 2288 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2289 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2290 break; 2291 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2292 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2293 break; 2294 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2295 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2296 break; 2297 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2298 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2299 break; 2300 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2301 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2302 break; 2303 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2304 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2305 break; 2306 case AMDGPU_UCODE_ID_MAXIMUM: 2307 default: 2308 return -EINVAL; 2309 } 2310 2311 return 0; 2312 } 2313 2314 static void psp_print_fw_hdr(struct psp_context *psp, 2315 struct amdgpu_firmware_info *ucode) 2316 { 2317 struct amdgpu_device *adev = psp->adev; 2318 struct common_firmware_header *hdr; 2319 2320 switch (ucode->ucode_id) { 2321 case AMDGPU_UCODE_ID_SDMA0: 2322 case AMDGPU_UCODE_ID_SDMA1: 2323 case AMDGPU_UCODE_ID_SDMA2: 2324 case AMDGPU_UCODE_ID_SDMA3: 2325 case AMDGPU_UCODE_ID_SDMA4: 2326 case AMDGPU_UCODE_ID_SDMA5: 2327 case AMDGPU_UCODE_ID_SDMA6: 2328 case AMDGPU_UCODE_ID_SDMA7: 2329 hdr = (struct common_firmware_header *) 2330 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2331 amdgpu_ucode_print_sdma_hdr(hdr); 2332 break; 2333 case AMDGPU_UCODE_ID_CP_CE: 2334 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2335 amdgpu_ucode_print_gfx_hdr(hdr); 2336 break; 2337 case AMDGPU_UCODE_ID_CP_PFP: 2338 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2339 amdgpu_ucode_print_gfx_hdr(hdr); 2340 break; 2341 case AMDGPU_UCODE_ID_CP_ME: 2342 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2343 amdgpu_ucode_print_gfx_hdr(hdr); 2344 break; 2345 case AMDGPU_UCODE_ID_CP_MEC1: 2346 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2347 amdgpu_ucode_print_gfx_hdr(hdr); 2348 break; 2349 case AMDGPU_UCODE_ID_RLC_G: 2350 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2351 amdgpu_ucode_print_rlc_hdr(hdr); 2352 break; 2353 case AMDGPU_UCODE_ID_SMC: 2354 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2355 amdgpu_ucode_print_smc_hdr(hdr); 2356 break; 2357 default: 2358 break; 2359 } 2360 } 2361 2362 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2363 struct psp_gfx_cmd_resp *cmd) 2364 { 2365 int ret; 2366 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2367 2368 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2369 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2370 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2371 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2372 2373 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2374 if (ret) 2375 DRM_ERROR("Unknown firmware type\n"); 2376 2377 return ret; 2378 } 2379 2380 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2381 struct amdgpu_firmware_info *ucode) 2382 { 2383 int ret = 0; 2384 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2385 2386 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2387 if (!ret) { 2388 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2389 psp->fence_buf_mc_addr); 2390 } 2391 2392 release_psp_cmd_buf(psp); 2393 2394 return ret; 2395 } 2396 2397 static int psp_load_smu_fw(struct psp_context *psp) 2398 { 2399 int ret; 2400 struct amdgpu_device *adev = psp->adev; 2401 struct amdgpu_firmware_info *ucode = 2402 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2403 struct amdgpu_ras *ras = psp->ras_context.ras; 2404 2405 /* 2406 * Skip SMU FW reloading in case of using BACO for runpm only, 2407 * as SMU is always alive. 2408 */ 2409 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2410 return 0; 2411 2412 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2413 return 0; 2414 2415 if ((amdgpu_in_reset(adev) && 2416 ras && adev->ras_enabled && 2417 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2418 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2419 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2420 if (ret) { 2421 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2422 } 2423 } 2424 2425 ret = psp_execute_non_psp_fw_load(psp, ucode); 2426 2427 if (ret) 2428 DRM_ERROR("PSP load smu failed!\n"); 2429 2430 return ret; 2431 } 2432 2433 static bool fw_load_skip_check(struct psp_context *psp, 2434 struct amdgpu_firmware_info *ucode) 2435 { 2436 if (!ucode->fw || !ucode->ucode_size) 2437 return true; 2438 2439 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2440 (psp_smu_reload_quirk(psp) || 2441 psp->autoload_supported || 2442 psp->pmfw_centralized_cstate_management)) 2443 return true; 2444 2445 if (amdgpu_sriov_vf(psp->adev) && 2446 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2447 return true; 2448 2449 if (psp->autoload_supported && 2450 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2451 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2452 /* skip mec JT when autoload is enabled */ 2453 return true; 2454 2455 return false; 2456 } 2457 2458 int psp_load_fw_list(struct psp_context *psp, 2459 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2460 { 2461 int ret = 0, i; 2462 struct amdgpu_firmware_info *ucode; 2463 2464 for (i = 0; i < ucode_count; ++i) { 2465 ucode = ucode_list[i]; 2466 psp_print_fw_hdr(psp, ucode); 2467 ret = psp_execute_non_psp_fw_load(psp, ucode); 2468 if (ret) 2469 return ret; 2470 } 2471 return ret; 2472 } 2473 2474 static int psp_load_non_psp_fw(struct psp_context *psp) 2475 { 2476 int i, ret; 2477 struct amdgpu_firmware_info *ucode; 2478 struct amdgpu_device *adev = psp->adev; 2479 2480 if (psp->autoload_supported && 2481 !psp->pmfw_centralized_cstate_management) { 2482 ret = psp_load_smu_fw(psp); 2483 if (ret) 2484 return ret; 2485 } 2486 2487 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2488 ucode = &adev->firmware.ucode[i]; 2489 2490 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2491 !fw_load_skip_check(psp, ucode)) { 2492 ret = psp_load_smu_fw(psp); 2493 if (ret) 2494 return ret; 2495 continue; 2496 } 2497 2498 if (fw_load_skip_check(psp, ucode)) 2499 continue; 2500 2501 if (psp->autoload_supported && 2502 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2503 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2504 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2505 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2506 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2507 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2508 /* PSP only receive one SDMA fw for sienna_cichlid, 2509 * as all four sdma fw are same */ 2510 continue; 2511 2512 psp_print_fw_hdr(psp, ucode); 2513 2514 ret = psp_execute_non_psp_fw_load(psp, ucode); 2515 if (ret) 2516 return ret; 2517 2518 /* Start rlc autoload after psp recieved all the gfx firmware */ 2519 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2520 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2521 ret = psp_rlc_autoload_start(psp); 2522 if (ret) { 2523 DRM_ERROR("Failed to start rlc autoload\n"); 2524 return ret; 2525 } 2526 } 2527 } 2528 2529 return 0; 2530 } 2531 2532 static int psp_load_fw(struct amdgpu_device *adev) 2533 { 2534 int ret; 2535 struct psp_context *psp = &adev->psp; 2536 2537 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2538 /* should not destroy ring, only stop */ 2539 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2540 } else { 2541 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2542 2543 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2544 if (ret) { 2545 DRM_ERROR("PSP ring init failed!\n"); 2546 goto failed; 2547 } 2548 } 2549 2550 ret = psp_hw_start(psp); 2551 if (ret) 2552 goto failed; 2553 2554 ret = psp_load_non_psp_fw(psp); 2555 if (ret) 2556 goto failed1; 2557 2558 ret = psp_asd_initialize(psp); 2559 if (ret) { 2560 DRM_ERROR("PSP load asd failed!\n"); 2561 goto failed1; 2562 } 2563 2564 ret = psp_rl_load(adev); 2565 if (ret) { 2566 DRM_ERROR("PSP load RL failed!\n"); 2567 goto failed1; 2568 } 2569 2570 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2571 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2572 ret = psp_xgmi_initialize(psp, false, true); 2573 /* Warning the XGMI seesion initialize failure 2574 * Instead of stop driver initialization 2575 */ 2576 if (ret) 2577 dev_err(psp->adev->dev, 2578 "XGMI: Failed to initialize XGMI session\n"); 2579 } 2580 } 2581 2582 if (psp->ta_fw) { 2583 ret = psp_ras_initialize(psp); 2584 if (ret) 2585 dev_err(psp->adev->dev, 2586 "RAS: Failed to initialize RAS\n"); 2587 2588 ret = psp_hdcp_initialize(psp); 2589 if (ret) 2590 dev_err(psp->adev->dev, 2591 "HDCP: Failed to initialize HDCP\n"); 2592 2593 ret = psp_dtm_initialize(psp); 2594 if (ret) 2595 dev_err(psp->adev->dev, 2596 "DTM: Failed to initialize DTM\n"); 2597 2598 ret = psp_rap_initialize(psp); 2599 if (ret) 2600 dev_err(psp->adev->dev, 2601 "RAP: Failed to initialize RAP\n"); 2602 2603 ret = psp_securedisplay_initialize(psp); 2604 if (ret) 2605 dev_err(psp->adev->dev, 2606 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2607 } 2608 2609 return 0; 2610 2611 failed1: 2612 psp_free_shared_bufs(psp); 2613 failed: 2614 /* 2615 * all cleanup jobs (xgmi terminate, ras terminate, 2616 * ring destroy, cmd/fence/fw buffers destory, 2617 * psp->cmd destory) are delayed to psp_hw_fini 2618 */ 2619 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2620 return ret; 2621 } 2622 2623 static int psp_hw_init(void *handle) 2624 { 2625 int ret; 2626 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2627 2628 mutex_lock(&adev->firmware.mutex); 2629 /* 2630 * This sequence is just used on hw_init only once, no need on 2631 * resume. 2632 */ 2633 ret = amdgpu_ucode_init_bo(adev); 2634 if (ret) 2635 goto failed; 2636 2637 ret = psp_load_fw(adev); 2638 if (ret) { 2639 DRM_ERROR("PSP firmware loading failed\n"); 2640 goto failed; 2641 } 2642 2643 mutex_unlock(&adev->firmware.mutex); 2644 return 0; 2645 2646 failed: 2647 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2648 mutex_unlock(&adev->firmware.mutex); 2649 return -EINVAL; 2650 } 2651 2652 static int psp_hw_fini(void *handle) 2653 { 2654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2655 struct psp_context *psp = &adev->psp; 2656 2657 if (psp->ta_fw) { 2658 psp_ras_terminate(psp); 2659 psp_securedisplay_terminate(psp); 2660 psp_rap_terminate(psp); 2661 psp_dtm_terminate(psp); 2662 psp_hdcp_terminate(psp); 2663 2664 if (adev->gmc.xgmi.num_physical_nodes > 1) 2665 psp_xgmi_terminate(psp); 2666 } 2667 2668 psp_asd_terminate(psp); 2669 psp_tmr_terminate(psp); 2670 2671 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2672 2673 psp_free_shared_bufs(psp); 2674 2675 return 0; 2676 } 2677 2678 static int psp_suspend(void *handle) 2679 { 2680 int ret = 0; 2681 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2682 struct psp_context *psp = &adev->psp; 2683 2684 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2685 psp->xgmi_context.context.initialized) { 2686 ret = psp_xgmi_terminate(psp); 2687 if (ret) { 2688 DRM_ERROR("Failed to terminate xgmi ta\n"); 2689 goto out; 2690 } 2691 } 2692 2693 if (psp->ta_fw) { 2694 ret = psp_ras_terminate(psp); 2695 if (ret) { 2696 DRM_ERROR("Failed to terminate ras ta\n"); 2697 goto out; 2698 } 2699 ret = psp_hdcp_terminate(psp); 2700 if (ret) { 2701 DRM_ERROR("Failed to terminate hdcp ta\n"); 2702 goto out; 2703 } 2704 ret = psp_dtm_terminate(psp); 2705 if (ret) { 2706 DRM_ERROR("Failed to terminate dtm ta\n"); 2707 goto out; 2708 } 2709 ret = psp_rap_terminate(psp); 2710 if (ret) { 2711 DRM_ERROR("Failed to terminate rap ta\n"); 2712 goto out; 2713 } 2714 ret = psp_securedisplay_terminate(psp); 2715 if (ret) { 2716 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2717 goto out; 2718 } 2719 } 2720 2721 ret = psp_asd_terminate(psp); 2722 if (ret) { 2723 DRM_ERROR("Failed to terminate asd\n"); 2724 goto out; 2725 } 2726 2727 ret = psp_tmr_terminate(psp); 2728 if (ret) { 2729 DRM_ERROR("Failed to terminate tmr\n"); 2730 goto out; 2731 } 2732 2733 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2734 if (ret) { 2735 DRM_ERROR("PSP ring stop failed\n"); 2736 } 2737 2738 out: 2739 return ret; 2740 } 2741 2742 static int psp_resume(void *handle) 2743 { 2744 int ret; 2745 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2746 struct psp_context *psp = &adev->psp; 2747 2748 DRM_INFO("PSP is resuming...\n"); 2749 2750 if (psp->mem_train_ctx.enable_mem_training) { 2751 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2752 if (ret) { 2753 DRM_ERROR("Failed to process memory training!\n"); 2754 return ret; 2755 } 2756 } 2757 2758 mutex_lock(&adev->firmware.mutex); 2759 2760 ret = psp_hw_start(psp); 2761 if (ret) 2762 goto failed; 2763 2764 ret = psp_load_non_psp_fw(psp); 2765 if (ret) 2766 goto failed; 2767 2768 ret = psp_asd_initialize(psp); 2769 if (ret) { 2770 DRM_ERROR("PSP load asd failed!\n"); 2771 goto failed; 2772 } 2773 2774 ret = psp_rl_load(adev); 2775 if (ret) { 2776 dev_err(adev->dev, "PSP load RL failed!\n"); 2777 goto failed; 2778 } 2779 2780 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2781 ret = psp_xgmi_initialize(psp, false, true); 2782 /* Warning the XGMI seesion initialize failure 2783 * Instead of stop driver initialization 2784 */ 2785 if (ret) 2786 dev_err(psp->adev->dev, 2787 "XGMI: Failed to initialize XGMI session\n"); 2788 } 2789 2790 if (psp->ta_fw) { 2791 ret = psp_ras_initialize(psp); 2792 if (ret) 2793 dev_err(psp->adev->dev, 2794 "RAS: Failed to initialize RAS\n"); 2795 2796 ret = psp_hdcp_initialize(psp); 2797 if (ret) 2798 dev_err(psp->adev->dev, 2799 "HDCP: Failed to initialize HDCP\n"); 2800 2801 ret = psp_dtm_initialize(psp); 2802 if (ret) 2803 dev_err(psp->adev->dev, 2804 "DTM: Failed to initialize DTM\n"); 2805 2806 ret = psp_rap_initialize(psp); 2807 if (ret) 2808 dev_err(psp->adev->dev, 2809 "RAP: Failed to initialize RAP\n"); 2810 2811 ret = psp_securedisplay_initialize(psp); 2812 if (ret) 2813 dev_err(psp->adev->dev, 2814 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2815 } 2816 2817 mutex_unlock(&adev->firmware.mutex); 2818 2819 return 0; 2820 2821 failed: 2822 DRM_ERROR("PSP resume failed\n"); 2823 mutex_unlock(&adev->firmware.mutex); 2824 return ret; 2825 } 2826 2827 int psp_gpu_reset(struct amdgpu_device *adev) 2828 { 2829 int ret; 2830 2831 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2832 return 0; 2833 2834 mutex_lock(&adev->psp.mutex); 2835 ret = psp_mode1_reset(&adev->psp); 2836 mutex_unlock(&adev->psp.mutex); 2837 2838 return ret; 2839 } 2840 2841 int psp_rlc_autoload_start(struct psp_context *psp) 2842 { 2843 int ret; 2844 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2845 2846 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2847 2848 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2849 psp->fence_buf_mc_addr); 2850 2851 release_psp_cmd_buf(psp); 2852 2853 return ret; 2854 } 2855 2856 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2857 uint64_t cmd_gpu_addr, int cmd_size) 2858 { 2859 struct amdgpu_firmware_info ucode = {0}; 2860 2861 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2862 AMDGPU_UCODE_ID_VCN0_RAM; 2863 ucode.mc_addr = cmd_gpu_addr; 2864 ucode.ucode_size = cmd_size; 2865 2866 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2867 } 2868 2869 int psp_ring_cmd_submit(struct psp_context *psp, 2870 uint64_t cmd_buf_mc_addr, 2871 uint64_t fence_mc_addr, 2872 int index) 2873 { 2874 unsigned int psp_write_ptr_reg = 0; 2875 struct psp_gfx_rb_frame *write_frame; 2876 struct psp_ring *ring = &psp->km_ring; 2877 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2878 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2879 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2880 struct amdgpu_device *adev = psp->adev; 2881 uint32_t ring_size_dw = ring->ring_size / 4; 2882 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2883 2884 /* KM (GPCOM) prepare write pointer */ 2885 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2886 2887 /* Update KM RB frame pointer to new frame */ 2888 /* write_frame ptr increments by size of rb_frame in bytes */ 2889 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2890 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2891 write_frame = ring_buffer_start; 2892 else 2893 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2894 /* Check invalid write_frame ptr address */ 2895 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2896 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2897 ring_buffer_start, ring_buffer_end, write_frame); 2898 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2899 return -EINVAL; 2900 } 2901 2902 /* Initialize KM RB frame */ 2903 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2904 2905 /* Update KM RB frame */ 2906 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2907 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2908 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2909 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2910 write_frame->fence_value = index; 2911 amdgpu_device_flush_hdp(adev, NULL); 2912 2913 /* Update the write Pointer in DWORDs */ 2914 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2915 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2916 return 0; 2917 } 2918 2919 int psp_init_asd_microcode(struct psp_context *psp, 2920 const char *chip_name) 2921 { 2922 struct amdgpu_device *adev = psp->adev; 2923 char fw_name[PSP_FW_NAME_LEN]; 2924 const struct psp_firmware_header_v1_0 *asd_hdr; 2925 int err = 0; 2926 2927 if (!chip_name) { 2928 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2929 return -EINVAL; 2930 } 2931 2932 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2933 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2934 if (err) 2935 goto out; 2936 2937 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2938 if (err) 2939 goto out; 2940 2941 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2942 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2943 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2944 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2945 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2946 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2947 return 0; 2948 out: 2949 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2950 release_firmware(adev->psp.asd_fw); 2951 adev->psp.asd_fw = NULL; 2952 return err; 2953 } 2954 2955 int psp_init_toc_microcode(struct psp_context *psp, 2956 const char *chip_name) 2957 { 2958 struct amdgpu_device *adev = psp->adev; 2959 char fw_name[PSP_FW_NAME_LEN]; 2960 const struct psp_firmware_header_v1_0 *toc_hdr; 2961 int err = 0; 2962 2963 if (!chip_name) { 2964 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2965 return -EINVAL; 2966 } 2967 2968 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2969 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2970 if (err) 2971 goto out; 2972 2973 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2974 if (err) 2975 goto out; 2976 2977 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2978 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2979 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2980 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2981 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2982 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2983 return 0; 2984 out: 2985 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 2986 release_firmware(adev->psp.toc_fw); 2987 adev->psp.toc_fw = NULL; 2988 return err; 2989 } 2990 2991 static int parse_sos_bin_descriptor(struct psp_context *psp, 2992 const struct psp_fw_bin_desc *desc, 2993 const struct psp_firmware_header_v2_0 *sos_hdr) 2994 { 2995 uint8_t *ucode_start_addr = NULL; 2996 2997 if (!psp || !desc || !sos_hdr) 2998 return -EINVAL; 2999 3000 ucode_start_addr = (uint8_t *)sos_hdr + 3001 le32_to_cpu(desc->offset_bytes) + 3002 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3003 3004 switch (desc->fw_type) { 3005 case PSP_FW_TYPE_PSP_SOS: 3006 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3007 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3008 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3009 psp->sos.start_addr = ucode_start_addr; 3010 break; 3011 case PSP_FW_TYPE_PSP_SYS_DRV: 3012 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3013 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3014 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3015 psp->sys.start_addr = ucode_start_addr; 3016 break; 3017 case PSP_FW_TYPE_PSP_KDB: 3018 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3019 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3020 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3021 psp->kdb.start_addr = ucode_start_addr; 3022 break; 3023 case PSP_FW_TYPE_PSP_TOC: 3024 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3025 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3026 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3027 psp->toc.start_addr = ucode_start_addr; 3028 break; 3029 case PSP_FW_TYPE_PSP_SPL: 3030 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3031 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3032 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3033 psp->spl.start_addr = ucode_start_addr; 3034 break; 3035 case PSP_FW_TYPE_PSP_RL: 3036 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3037 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3038 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3039 psp->rl.start_addr = ucode_start_addr; 3040 break; 3041 case PSP_FW_TYPE_PSP_SOC_DRV: 3042 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3043 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3044 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3045 psp->soc_drv.start_addr = ucode_start_addr; 3046 break; 3047 case PSP_FW_TYPE_PSP_INTF_DRV: 3048 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3049 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3050 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3051 psp->intf_drv.start_addr = ucode_start_addr; 3052 break; 3053 case PSP_FW_TYPE_PSP_DBG_DRV: 3054 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3055 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3056 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3057 psp->dbg_drv.start_addr = ucode_start_addr; 3058 break; 3059 case PSP_FW_TYPE_PSP_RAS_DRV: 3060 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3061 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3062 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3063 psp->ras_drv.start_addr = ucode_start_addr; 3064 break; 3065 default: 3066 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3067 break; 3068 } 3069 3070 return 0; 3071 } 3072 3073 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3074 { 3075 const struct psp_firmware_header_v1_0 *sos_hdr; 3076 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3077 uint8_t *ucode_array_start_addr; 3078 3079 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3080 ucode_array_start_addr = (uint8_t *)sos_hdr + 3081 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3082 3083 if (adev->gmc.xgmi.connected_to_cpu || 3084 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3085 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3086 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3087 3088 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3089 adev->psp.sys.start_addr = ucode_array_start_addr; 3090 3091 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3092 adev->psp.sos.start_addr = ucode_array_start_addr + 3093 le32_to_cpu(sos_hdr->sos.offset_bytes); 3094 } else { 3095 /* Load alternate PSP SOS FW */ 3096 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3097 3098 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3099 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3100 3101 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3102 adev->psp.sys.start_addr = ucode_array_start_addr + 3103 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3104 3105 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3106 adev->psp.sos.start_addr = ucode_array_start_addr + 3107 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3108 } 3109 3110 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3111 dev_warn(adev->dev, "PSP SOS FW not available"); 3112 return -EINVAL; 3113 } 3114 3115 return 0; 3116 } 3117 3118 int psp_init_sos_microcode(struct psp_context *psp, 3119 const char *chip_name) 3120 { 3121 struct amdgpu_device *adev = psp->adev; 3122 char fw_name[PSP_FW_NAME_LEN]; 3123 const struct psp_firmware_header_v1_0 *sos_hdr; 3124 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3125 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3126 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3127 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3128 int err = 0; 3129 uint8_t *ucode_array_start_addr; 3130 int fw_index = 0; 3131 3132 if (!chip_name) { 3133 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3134 return -EINVAL; 3135 } 3136 3137 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3138 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3139 if (err) 3140 goto out; 3141 3142 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3143 if (err) 3144 goto out; 3145 3146 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3147 ucode_array_start_addr = (uint8_t *)sos_hdr + 3148 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3149 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3150 3151 switch (sos_hdr->header.header_version_major) { 3152 case 1: 3153 err = psp_init_sos_base_fw(adev); 3154 if (err) 3155 goto out; 3156 3157 if (sos_hdr->header.header_version_minor == 1) { 3158 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3159 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3160 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3161 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3162 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3163 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3164 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3165 } 3166 if (sos_hdr->header.header_version_minor == 2) { 3167 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3168 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3169 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3170 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3171 } 3172 if (sos_hdr->header.header_version_minor == 3) { 3173 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3174 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3175 adev->psp.toc.start_addr = ucode_array_start_addr + 3176 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3177 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3178 adev->psp.kdb.start_addr = ucode_array_start_addr + 3179 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3180 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3181 adev->psp.spl.start_addr = ucode_array_start_addr + 3182 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3183 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3184 adev->psp.rl.start_addr = ucode_array_start_addr + 3185 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3186 } 3187 break; 3188 case 2: 3189 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3190 3191 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3192 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3193 err = -EINVAL; 3194 goto out; 3195 } 3196 3197 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3198 err = parse_sos_bin_descriptor(psp, 3199 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3200 sos_hdr_v2_0); 3201 if (err) 3202 goto out; 3203 } 3204 break; 3205 default: 3206 dev_err(adev->dev, 3207 "unsupported psp sos firmware\n"); 3208 err = -EINVAL; 3209 goto out; 3210 } 3211 3212 return 0; 3213 out: 3214 dev_err(adev->dev, 3215 "failed to init sos firmware\n"); 3216 release_firmware(adev->psp.sos_fw); 3217 adev->psp.sos_fw = NULL; 3218 3219 return err; 3220 } 3221 3222 static int parse_ta_bin_descriptor(struct psp_context *psp, 3223 const struct psp_fw_bin_desc *desc, 3224 const struct ta_firmware_header_v2_0 *ta_hdr) 3225 { 3226 uint8_t *ucode_start_addr = NULL; 3227 3228 if (!psp || !desc || !ta_hdr) 3229 return -EINVAL; 3230 3231 ucode_start_addr = (uint8_t *)ta_hdr + 3232 le32_to_cpu(desc->offset_bytes) + 3233 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3234 3235 switch (desc->fw_type) { 3236 case TA_FW_TYPE_PSP_ASD: 3237 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3238 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3239 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3240 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3241 break; 3242 case TA_FW_TYPE_PSP_XGMI: 3243 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3244 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3245 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3246 break; 3247 case TA_FW_TYPE_PSP_RAS: 3248 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3249 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3250 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3251 break; 3252 case TA_FW_TYPE_PSP_HDCP: 3253 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3254 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3255 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3256 break; 3257 case TA_FW_TYPE_PSP_DTM: 3258 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3259 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3260 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3261 break; 3262 case TA_FW_TYPE_PSP_RAP: 3263 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3264 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3265 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3266 break; 3267 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3268 psp->securedisplay_context.context.bin_desc.fw_version = 3269 le32_to_cpu(desc->fw_version); 3270 psp->securedisplay_context.context.bin_desc.size_bytes = 3271 le32_to_cpu(desc->size_bytes); 3272 psp->securedisplay_context.context.bin_desc.start_addr = 3273 ucode_start_addr; 3274 break; 3275 default: 3276 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3277 break; 3278 } 3279 3280 return 0; 3281 } 3282 3283 int psp_init_ta_microcode(struct psp_context *psp, 3284 const char *chip_name) 3285 { 3286 struct amdgpu_device *adev = psp->adev; 3287 char fw_name[PSP_FW_NAME_LEN]; 3288 const struct ta_firmware_header_v2_0 *ta_hdr; 3289 int err = 0; 3290 int ta_index = 0; 3291 3292 if (!chip_name) { 3293 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3294 return -EINVAL; 3295 } 3296 3297 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3298 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3299 if (err) 3300 goto out; 3301 3302 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3303 if (err) 3304 goto out; 3305 3306 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3307 3308 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3309 dev_err(adev->dev, "unsupported TA header version\n"); 3310 err = -EINVAL; 3311 goto out; 3312 } 3313 3314 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3315 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3316 err = -EINVAL; 3317 goto out; 3318 } 3319 3320 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3321 err = parse_ta_bin_descriptor(psp, 3322 &ta_hdr->ta_fw_bin[ta_index], 3323 ta_hdr); 3324 if (err) 3325 goto out; 3326 } 3327 3328 return 0; 3329 out: 3330 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3331 release_firmware(adev->psp.ta_fw); 3332 adev->psp.ta_fw = NULL; 3333 return err; 3334 } 3335 3336 int psp_init_cap_microcode(struct psp_context *psp, 3337 const char *chip_name) 3338 { 3339 struct amdgpu_device *adev = psp->adev; 3340 char fw_name[PSP_FW_NAME_LEN]; 3341 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3342 struct amdgpu_firmware_info *info = NULL; 3343 int err = 0; 3344 3345 if (!chip_name) { 3346 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3347 return -EINVAL; 3348 } 3349 3350 if (!amdgpu_sriov_vf(adev)) { 3351 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3352 return -EINVAL; 3353 } 3354 3355 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3356 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3357 if (err) { 3358 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3359 err = 0; 3360 goto out; 3361 } 3362 3363 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3364 if (err) { 3365 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3366 goto out; 3367 } 3368 3369 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3370 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3371 info->fw = adev->psp.cap_fw; 3372 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3373 adev->psp.cap_fw->data; 3374 adev->firmware.fw_size += ALIGN( 3375 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3376 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3377 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3378 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3379 3380 return 0; 3381 3382 out: 3383 release_firmware(adev->psp.cap_fw); 3384 adev->psp.cap_fw = NULL; 3385 return err; 3386 } 3387 3388 static int psp_set_clockgating_state(void *handle, 3389 enum amd_clockgating_state state) 3390 { 3391 return 0; 3392 } 3393 3394 static int psp_set_powergating_state(void *handle, 3395 enum amd_powergating_state state) 3396 { 3397 return 0; 3398 } 3399 3400 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3401 struct device_attribute *attr, 3402 char *buf) 3403 { 3404 struct drm_device *ddev = dev_get_drvdata(dev); 3405 struct amdgpu_device *adev = drm_to_adev(ddev); 3406 uint32_t fw_ver; 3407 int ret; 3408 3409 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3410 DRM_INFO("PSP block is not ready yet."); 3411 return -EBUSY; 3412 } 3413 3414 mutex_lock(&adev->psp.mutex); 3415 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3416 mutex_unlock(&adev->psp.mutex); 3417 3418 if (ret) { 3419 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3420 return ret; 3421 } 3422 3423 return sysfs_emit(buf, "%x\n", fw_ver); 3424 } 3425 3426 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3427 struct device_attribute *attr, 3428 const char *buf, 3429 size_t count) 3430 { 3431 struct drm_device *ddev = dev_get_drvdata(dev); 3432 struct amdgpu_device *adev = drm_to_adev(ddev); 3433 int ret, idx; 3434 char fw_name[100]; 3435 const struct firmware *usbc_pd_fw; 3436 struct amdgpu_bo *fw_buf_bo = NULL; 3437 uint64_t fw_pri_mc_addr; 3438 void *fw_pri_cpu_addr; 3439 3440 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3441 DRM_INFO("PSP block is not ready yet."); 3442 return -EBUSY; 3443 } 3444 3445 if (!drm_dev_enter(ddev, &idx)) 3446 return -ENODEV; 3447 3448 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3449 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3450 if (ret) 3451 goto fail; 3452 3453 /* LFB address which is aligned to 1MB boundary per PSP request */ 3454 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3455 AMDGPU_GEM_DOMAIN_VRAM, 3456 &fw_buf_bo, 3457 &fw_pri_mc_addr, 3458 &fw_pri_cpu_addr); 3459 if (ret) 3460 goto rel_buf; 3461 3462 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3463 3464 mutex_lock(&adev->psp.mutex); 3465 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3466 mutex_unlock(&adev->psp.mutex); 3467 3468 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3469 3470 rel_buf: 3471 release_firmware(usbc_pd_fw); 3472 fail: 3473 if (ret) { 3474 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3475 count = ret; 3476 } 3477 3478 drm_dev_exit(idx); 3479 return count; 3480 } 3481 3482 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3483 { 3484 int idx; 3485 3486 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3487 return; 3488 3489 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3490 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3491 3492 drm_dev_exit(idx); 3493 } 3494 3495 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3496 psp_usbc_pd_fw_sysfs_read, 3497 psp_usbc_pd_fw_sysfs_write); 3498 3499 int is_psp_fw_valid(struct psp_bin_desc bin) 3500 { 3501 return bin.size_bytes; 3502 } 3503 3504 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3505 struct bin_attribute *bin_attr, 3506 char *buffer, loff_t pos, size_t count) 3507 { 3508 struct device *dev = kobj_to_dev(kobj); 3509 struct drm_device *ddev = dev_get_drvdata(dev); 3510 struct amdgpu_device *adev = drm_to_adev(ddev); 3511 3512 adev->psp.vbflash_done = false; 3513 3514 /* Safeguard against memory drain */ 3515 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3516 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3517 kvfree(adev->psp.vbflash_tmp_buf); 3518 adev->psp.vbflash_tmp_buf = NULL; 3519 adev->psp.vbflash_image_size = 0; 3520 return -ENOMEM; 3521 } 3522 3523 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3524 if (!adev->psp.vbflash_tmp_buf) { 3525 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3526 if (!adev->psp.vbflash_tmp_buf) 3527 return -ENOMEM; 3528 } 3529 3530 mutex_lock(&adev->psp.mutex); 3531 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3532 adev->psp.vbflash_image_size += count; 3533 mutex_unlock(&adev->psp.mutex); 3534 3535 dev_info(adev->dev, "VBIOS flash write PSP done"); 3536 3537 return count; 3538 } 3539 3540 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3541 struct bin_attribute *bin_attr, char *buffer, 3542 loff_t pos, size_t count) 3543 { 3544 struct device *dev = kobj_to_dev(kobj); 3545 struct drm_device *ddev = dev_get_drvdata(dev); 3546 struct amdgpu_device *adev = drm_to_adev(ddev); 3547 struct amdgpu_bo *fw_buf_bo = NULL; 3548 uint64_t fw_pri_mc_addr; 3549 void *fw_pri_cpu_addr; 3550 int ret; 3551 3552 dev_info(adev->dev, "VBIOS flash to PSP started"); 3553 3554 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3555 AMDGPU_GPU_PAGE_SIZE, 3556 AMDGPU_GEM_DOMAIN_VRAM, 3557 &fw_buf_bo, 3558 &fw_pri_mc_addr, 3559 &fw_pri_cpu_addr); 3560 if (ret) 3561 goto rel_buf; 3562 3563 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3564 3565 mutex_lock(&adev->psp.mutex); 3566 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3567 mutex_unlock(&adev->psp.mutex); 3568 3569 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3570 3571 rel_buf: 3572 kvfree(adev->psp.vbflash_tmp_buf); 3573 adev->psp.vbflash_tmp_buf = NULL; 3574 adev->psp.vbflash_image_size = 0; 3575 3576 if (ret) { 3577 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3578 return ret; 3579 } 3580 3581 dev_info(adev->dev, "VBIOS flash to PSP done"); 3582 return 0; 3583 } 3584 3585 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3586 struct device_attribute *attr, 3587 char *buf) 3588 { 3589 struct drm_device *ddev = dev_get_drvdata(dev); 3590 struct amdgpu_device *adev = drm_to_adev(ddev); 3591 uint32_t vbflash_status; 3592 3593 vbflash_status = psp_vbflash_status(&adev->psp); 3594 if (!adev->psp.vbflash_done) 3595 vbflash_status = 0; 3596 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3597 vbflash_status = 1; 3598 3599 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3600 } 3601 3602 static const struct bin_attribute psp_vbflash_bin_attr = { 3603 .attr = {.name = "psp_vbflash", .mode = 0664}, 3604 .size = 0, 3605 .write = amdgpu_psp_vbflash_write, 3606 .read = amdgpu_psp_vbflash_read, 3607 }; 3608 3609 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3610 3611 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3612 { 3613 int ret = 0; 3614 struct psp_context *psp = &adev->psp; 3615 3616 if (amdgpu_sriov_vf(adev)) 3617 return -EINVAL; 3618 3619 switch (adev->ip_versions[MP0_HWIP][0]) { 3620 case IP_VERSION(13, 0, 0): 3621 case IP_VERSION(13, 0, 7): 3622 if (!psp->adev) { 3623 psp->adev = adev; 3624 psp_v13_0_set_psp_funcs(psp); 3625 } 3626 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3627 if (ret) 3628 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3629 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3630 if (ret) 3631 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3632 return ret; 3633 default: 3634 return 0; 3635 } 3636 } 3637 3638 const struct amd_ip_funcs psp_ip_funcs = { 3639 .name = "psp", 3640 .early_init = psp_early_init, 3641 .late_init = NULL, 3642 .sw_init = psp_sw_init, 3643 .sw_fini = psp_sw_fini, 3644 .hw_init = psp_hw_init, 3645 .hw_fini = psp_hw_fini, 3646 .suspend = psp_suspend, 3647 .resume = psp_resume, 3648 .is_idle = NULL, 3649 .check_soft_reset = NULL, 3650 .wait_for_idle = NULL, 3651 .soft_reset = NULL, 3652 .set_clockgating_state = psp_set_clockgating_state, 3653 .set_powergating_state = psp_set_powergating_state, 3654 }; 3655 3656 static int psp_sysfs_init(struct amdgpu_device *adev) 3657 { 3658 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3659 3660 if (ret) 3661 DRM_ERROR("Failed to create USBC PD FW control file!"); 3662 3663 return ret; 3664 } 3665 3666 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3667 { 3668 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3669 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3670 } 3671 3672 static void psp_sysfs_fini(struct amdgpu_device *adev) 3673 { 3674 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3675 } 3676 3677 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3678 { 3679 .type = AMD_IP_BLOCK_TYPE_PSP, 3680 .major = 3, 3681 .minor = 1, 3682 .rev = 0, 3683 .funcs = &psp_ip_funcs, 3684 }; 3685 3686 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3687 { 3688 .type = AMD_IP_BLOCK_TYPE_PSP, 3689 .major = 10, 3690 .minor = 0, 3691 .rev = 0, 3692 .funcs = &psp_ip_funcs, 3693 }; 3694 3695 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3696 { 3697 .type = AMD_IP_BLOCK_TYPE_PSP, 3698 .major = 11, 3699 .minor = 0, 3700 .rev = 0, 3701 .funcs = &psp_ip_funcs, 3702 }; 3703 3704 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3705 .type = AMD_IP_BLOCK_TYPE_PSP, 3706 .major = 11, 3707 .minor = 0, 3708 .rev = 8, 3709 .funcs = &psp_ip_funcs, 3710 }; 3711 3712 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3713 { 3714 .type = AMD_IP_BLOCK_TYPE_PSP, 3715 .major = 12, 3716 .minor = 0, 3717 .rev = 0, 3718 .funcs = &psp_ip_funcs, 3719 }; 3720 3721 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3722 .type = AMD_IP_BLOCK_TYPE_PSP, 3723 .major = 13, 3724 .minor = 0, 3725 .rev = 0, 3726 .funcs = &psp_ip_funcs, 3727 }; 3728 3729 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3730 .type = AMD_IP_BLOCK_TYPE_PSP, 3731 .major = 13, 3732 .minor = 0, 3733 .rev = 4, 3734 .funcs = &psp_ip_funcs, 3735 }; 3736